Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
GENERAL DESCRIPTION
The ALD2721E/ALD2721 is a dual monolithic rail-to-rail precision CMOS
operational amplifier with integrated user programmable EPAD (Electri-
cally Programmable Analog Device) based offset voltage adjustment. The
ALD2721E/ALD2721 is a dual version of the ALD1721E/ALD2721 opera-
tional amplifier. Each ALD2721E/ALD2721 operational amplifier features
individual user-programming offset voltage trimming, resulting in signifi-
cantly enhanced total system performance and user flexibility. EPAD
technology is an exclusive ALD design which has been refined for analog
applications where precision voltage trimming is necessary to achieve a
desired performance. It utilizes CMOS FETs as in-circuit elements for
trimming of offset voltage bias characteristics with the aid of a personal
computer under software control. Once programmed, the set parameters
are stored indefinitely within the device even after power-down. EPAD
offers the circuit designer a convenient and cost-effective trimming solution
for achieving the very highest amplifier/system performance.
The ALD2721E/ALD2721 dual operational amplifier features rail-to-rail
input and output voltage ranges, tolerance to over-voltage input spikes of
300mV beyond supply rails, capacitive loading up to 50pF, extremely low
input currents of 0.01pA typical, high open loop voltage gain, useful
bandwidth of 700KHz, slew rate of 0.7V/µs, and low typical supply current
of 200µA for both amplifiers.
BENEFITS
• Eliminates manual and elaborate
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal clocking noise source
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
• Low system implementation cost
• Micropower and Low Voltage
APPLICATIONS
• Sensor interface circuits
• Transducer biasing circuits
• Capacitive and charge integration circuits
• Biochemical probe interface
• Signal conditioning
• Portable instruments
• High source impedance electrode
amplifiers
• Precision Sample and Hold amplifiers
• Precision current to voltage converter
• Error correction circuits
• Sensor compensation circuits
• Precision gain amplifiers
• Periodic In-system calibration
• System output level shifter
KEY FEATURES
• EPAD (Electrically Programmable Analog Device)
• User programmable VOS trimmer
• Computer-assisted trimming
• Rail-to-rail input/output
• Compatible with standard EPAD Programmer
• Each amplifier VOS can be trimmed to a different VOS level
• High precision through in-system circuit precision trimming
• Reduces or eliminates VOS, PSRR, CMRR and TCVOS errors
• System level “calibration” capability
• Application Specific Programming mode
• In-System Programming mode
• Electrically programmable to compensate for external
component tolerances
• Achieves 0.01pA input bias current and 35µV input offset
voltage simultaneously
• Low voltage operation
1
2
3
4
5
6
7
11
12
13
14
8
9
10
VE
2A
VE
1A
V-
N/C
VE
2B
VE
1B
OUT
B
OUT
A
+IN
A
-IN
A
+IN
B
-IN
B
N/C V+
PIN CONFIGURATION
TOP VIEW
SB, PB, DB PACKAGES
* N/C Pins are internally connected. Do not connect externally.
ORDERING INFORMATION
Operating Temperature Range
0°C to +70°C0°C to +70°C -55°C to +125°C
14-Pin 14-Pin 14-Pin
Small Outline Plastic Dip CERDIP
Package (SOIC) Package Package
ALD2721ESB ALD2721EPB ALD2721EDB
ALD2721SB ALD2721PB ALD2721DB
* Contact factory for high temperature versions.
e
EPAD
TM
®
N
A
B
L
E
D
E
DUAL EPAD® MICROPOWER CMOS OPERATIONAL AMPLIFIER
ALD2721E/ALD2721
A
DVANCED
L
INEAR
D
EVICES,
I
NC.
ALD2721E/ALD2721 Advanced Linear Devices 2 of 13
FUNCTIONAL DESCRIPTION
The ALD2721E/ALD2721 uses EPADs as in-circuit ele-
ments for trimming of offset voltage bias characteristics.
Each ALD2721E/ALD2721 has a pair of EPAD-based cir-
cuits connected such that one circuit is used to adjust VOS in
one direction and the other circuit is used to adjust VOS in the
other direction. While each of the EPAD devices is a
monotonically adjustable programmable device, the VOS of
the ALD2721E can be adjusted many times in both direc-
tions. Once programmed, the set VOS levels are stored
permanently, even when the device power is removed.
Functional Description of ALD2721E
The ALD2721E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
The ALD2721E is an operational amplifier that can be
trimmed with user application-specific programming or in-
system programming conditions. User application-specific
circuit programming refers to the situation where the Total
Input Offset Voltage of the ALD2721E can be trimmed with
the actual intended operating conditions.
For example, an application circuit may have +1V and -1V
power supplies, and the operational amplifier input is biased
at +1V, and an average operating temperature at +85°C.
The circuit can be wired up to these conditions within an
environmental chamber with the ALD2721E inserted into a
test socket connected to this circuit while it is being electri-
cally trimmed. Any error in VOS due to these bias conditions
can be automatically zeroed out. The Total VOS error is now
limited only by the adjustable range and the stability of VOS,
and the input noise voltage of the operational amplifier.
Therefore, this Total VOS error now includes VOS as VOS is
traditionally specified; plus the VOS error contributions from
PSRR, CMRR, TCVOS, and noise. Typically this total VOS
error (VOST) is approximately ±35µV for the ALD2721E.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD2721E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD2721E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD2721E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as
resistor or sensor induced voltage errors, can also be cor-
rected. In this way, the “in-system” circuit output can be
adjusted to a desired level, eliminating the need for another
trimming function.
Functional Description of ALD2721
The ALD2721 is pre-programmed at the factory under stan-
dard operating conditions for minimum equivalent input off-
set voltage. The ALD2721 offers similar programmable
features as the ALD2721E, but with a more limited offset
voltage program range. In is intended for standard opera-
tional amplifier applications, where little or no electrical
porggramming by the user is necessary.
USER PROGRAMMABLE VOS FEATURE
Each ALD2721E/ALD2721 has four additional pins, com-
pared to a conventional dual operational amplifier which has
eight pins. These four additional pins are named VE1A,
VE2A for op amp A and VE1B, VE2B for op amp B. Each of
these pins VE1A, VE2A, VE1B, VE2B (represented by VExx)
are connected to a separate, internal offset bias circuit. VExx
pins have initial internal bias voltage values of approximately
1V to 2V. The voltage on these pins can be programmed
using the ALD E100 EPAD Programmer and the appropriate
Adapter Module. The useful programming range of voltages
on VExx pins are 1V to 3V.
VExx pins are programming pins, used during electrical
programming mode to inject charge into the internal EPADs.
Increasing voltage on VE1A/VE1B increases the offset volt-
age whereas increasing voltage on VE2A/VE2B decreases
the offset voltage of op amp A and op amp B, respectively.
The injected charge is then permanently stored. After
programming, VExx pins must be left open in order for these
voltages to remain at the programmed levels.
During programming, voltages on VExx pins are increased
incrementally to program the offset voltage of the operational
amplifier to the desired VOS. Note that desired VOS can be
any value within the offset voltage programmable ranges,
and can be equal zero, a positive value or a negative value.
This VOS value can also be reprogrammed to a different
value at a later time, provided that the useful VE1x or VE2x
programming voltage range has not been exceeded. VExx
pins can also serve as capacitively coupled input pins.
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
While programming, V+, VE1 and VE2 pins may be alter-
nately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD2721E application circuit to accommodate these
programming pulses. This can be accomplished by adding
resistors at certain appropriate circuit nodes. For more
information, see Application Note AN1700.
ALD2721E/ALD2721 Advanced Linear Devices 3 of 13
Supply voltage, V+ 10.6V
Differential input voltage range -0.3V to V+ +0.3V
Power dissipation 600 mW
Operating temperature range SB, PB packages 0°C to +70°C
DB package -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature, 10 seconds +260°C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
ABSOLUTE MAXIMUM RATINGS
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
2721E 2721
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Supply Voltage VS±1.0 ±5.0 ±1.0 ±5.0 V Dual Supply
V+2.0 10.0 2.0 10.0 V Single Supply
Initial Input Offset Voltage1VOS i 35 100 50 150 µVR
S
≤ 100KΩ
Offset Voltage Program Range 2∆VOS ±5±7±0.5 ±2mV
Programmed Input Offset VOS 50 100 50 150 µV At user specified
Voltage Error3target offset voltage
Total Input Offset Voltage 4VOST 50 100 50 150 µV At user specified
target offset voltage
Input Offset Current 5IOS 0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C
Input Bias Current 5IB0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C
Input Voltage Range 6VIR -0.3 5.3 -0.3 5.3 V V+ = +5V
-2.8 +2.8 -2.8 +2.8 V VS = ±2.5V
Input Resistance RIN 1014 1014 Ω
Input Offset Voltage Drift 7TCVOS 77µV/°CR
S ≤ 100KΩ
Initial Power Supply PSRR i90 90 dB RS ≤ 100KΩ
Rejection Ratio 8
Initial Common Mode CMRR i90 90 dB RS ≤ 100KΩ
Rejection Ratio 8
Large Signal Voltage Gain AV15 100 15 100 V/mV RL =100KΩ
10 10 V/mV 0°C ≤ TA ≤ +70°C
VO low 0.001 0.01 0.001 0.01 V RL =1MΩ V =5V
Output Voltage Range VO high 4.99 4.999 4.99 4.999 V 0°C ≤ TA ≤ +70°C
VO low -2.48 -2.40 -2.48 -2.40 V RL =100KΩ
VO high 2.40 2.48 2.40 2.48 V 0°C ≤ TA ≤ +70°C
Output Short Circuit Current ISC 11mA
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25oC VS = ±2.5V unless otherwise specified
ALD2721E/ALD2721 Advanced Linear Devices 4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
2721E 2721
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Supply Current IS200 400 200 400 µAV
IN = 0V
No Load
Power Dissipation PD1.00 2.00 1.00 2.00 mW VS = ±2.5V
Input Capacitance CIN 11
pF
Maximum Load Capacitance CL50 50 pF
Equivalent Input Noise Voltage en55 55 nV/√Hz f = 1KHz
Equivalent Input Noise Current in0.6 0.6 fA/√Hz f =10Hz
Bandwidth BW700 700 KHz
Slew Rate SR0.7 0.7 V/µsA
V
= +1
RL = 100KΩ
Rise time tr0.2 0.2 µsR
L = 100KΩ
Overshoot Factor 20 20 % RL=100KΩ
CL=50pF
Settling Time tS10 10 µs 0.1% AV = -1
RL= 100KΩ
CL = 50pF
Channel Separation CS 140 140 dB AV =100
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
2721E 2721
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Average Long Term Input Offset ∆ VOS 0.02 0.02 µV/
Voltage Stability 9∆ time 1000 hrs
Initial VE Voltage VE1 i, VE2 i1.2 1.7 V
Programmable Change of ∆VE1, ∆VE2 1.5 2.5 1.0 V
VE Range
Programmed VE Voltage Error e(VE1-VE2) 0.1 0.1 %
VE Pin Leakage Current ieb -5 -5 µA
TA = 25oC VS = ±2.5V unless otherwise specified
TA = 25oC VS = ±2.5V unless otherwise specified
ALD2721E/ALD2721 Advanced Linear Devices 5 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
2721E 2721
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Initial Power Supply PSRR i85 85 dB RS ≤ 100KΩ
Rejection Ratio 8
Initial Common Mode CMRRi83 83 dB RS ≤ 100KΩ
Rejection Ratio 8
Large Signal Voltage Gain AV250 250 V/mV RL = 100KΩ
Output Voltage Range VO low -4.98 -4.90 -4.98 -4.90 V RL = 100KΩ
VO high 4.90 4.98 4.90 4.98
Bandwidth BW1.0 1.0 MHz
Slew Rate SR1.0 1.0 V/µsA
V
= +1, CL = 50pF
2721E 2721
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Initial Input offset Voltage VOS i 0.7 0.7 mV RS ≤ 100KΩ
Input Offset Current IOS 2.0 2.0 nA
Input Bias Current IB2.0 2.0 nA
Initial Power Supply PSRR i85 85 dB RS ≤ 100KΩ
Rejection Ratio 8
Initial Common Mode CMRR i83 83 dB RS ≤ 100KΩ
Rejection Ratio 8
Large Signal Voltage Gain AV15 50 15 50 V/mV RL = 100KΩ
Output Voltage Range VO low -2.47 -2.40 -2.47 -2.40 V
VO high 2.35 2.45 2.35 2.45 V RL = 100KΩ
VS = ±2.5V -55°C ≤ TA ≤ +125°C unless otherwise specified
TA = 25oC VS = ±5.0V unless otherwise specified
ALD2721E/ALD2721 Advanced Linear Devices 6 of 13
DEFINITIONS AND DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD2721E/ALD2721 operational amplifier when shipped from
the factory. The device has been pre-programmed and tested
for programmability.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input offset
programming pins, VE1A/VE1B or VE2A/VE2B, change the
input offset voltage in the negative or positive direction, for each
of the amplifiers, A or B respectively. User specified target offset
voltage can be any offset voltage within this programming
range.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVOS and noise. It can also include errors
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD2721E/
ALD2721, the switching point between the two stages occurs at
approximately 1.5V below the positive supply voltage.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25°C, assuming activation energy of 1.0eV.
This parameter is sample tested.
ADDITIONAL DESIGN NOTES:
A. The ALD2721E/ALD2721 is internally compensated for
unity gain stability using a novel scheme which produces a single
pole role off in the gain characteristics while providing more than
70 degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD2721E/ALD2721 will typically drive 50pF
of external load capacitance.
B. The ALD2721E/ALD2721 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail-to-rail input common mode voltage range. The
switching point between the two differential stages is 1.5V below
positive supply voltage. For applications such as inverting
amplifiers or non-inverting amplifiers with a gain larger than 2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
does take place if the operational amplifier is connected as a rail-
to-rail unity gain buffer and the design must allow for input offset
voltage variations.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail-
to-rail input and output feature, makes the ALD2721E/
ALD2721 an effective analog signal buffer for high source
impedance sensors, transducers, and other circuit networks.
D. The ALD2721E/ALD2721 has static discharge protection.
However, care must be exercised when handling the device to
avoid strong static fields that may degrade a diode junction,
causing increased input leakage currents. The user is advised
to power up the circuit before, or simultaneously with, any input
voltages applied and to limit input voltages not to exceed 0.3V of
the power supply voltage levels.
E. VExx are high impedance terminals, as the internal bias
currents are set very low to a few microamperes to conserve
power. For some applications, these terminals may need to be
shielded from external coupling sources. For example, digital
signals running nearby may cause unwanted offset voltage
fluctuations. Care during the printed circuit board layout, to
place ground traces around these pins and to isolate them from
digital lines, will generally eliminate such coupling effects. In
addition, optional decoupling capacitors of 1000pF or greater
value can be added to VExx terminals.
F. The ALD2721E/ALD2721 is designed for use in low voltage,
micropower circuits. The maximum operating voltage during
normal operation should remain below 10V at all times. Care
should be taken to insure that the application in which the device
is used does not experience any positive or negative transient
voltages that will cause any of the terminal voltages to exceed
this limit.
G. All inputs or unused pins except VExx pins should be
connected to a supply voltage such as Ground so that they do not
become floating pins, since input impedance at these pins is very
high. If any of these pins are left undefined, they may cause
unwanted oscillation or intermittent excessive current drain. As
these devices are built with CMOS technology, normal operating
and storage temperature limits, ESD and latchup handling
precautions pertaining to CMOS device handling should be
observed.
ALD2721E/ALD2721 Advanced Linear Devices 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF FREQUENCY
FREQUENCY (Hz)
1 10 100 1K 10K 1M 10M100K
120
100
80
60
40
20
0
-20
OPEN LOOP VOLTAGE
GAIN (dB)
90
0
45
180
135
PHASE SHIFT IN DEGREES
VS = ±2.5V
TA = 25°C
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
100
10
1.0
0.01
0.1
INPUT BIAS CURRENT (pA)
100-25 0 75 1255025-50
1000
V
S
= ±2.5V
SUPPLY CURRENT (µA)
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
500
400
200
300
0
100
0±1±2±3±4±5±6
T
A
= -55°C
+25°C
+70°C+125°C
INPUTS GROUNDED
OUTPUT UNLOADED
-25°C
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE (V)
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
0 ±2 ±4 ±6 ±8
-55°C ≤ T
A
≤ +125°C
R
L
= 100KΩ
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
0±1±2±3±4±7±6±5
±6
±5
±4
±3
±2
±1
OUTPUT VOLTAGE SWING (V)
-55°C ≤ T
A
≤ +125°C
R
L
= 100KΩ
ADJUSTMENT IN INPUT OFFSET VOLTAGE
AS A FUNCTION OF CHANGE IN VE1 AND VE2
ADJUSTMENT IN INPUT OFFSET
VOLTAGE ∆V
OS
(mV)
0.50 0.75 1.00 1.25 1.50 1.75 2.00
-10
-8
-6
-4
-2
0
2
4
6
8
10
VE1
VE2
CHANGE IN VE1 AND VE2 (V)
ALD2721E/ALD2721 Advanced Linear Devices 8 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
LARGE - SIGNAL TRANSIENT
RESPONSE
2V/div
500mV/div 5µs/div
V
S
= ±1.0V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
LARGE - SIGNAL TRANSIENT
RESPONSE
5V/div
2V/div 5µs/div
V
S
= ±2.5V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
LOAD RESISTANCE (Ω)10M
10K 100K 1M
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
V
S
= ±2.5V
T
A
= 25°C
SMALL - SIGNAL TRANSIENT
RESPONSE
100mV/div
20mV/div 2µs/div
V
S
= ±2.5V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
-2500 -2000 -1500 -1000 -500 0500 1000 1500 2000 2500
TOTAL INPUT OFFSET VOLTAGE (µV)
100
80
60
40
20
0
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
EXAMPLE B:
V
OST
AFTER EPAD
PROGRAMMING
V
OST
TARGET = -750µV
EXAMPLE A:
V
OST
AFTER EPAD
PROGRAMMING
V
OST
TARGET = 0.0µV
V
OST
BEFORE EPAD
PROGRAMMING
PERCENTAGE OF UNITS (%)
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
COMMON MODE INPUT
VOLTAGE RANGE (V)
±7
±6
±5
±4
±3
±2
±1
00 ±1 ±2 ±3 ±4 ±5 ±6 ±7
T
A
= 25°C
ALD2721E/ALD2721 Advanced Linear Devices 9 of 13
0123456789 10
500
400
300
200
100
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE (µV)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
PSRR = 80 dB
EXAMPLE B:
V
OS
EPAD
PROGRAMMED
AT V
SUPPLY
= +8V
EXAMPLE A:
V
OS
EPAD PROGRAMMED
AT V
SUPPLY
= +5V
-5 -4 -3 -2 -1 012345
COMMON MODE VOLTAGE (V)
500
400
300
200
100
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
EXAMPLE A:
V
OS
EPAD PROGRAMMED
AT V
IN
= 0V
EXAMPLE B:
V
OS
EPAD
PROGRAMMED
AT V
IN
= -4.3V
EXAMPLE C:
V
OS
EPAD PROGRAMMED
AT V
IN
= +5V
V
SUPPLY
= ±5V
CMRR = 80dB
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
COMMON MODE VOLTAGE (V)
50
40
30
20
10
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
V
OS
EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
CMRR = 80dB
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
COMMON MODE VOLTAGE RANGE OF 0.5V
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
ALD2721E/ALD2721 Advanced Linear Devices 10 of 13
Total Input V
OS
after EPAD
Programming
+
Device input V
OS
PSRR equivalent V
OS
CMRR equivalent V
OS
T
A
equivalent V
OS
Noise equivalent V
OS
External Error equivalent V
OS
X
EXAMPLE A
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
+
X
EXAMPLE B
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
EXAMPLE C
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
EXAMPLE D
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET AFTER
EPAD PROGRAMMING
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
ALD2721E/ALD2721 Advanced Linear Devices 11 of 13
Millimeters Inches
Min Max Min MaxDim
A
A
1
b
C
D-14
E
e
H
L
S
1.75
0.25
0.45
0.25
8.75
4.05
6.30
0.937
8°
0.50
0.053
0.004
0.014
0.007
0.336
0.140
0.224
0.024
0°
0.010
0.069
0.010
0.018
0.010
0.345
0.160
0.248
0.037
8°
0.020
1.27 BSC 0.050 BSC
1.35
0.10
0.35
0.18
8.55
3.50
5.70
0.60
0°
0.25
ø
14 Pin Plastic SOIC Package
SOIC-14 PACKAGE DRAWING
E
D
e
A
A
1
b
S (45°)
L
C
H
S (45°)
ø
ALD2721E/ALD2721 Advanced Linear Devices 12 of 13
14 Pin Plastic DIP Package
PDIP-14 PACKAGE DRAWING
b
1
D
S
be
A
2
A
1
A
L
EE1
ce
1
ø
Millimeters Inches
Min Max Min MaxDim
A
A
1
A
2
b
b
1
c
D-14
E
E
1
e
e
1
L
S-14
ø
3.81
0.38
1.27
0.89
0.38
0.20
17.27
5.59
7.62
2.29
7.37
2.79
1.02
0°
5.08
1.27
2.03
1.65
0.51
0.30
19.30
7.11
8.26
2.79
7.87
3.81
2.03
15°
0.105
0.015
0.050
0.035
0.015
0.008
0.680
0.220
0.300
0.090
0.290
0.110
0.040
0°
0.200
0.050
0.080
0.065
0.020
0.012
0.760
0.280
0.325
0.110
0.310
0.150
0.080
15°
ALD2721E/ALD2721 Advanced Linear Devices 13 of 13
EE
1
C
e
1
ø
D
s
b
1
e
b
L
A
L
2
A
1
L
1
A
A1
b
b1
C
D-14
E
E1
e
e1
L
L1
L2
S
Ø
3.55
1.27
0.97
0.36
0.20
--
5.59
7.73
3.81
3.18
0.38
--
0°
5.08
2.16
1.65
0.58
0.38
19.94
7.87
8.26
5.08
--
1.78
2.49
15°
Millimeters Inches
Min Max Min MaxDim 0.140
0.050
0.038
0.014
0.008
--
0.220
0.290
0.150
0.125
0.015
--
0°
0.200
0.085
0.065
0.023
0.015
0.785
0.310
0.325
0.200
--
0.070
0.098
15°
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
14 Pin CERDIP Package
CERDIP-14 PACKAGE DRAWING