Features
•Single 3-V Supply Voltage
•High Power-added Efficient Po wer Amplifier (Pout Typically 23 dBm)
•Ramp-controlled Output Power
•Low-noise Preamplifier (NF Typically 2.1 dB)
•Biasing for External PIN Diode T/R Switch
•Current-saving Standby Mode
•Few External Components
•Packages:
– PSSO20
– QFN20 with Extended Performance
1. Description
The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier,
low-noise amplifier and T/R switch driver. It is especially designed for operation in
TDMA systems like Bluetooth® and WDCT.
Due to the ramp-control feature and a very low quiescent current, an external switch
transistor for VS is not required.
Figure 1-1. Block Diagram
PA
PA_IN V3_PA_OUT
RAMP V2_PA
V1_PA
LNA
LNA_OUT LNA_IN
TX/RX/
standby
Control
PU
RX_ON VS_LNA
SWITCH_OUT
R_SWITCH
TX
RX
Bluetooth/ISM
2.4-GHz
Front-End IC
T7024
4533H–BLURF–07/07
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4533H–BLURF–07/07
T7024
2. Pin Configuration
Figure 2-1. Pinning PSSO20 Figure 2-2. Pinning QFN20
1
2
3
4
5
6
7
8
10
9
19
18
17
16
14
15
13
12
11
20
LNA_IN
VS_LNA
GND
V3_PA_OUT
V3_PA_OUT
V3_PA_OUT
SWITCH_OUT
GND
GND
PA_IN
V1_PA
GND
V2_PA
V2_PA
RX_ON
LNA_OUT
GND RAMP
R_SWITCH PU
T7024
1
2
3
4
5
15
14
13
12
11
10 6789
16 2019
18
17
LNA_OUT
RX_ON
PU
R_SWITCH
SWITCH_OUT
GND
VS_LNA
GND
LNA_IN
GND
V3_PA_OUT
V3_PA_OUT
V3_PA_OUT
GND
RAMP
V2_PA
V2_PA
GND
V1_PA
PA_IN
T7024
Table 2-1. Pin Description
Pins PSSO20 Pins QFN20 Symbol Function
1 4 R_SWITCH Resistor to GND sets the PIN diode current
2 5 SWITCH_OUT Switched current output for PIN diode
3 6 GND Ground
4 7 LNA_IN Low-noise amplifier input
5 9 VS_LNA Supply voltage input for low-noise amplifier
6 8 GND Ground
7 11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
8 12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
9 13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output
10 10 GND Ground
11 15 RAMP Power ramping control input
12 16 V2_PA Inductor to power supply for power amplifier
13 17 V2_PA Inductor to power supply for power amplifier
14 14 GND Ground
15 19 V1_PA Supply voltage for power amplifier
16 20 PA_IN Power amplifier input
17 18 GND Ground
18 1 LNA_OUT Low-noise amplifier output
19 2 RX_ON RX active high
20 3 PU Power-up active high
Slug Slug GND Ground
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4533H–BLURF–07/07
T7024
Electrostatic sensitive device.
Observe precautions for handling.
5. Handling
Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test require-
ment (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test
requirement (MM) in accordance to EIA/JESD22-A115A.
3. Absolute Maxim um Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Supply voltage
Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT VS6V
Junction temperature Tj150 °C
Storage temperature Tstg –40 to +125 °C
RF input power LNA PinLNA 5dBm
RF input power PA PinPA 10 dBm
4. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient PSSOP20, slug soldered on PCB RthJA 19 K/W
Junction ambient QFN20, slug soldered on PCB RthJA 27 K/W
6. Operating Range
All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT.
The table represents the sum of all supply currents depending on the TX/RX mode.
Parameters Symbol Min. Typ. Max. Unit
Supply voltage
Pins V1_PA, V2_PA and V3_PA_OUT VS2.7 3.0 4.6 V
Supply voltage, pin VS_LNA VS2.7 3.0 5.5 V
Supply current TX, PSSO20
QFN20
Supply current RX
IS
IS
IS
190
165
8
mA
mA
mA
Standby current, PU = 0 IS_standby 10 µA
Ambient temperature Tamb –25 +25 +85 °C
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4533H–BLURF–07/07
T7024
7. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Power Amplifier(1)
Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT VS2.7 3.0 4.6 V
Supply current
TX, PSSO20
TX, QFN20
IS_TX
IS_TX
190
165
mA
mA
RX (PA off), VRAMP ≤ 0.1V IS_RX 10 µA
Standby current Standby IS_standby 10 µA
Frequency range TX f 2.4 2.5 GHz
Gain-control range TX ∆Gp 60 42 dB
Power gain maximum TX, pin PA_IN to V3_PA_OUT Gp 28 30 33 dB
Power gain minimum TX, pin PA_IN to V3_PA_OUT Gp –40 –17 dB
Ramping voltage maximum TX, power gain (maximum)
Pin RAMP VRAMP max 1.7 1.75 1.83 V
Ramping voltage minimum TX, power gain (minimum)
Pin RAMP VRAMP min 0.1 V
Ramping current maximum TX, VRAMP = 1.75V, pin RAMP IRAMP max 0.5 mA
Power-added efficiency TX, PSSO20
TX, QFN20
PAE
PAE
30
35
35
40
%
%
Saturated output power TX, input power = 0 dBm referred to
pins V3_PA_OUT Psat 22 23 24 dBm
Input matching(2) TX, pin PA_IN Load
VSWR < 1.5:1
Output matching(2) TX, pins V3_PA_OUT Load
VSWR < 1.5:1
Harmonics at Psat = 23 dBm TX, pins V3_PA_OUT 2 fo –30 dBc
TX, pins V3_PA_OUT 3 fo –30 dBc
T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND)
Switch-out current output
Standby, pin SWITCH_OUT IS_O_standby 1µA
RX IS_O_RX 1µA
TX at 100ΩIS_O_100 1.7 mA
TX at 1.2 kΩIS_O_1k2 7mA
TX at 33 kΩIS_O_33k 17 mA
TX at ∞IS_O_R 19 mA
Low-noise Amplifier(3)
Supply voltage All, pin VS_LNA VS2.7 3.0 5.5 V
Supply current RX IS89mA
Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch
and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω.
2. With external matching network, load impedance 50Ω.
3. Low-noise amplifier shall be unconditionally stable.
4. With external matching components.
5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below
1.4V the T/R switch driver switches to TX mode.
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4533H–BLURF–07/07
T7024
Supply current
(LNA and control logic)
TX (control logic active)
Pin VS_LNA IS0.5 mA
Standby current Standby, pin VS_LNA IS_standby 110µA
Frequency range RX f 2.4 2.5 GHz
Power gain(5) RX, pin LNA_IN to LNA_OUT Gp 15 16 19 dB
Noise figure RX, PSSO20
RX, QFN20
NF
NF
2.5
2.1
2.8
2.3
dB
dB
Gain compression RX, referred to pin LNA_OUT O1dB –9 –7 –6 dBm
3rd-order input interception point RX IIP3 –16 –14 –13 dBm
Input matching(4) RX, pin LNA_IN VSWRin 2:1
Output matching(4) RX, pin LNA_OUT VSWRout 2:1
Logic Input Levels (RX_ON, PU)(5)
High input level = ‘1’ pins RX_ON and PU ViH 2.4 VS, LNA V
Low input level = ‘0’ ViL 00.5V
High input current = ‘1’ ViH = 2.4V IiH 40 60 µA
Low input current = ‘0’ IiL 0.2 µA
7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C
Parameters Test Conditions Symbol Min. Typ. Max. Unit
Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch
and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω.
2. With external matching network, load impedance 50Ω.
3. Low-noise amplifier shall be unconditionally stable.
4. With external matching components.
5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below
1.4V the T/R switch driver switches to TX mode.
8. Control Logic PA and LNA/Antenna Switch Driver
PU RX_ON Ramp(1) PA LNA Antenna Switch Driver Operation Mode
0 0 0 off off off standby
0 0 1 on off off (2)
0 1 0 off on off (3)
011onon off (4)
1 0 0 off off on (4)
101onoff on TX
1 1 0 off on off RX
111onon off (5)
Notes: 1. “0” = VRAMP ≤ 0.1V, “1” = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-6
on page 7 and Figure 9-10 on page 9
2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation
3. Only for special operation, e.g. no switch driver operation
4. Only for special operation
5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time
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4533H–BLURF–07/07
T7024
9. Typical Operating Characteristics
Figure 9-1. LNA (PSSO20): Gain and Noise Figure versus Frequency
Figure 9-2. LNA (N20): Gain and Noise Figure versus Frequency
Figure 9-3. LNA: NF and Gain versus Temperature
0
5
10
15
20
2000 2200 2400 2600 2800 3000
Frequency (MHz)
Gain (dB)
0
1
2
3
4
5
6
7
8
NF (dB)
NF
Gain
0
5
10
15
20
25
2000 2200 2400 2600 2800 3000
Frequency (MHz)
Gain (dB)
0
1
2
3
4
5
NF (dB)
NF
Gain
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
-40 -20 0 20 40 60 80
Temperature (°C)
Relative gain,
relative NF (dB)
NF
Gain
V
S
= 3 V
7
4533H–BLURF–07/07
T7024
Figure 9-4. LNA: Typical Switch-out Current versus Rswitch
Figure 9-5. PA (PSSO20): Output Power and PAE versus Supply
Figure 9-6. PA (PSSO20): Output Power and PAE versus Ramp Voltage
0
4
8
12
16
20
1 10 100 1000 10000 100000 1000000 10000000
R
switch
(Ω)
I
S_O
(mA)
0
10
20
30
40
50
2.7 3.1 3.5 3.9 4.3 4.7
Supply Voltage (V)
Pout (dBm ), PAE (%)
100
130
160
190
220
250
I
S_TX
(mA)
PAE
Pout
I_S_TX
f = 2.4 GHz
V
ramp
= 1.75 V
P
inPA
= 0 dBm
-50
-30
-10
10
30
50
1.2 1.4 1.6 1.8 2.0
V
ramp
(V)
Pout (dBm), PAE (%)
0
50
100
150
200
250
I
S_TX
(mA)
PAE
Pout
I_S_TX f = 2.4 GHz
V
S
= 3 V
P
inPA
= 0 dBm
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4533H–BLURF–07/07
T7024
Figure 9-7. PA (PSSO20): Output Power and PAE versus Input Power
Figure 9-8. PA (PSSO20): Output Power and PAE versus Frequency
Figure 9-9. PA (QFN20): Output Power and PAE versus Supply Voltage
-10
0
10
20
30
40
-40 -30 -20 -10 0 10
Input Power (dBm)
Pout (dBm ), PAE (%), Gp (d B)
0
50
100
150
200
250
PAE
Pout
I_S_TX
VS = 3 V
f = 2.4 GHz
Vramp = 1.75 V
PinPA = 0 dBm
Gain
IS_TX (mA)
0
10
20
30
40
50
2400 2420 2440 2460 2480 2500
Frequency (MHz)
Pout (dBm), P AE (%)
0
50
100
150
200
250
I
S_TX
(mA)
PAE
Pout
I_S_TX
V
S
= 3 V
V
ramp
= 1.7 V
P
inPA
= 0 dBm
0
10
20
30
40
50
2.7 3.1 3.5 3.9 4.3 4.7
Supply Voltage (V)
Pout (dBm), PAE (%)
100
130
160
190
220
250
I
S_TX
(mA)
PAE
Pout
I_S_TX
f = 2.4 GHz
V
ramp
= 1.8 V
P
inPA
= 0 dBm
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4533H–BLURF–07/07
T7024
Figure 9-10. PA (QFN20) Output Power and PAE versus Ramp Voltage
Figure 9-11. PA (QFN20): Output Power and PAE versus Input Power
Figure 9-12. PA (QFN20): Output Power and PAE versus Frequency
-50
-30
-10
10
30
50
1.2 1.4 1.6 1.8 2.0
V
ramp
(V)
Pout (dBm ), PAE (%)
0
50
100
150
200
250
I
S_TX
(mA)
PAE
Pout
I_S_TX
f = 2.4 GHz
VS = 3 V
PinPA = 0 dBm
-10
0
10
20
30
40
50
-40 -30 -20 -10 0 10
Input Power (dBm)
Pout (dBm ), PAE (%), Gp (dB)
0
50
100
150
200
250
300
I
S_TX
(mA)
PAE
Pout
I_S_TX
V
S
= 3 V
f = 2.4 GHz
V
ramp
= 1.8 V
P
inPA
= 0 dBm
Gain
0
10
20
30
40
50
2400 2420 2440 2460 2480 2500
Frequency (MHz)
Pout (dBm), PAE (%)
0
50
100
150
200
250
I
S_TX
(mA)
PAE
Pout
I_S_TX
V
S
= 3 V
V
ramp
= 1.8 V
P
inPA
= 0 dBm
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4533H–BLURF–07/07
T7024
Figure 9-13. LNA: Supply Current versus Temperature
Figure 9-14. PA (PSSO20): Supply Current versus Iramp and Temperature
Figure 9-15. PA (PSSO20, QFN20): Pout versus VRAMP and Temperature
6.0
6.2
6.4
6.6
6.8
7.0
7.2
7.4
7.6
7.8
8.0
-40 -20 0 20 40 60 80
Temperature (°C)
Supply current (mA)
0
20
40
60
80
100
120
140
160
180
200
0.1 1.0 10.0 100.0 1000.0
Iramp (µA)
Supply current (mA)
-40°C
80°C
40°C
0°C
-20
-10
0
10
20
30
1.0 1.2 1.4 1.6 1.8
V
ramp
(V)
Pout (dBm)
-40°C
5
80
25
-15
f = 2.4 GHz
V
S
= 3 V
P
in
= 0 dBm
11
4533H–BLURF–07/07
T7024
Figure 9-16. (PSSO20, QFN20): LNA Gain (dB) versus RX_ON (V)
10. Input/Output Circuits
Figure 10-1. Input Circuit PA_IN/V1_PA
Figure 10-2. Input Circuit RAMP/V1_PA
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
1.0 1.5 2.0 2.5 3.0
RX_ON (V)
Gain (dB)
VS = 3 V
PA_IN
V1_PA
GND
V1_PA
RAMP
12
4533H–BLURF–07/07
T7024
Figure 10-3. Input Circuit V2_PA
Figure 10-4. Input/Output Circuit V3_PA_OUT
Figure 10-5. Input Circuit SWITCH_OUT/R_SWITCH
V2_PA
GND
V3_PA_OUT
GND
V1_PA
GND
SWITCH_OUT
R_SWITCH
13
4533H–BLURF–07/07
T7024
Figure 10-6. Input Circuit LNA_IN/VS_LNA
Figure 10-7. Input Circuit PU/RX_ON
Figure 10-8. Output Circuit LNA_OUT
VS_LNA
GND
LNA_IN
VS_LNA
LNA_IN /
PU
VS_LNA
GND
LNA_OUT
14
4533H–BLURF–07/07
T7024
Figure 10-9. Typical Application T7024 (PSSO20 Package)
Blocking capacitors
depending on application
Pin-diode replaced
by LED on
application-board
R1 is selected
with DIL-switch
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PU
RX ON
3.9p
3.9nH
LNA OUT PA IN
V1_PA
V2_PA
3p3
PA ramp
15nH
VS_LNA
1.8p
LNA IN
Switch Out
R1
5.6nH
V3_PA
0p8
PA OUT
harm. termination
T7024
1p5
15
4533H–BLURF–07/07
T7024
Figure 10-10. Typical Application T7024 (QFN20 Package)
20 19 18 17 16
6 7 8 9 10
1
2
3
4
5
15
14
13
12
11
T7024
3p3
V2_PA
1p2.2p
RX ON
PU
Switch Out
1.8p
LNA IN
VS_LNA
18nH
V3_PA
0p8
2p2
PA OUT
PA ramp
R1
Var
V1_PA
PA IN
LNA OUT
harm. termination
blocking capacitors
depending on application
Pin-diode replaced by
LED on application-board
R1 is selected
with DIL-switch
11. Ordering Information
Extended Type Number Package Remarks MOQ
T7024-TRSY PSSO20 Tube, Pb-free 830 pcs.
T7024-TRQY PSSO20 Taped and reeled, Pb-free 4000 pcs.
T7024-PGPM QFN20 Taped and reeled
Pb free, halogen free 1500 pcs.
T7024-PGQM QFN20 Taped and reeled
Pb free, halogen free 6000 pcs.
Demoboard-T7024-PGM QFN20 Evaluation board QFN 1
Demoboard-T7024-TR PSSO20 Evaluation board PSSO 1
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4533H–BLURF–07/07
T7024
12. Packa ge Information
specifications
according to DIN
technical drawings
Package: PSSO20
Dimensions in mm
0.18 max.
1.3
2.15
0.575
20 11
110
∅ 0.4 A
0.15
0.12
(20x)
CA
A
B
B
6.7 max.
6.75 max.
2.6
0.25
0.65
5.85
0.05+0.09
6.45±0.15
5.4±0.2
4.4±0.1
Issue: 1; 05.06.01
Drawing-No.: 6.543-5078.01-4
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4533H–BLURF–07/07
T7024
13. Package Information PB Free
20
5
1
610
2016
11
15
5
1
5
3.1
2.6
0.65 nom.
specifications
according to DIN
technical drawings
Issue: 1; 19.12.02
Drawing-No.: 6.543-5094.01-4
Package: QFN 20 - 5 x 5
Exposed pad 3.1 x 3.1
Dimensions in mm
Not indicated tolerances ± 0.05
0.28
0.6
0.9±0.1
0.05-0.05
+0
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4533H–BLURF–07/07
T7024
14. Recommended PCB Land Pattern
Figure 14-1. Recommended PCB Land Pattern
15. Revision History
Table 14-1. Recommended PCB Land Pattern Signs
Sign Description Size
A Distance of vias 1.6 mm
B Size of slug pattern 3.1 mm
C Distance slug to pins 0.33 mm
D Diameter of vias 1 mm
E Width of pin pattern 0.3 mm
F Distance of pin pattern 0.33 mm
A
C
E
F
D
B
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4533H-BLURF-07/07
• Put datasheet in a new template
• Page 1: Block diagram changed
• Page 13: Figure 10-8 changed
4533H–BLURF–07/07
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