MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
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Soft-Start
The soft-start feature effectively limits the inrush current
during startup by linearly ramping up the step-up con-
verter’s peak switch current limit. The soft-start period
terminates when either the output voltage reaches reg-
ulation or the full current limit has been reached. By
default, the current limit is controlled by an internal
timer that allows the current limit to rise from 0 to the full
current limit in approximately 10ms. If an adjustable
soft-start period is desired, an external capacitor (CSS)
greater than 200pF can be connected between SS and
GND. In this case, CSS is charged with a 5μA current
source such that the full current limit is reached until the
voltage across CSS reaches 1.235V.
Fault Protection
The MAX17094 monitors AVDD for an overvoltage condi-
tion. If the AVDD voltage is above 14.1V (min), the
MAX17094 disables the gate driver of the step-up regula-
tor and prevents the internal MOSFET from switching. The
AVDD overvoltage condition does not set the fault latch.
Operational Amplifier
The MAX17094 has an operational amplifier that is typi-
cally used to drive the LCD backplane (VCOM). The
operational amplifier features ±200mA output short-circuit
current, 45V/μs slew rate, and 20MHz bandwidth. While
the op amp is a rail-to-rail input and output design, its
accuracy is significantly degraded for input voltages with-
in 1V of its supply rails (AVDD and BGND).
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately ±200mA if the output is directly shorted
to AVDD or to AGND. If the short-circuit condition per-
sists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-
shutdown threshold, an internal thermal sensor immedi-
ately sets the thermal-fault latch, shutting off the main
step-up regulator, the linear regulator, the switch-con-
trol block, and the operational amplifier. Those portions
of the device remain inactive until the input voltage is
cycled off, then on, again.
Driving Pure Capacitive Loads
The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction-
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation. As the operational amplifier’s capaci-
tive load increases, the amplifier’s bandwidth decreas-
es and gain peaking increases. A 5Ωto 50Ωsmall
resistor placed between VCOM and the capacitive load
reduces peaking, but also reduces the gain. An alterna-
tive method of reducing peaking is to place a series RC
network (snubber) in parallel with the capacitive load.
The RC network does not continuously load the output
or reduce the gain. Typical values of the resistor are
between 100Ωand 200Ωand the typical value of the
capacitor is 10pF.
High-Voltage Level-Shifting Scan Driver
The MAX17094 includes seven logic-level to high-volt-
age level-shifting buffers, which can buffer seven logic
inputs (A2–A8) and shift them to a desired level (Y2–Y8)
to drive TFT-LCD row logic. The driver outputs, Y2–Y8,
swing between their power-supply rails, according to
the input-logic level on A2–A8. The driver output is
GOFF when its respective input is logic low, and GON_
when its respective input is logic high. These seven dri-
ver channels are grouped for different high-level sup-
plies. A2–A6 are supplied from GON1, and A7 and A8
are supplied from GON2. GON1 and GON2 can be tied
together to make A2–A8 use identical supplies. The
high-voltage, level-shifting scan drivers are designed to
drive the TFT panels with row drivers integrated on the
panel glass. Its seven outputs swing from +30V (max)
to -10V (min) and can swiftly drive capacitive loads.
The typical propagation delays are 80ns, with fast 16ns
rise-and-fall times. The buffers can operate at frequen-
cies up to 50kHz. A YDCHG is the output of the eight-
level shifting buffer. It is driven by the input-voltage-
detector circuit.
Input-Voltage Detector
The input-voltage detector is used to drive the YDCHG
level-shifter buffer to VGON1 during a power-down once
the input voltage has fallen below a user-defined thresh-
old. The input voltage is sensed at the SENSE pin through
a voltage-divider. Once the falling edge of VSENSE falls
below 1.235V (typ), YDCHG is driven to VGON1.
Low-Dropout Linear Regulator (LDO)
The MAX17094 has an integrated 1.2Ω (max) pass
element and can provide at least 250mA. The output
voltage is accurate within ±2%.