General Description
The MAX17094 includes a high-performance step-up
regulator, a 250mA low-dropout (LDO) linear regulator, a
high-speed operational amplifier, a digitally adjustable
VCOM calibration device with nonvolatile memory and
I2C interface, and seven integrated high-voltage level
shifters. The device is optimized for thin-film transistor
(TFT) liquid-crystal display (LCD) applications.
The step-up DC-DC converter is a current-mode regu-
lator that provides the regulated supply voltage for
panel source driver ICs. The current-mode architecture
provides fast-transient responses to pulsed loads typi-
cal of source driver loads. The high switching frequen-
cy, which is programmable to any frequency between
450kHz to 1.2MHz with a single resistor, allows the use
of ultra-small inductors and ceramic capacitors. The
step-up regulator’s soft-start time is controlled by an
internal 10ms digital timer that requires no external
components; or if desired, the soft-start time can be
adjusted by adding a single external capacitor.
The low-voltage LDO linear regulator can provide at
least 250mA. The output voltage is accurate within ±2%.
The high-voltage, level-shifting scan driver is designed
to work with panels that incorporate row drivers on the
panel glass. Its seven outputs swing from +30V to -10V
and can swiftly drive capacitive loads.
The high-performance op amp is designed to drive the
LCD backplane and features 20MHz bandwidth, 45V/µs
slew rate, and 150mA output currents.
The programmable VCOM calibrator is externally
attached to the VCOM amplifier’s resistive voltage-
divider and sinks a programmable current to adjust the
VCOM voltage level. An internal 7-bit digital-to-analog
converter (DAC) controls the sink current. The DAC is
ratiometric relative to AVDD and is guaranteed monoto-
nic over all operating conditions. The calibrator
includes a nonvolatile memory device (IVR) to store the
desired VCOM voltage level. The 2-wire I2C interface
simplifies production equipment.
The MAX17094 is available in a 48-pin, 6mm x 6mm
TQFN package with a maximum thickness of 0.8mm for
thin LCD panels.
Applications
Notebook Computer Displays
Features
o1.8V to 5.5V IN Supply Voltage Range
o450kHz to 1.2MHz Adjustable Frequency Current-
Mode Step-Up Regulator
Fast-Transient Response
Integrated 14V, 2.5A, 150mΩMOSFET
High Efficiency (> 85%)
oLow-Dropout Linear Regulator
High-Accuracy Output Voltage (2.0%)
Internal Digital Soft-Start
oHigh-Performance Operational Amplifier
200mA Output Short-Circuit Current
45V/µs Slew Rate
20MHz, -3dB Bandwidth
Rail-to-Rail Inputs and Outputs
oHigh-Voltage Drivers
+30V to -10V Outputs
oI2C Programmable VCOM Calibrator
7-Bit Adjustable Current-Sink Output
Nonvolatile IVR Memory
oThermal-Overload Protection
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
________________________________________________________________
Maxim Integrated Products
1
TOP VIEW
MAX17094
TQFN
13
14
15
16
17
18
19
20
21
22
23
24
A4
A3
A2
SS
YDCHG
Y2
Y3
Y4
Y5
Y6
Y7
Y8
48
47
46
45
44
43
42
41
40
39
38
37
12345
*EP
*EP = EXPOSED PAD.
678910
11 12
VL
AGND
COMP
SENSE
IN
EN
FREQ
LX
LX
PGND
PGND
FB
A5
A6
A7
A8
SDA
SCL
ADDR1
ADDR0
GND
FBL
LOUT
LIN
36 35 34 33 32 31 30 29 28 27 26 25
GOFF
GND
GON2
GON1
GND
SET
BGND
VCOM
NEG
POS
OUT
AVDD
Pin Configuration
Ordering Information
19-4348; Rev 0; 10/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX17094ETM+ -40°C to +85°C 48 TQFN-EP*
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V, TA= 0°C to +85°C. Typical val-
ues are at TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, LIN, LOUT, EN, VL, A2–A8,
SCL, SDA, ADDR0, ADDR1.. ............................-0.3V to +7.5V
COMP, FB, SENSE, SS to AGND ............…-0.3V to (VVL + 0.3V)
FBL to AGND.............................................-0.3V to (VLIN + 0.3V)
FREQ, SET to GND .....................................-0.3V to (VVL + 0.3V)
LX to PGND ............................................................-0.3V to +16V
AVDD to BGND ......................................................-0.3V to +16V
POS, NEG, OUT, VCOM to BGND ......-0.3V to (VAVDD to +0.3V)
POS to NEG.................................................................-6V to +6V
GND, PGND, BGND to AGND...............................-0.3V to +0.3V
GON1, GON2 to GND ............................................-0.3V to +35V
GOFF to GND ........................................................-14V to + 0.3V
Y2–Y6, YDCHG to GND ..........(VGOFF - 0.3V) to (VGON1 + 0.3V)
Y7, Y8 to GND .........................(VGOFF - 0.3V) to (VGON2 + 0.3V)
LX, PGND RMS Current .......................................................2.4A
Y1–Y7, YDCHG RMS Current..............................................33mA
GON1 RMS Current ...........................................................46mA
GON2 RMS Current ...........................................................83mA
GOFF RMS Current ..........................................................115mA
Continuous Power Dissipation (TA= +70°C)
48-Pin, 6mm x 6mm TQFN
(derate 20mW/°C above +70°C).. .............................2963mW
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
IN Input-Voltage Range 1.8 5.5 V
IN Shutdown Current EN = 0 30 100 μA
IN Quiescent VIN = 3V, VFB = 1.5V, not switching, VL > 2.3V 100 μA
IN Undervoltage Lockout VIN rising, typical hysteresis 200mV 1.30 1.75 V
Thermal Shutdown Rising edge, typical hysteresis 15°C 160 °C
BOOTSTRAP LINEAR REGULATOR (VL)
VL Output Voltage 3.8 4.0 4.2 V
VL Maximum Output Current VL = 3.7V 10 mA
LINEAR REGULATOR
LIN Input-Voltage Range VLOUT < VLIN 1.8 5.5 V
LIN Quiescent Current No load 2 mA
Dropout Voltage ILOUT = 250mA, VLIN - VLOUT 0.3 V
FBL Regulation Voltage ILOUT = 100mA 605 618 631 mV
FBL Input Bias Current VFBL = 0.618V, TA = +25°C -50 +50 nA
LOUT Maximum Output Current VFBL = 0.5V 250 mA
LOUT Load Regulation VLIN =5V, 5mA < I
OUT < 250mA, not in dropout 1 %
Soft-Start Period 7-bit voltage ramp 3 ms
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
STEP-UP DC-DC CONVERTER
RFREQ = 80k 1000 1200 1500
RFREQ = 30k 382 450 518
Switching Frequency f (MHz) = 0.015 x RFREQ (k)
RFREQ = unconnected 570 600 690
kHz
Oscillator Maximum Duty Cycle 88 92 96 %
FB Regulation Voltage 1.216 1.235 1.254 V
FB Load Regulation 0 < IMAIN < 200mA, transient only -1 %
FB Line Regulation VIN = 1.8V to 5.5V -0.15 -0.08 +0.15 %/V
FB Input Bias Current VFB = 1.3V 25 75 150 nA
FB Transconductance I = 5μA at COMP 75 160 280 μS
FB Voltage Gain FB to COMP 2400 V/V
LX On-Resistance ILX = 200mA 150 250 m
LX Leakage Current VLX = 16V 10 20 μA
LX Current Limit Duty cycle = 65% 2 2.5 3 A
Current-Sense Transresistance 0.15 0.3 0.45 V/A
Soft-Start Period CSS < 200pF 10 ms
SS Output Current 3.5 5 6.5 μA
HIGH-VOLTAGE DRIVER BLOCK
GON1, GON2 Input Voltage 12 30 V
GOFF Input Voltage -10 -4 V
GOFF Supply Current A2A8 = AGND, no load 120 250 μA
GON1, GON2 Supply Current A2A8 = AGND, no load 265 430 μA
Output-Voltage Low
(Y2–Y8, YDCHG) IOUT = 10mA VGOFF
+ 0.3
VGOFF
+ 1 V
Output-Voltage High
(Y2–Y8, YDCHG) IOUT = 10mA VGON_
- 1
VGON_
- 0.3 V
Rise Time (Y2–Y8) CLOAD = 100pF, VGON1 =V
GON2 = 30V, VGOFF = -10V
(Note 1) 16 32 ns
Fall Time (Y2–Y8) CLOAD = 100pF, VGON1 = VGON2 = 30V, VGOFF = -10V
(Note 1) 16 32 ns
Propagation Delay High-to-Low
Transition (Y2–Y8)
CLOAD = 100pF
(Note 1) 80 125 ns
Propagation Delay Low-to-High
Transition (Y2–Y8)
CLOAD = 100pF
(Note 1) 80 125 ns
Operating Frequency CLOAD = 100pF 50 kHz
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V, TA= 0°C to +85°C. Typical val-
ues are at TA= +25°C, unless otherwise noted.)
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V, TA= 0°C to +85°C. Typical values
are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
OPERATIONAL AMPLIFIER
AVDD Supply Voltage Range 6 14 V
AVDD Overvoltage Threshold Rising edge, 400mV hysteresis 14.1 15 15.9 V
AVDD Input Supply Current FB = 1.1V, buffer configuration, VPOS = VAVDD/2, no load 5 10 mA
Input Offset Voltage VNEG, VPOS = VAVDD/2, TA = +25°C -12 +12 mV
Input Bias Current VNEG, VPOS = VAVDD/2, TA = +25°C -50 +50 nA
Input Common-Mode
Voltage Range 0 VAVDD V
Input Common-Mode
Rejection Ratio 80 dB
Output-Voltage Swing High IOUT = 50mA VAVDD -
300 mV
Output-Voltage Swing Low IOUT = -50mA 300 mV
Large-Signal Voltage Gain VOUT = 1V to VAVDD - 1V 80 dB
Slew Rate 45 V/μs
-3dB Bandwidth 20 MHz
Short to VAVDD - 3V sourcing 200
Short-Circuit Current Short to 3V sinking 200 mA
CONTROL INPUTS
Logic-Input Voltage Low
(A2–A8, EN) 1.8V < VIN < 5.5V 0.8 V
Logic-Input Voltage High
(A2–A8, EN) 1.8V < VIN < 5.5V 1.6 V
Logic-Input Bias Current (A2A8) 0 < AX < VIN, TA = +25°C -1 +1 μA
Logic-Input Bias Current (EN) 0 < VEN < VIN, TA = +25°C -1 +1 μA
INPUT-VOLTAGE DETECTOR
SENSE Voltage Range VVL V
SENSE Bias Current 0 < VSENSE < VL, TA = +25°C -1 +1 μA
SENSE Threshold Voltage Falling edge 1.200 1.235 1.270 V
PROGRAMMABLE VCOM CALIBRATOR
GON2 Calibrating Threshold Rising edge, 230mV hysteresis 7 8.5 10.5 V
GON2 Input-Voltage Range 11 30 V
SET Voltage Resolution 7 Bits
SET Differential Nonlinearity -1 +1 LSB
SET Zero-Scale Error -1 +1 +3 LSB
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V, TA= 0°C to +85°C. Typical values
are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SET Full-Scale Error -4 +5 LSB
SET Current 120 μA
To GND, VAVDD = 14V 8.5 170
SET External Resistance To GND, VAVDD = 6V 2.5 50
k
VSET/VAVDD Voltage Ratio DAC zero scale 0.05 V/V
POS Settling Time To ±0.5 LSB error band 20 μs
Memory Write Cycles 30 Times
Memory Write Time RFREQ = unconnected 150 ms
I2C INTERFACE
Logic-Input Low Voltage (VIL ) SDA, SCL 0.3 x
VIN V
Logic-Input Low Voltage ADDR0_ADDR1 0.2 x
VIN V
Logic-Input High Voltage (VIH ) SDA, SCL, ADDR0, ADDR1 0.7 x
VIN V
SDA Output Low Voltage ISDA = -3mA sink 0 0.4 V
Logic-Input Current SDA, SCL, ADDR0, ADDR1, TA = +25°C -1 +1 μA
SDA and SCL Input Capacitance (Note 1) 5 10 pF
SCL Frequency (fSCL) DC 400 kHz
SCL High Time (tHIGH) 600 ns
SCL Low Time (tLOW) 1300 ns
SDA and SCL Rise Time and
Fall (tR, tF)Cb = total capacitance of bus line in pF (Note 1) 20 + 0.1
x Cb 300 ns
START Condition Hold Time
(tHD:STA )10% of SDA to 90% of SCL 600 ns
START Condition Setup Time
(tSU:STA ) 600 ns
Data Input Hold Time (tHD:DAT) 50 ns
Data Input Setup Time (tSU:DAT) 100 ns
STOP Condition Setup Time
(tSU:STO) 600 ns
Bus Free Time (tBUF) 1300 ns
SDA Capacitive Loading (Cb) (Note 2) 400 pF
Input Filter Spike Suppression SDA, SCL, not tested 50 ns
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V. TA= -40°C to +85°C, unless oth-
erwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
IN Input-Voltage Range 1.8 5.5 V
IN Shutdown Current EN = 0, VL > 2.4V 100 μA
IN Quiescent VIN = 3V, VFB = 1.5V, not switching 100 μA
IN Undervoltage Lockout VIN rising 1.75 V
BOOTSTRAP LINEAR REGULATOR (VL)
VL Output Voltage 3.8 4.2 V
VL Maximum Output Current VL = 3.7V 10 mA
LINEAR REGULATOR
LIN Input-Voltage Range VLOUT < VLIN 1.8 5.5 V
LIN Quiescent Current No load 2 mA
Dropout Voltage ILOUT = 250mA 0.3 V
FBL Regulation Voltage ILOUT = 100mA 605 631 mV
LOUT Maximum Output Current VFBL = 0.5V 250 mA
LOUT Load Regulation VLIN = 5V, 5mA < IOUT < 250mA, not in dropout 1 %
STEP-UP DC-DC CONVERTER
Output-Voltage Range 6 14 V
RFREQ = 80k 1000 1500
RFREQ = 30k 382 518
Switching Frequency f (MHz) = 0.015 x RFREQ (k)
RFREQ = unconnected 510 690
kHz
Oscillator Maximum Duty Cycle 88 96 %
FB Regulation Voltage 1.216 1.254 V
LX On-Resistance ILX = 200mA 250 m
LX Leakage Current VLX = 16V 20 μA
LX Current Limit Duty cycle = 65% 2 3 A
Current-Sense Transresistance 0.15 0.45 V/A
SS Output Current 3.5 6.5 μA
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V. TA= -40°C to +85°C, unless oth-
erwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
HIGH-VOLTAGE DRIVER BLOCK
GON1, GON2 Input Voltage 12 30 V
GOFF Input Voltage -10 -4 V
GOFF Supply Current A2A8 = AGND, no load 250 μA
GON1, GON2 Supply Current A2A8 = AGND, no load 430 μA
Output-Voltage Low (Y2–Y8) IOUT = 10mA VGOFF
+ 1 V
Output-Voltage High (Y2–Y8) IOUT = 10mA VGON_
- 1 V
Rise Time (Y2–Y8) CLOAD = 100pF, VGON1 =V
GON2 =30V, V
GOFF = -10V
(Note 1) 32 ns
Fall Time (Y2–Y8) CLOAD = 100pF, VGON1 = VGON2 = 30V, VGOFF = -10V
(Note 1) 32 ns
Propagation Delay High-to-Low
Transition (Y2–Y8)
CLOAD = 100pF
(Note 1) 125 ns
Propagation Delay Low-to-High
Transition (Y2–Y8)
CLOAD = 100pF
(Note 1) 125 ns
Operating Frequency CLOAD = 100pF 50 kHz
OPERATIONAL AMPLIFIER
AVDD Supply Voltage Range 6 14 V
AVDD Overvoltage Threshold Rising edge, 400mV hysteresis 14.1 15.9 V
AVDD Input Supply Current FB = 1.1V, buffer configuration, VPOS = VAVDD/2, no load 10 mA
Input Common-Mode
Voltage Range 0 VAVDD V
Output-Voltage Swing High IOUT = 50mA VAVDD -
300 mV
Output-Voltage Swing Low IOUT = -50mA 300 mV
Short to VAVDD - 3V sourcing 200
Short-Circuit Current Short to 3V sinking 200 mA
CONTROL INPUTS
Logic-Input Voltage Low
(A2–A8, EN) 1.8V < VIN < 5.5V 0.8 V
Logic-Input Voltage High
(A2–A8, EN) 1.8V < VIN < 5.5V 1.6 V
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V. TA= -40°C to +85°C, unless oth-
erwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT-VOLTAGE DETECTOR
SENSE Voltage Range VVL V
SENSE Threshold Voltage Falling edge, 10mV (typ) hysteresis 1.200 1.270 V
PROGRAMMABLE VCOM CALIBRATOR
GON2 Calibrator Threshold Rising edge, 230mV hysteresis 7 8.5 10.5 V
GON1 Voltage Threshold to
Enable Program Rising edge, 230mV hysteresis 7 10.5 V
GON2 Input-Voltage Range 11 30 V
SET Voltage Resolution 7 Bits
SET Differential Nonlinearity -1 +1 LSB
SET Zero-Scale Error -1 +1 +3 LSB
SET Full-Scale Error -4 +5 LSB
SET Current 120 μA
To GND, VAVDD = 14V 8.5 170 k
SET External Resistance To GND, VAVDD = 6V 2.5 50 k
Memory Write Cycles 30 Times
Memory Write Time RFREQ = unconnected 150 ms
I2C INTERFACE
Logic-Input Low Voltage (VIL ) SDA, SCL
0.3 x VIN V
Logic-Input Low Voltage ADDR0, ADDR1 0.2 x VIN V
Logic-Input High Voltage (VIH ) SDA, SCL, ADDR0, ADDR1 0.7 x VIN V
SDA Output Low Voltage ISDA = -3mA sink 0 0.4 V
SDA and SCL Input Capacitance SDA, SCL (Note 1) 10 pF
SCL Frequency (fSCL) DC 400 kHz
SCL High Time (tHIGH) 600 ns
SCL Low Time (tLOW) 1300 ns
SDA and SCL Rise and Fall Time
(tR, tF)Cb = total capacitance of bus line in pF (Note 1) 20 + 0.1
x Cb 300 ns
START Condition Hold Time
(tHD:STA)10% of SDA to 90% of SCL 600 ns
START Condition Setup Time
(tSU:STA) 600 ns
Data Input Hold Time (tHD:DAT ) 50 ns
Data Input Setup Time (tSU:DAT ) 100 ns
STOP Condition Setup Time
(tSU:STO ) 600 ns
Bus Free Time (tBUF) 1300 ns
SDA Capacitive Loading (Cb) (Note 2) 400 pF
Input Filter Spike Suppression SDA, SCL, not tested 50 ns
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VLIN = VEN = +3.3V, circuit of Figure 2, VMAIN = 8V, VGON1 = VGON2 = 21V, VGOFF = -6.5V. TA= -40°C to +85°C, unless oth-
erwise noted.) (Note 3)
Note 1: Guaranteed by design, not production tested.
Note 2: The maximum amount capacitance allowed on the SDA bus lines.
Note 3: TA= -40°C specifications are guaranteed by design, not production tested.
tF
tHD:DAT tSU:STA
tSU:STO
tSU:DAT
tBUF
tR
VIH
VIL
tHD:STA
tLOW
tHIGH
SDA
SCL
Figure 1. Timing Definitions Used in the Electrical Characteristics
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17094 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010
50
60
70
80
90
100
40
1 1000
VIN = 3.0V
VIN = 2.2V
VMAIN = 8.0V
fSW = 1.2MHz
VIN = 5.0V
STEP-UP REGULATOR OUTPUT
LOAD REGULATION vs. LOAD CURRENT
MAX17094 toc02
LOAD CURRENT (mA)
OUTPUT ERROR (%)
10010
-0.4
-0.3
-0.1
-0.2
0
0.1
0.2
-0.5
1 1000
VIN = 3.0V
VIN = 2.2V
VIN = 5.0V
STEP-UP CONVERTER LINE REGULATION
vs. INPUT VOLTAGE
MAX17094 toc03
SUPPLY VOLTAGE (V)
OUTPUT ERROR (%)
4.92.7 3.8
0.001
0.003
0.002
0.004
0.005
0.006
0
1.6 6.0
0.3A LOAD
0.2A LOAD
0.1A LOAD
NO LOAD
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
10 ______________________________________________________________________________________
IN SUPPLY QUIESCENT CURRENT
vs. IN SUPPLY VOLTAGE
MAX17094 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
4.92.7 3.8
5
10
20
25
15
30
35
40
0
1.6 6.0
NO LOAD
0.2A LOAD
IN SUPPLY QUIESCENT CURRENT
vs. TEMPERATURE
MAX17094 toc05
TEMPERATURE (°C)
IN SUPPLY CURRENT (μA)
60-15 10 35
5
10
20
25
15
30
35
40
0
-40 85
VIN = 3.3V
VEN = 0
VIN = 5.0V
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAX17094 toc06
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1269
0.5
1.5
1.0
3.0
3.5
4.0
4.5
2.0
2.5
5.0
5.5
6.0
0
315
NO LOAD ON VMAIN
VIN = 3.3V
VIN = 5.0V
AVDD CURRENT
vs. TEMPERATURE
MAX17094 toc07
TEMPERATURE (°C)
AVDD CURRENT (mA)
60-15 10 35
4.2
4.4
4.8
5.0
5.2
4.6
5.4
5.6
4.0
-40 85
NO LOAD ON VMAIN
VAVDD = 14V
VAVDD = 8V
VIN = 3.3V
STEP-UP CONVERTER
SWITCHING FREQUENCY vs. RFREQ
MAX17094 toc08
RFREQ (kΩ)
SWITCHING FREQUENCY (MHz)
7525 50
200
400
800
1000
1200
600
1400
1600
0
0 100
IMAIN = 350mA LOAD
VIN = 3.3V
VMAIN = 8V
STEP-UP CONVERTER SWITCHING
FREQUENCY vs. INPUT VOLTAGE
MAX17094 toc09
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
4.92.7 3.8
1.22
1.26
1.24
1.30
1.32
1.34
1.36
1.28
1.38
1.40
1.20
1.6 6.0
IMAIN = 200mA
RFREQ = 80.6kΩ
VMAIN = 8V
STEP-UP REGULATOR
HEAVY-LOAD SOFT-START
MAX17094 toc10
2ms/div
0
0
0
0
LX
5V/div
VMAIN
5V/div
IL
500mA/div
EN
5V/div
STEP-UP REGULATOR LOAD-TRANSIENT
RESPONSE (20mA TO 300mA)
MAX17094 toc11
100μs/div
0
0
0
0
VLX
10V/div
IL1
1A/div
VMAIN
(AC-COUPLED)
500mV/div
IMAIN
200mA/div
L1 = 4.1μH
RCOMP = 40.2kΩ
CCOMP = 1000pF
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________
11
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE (20mA TO 1A)
MAX17094 toc12
10μs/div
0
0
0
0
VLX
10V/div
IL1
1A/div
VMAIN
(AC-COUPLED)
500mV/div
IMAIN
1A/div
L1 = 4.1μHF RCOMP = 40.2kΩ
CCOMP = 1000pF
POWER-UP SEQUENCE
OF ALL SUPPLY OUTPUTS
MAX17094 toc13
1ms/div
0
0
0
0
0
0
0
VIN
5V/div
VL
5V/div
VCOM
5V/div
VLOUT
5V/div
VGON
20V/div
VGOFF
20V/div
VMAIN
5V/div
LDO OUTPUT REGULATION
vs. LOAD CURRENT
MAX17094 toc14
LOAD CURRENT (mA)
OUTPUT ERROR (%)
10 100
-0.20
0
0.20
-0.40
0 1000
VIN = 3.0V
VIN = 5.0V
LDO OUTPUT LINE REGULATION
vs. INPUT VOLTAGE
MAX17094 toc15
VLIN VOLTAGE (V)
OUTPUT ERROR (%)
12345
0.05
0.10
0.15
0.20
0.25
0
06
IOUT = 250mA
ILOUT = 100mA
OPERATIONAL AMPLIFIER
FREQUENCY RESPONSE
MAX17094 toc16
FREQUENCY (kHz)
GAIN (dB)
1000 10,000
-20
-10
-15
0
-5
5
10
-25
100 100,000
NO LOAD
100pF LOAD
AV = 1
VIN = 3.3V
OPERATIONAL AMPLIFIER RAIL-TO-RAIL
INPUT/OUTPUT WAVEFORMS
MAX17094 toc17
10
μ
s/div
0
0
VCOM
5V/div
VPOS
5V/div
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX17094 toc18
2
μ
s/div
0
0
IVCOM
100mA/div
VVCOM
(AC-COUPLED)
1V/div
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
MAX17094 toc19
200ns/div
0
0
VVCOM
2V/div
VPOS
2V/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
12 ______________________________________________________________________________________
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX17094 toc20
200ns/div
0
0
VVCOM
(AC-COUPLED)
100mV/div
VPOS
(AC-COUPLED)
100mV/div
SCAN DRIVER INPUT/OUTPUT
WAVEFORMS WITH LOGIC INPUT
MAX17094 toc21
4
μ
s/div
0
0
VY2
10V/div
VA2
5V/div
SCAN DRIVER PROPAGATION DELAY
(RISING EDGE)
MAX17094 toc22
100ns/div
0
0
VY2
10V/div
VA2
5V/div
SCAN DRIVER PROPAGATION DELAY
(FALLING EDGE)
MAX17094 toc23
100ns/div
0
0
VY2
10V/div
VA2
5V/div
CALIBRATION SIGNAL LSB
DOWNWARD STEP RESPONSE
MAX17094 toc24
40
μ
s/div
0
0
0
0
VCOM
(AC-COUPLED)
10mV/div
VSET
(AC-COUPLED)
10mV/div
SCL
5V/div
SDA
5V/div
CALIBRATION SIGNAL LSB
UPWARD STEP RESPONSE
MAX17094 toc25
40
μ
s/div
0
0
0
0
VCOM
(AC-COUPLED)
10mV/div
VSET
(AC-COUPLED)
10mV/div
SCL
5V/div
SDA
5V/div
CALIBRATION FULL-SCALE
DOWNWARD STEP RESPONSE
MAX17094 toc26
40
μ
s/div
0
0
3.975V
2.354V
0
0
VCOM
2V/div
VSET
200mV/div
SCL
5V/div
SDA
5V/div
CALIBRATION FULL-SCALE
UPWARD STEP RESPONSE
MAX17094 toc27
40
μ
s/div
0
0
3.975V
2.354V
0
VCOM
2V/div
VSET
200mV/div
SCL
5V/div
SDA
5V/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 13
Pin Description
PIN NAME FUNCTION
1 LIN Input of the Internal Linear Regulator. Bypass LIN to GND with a 4μF capacitor close to the IC.
2 LOUT Internal Linear Regulator Output. Bypass LOUT to GND with a 4.F capacitor.
3 FBL
Linear Regulator Feedback Pin. Connect external resistor-divider tap here and minimize trace area.
Set VLOGIC according to: VLOGIC = 0.618V x (1 + R7/R8) (Figure 2).
4, 26, 29 GND Analog Ground
5 ADDR0 Address Select Pin to Set Address for the I2C Slave Address
6 ADDR1 Address Select Pin to Set Address for the I2C Slave Address
7 SCL I2C-Compatible Clock Input
8 SDA I2C-Compatible Serial Bidirectional Data Line
9–15 A2–A8 Level-Shifter Logic-Level Inputs
16 SS
Step-Up Regulator Soft-Start Control. Connect a capacitor greater than 200pF between SS and
AGND to set the step-up regulator soft-start timing. SS is connected to AGND when EN is low.
When EN goes high, the capacitor at SS is charged by an internalA current source, slowly
raising the internal current limit. The full LX current limit is available when VSS = 1.235V or when
VMAIN reaches its regulation threshold, whichever occurs first. If no capacitor is connected, the
soft-start time is controlled by an internal 10ms digital timer.
17 YDCHG Level-Shifter Output Used to Discharge the Panel
1824 Y2–Y8 Level-Shifter Outputs
25 GOFF
Gate-Off Supply. GOFF is the negative supply voltage for the Y2–Y8 and YDCHG level-shifter
circuitry. Bypass to GND with a minimum 0.1μF ceramic capacitor.
27 GON2
Gate-On Supply. GON2 is the positive supply for the Y7 and Y8 level-shifter circuitry. Bypass to
GND with a minimum 0.1μF ceramic capacitor.
28 GON1
Gate-On Supply. GON1 is the positive supply for the Y2–Y6 and YDCHG level-shifter circuitry.
Bypass to GND with a minimum 0.1μF ceramic capacitor.
30 SET
Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set the full-
scale adjustable sink current, which is VAVDD/(20 x RSET). IOUT is equal to the current through RSET.
31 BGND Operational Amplifier GND
32 VCOM Operational Amplifier Output
33 NEG Operational Amplifier Negative Input
34 POS Operational Amplifier Positive Input
35 OUT
Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp input
POS (between AVDD and BGND) that determines the VCOM output voltage. IOUT lowers the divider
voltage by a programmable amount.
36 AVDD Op Amp and Internal VL Linear Regulator Supply Input. Bypass AVDD to BGND with a 0.1μF capacitor.
37 FB
Step-Up Regulator Feedback. Connect external resistor-divider tap here and minimize trace area.
Set VOUT according to: VOUT = 1.235V x (1 + R1/R2) (Figure 2).
38, 39 PGND Power Ground
40, 41 LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
42 FREQ
SMPS Frequency Adjust. Connect a resistor between 30k and 80k to select the step-up
converter’s operating frequency as determined by: f (mHz) = 0.015 x RFREQ (k). Leave
unconnected for f = 600kHz.
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
43 EN
Enable. Pull EN low to turn off the DC-DC converter and the op amp. The high-voltage scan drivers
and LDO remain active if sufficient voltage is available for operation.
44 IN Supply. Bypass to AGND with a minimum 0.1μF ceramic capacitor.
45 SENSE
Input-Voltage Threshold Detector. Connect this pin to VIN through a resistor-divider. When the
voltage at the SENSE pin falls below a 1.235V threshold, YDCHG is driven to VGON1.
46 COMP
Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND. Typical values
are 40.2k and 1000pF.
47 AGND Analog GND
48 VL
On-Chip Regulator Output. This regulator powers internal analog circuitry. Bypass VL to AGND with
a 0.22μF or greater ceramic capacitor.
— EP
Exposed Backside Pad. Connect to AGND and make AGND copper plane as level as possible to
help external dissipation.
Typical Operating Circuit
The MAX17094 typical operating circuit (Figure 2) gen-
erates a +8V source-driver supply and approximately
+22V and -6.5V gate-driver supplies for TFT displays.
The input-voltage range for the IC is from +1.8V to
+5.5V, but the Figure 2 circuit is designed to run from
2.5V to 3.6V. Table 1 lists the recommended compo-
nents and Table 2 lists the component suppliers. Figure
3 is the MAX17094 functional diagram.
Table 1. Component List
DESIGNATION DESCRIPTION
C1
4.7μF ±10%, 6.3V X5R ceramic
capacitor (0603)
Murata GRM188R60J475K
TDK C1608X5R0J475K
C2, C3
F ±20%, 6.3V X5R ceramic
capacitors (0402)
Murata GRM155R60J105K
TDK C1005X5R0J105M
C4
10μF ±20%, 6.3V X5R ceramic
capacitor (0603)
Murata GRM188R60J106M
TDK C1608X5R0J106K
C5, C6
4.7μF ±10%, 16V X5R ceramic
capacitors (0805)
Murata GRM21BR61C475K
Taiyo Yuden EMK212BJ475KG
D1 30V Schottky diode, 1A (S-Flat)
Toshiba CRS02
L1
4.1μH, 1.95A, 57m inductor (6mm x
6mm x 2mm)
Sumida CDRH5D18NP-4R1NC
Coiltronics SD6020-4R1-R
Table 2. Component Suppliers
SUPPLIER WEBSITE
Coiltronics www.cooperet.com
Murata Electronics North
America, Inc. www.murata-northamerica.com
Sumida Corp. www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK Corp. www.component.tdk.com
Toshiba America Electronic
Components, Inc. www.toshiba.com/taec
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 15
VMAIN
8V, 300mA
VIN
3.3V
VLOGIC
2.5V, 250mA
VN
-6.5V, 50mA
VP
21V, 50mA
TO PANEL
TO VCOM
BACKPLANE
COMP
PGND
YDCHG
FB
C1
4.7μF
R7
63.4kΩ
C5
4.7μF
C6
4.7μF
0.1μF
RCOMP
40.2kΩ
CCOMP
1000pF
CSS
0.1μF
AVDD
L1
4.1μH
RENA
80.6kΩ
EP
IN EN
LOUT
SENSE
OUT
FROM TCON
VN
I2C BUS
0.47μF
GOFF
AGND
SS
C4
10μF
C2
1μF
0.1μF
15pF
0.1μF
0.1μF0.1μF
0.1μF
R5
6.81kΩ
D1
D4D2
D3
LX
Y2
LIN
0.1μF
VCOM
BGND
POS
NEG 0.1μF
FBL
GND
R2
36.5kΩ
R1
200kΩ
R3
200kΩ
RSET
24.9kΩ
R4
200kΩ
GON2VP
VIN
FREQ
MAX17094
C3
1μF
GND
SET
Y3
Y4
Y5
Y6
Y7
Y8
A2
A3
A4
A5
A6
A7
A8
SDA
SCL
0.22μF
10kΩ
10kΩ
VL
ADDR0
ADDR1
R8
21kΩ
R6
15kΩ
0.1μF
GON1
Figure 2. MAX17094 Typical Operating Circuit
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
16 ______________________________________________________________________________________
VMAIN
VIN
VLOGIC
VN VP
TO PANEL
TO VCOM
BACKPLANE
COMP
PGND
YDCHGIRESET
FB
AVDD
EP
IN EN
LOUT
SENSE
REF
OUT
FROM TCON
VN
I2C BUS
GOFF
AGND
SS
LX
Y2
LIN
VCOM
BGND
POS
NEG
FBL
GND
GON2
VP
VIN
FREQ
STEP-UP
CONVERTER
SET
Y3
Y4
Y5
Y6
Y7
Y8
A2
A3
A4
A5
A6
A7
A8
SDA
SCL
VL
ADDR0
ADDR1
GON1
250mA
LINEAR
REGULATOR
BOOTSRAP
LINEAR
REGULATOR
OP
COMP
DAC
00
7F
19R
R
7
RSB
1
7
I2C
CONTROL
INTERFACE
DATA
REGISTER
00H
WR
CONTROL
REGISTER
02H
IVR
Figure 3. MAX17094 Functional Diagram
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 17
Detailed Description
The MAX17094 includes a high-performance step-up
regulator, a 250mA LDO linear regulator, a high-speed
operational amplifier, a digitally adjustable VCOM cali-
bration device with nonvolatile memory and I2C inter-
face, and a high-voltage, level-shifting scan driver
optimized for active-matrix TFT LCDs.
Step-Up Regulator
The step-up regulator employs a peak current-mode
control architecture with an adjustable (600kHz to
1.2MHz), constant-switching frequency that maximizes
loop bandwidth and provides a fast-transient response
to pulsed loads found in source drivers of TFT LCD
panels. The high switching frequency is programmable
from 450kHz to 1.2MHz by selecting an appropriate
external resistor connected between the FREQ input
and AGND. The high switching frequency also allows
the use of low-profile inductors and ceramic capacitors
to minimize the thickness of LCD panel designs. The
integrated high-efficiency MOSFET and the IC’s built-in
digital soft-start functions reduce the number of exter-
nal components required while controlling inrush cur-
rent. The output voltage can be set from VIN to 14V with
an external resistive voltage-divider.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
Figure 4 shows the block diagram of the step-up regu-
lator. An error amplifier compares the signal at FB to
1.235V and changes the COMP output. The voltage at
COMP determines the current trip point each time the
internal MOSFET turns on. As the load varies, the error
amplifier sources or sinks current to the COMP output
accordingly to produce the inductor peak current nec-
essary to service the load. To maintain stability at high
duty cycles, a slope compensation signal is summed
with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceed the COMP voltage, the controller resets the flip-
flop and turns off the MOSFET. Since the inductor cur-
rent is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit compares the
input voltage at IN with the UVLO (1.3V typ) to ensure
that the input voltage is high enough for reliable opera-
tion. The 200mV (typ) hysteresis prevents supply tran-
sients from causing a restart. Once the input voltage
exceeds the UVLO-rising threshold, startup begins.
When the input voltage falls below the UVLO falling
threshold, the controller turns off the main step-up regu-
lator and the linear regulator, disables the switch-con-
trol block, and the operational amplifier output
becomes high impedance.
DVV
V
MAIN IN
MAIN
-
SOFT-
START
OSCILLATOR
1.235V
FB
LX
ILIM
COMPARATOR
ILIMIT
CURRENT
SENSE
PGND
COMP
CLOCK
ERROR AMP
PWM
COMPARATOR
SLOPE COMP
LOGIC AND DRIVER
Figure 4. Step-Up Regulator Block Diagram
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
18 ______________________________________________________________________________________
Soft-Start
The soft-start feature effectively limits the inrush current
during startup by linearly ramping up the step-up con-
verter’s peak switch current limit. The soft-start period
terminates when either the output voltage reaches reg-
ulation or the full current limit has been reached. By
default, the current limit is controlled by an internal
timer that allows the current limit to rise from 0 to the full
current limit in approximately 10ms. If an adjustable
soft-start period is desired, an external capacitor (CSS)
greater than 200pF can be connected between SS and
GND. In this case, CSS is charged with a 5μA current
source such that the full current limit is reached until the
voltage across CSS reaches 1.235V.
Fault Protection
The MAX17094 monitors AVDD for an overvoltage condi-
tion. If the AVDD voltage is above 14.1V (min), the
MAX17094 disables the gate driver of the step-up regula-
tor and prevents the internal MOSFET from switching. The
AVDD overvoltage condition does not set the fault latch.
Operational Amplifier
The MAX17094 has an operational amplifier that is typi-
cally used to drive the LCD backplane (VCOM). The
operational amplifier features ±200mA output short-circuit
current, 45V/μs slew rate, and 20MHz bandwidth. While
the op amp is a rail-to-rail input and output design, its
accuracy is significantly degraded for input voltages with-
in 1V of its supply rails (AVDD and BGND).
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately ±200mA if the output is directly shorted
to AVDD or to AGND. If the short-circuit condition per-
sists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-
shutdown threshold, an internal thermal sensor immedi-
ately sets the thermal-fault latch, shutting off the main
step-up regulator, the linear regulator, the switch-con-
trol block, and the operational amplifier. Those portions
of the device remain inactive until the input voltage is
cycled off, then on, again.
Driving Pure Capacitive Loads
The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction-
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation. As the operational amplifier’s capaci-
tive load increases, the amplifier’s bandwidth decreas-
es and gain peaking increases. A 5Ωto 50Ωsmall
resistor placed between VCOM and the capacitive load
reduces peaking, but also reduces the gain. An alterna-
tive method of reducing peaking is to place a series RC
network (snubber) in parallel with the capacitive load.
The RC network does not continuously load the output
or reduce the gain. Typical values of the resistor are
between 100Ωand 200Ωand the typical value of the
capacitor is 10pF.
High-Voltage Level-Shifting Scan Driver
The MAX17094 includes seven logic-level to high-volt-
age level-shifting buffers, which can buffer seven logic
inputs (A2–A8) and shift them to a desired level (Y2–Y8)
to drive TFT-LCD row logic. The driver outputs, Y2–Y8,
swing between their power-supply rails, according to
the input-logic level on A2–A8. The driver output is
GOFF when its respective input is logic low, and GON_
when its respective input is logic high. These seven dri-
ver channels are grouped for different high-level sup-
plies. A2–A6 are supplied from GON1, and A7 and A8
are supplied from GON2. GON1 and GON2 can be tied
together to make A2–A8 use identical supplies. The
high-voltage, level-shifting scan drivers are designed to
drive the TFT panels with row drivers integrated on the
panel glass. Its seven outputs swing from +30V (max)
to -10V (min) and can swiftly drive capacitive loads.
The typical propagation delays are 80ns, with fast 16ns
rise-and-fall times. The buffers can operate at frequen-
cies up to 50kHz. A YDCHG is the output of the eight-
level shifting buffer. It is driven by the input-voltage-
detector circuit.
Input-Voltage Detector
The input-voltage detector is used to drive the YDCHG
level-shifter buffer to VGON1 during a power-down once
the input voltage has fallen below a user-defined thresh-
old. The input voltage is sensed at the SENSE pin through
a voltage-divider. Once the falling edge of VSENSE falls
below 1.235V (typ), YDCHG is driven to VGON1.
Low-Dropout Linear Regulator (LDO)
The MAX17094 has an integrated 1.2Ω (max) pass
element and can provide at least 250mA. The output
voltage is accurate within ±2%.
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 19
VCOM Calibrator
The VCOM calibrator is a solid-state alternative to
mechanical potentiometers used for adjusting the LCD
backplane voltage (VCOM) in TFT LCD displays. OUT
attaches to the external resistive voltage-divider at the
POS terminal of the op amp and sinks a programmable
current (IOUT), which sets the VCOM levels (Figure 5).
The DAC setting that controls the wiper setting of the
potentiometer is directly determined by the value stored
in the wiper register (WR). Changing the value in WR
allows the user to change the wiper position to increase
or decrease the VCOM levels. The user can store a WR
setting into the nonvolatile initial value register (IVR)
such that on power-up, WR is preset to the last stored
value in IVR. The 2-wire I2C interface between the sys-
tem controller and the programming circuit adjusts WR
and programs IVR. The resistive voltage-divider and
AVDD supply set the maximum value of VCOM. OUT
sinks current from the voltage-divider to reduce the
POS voltage level and VCOM output. The external
resistor at SET (RSET) sets the full-scale sink current
and the minimum value of VCOM.
The GON2 input provides the high voltage required to
program IVR. GON2 is connected to the TFT LCD VGON2
supply. VGON2 should be between 12V and 30V. IVR pro-
gramming is guaranteed only when GON2 is greater than
7V. Bypass GON2 to GND (which is bypassed to GND)
with a 0.1μF or greater capacitor.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the device. When
the junction temperature exceeds TJ= +160°C, a ther-
mal sensor immediately activates the fault protection,
which shuts down the step-up regulator, LDO, and the
operational amplifiers, allowing the device to cool down.
Once the device cools down by approximately 15°C,
cycle the input voltage (below the UVLO falling thresh-
old) to clear the fault latch and reactivate the device.
The thermal-overload protection protects the IC in the
event of fault conditions. For continuous operation, do
not exceed the absolute maximum junction temperature
rating of TJ= +150°C.
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output-load capability,
transient-response time, and output-voltage ripple.
Physical size and cost are also important factors to be
considered.
SDA
SCL
ADDR0
ADDR1
AVDD
RSET
SET
OUT
VGON
GON2
R4
R3
VCOM
VMAIN
DAC
00
7F
19R
R
7
RSB
1
7
VIN
POS
NEG
VCOM
I2C BUS
I2C
CONTROL
INTERFACE
DATA
REGISTER
00H
WR
CONTROL
REGISTER
02H
MAX17094
IVR
Figure 5. VCOM Calibrator Functional Diagram
MAX17094
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple and therefore reduce the peak current, which
decreases core losses in the inductor and I2R losses in
the entire power path. However, large inductor values
also require more energy storage and more turns of
wire, which increase physical size and can increase I2R
losses in the inductor. Low inductance values decrease
the physical size but increase the current ripple and
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant called LIR,
which is the ratio of the inductor peak-to-peak ripple
current to the average DC inductor current at the full
load current. The best trade-off between inductor size
and circuit efficiency for step-up regulators generally
has an LIR between 0.3 and 0.5. However, depending
on the AC characteristics of the inductor core material
and ratio of inductor resistance to other power-path
resistances, the best LIR can shift up or down. If the
inductor resistance is relatively high, more ripple can
be accepted to reduce the number of turns required
and increase the wire diameter. If the inductor resis-
tance is relatively low, increasing inductance to lower
the peak current can decrease losses throughout the
power path. If extremely thin high-resistance inductors
are used, as is common for LCD panel applications, the
best LIR can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
In Figure 2’s typical operating circuit, the LCD’s gate-on
and gate-off supply voltages are generated from two
unregulated charge pumps driven by the step-up regu-
lator’s LX node. The additional load on LX must there-
fore be considered in the inductance and current
calculations. The effective maximum output current,
IMAIN(EFF), becomes the sum of the maximum load cur-
rent of the step-up regulator’s output plus the contribu-
tions from the positive and negative charge pumps:
where IMAIN(MAX) is the maximum step-up output cur-
rent, nVN is the number of negative charge-pump
stages, nVP is the number of positive charge-pump
stages, IVN is the negative charge-pump output cur-
rent, and IVP is the positive charge-pump output cur-
rent, assuming the initial pump source for IVP is VMAIN.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IMAIN(EFF)), the expected efficiency (ηTYP) taken from
an appropriate curve in the
Typical Operating
Characteristics
, the desired switching frequency (fOSC),
and an estimate of LIR based on the above discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VIN(MIN) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from an appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX17094 LX current limit should exceed IPEAK and
the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.1Ωseries resistance.
Considering the typical operating circuit, the maximum
load current (IMAIN(MAX)) is 300mA, with an 8V output
and a typical input voltage of 3.3V. The effective full-
load step-up current is:
Choose a switching frequency of 1.2MHz and a LIR of
0.36, and estimate the efficiency to be 85% at this operat-
ing point:
LV
V
VV
AMHz
=
×
33
8
833
0 380 1 2
0
2
..
..
.- 885
036 41
..
μH
ImAmAmAmA
MAIN EFF() ()=+×++×=300 1 20 2 1 20 380
II I
PEAK IN DC MAX RIPPLE
=+
(, ) 2
IVVV
LV f
RIPPLE
IN MIN MAIN IN MIN
MAIN O
=×
()
××
() ()
-
SSC
IIV
V
IN DC MAX MAIN EFF MAIN
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
If
IN
MAIN
MAIN IN
MAIN EFF OSC
=
×
2-
()
ηTYP
LIR
II nInI
MAIN EFF MAIN MAX VN VN VP VP() ( ) ()=+×++×1
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
20 ______________________________________________________________________________________
A 4.1μH inductor is chosen. Then, using the circuit’s
minimum input voltage (3.0V) and estimating efficiency
of 82% at that operating point:
The ripple current and the peak current at that input
voltage are:
Setting the Switching Frequency
To set the switching frequency, connect a resistor from
FREQ to AGND. Calculate the resistor value in kΩfrom
the following equation:
Output Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharging
of the output capacitance, and the ohmic ripple due to
the capacitor’s equivalent series resistance (ESR):
and:
where IPEAK is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output-voltage ripple is typically dominated by VRIPPLE(C).
The voltage rating and temperature characteristics of
the output capacitor must also be considered.
Input Capacitor Selection
The input capacitor (C4) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. A 10μF ceramic capacitor is used in the
typical operating circuit (Figure 2) because of the high
source impedance seen in typical lab setups. Actual
applications usually have much lower source imped-
ance since the step-up regulator often runs directly
from the output of another regulated supply. Typically,
C4 can be reduced below the values used in the typical
operating circuit. Ensure a low noise supply at IN by
using an adequate value for C4.
Rectifier Diode
The MAX17094’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 3A Schottky
diode complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the main step-up regulator is
adjusted by connecting a resistive voltage-divider from
the output (VMAIN) to AGND with the center tap con-
nected to FB (see Figure 2). Select R2 in the 10kΩto
50kΩrange. Calculate R1 with the following equation:
where VREF, the step-up regulator’s feedback set point,
is 1.235V (typical). Place R1 and R2 close to the IC.
Loop Compensation
Choose RCOMP to set the high-frequency integrator
gain for fast-transient response. Choose CCOMP to set
the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient-response waveforms.
Setting the LDO Output Voltage
The output voltage of the LDO is adjusted by connect-
ing a resistive voltage-divider from the output (VLOUT)
to AGND with the center tap connected to FBL (see
Figure 2). Select R8 in the 10kΩto 50kΩrange.
Calculate R7 with the following equation:
Place R7 and R8 close to the IC.
Connect to a 1μF capacitor between LIN and AGND to
keep the source impedance to the LDO low and con-
nect a 4.7μF low equivalent-series-resistance (ESR)
capacitor between LOUT and AGND to ensure stability
and to provide good output-transient performance.
RR V
V
LOUT
780 618 1
.-
CVLI
VR
COMP MAIN MAIN MAX
IN COMP
×××
×
10
2
()
()
RVV C
LI
COMP IN MAIN OUT
MAIN MAX
×× ×
×
250
()
RR V
V
MAIN
121 235 1
.-
VIR
RIPPLE ESR PEAK ESR COUT() ( )
VI
C
VV
Vf
RIPPLE C MAIN
OUT
MAIN IN
MAIN OSC
()
-
VV V
RIPPLE RIPPLE C RIPPLE ESR
=+
() ( )
fR
MHZ FREQ k() ()
.0 015 Ω
IVVV
μH V MHz A
I
RIPPLE
PE
=×
()
××
383
41 8 12 0 381
-
..
.
AAK AAA=+ =124 0 381
2143...
IAV
VA
IN DC MAX(, )
.
..=×
×
038 8
3082
124
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 21
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
22 ______________________________________________________________________________________
Input-Voltage Detector
The falling-edge input-voltage threshold used by the volt-
age detector to drive YDCHG to VGON1 during power-
down is adjusted by connecting a resistive voltage-
divider from VIN to AGND with the center tap connected
to SENSE (see Figure 2). Select R6 in the 10kΩrange.
Calculate R5 with the following equation:
Setting the VCOM Adjustment Range
The external resistive voltage-divider sets the maximum
value of the VCOM adjustment range. RSET sets the full-
scale sink current, IOUT, which determines the minimum
value of the VCOM adjustment range. Large RSET val-
ues increase resolution but decrease the VCOM adjust-
ment range. Calculate R3, R4, and RSET using the
following procedure:
1) Choose the maximum VCOM level (VMAX), the mini-
mum VCOM level (VMIN), and the AVDD supply
voltage (VAVDD).
2) Select R3 between 10kΩand 500kΩbased on the
acceptable power loss from the VMAIN supply rail
connected to AVDD.
3) Calculate R4:
4) Calculate RSET:
5) Verify that ISET does not exceed 120μA:
6) If ISET exceeds 120μA, return to step 2 and choose
a larger value for R1.
The resulting resolution is:
A complete design example is given below:
VMAX = 4V, VMIN = 2.4V, VMAIN = 8V
If R3 = 200kΩ, then R4 = 200kΩand RSET = 24.9kΩ.
Resolution = 12.5mV
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PCB copper area,
other thermal mass, and airflow.
The MAX17094, with its exposed backside paddle sol-
dered to 1in2of PCB copper, can dissipate about
2222mW into +70°C still air. More PCB copper, cooler
ambient air, and more airflow increase the possible dis-
sipation, while less copper or warmer air decreases the
IC’s dissipation capability. The major components of
power dissipation are the power dissipated in the step-
up regulator and the power dissipated by the opera-
tional amplifiers.
The MAX17094’s largest on-chip power dissipation
occurs in the step-up switch, the VCOM amplifiers, the
LDO, and the high-voltage scan driver outputs.
Step-Up Regulator
The largest portions of the power dissipated by the
step-up regulator are the internal MOSFET, the induc-
tor, and the output diode. If the step-up regulator with
3.3V input and 300mA output has approximately 85%
efficiency, approximately 5% of the power is lost in the
internal MOSFET, approximately 3% in the inductor,
and approximately 5% in the output diode. The remain-
ing few percent are distributed among the input and
output capacitors and the PCB traces. If the input
power is approximately 3W, the power lost in the inter-
nal MOSFET is approximately 150mW.
Operational Amplifiers
The power dissipated in the operational amplifiers
depends on the output current, the output voltage, and
the supply voltage:
where IVCOM_SOURCE is the output current sourced by
one operational amplifier, and IVCOM_SINK is the output
current that the operational amplifier sinks.
In a typical case where the supply voltage is 8V and the
output voltage is 4V with an output source current of
30mA for each of the four operational amplifiers, the
power dissipated is 480mW.
PD I V V
PD
SOURCE VCOM SOURCE AVDD VCOM
SINK
()
=
_-
IIV
VCOM SINK VCOM_×
(V - V
127
MAX MIN)
ISET AVDD
=×
V
20 RSET
RR
SET =××
V
20 (V - V
MAX
MAX MIN)3
RR43
()
×
V
V-V
MAX
AVDD MAX
RR56 1
V
1.235V
IN(THRESHOLD) -
LDO
The power dissipated in the LDO depends on the
LDO’s output current, input voltage, and output voltage:
Scan Driver Outputs
The power dissipated by the scan driver outputs
(Y2–Y8) depends on the scan frequency, the voltage
difference between the power rails across each driver,
and the capacitive load driven by each output.
Assuming the voltage difference between the power
rails of each driver is 30V and all outputs are driving a
load capacitance of 4nF at 50kHz, then the total
expected power dissipation would be:
VCOM Calibrator Interface
The MAX17094 is a slave-only device. The 2-wire I2C-
bus-like serial interface (pins SCL and SDA) is
designed to attach to an I2C bus that is pulled up to
VIN. Connect both SCL and SDA lines to the I2C bus
supply through individual pullup resistors. Calculate the
required value of the pullup resistors using:
where tRis the rise time in the
Electrical Characteristics
,
and CBUS is the total capacitance on the bus.
The MAX17094 uses a nonstandard I2C interface proto-
col with standard voltage and timing parameters, as
defined in the following subsections.
Bus Not Busy
Both data and clock lines remain high. Data transfers
can be initiated only when the bus is not busy (Figure 6).
Start Data Transfer (S)
Starting from an idle bus state (both SDA and SCL are
high), a high-to-low transition of the SDA line while the
clock (SCL) is high determines a START condition. All
commands must be preceded by a START condition
from a master device on the bus.
Stop Data Transfer (P)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition from the
master device.
Data Valid
The state of the data line represents valid data when, after
a START condition, the data line is stable for the duration
of the high period of the clock signal. The data on the line
must be changed during the low period of the clock sig-
nal. The master generates one clock pulse per bit of data
during write operations and the slave device outputs 1
data bit per clock pulse during read operations. Each
data transfer is initiated with a START condition and termi-
nated with a STOP condition. Two bytes are transferred
between the START and STOP conditions.
Acknowledge/Polling
The MAX17094, when addressed, generates an
acknowledge pulse after the reception of each byte.
The master device must generate an extra clock pulse
that is associated with this acknowledge bit. The device
that acknowledges has to pull down the SDA line dur-
ing the acknowledge clock pulse in such a way that the
SDA line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. The master sig-
nals an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the
STOP condition.
Rt
PULLUP R
CBUS
PD f C V V
SCAN SCAN PANEL GON GOFF
× ×
()
7
750
2
_-
kkHz nF V W××
()
=430 126
2.
PD I V V
LDO LOUT LIN LOUT
()
-
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 23
SCL
SDA
START
CONDITION
S
STOP
CONDITION
P
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 6. I2C Bus START, STOP, and Data Change Conditions
MAX17094
The MAX17094 does not generate an acknowledge
while an internal programming cycle is in progress.
Once the internally timed write cycle has started and
the IVR inputs are disabled, acknowledge polling can
be initiated. This involves sending a START condition
followed by the device address byte. Only if the internal
write cycle has completed does the MAX17094
respond with an acknowledge pulse, allowing the read
or write sequence to continue.
The MAX17094 does not acknowledge a command to
program IVR if VGON is not high enough to properly
program the device. Also, a program command must
be preceded by a write command. The IC does not
acknowledge a program command or program IVR
unless the WR data has been modified since the most
recent program command.
Address Byte and Address Pins
The MAX17094’s slave address is determined by the
state of the A0 and A1 address pins. These pins allow up
to four devices to reside on the same I2C bus. Address
pins tied to AGND result in a 0 in the corresponding bit
position in the slave address. Conversely, address pins
tied to VIN result in a 1 in the corresponding bit positions.
For example, the MAX17094’s slave address byte is 50h
when A0 and A1 pins are grounded (see Figure 8).
Registers
The MAX17094 contains two user-accessible registers:
the data register located at 00h and the access control
register (ACR) located at 02h.
Data Register 00h
The data register contains the WR value that directly
determines the wiper position of the potentiometer, and
the IVR value stored in the nonvolatile memory, which is
used to preset the WR during power-up. The status of
the ACR determines whether WR and/or IVR is
accessed during read and write operations involving
the data register (see the
Access Control Register
(ACR) 02h
section). When reading and writing to the
data register, the most significant bit (MSB) is ignored.
Figure 9 shows the data register byte.
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
24 ______________________________________________________________________________________
SCL FROM
MASTER
DATA OUTPUT
BY MAX17094
DATA OUTPUT
BY MASTER
CLK1
START
CONDITION
S
1
CLK2
2
CLK8
8
CLK9
9
ACKNOWLEDGE
CLOCK PULSE
ACKNOWLEDGE
NOT ACKNOWLEDGE
D7 D6 D0
Figure 7. I2C Bus Acknowledge
0 01 1 0 A1 A2 R/W
SLAVE
ADDRESS*
MSB LSB
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
Figure 8. Address Byte
MSB LSB
X
VCOM DATA BYTE
b6 b5 b4 b3 b2 b1 b0
Figure 9. Data Register Byte
Table 3 lists the WR values and the corresponding ISET,
VSET, and VOUT values.
Access Control Register (ACR) 02h
The register select bit (RSB) is the most significant bit
of the byte stored in the ACR and is used to select
whether WR or IVR is accessed during read and write
cycles involving the data register.
When writing to the data register, if RSB is set to 1, only
WR is updated with the value written to the data register.
If RSB is set to 0, both WR and IVR are updated with the
value written that was written to the data register.
When reading the data register, if RSB is set to 1, the
value read from the data register is from WR: otherwise,
if RSB is set to 0, the value read from the data register
is from IVR.
When configuring RSB, only 00h or 80h should be writ-
ten to the ACR to set RSB to 0 or 1, respectively, in
order to keep all bits other than the RSB bit in the ACR
to zeros. The ACR comprises volatile memory, which is
preset to 00h during power-up. Figure 10 shows the
ACR byte.
Write Operation
To perform a write operation, the master must generate
a START condition, write the slave address byte (R/W =
0), write the register address, write the byte of data,
and generate a STOP condition. When writing to the
WR/IVR register, the potentiometer adjusts to the new
setting once it has acknowledged the new data has
been written to WR. If the ACR is set such that both WR
and IVR are to be updated with the value written to the
WR/IVR register, a write cycle is performed first to
update WR, followed by an internal write cycle to
update IVR. The SCL and SDA lines are ignored until
the internal IVR write cycle has finished. Figure 11
shows the write operation.
Read Operation
To perform a read operation, the master generates a
START condition, writes the slave address byte (R/W =
0), writes the register address, generates a repeated
START condition, writes the slave address byte (R/W =
1), reads data with ACK or NACK as applicable, and
generates a STOP condition. Figure 12 shows a read
operation.
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 25
Table 3. DAC Settings
7-BIT
VCOM DATA
BYTE
ISET V
SET (V) VOUT (V)
0000000 ISET(MAX) V
SET(MAX) V
MIN
0000001 ISET(MAX) -
1 LSB
VSET(MAX) -
1 LSB
VMIN +
1 LSB
.
.
.
.
.
.
.
.
.
.
.
.
1111110 ISET(MIN) +
1 LSB
VSET(MIN) +
1 LSB
VMAX -
1 LSB
1111111 ISET(MIN) V
SET(MIN) V
MAX
MSB LSB
RESERVED
b7 0 0 0 0000
REGISTER
SELECT
BIT (RSB)
Figure 10. Access Control Register Byte
START 0 01 1 0 A1 A2 0STOP
b7 b6 b5 b4 b3 b2 b1 b0 SLAVE
ACK
SLAVE
ACK b7 b6 b5 b4 b3 b2 b1 b0 SLAVE
ACK
MSB LSB MSB LSB MSB LSB
SLAVE
ADDRESS*
READ/WRITE
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
REGISTER ADDRESS DATA
Figure 11. Write Operation
0 01 1 0 A1 A2 STOP
b7 b6 b5 b4 b3 b2 b1 1
SLAVE
ACK
START REPEATED
START
00 0
110A1 A2 1
SLAVE
ADDRESS*
READ/
WRITE
b6 b5 b4 b3 b2 b1
b7 b0
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
MSB LSB LSB
MSB MSB LSB MSB LSB
REGISTER ADDRESS SLAVE
ADDRESS*
READ/WRITE DATA
SLAVE
ACK
SLAVE
ACK MASTER
NACK
Figure 12. Read Operation
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
Minimize the area of high-current loops by placing
the inductor, output diode, and output capacitors
near the input capacitors and near the LX and
PGND pins. The high-current input loop goes from
the positive terminal of the input capacitor to the
inductor, to the IC’s LX pin, out of PGND, and to the
input capacitor’s negative terminal. The high-cur-
rent output loop is from the positive terminal of the
input capacitor to the inductor, to the output diode
(D1), to the positive terminal of the output capaci-
tors, reconnecting between the output capacitor
and input capacitor ground terminals. Connect
these loop components with short, wide connec-
tions. Avoid using vias in the high-current paths. If
vias are unavoidable, use many vias in parallel to
reduce resistance and inductance.
Create a power ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all
these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put-voltage ripple and noise spikes. Create an analog
ground plane (AGND) consisting of the AGND pin, all
the feedback-divider ground connections, the opera-
tional-amplifier-divider ground connections, the
COMP capacitor ground connection, the AVDD
capacitor ground connection, and the device’s
exposed backside pad. Create a ground plane
(BGND) to carry operational amplifier return current
with the AVDO bypass capacitor connected to this
ground plane. Connect the AGND, BGND, and PGND
islands by connecting the PGND and BGND pins
directly to the exposed backside pad. Make no other
connections between these separate ground planes.
Place the feedback-voltage-divider resistors as
close to the feedback pin as possible. The divider’s
center trace should be kept short. Placing the resis-
tors far away causes the FB trace to become an
antenna that can pick up switching noise. Care
should be taken to avoid running the feedback
trace near LX or the switching nodes in the charge
pumps.
Place IN pin bypass capacitors as close to the
device as possible. The ground connections of the
IN bypass capacitor should be connected directly
to the AGND pin with a wide trace.
Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from the
feedback node and analog ground. Use DC traces
as shields, if necessary.
Refer to the MAX17094 evaluation kit for an example of
proper board layout.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFN T4866N+1 21-0141
Mouser Electronics
Authorized Distributor
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