K4C89093AF-AIF50 - Samsung Semiconductor Division

K4C89093AF

REV. 0.6 Jan. 2005

- 1 -

288Mb Network-DRAM-II Specification

Version 0.6

K4C89093AF

REV. 0.6 Jan. 2005

- 2 -

Revision History

Version 0.0 (Nov. 2002)

- First Release

Version 0.1 (Apr. 2003)

- Added 800Mbps(400Mhz) product

- Changed operating temperature from Ta to Tc.

- Changed capacitance of ADDR/CMD/CLK

- Changed tDSS(DS input Falling Edge to Clock Setup Time)

- Added CL7 for 800Mbps

- Deleted TSOP package outline

Version 0.11 (Apr. 2003)

- Corrected typo in page 3.(Deleted bi-directional strobe)

- Corrected min. Vref to VDDQ/2x95% in page 7

Version 0.2 (Jul. 2003)

- Changed ballout

- Added physical package dimension

- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)

- Changed DC test condition

- Changed low frequency spec like below

- Changed AC test load picture

Version 0.3 (Nov. 2003)

- Changed Packge type from die-exposed to full molded

- Changed Package code in Partnumber

From To

Min Max Min Max

Addr/CMD/CLK 1.5 2.5 1.5 3.0

From To

F6 FB F5 G7 F6 FB F5

CL4 0.9 0.9 1.0 0.75 0.75 0.8 1.0

CL5 0.9 0.9 1.0 0.75 0.75 0.8 1.0

CL6 0.9 0.9 1.0 0.75 0.75 0.8 1.0

CL7 ---0.75---

From To Changed point

IDD1S,IDD2N,IDD2P,IDD5,IDD6 IDD1S,IDD2N,IDD2P,IDD5B,IDD6 Changed condition

- IDD4W, IDD4R newly inserted

From To

Unit : ns F6 FB F5 F6 FB F5

tCK max@CL=4 7.5 7.5 7.5 6.0 6.0 6.0

tCK max@CL=5 7.5 7.5 7.5 6.0 6.0 6.0

tCK max@CL=6 7.5 7.5 7.5 6.0 6.0 6.0

K4C89093AF

REV. 0.6 Jan. 2005

- 3 -

Version 0.31 (Mar., 2004)

- Corrected typo. in page 7 (Changed operating Temperature to 85’C, case temperature)

Version 0.4 (Jul., 2004)

- Changed spec version from "Target" to " Preliminary"

- Deleted self-refresh function and BL2 from spec

- Changed min. tCK@CL5 to 3.5ns in "-F6"

Version 0.41 (Aug., 2004)

- Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing)

Version 0.5 (Nov., 2004)

- Deleted "preliminary"

- Added current value in page 9

Version 0.6 (Jan., 2005)

- Deleted the tDQSQA in page 11

- Deleted the tSSK in page 11

From To

F6 F6

tCK Clock Cycle Time (min) CL = 4 4.0 ns 4.0 ns

CL = 5 3.33 ns 3.5 ns

CL = 6 3.0ns 3.0ns

K4C89093AF

REV. 0.6 Jan. 2005

- 4 -

8,388,608-WORDS x 4 BANKS x 9-BITS DOUBLE DATA RATE Network-DRAM

DESCRIPTION

K4C89093AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89093AF is organized as

8,388,608-words x 4 banks x9 bits. K4C89093AF feature a fully synchronous operation referenced to clock edge whereby all operations

are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89093A F can operate

fast core cycle compared with regular DDR SDRAM.

K4C89093AF is suitable for Server, Network and other applications where large memory density and low power consumption are

required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.

FEATURES

• Fully Synchronous Operation

- Double Data Rate (DDR)

- Data input/output are synchronized with both edges of DS / QS.

- Differential Clock (CLK and CLK) inputs

- CS, FN and all address input signals are sampled on the positive edge of CLK.

- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.

• Fast clock cycle time of 3.0 ns minimum

- Clock : 333 MHz maximum

- Data : 666 Mbps/pin maximum

• Quad Independent Banks operation

• Fast cycle and Short Latency

• Uni-directional data Strobe

• Distributed Auto-Refresh cycle in 3.9us

• Power Down Mode

• Variable Write Length Control

• Write Latency = CAS Latency-1

• Programable CAS Latency and Burst Length

- CAS Laatency = 4, 5, 6

- Burst Length = 4

• Organization : 8,388,608 words x 4 banks x 9 bits

• Power Supply Voltage VDD : 2.5V ± 0.125V

• VDDQ : 1.4V ∼ 1.9V

• 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL

• Package : 60Ball BGA, 1mm x 1mm Ball pitch

• Notice : Network-DRAM is tradema rk of Samsung Electronics., Co LTD

Parameter K4C89093AF

F6 FB F5

tCK Clock Cycle Time (min) CL = 4 4.0 ns 4.5 ns 5.0 ns

CL = 5 3.5 ns 3.75 ns 4.5 ns

CL = 6 3.0ns 3.33 ns 4.0 ns

tRC Random Read/Write Cycle Time (min) 20.0 ns 22.5 ns 25 ns

tRAC Random Access Time (min) 20.0 ns 22.5 ns 25 ns

IDD1S Operating Current (single bank) (max) 320 300 280

IDD2P Power Down Current (max) 70 65 60

K4C89093AF

REV. 0.6 Jan. 2005

- 5 -

Pin Names

Pin Name

A0 ~ A14 Address Input

BA0, BA1 Bank Address

DQ0 ~ DQ8 Data Input/Output

CS Chip Select

FN Function Control

PD Power Down Control

CLK, CLK Clock Input

DS/QS Write/Read data strobe

VDD Power (+2.5V)

VSS Ground

VDDQ Power (+1.8V)

(for I/O buffer)

VSSQ Ground

(for I/O buffer)

VREF Reference Voltage

NC No Connection

ball pitch=1.0 x 1.0mm

PIN ASSIGNMENT (TOP VIEW)

Index

Vss

DQ6

DQ4

DQ8

VREF

CLK

A12

A11

VSS

DQ7

VssQ

VDDQ

DQ5

VssQ

VDDQ

VssQ

Vss

CLK

DQ0

VDDQ

VssQ

DQ2

VDDQ

VssQ

VDDQ

VDD

BA1

VDD

DQ1

DQ3

A14

A13

BA0

A10

VDD

123456

K4C89093AF

REV. 0.6 Jan. 2005

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Block Diagram

CLK

DLL

CLOCK

BUFFER

COMMAND

DECODER

CONTROL

GENERATOR

SIGNAL

ADDRESS

BUFFER

MODE

UPPER ADDRESS

LATCH

LOWER ADDRESS

LATCH

COLUMN DECODER

ROW DECODER

BANK #3

BANK #2

BANK #1

BANK #0

MEMORY

CELL

ARRAY

DATA

CONTROL AND LATCH

CIRCUIT

BURST

COUNTER

READ

DATA

BUFFER

WRITE

DATA

BUFFER

DQ BUFFER

A0 ~ A14

BA0, BA1

REFRESH

COUNTER

WRITE ADDRESS

LATCH

ADDRESS

COMPARATOR

DQ0 ~ DQ8

To Eac h Block

Note : The K4C89093AD configuration is 4 Bank of 65536 x 128 x 9 of cell array with the DQ pins numbered DQ0~DQ8.

K4C89093AF

REV. 0.6 Jan. 2005

- 7 -

Absolute Maximum Ratings

Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.

The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-

cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.

Recommended DC,AC Operating Conditions (Notes : 1) (Tcase = 0 ~ 85 OC)

Symbol Parameter Rating Units Notes

VDD Power Supply Voltage -0.3 ~ 3.3 V

VDDQ Power Supply Voltage (for I/O buffer) -0.3 ~ VDD + 0.3 V

VIN Input Voltage -0.3 ~ VDD + 0.3 V

VOUT DQ pin Voltage -0.3 ~ VDDQ + 0.3 V

VREF Input Reference Voltage -0.3 ~ VDDQ + 0.3 V

TOPR Operating Temperature 0 ~ 85 OCCase Temp.

TSTG Storage Temperature -55 ~ 150 OC

TSOLDER Soldering Temperature(10s) 260 OC

PDPower Dissipation 2 W

IOUT Short Circuit Output Current ± 50 mA

Symbol Parameter Min Typ Max Units Notes

VDD Power Supply V oltage 2.375 2.5 2.625 V

VDDQ Power Supply Voltage (for I/O Buffer) 1.7 1.8 1.9 V

VREF Input Reference Voltage VDDQ/2x95% VDDQ/2 VDDQ/2x105% V 2

VIH (DC) Input DC high Voltage VREF+0.125 - VDDQ+0.2 V 5

VIL(DC) Input DC Low Voltage -0.1 - VREF-0.125 V 5

VICK (DC) Differential Clock DC Input Voltage -0.1 - VDDQ+0.1 V 10

VID (DC) Input Differential Voltage. CLK and CLK Inputs (DC) 0.4 - VDDQ+0.2 V 7,10

VIH (AC) Input AC High Voltage VREF+0.2 - VDDQ+0.2 V 3,6

VIL (AC) Input AC Low Voltage -0.1 - VREF-0.2 V 4,6

VID (AC) Input Differential Voltage. CLK and CLK Inputs (AC) 0.55 - VDDQ+0.2 V 7,10

VX (AC) Differential AC Input Cross Point Voltage VDDQ/2-0.125 - VDDQ/2+0.125 V 8,10

VISO (AC) Differential Clock AC Middle Level VDDQ/2-0.125 - VDDQ/2+0.125 V 9,10

K4C89093AF

REV. 0.6 Jan. 2005

- 8 -

1. All voltages are referenced to Vss, VssQ.

2. VREF is expected to track variations in VddQ DC level of the transmitting device.

Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC).

3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns

4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns

5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.

6. VIH(AC) and VIL(AC) are levels to change to the new logic state.

7. VID is magnitude of the difference between CLK input level and CLK input level.

8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.

9. VISO means [VICK(CLK) + VICK(CLK)]/2

10. Refer to the figure below.

Notes:

11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V.

Pin Capacitance (VDD= 2.5V, VDDQ = 1.8V, f = 1 MHz, Ta = 25oC)

Note : These parameters are periodically sampled and not 100% tested.

Symbol Parameter Min Max Delts Units

CIN Input Pin Capacitance 1.5 3.0 0.25 pF

CINC Clock Pin (CLK, CLK) Capacitance 1.5 3.0 0.25 pF

CI/O DQ, DS, QS Capacitance 2.5 3.5 0.5 pF

CNC NC Pin Capacitance - 1.5 - pF

CLK

VSS

VID(AC)

0 V Differential

VISO

VSS

VICK

VISO(min)

VXVX

VICK VICK VICK

VISO(max)

VXVID(AC)

K4C89093AF

REV. 0.6 Jan. 2005

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DC Characteristics and Operating Conditions (VDD = 2.5V ± 0 .12 5V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)

Parameter Symbol Max Units Notes

F6 FB F5

Operating Current

One bank Read or Write operation;

tCK = min, IRC = min, IOUT = 0mA;

Burst Length = 4, CAS Latency = 6, Free running QS mode;

0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;

Address inputs change up to 2 times during minimum IRC,

Read data change twice per clock cycle

IDD1S 320 300 280

1, 2

Standby Current

All Banks : inactive state;

tCK=min, CS = VIH, PD = VIH;

0V ≤ VIN ≤ VIL(AC)(max.), V IH(AC)(min.) ≤ VIH ≤ VDDQ;

Other input signals change one time during 4*tCK,

DQ and DS inputs change twice per clock cycle

IDD2N 100 95 90 1

Standby (Power Down) Current

All Banks : inactive state;

tCK=min, PD = VIL (Power Down);

CAS Latency = 6, Free running QS mode;

0V ≤ VIN ≤ VIL(AC)(max), VIH(AC)(min) ≤ VIN ≤ VDDQ;

Other input signals change one time during 4*tCK,

DQ and DS inputs are floating(VDDQ/2)

IDD2P 70 65 60 1

Write Operating Current(4 Banks)

4 Bank intereaved continuous burst write operation;

tCK = min, IRC = min;

Burst Length = 4, CAS Latency = 6, Free running QS mode;

0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;

Address inputs change once per clock cycle,

DQ and DS inputs change twice per clock cycle

IDD4W 650 600 550 1

Read Operating Current(4 Banks)

4 Bank intereaved continuous burst write operation;

tCK = min, IRC = min, IOUT = 0mA;

Burst Length = 4, CAS Latency = 6, Free running QS mode;

0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;

Address inputs change once per clock cycle,

Read data change twice per clock cycle

IDD4R 650 600 550 1,2

Burst Auto-Refresh Current

Refresh command at every IREFC interval;

tCK = min, IREFC= min;

CAS Latency = 6, Free running QS mode;

0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC) (min.) ≤ VIN ≤ VDDQ;

Address change up to 2 times during minimum IREFC,

DQ and DS inputs change twice per clock cycle

IDD5B 250 235 210 1,3

K4C89093AF

REV. 0.6 Jan. 2005

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DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)

Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of

tCK, tRC and IRC.

2. These parameters depend on the output loading. The specified va lues are obtained with the output open.

3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification

4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.

Parameter Symbol Min Max Unit Notes

Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V) ILI -5 5 uA

Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ) ILO -5 5 uA

VREF Current IREF -5 5 uA

Normal O utput

Driver

Output DC Current

(VDDQ = 1.7 ~ 1.9V)

VOH = 1.420V IOH(DC) -5.6 -

VOL = 0.280V IOL(DC) 5.6 - 4

Strong Output

Driver VOH = 1.420V IOH(DC) -9.8 - 4

VOL = 0.280V IOL(DC) 9.8 - 4

Weak Output

Driver VOH = 1.420V IOH(DC) -2.8 - 4

VOL = 0.280V IOL(DC) 2.8 -

Normal O utput

Driver

Output DC Current

(VDDQ = 1.4 ~ 1.6V)

VOH = VDDQ - 0.4 IOH(DC) -4 -

VOL = 0.4V IOL(DC) -4 - 3

Strong Output

Driver VOH = VDDQ - 0.4 IOH(DC) -8 - 3

VOL = 0.4V IOL(DC) -8 - 3

Weak Output

Driver Not defined IOH(DC) --

Not defined IOL(DC) --

K4C89093AF

REV. 0.6 Jan. 2005

- 11 -

AC Characteristics and Operating Conditions (Notes : 1, 2)

Symbol Parameter F6 FB F5 Units Notes

Min Max Min Max Min Max

tRC Random Cycle Time 20.0 - 22.5 - 25 -

tCK Clock Cycle Time

CL = 4 4.0 6.0 4.5 6.0 5.0 6.0 3

CL = 5 3.33 6.0 3.75 6.0 4.5 6.0 3

CL = 6 3.0 6.0 3.33 6.0 4.0 6.0 3

tRAC Random Access Time - 20.0 - 22.5 - 25 3

tCH Clock High Time 0.45*tCK -0.45*tCK -0.45*tCK -3

tCL Clock Low Time 0.45*tCK -0.45*tCK -0.45*tCK -3

tCKQS QS Access Time from CLK -0.45 0.45 -0.45 0.45 -0.5 0.5 3, 8

tQSQ Data Output Skew from QS - 0.2 - 0.25 - 0.3 4

tAC Data Access Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8

tOH Data Output Hold Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8

tHP CLK half period ( minium of Actual tCH, tCL)min(tCH,

tCL)-min(tCH,

tCL)-3

tQSP QS(Read) Pulse Widt h tHP-tQHS -tHP-tQHS -tHP-tQHS -4, 8

tQSQV Data Output Valid Time from QS tHP-tQHS -tHP-tQHS -tHP-tQHS -4, 8

tQHS DQ, QS Hold skew factor - 0.055x

tCK+0.17 -0.055x

tCK+0.17

tDQSS DS(Write) Low to High Setup Time 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK 3

tDSPRE DS(Write) Preamble Pulse Width 0.4*tCK -0.4*tCK -0.4*tCK -4

tDSPRES DS First Input Setup Time 0 - 0 - 0 - 3

tDSPREH DS First Low Input Hold Time 0.3*tCK -0.3*tCK -0.3*tCK -3

tDSP DS High or Low Input Pulse Width 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 4

tDSS DS Input Falling Edge to Clock Setup

Time

CL = 4 0. 75 - 0.8 - 1.0 - 3, 4

CL = 5 0. 75 - 0.8 - 1.0 - 3, 4

CL = 6 0. 75 - 0.8 - 1.0 - 3, 4

CL = 7 ------ 3, 4

tDSPST DS(Wri te) Postamble Pulse Width 0.45*tCK -0.45*tCK 0.45*tCK -4

tDSPSTH DS(Write) Postamble Hold Time

CL = 4 0. 75 - 0.8 - 1.0 - 3, 4

CL = 5 0. 75 - 0.8 - 1.0 - 3, 4

CL = 6 0.75 - 0.8 - 1.0 3, 4

CL = 7 ------ 3, 4

tDS Data Input Setup Time from DS 0.3 - 0.35 - 0.4 - 4

tDH Data Input Hold Time from DS 0.3 - 0.35 - 0.4 - 4

tIS Command / Address Input Setup Time 0.6 - 0.6 - 0.7 - 3

tIH Command / Address Input Hold Time 0.6 - 0.6 - 0.7 - 3

K4C89093AF

REV. 0.6 Jan. 2005

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AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)

Symbol Parameter F6 FB F5 Units Notes

Min Max Min Max Min Max

tLZ Data-out Low Impedance Time from CLK -0.5 - -0.5 - -0.6 - 3, 6, 8

tHZ Data-out High Impedance Time from CLK - 0.5 - 0.5 - 0.6 3, 7, 8

tQPDH Last Output to PD High Hold Time 0 - 0 - 0 -

tPDEX Power Down Exit Time 0.6 - 0.6 - 0.7 - 3

tTInput Transition Time 0.1 1 0.1 1 0.1 1

tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3. 9 us 5

tPAUSE Pause Time after Power-up 200 - 200 - 200 -

IRC Random Read/Write Cycle Time

(Applicable to Same Bank)

CL = 4 5-5-5-

Cycle

CL = 5 6-6-6-

CL = 6 7-7-7-

CL = 7 ------

IRCD RDA/WRA to LAL Command Input Delay

(Applicable to Same Bank) 111111

IRAS LAL to RDA/WRA Command Input Delay

(Applicable to Same Bank)

CL = 4 4-4-4-

CL = 5 5-5-5-

CL = 6 6-6-6-

CL = 7 ------

IRBD Random Bank Access Delay

(Applicable to Other Bank) 2-2-2-

IRWD LAL following RDA to WRA Delay

(Applicable to Other Bank) BL = 4 3 - 3 - 3 -

IWRD LAL following WRA to RDA Delay

(Applicable to Other Bank) 1-1-1-

IRSC Mode Register Set Cycle Time

CL = 4 7-7-7-

CL = 5 7-7-7-

CL = 6 7-7-7-

CL = 7

IPD PD Low to Inactive State of Input Buffer - 2 - 2 - 2

IPDA PD High to Active State of Inp ut Buffer 1 - 1 - 1 -

IPDV Power down mode valid from REF com-

mand

CL = 4 19 - 19 - 19 -

CL = 5 23 - 23 - 23 -

CL = 6 25 - 25 - 25 -

CL = 7

IREFC Auto-Refresh Cycle Time

CL = 4 19 - 19 - 19 -

CL = 5 23 - 23 - 23 -

CL = 6 25 - 25 - 25 -

CL = 7

ILOCK DLL Lock-on Time (Applicable to RDA command) 200 - 200 - 200 -

K4C89093AF

REV. 0.6 Jan. 2005

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AC Test Conditions

Symbol Parameter Value Units Notes

VIH(min) Input high voltage (minimum) VREF + 0.2 V

VIL (max) Input low voltage (maximum) VREF - 0.2 V

VREF Input re ference volt ag e VddQ/2 V

VTT Termination voltage VREF V

VSWING Input signal peak to peak swing 0.7 V

VRDifferential clock input reference level VX(AC) V

VID(AC) Input differential voltage 1.0 V

SLEW Input signal minimum slew rate 2.5 V/ns

VOTR Output timing measurement reference voltage VddQ/2 V 9

VIH min(AC)

VREF

VIL max(AC)

VSWING

VddQ

Vss

VTT

Output

Slew=(VIHmin(AC) - VILmax(AC))/∆T

∆T∆T

Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC).

Transition (rise and fall) of input signals have a fixed slope.

2. If the result of nominal calculation with regard to tCK contains more than

one decimal place, the result is rounded up to the nearest decimal place.

(i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)

3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.

4. These parameters are measured from signal transition poin t of DS crossing VREF level.

5. The tREFI (MAX.) applies to equally distributed refresh method.

The tREFI (MIN.) applies to both burst refresh method and distributed refresh method.

In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always . In

other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the

maximum.

6. Low Impedance State is speifie d at VddQ/2± 0.2V fro m stead y state.

7. High Impedance State is specified where output buffer is no longer driven.

8. These parameters depend on the clock jitter. These parameters are measured at stable clock.

9. Output timing is measured by using Normal driver strength at VDDQ = 1.7V ~ 1.9V.

Output timing is measured by using Strong driver strength at VDDQ = 1.4V ~ 1.6V

AC Test Load

25 Ω

Measurement Point

K4C89093AF

REV. 0.6 Jan. 2005

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Power Up Sequence

1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.

2. Apply VDD before or at the same time as VDDQ.

3. Apply VDDQ before or at the same time as VREF.

4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).

5. After stable power and clock, apply DESL and take PD = H.

6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)

7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)

8. Issue two or more Auto-Refresh commands. (Note:1)

9. Ready for normal operation after 200 clocks from Extended Mode Register programming.

Note : 1. Sequence 6, 7 and 8 can be issued in random order.

2. L=Logic Low, H = Logic High

DESL RDA MRS DESL RDA MRS DESL WRA REF WRA REFDESL DESL

EMRS MRS

op-code op-code

VDD

VDDQ

VREF

CLK

Command

Address

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

∼∼

∼

200 µs(min) IPDA lRSC lRSC lREFC

2.5V(TYP)

1.8V(TYP)

0.9V(TYP)

lREFC

tPDEX

200 clock cycle(min)

EMRS

Hi-Z

(Free Running mode)

(Uni-QS mode)

MRS Auto Refresh cycle Normal Operation

∼

Low

K4C89093AF

REV. 0.6 Jan. 2005

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tCK

tCK tCH tCL

tIS tIH

tIPW

1st

tIS tIH

2nd

tIS tIH

1st

tIS tIH

2nd

tIPW

tIS tIH

UA, BA

tIS tIH

tDS tDH

CLK

A0-A14

BA0.BA1

DQn (Input)

Basic Timing Diagrams

Timing of the CLK, CLK

Input Timing

tCH tCL

tCK

tTtT

VIH

VIH(AC)

VIL(AC)

VIL

CLK

VIH

VIL

VID(AC)

VXVXVX

Command and Address

tDH

tDS

tDS tDH

DQm (Input)

tDH

tDS

Data

Refer to the Command Truth Table.

K4C89093AF

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LAL

(after RDA)

tIS tIH

tCH tCL tCK

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

Low

High-Z

Input

(Control &

Addresses)

CAS latency = 4

LQS/UQS

(Output)

Read Timing (Burst Length = 4)

Low

DESL

LDS/UDS

(Input)

Q1 Q2 Q3

tAC tAC tOH

0123456789101112131415161718

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

Low

High-Z

CAS latency = 5

LQS/UQS

(Output)

Low

Q1 Q2 Q3

tAC tAC tOH

Note : DQ0 to DQ17 are aligned with LQS.

Unidirectional DS/QS mode

DQ18 to DQ35 are aligned with UQS.

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

Low

High-Z

CAS latency = 6

LQS/UQS

(Output)

Low

Q1 Q2 Q3

tAC tAC tOH

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- 17 -

LAL

(after RDA)

tIS tIH

tCH tCL tCK

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

High-Z

Input

(Control &

Addresses)

CAS latency = 4

LQS/UQS

(Output)

Read Timing (Burst Length = 4)

DESL

LDS/UDS

(Input)

Q1 Q2 Q3

tAC tAC tOH

0123456789101112131415161718

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

High-Z

CAS latency = 5

LQS/UQS

(Output)

(Output) Q1 Q2 Q3

tAC tAC tOH

Note : DQ0 to DQ17 are aligned with LQS.

LQS/UQS is always asserted in Free Running QS mode.

Unidirectional DS/Free Running QS mode

DQ18 to DQ35 are aligned with UQS.

tCKQS

tCKQS tQSP tQSP

tCKQS

tQSQ

tLZ tQSQV

tAC

tQSQV

tQSQ

tHZ

tQSQ

High-Z

CAS latency = 6

LQS/UQS

(Output)

(Output) Q1 Q2 Q3

tAC tAC tOH

K4C89093AF

REV. 0.6 Jan. 2005

- 18 -

tDSPSTH

LAL

(after RDA)

tIS tIH

tCH tCL tCK

Input

(Control &

Addresses)

Write Timing (Burst Length = 4)

DESL

0123456789101112131415161718

tDSP

tDQSS

tDSP tDSP

tDSS

tDH

Q1 Q2 Q3

tDSPREStDSPREH tDSPST

tDSS

tDSPSTH

PostamblePreamble

tDSPRE tDS tDS

tDH

tDQSS

tDH

tDS

CAS latency = 4

LDS/UDS

(Input)

tDSP tDSP tDSP

tDH

Q1 Q2 Q3

tDSPREStDSPREH tDSPST

tDSS

PostamblePreamble tDSPRE

tDS tDS

tDH tDH

tDS

CAS latency = 5

LDS/UDS

(Input)

tDSS

LQS/UQS

(Uni-QS)

LQS/UQS

(Free Runninig)

Low

Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode

Note : DQ0 to DQ17 are sampled at both edges of LDS.

DQ18 to DQ35 are sampled at both edges of UDS.

tDSPSTH

tDQSS

tDSP tDSP tDSP

tDH

Q1 Q2 Q3

tDSPREStDSPREH tDSPST

tDSS

PostamblePreamble tDSPRE

tDS tDS

tDH tDH

tDS

CAS latency = 6

LDS/UDS

(Input)

tDSS

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Command

CLK

Input

(Control &

Addresses)

tIS tIH

tREFI, tPAUSE, Ixxxx Timing

tIS tIH

Command

tREFI,tPAUSE,IXXXX

Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.

K4C89093AF

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Function Truth Table (Notes : 1,2,3)

Command Truth Table (Notes : 4)

•The First Command

Symbol Function CS FN BA1-BA0 A14-A9 A8 A7 A6-A0

DESL Device Dese lect H X X X X X X

RDA Read with Auto-close L H BA UA UA UA UA

WRA Write with Auto-close L L BA UA UA UA UA

•The Second Command (The next clock of RDA or WRA command)

Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address,

LA = Lower Address.

2. All commands are assumed to issue at a valid state.

3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where

CLK goes to High.

4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the

command table below.

Symbol Function CS FN BA1-BA0 A14-A13 A12-A11 A10-A9 A8 A7 A6-A0

LAL Lower Address Latch H X X V X X X LA LA

REF Auto-Refresh L X X X X X X X X

MRS Mode Register Set L X V L L L L V V

Read Command Table

Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes

RDA (1st) L H BA UA UA UA UA

LAL (2nd) H X X X X LA LA

Write Command Table

Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.

Command (Symbol) CS FN BA1-

BA0 A14 A13 A12 A11 A10~

A9 A8 A7 A6-A0

WRA (1st) L L BAUAUAUAUAUAUAUAUA

LAL (2nd) HXXVW0VW1XXXXLALA

VW Truth Table

Function VW0 VW1

BL = 4

Reserved L L

Write All Words H L

Write First Tw o Words L H

Write First O ne Word H H

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Auto-Refresh Command Table

Function Command

(Symbol) Current

State

PD CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes

n-1 n

Active WRA(1st) Standby H H L L X X X X X

Auto-Refresh REF(2nd) Active H H L X X X X X X

Power Down Table

Notes : 7. PD has to be brought to Low within tFPDL from REF command.

8. PD should be brought to Low after DQ’s state turned high impedance.

9. When PD is brought to High from Low, this function is executed asynchronously.

Function Command

(Symbol) Current

State

PD CS FN BA1-

BA0 A14-A9 A8 A7 A6-A0 Notes

n-1 n

Power Down Entry PDEN Standby H L H X X X X X X 8

Power Down Continue - Power Down L L X X X X X X X

Power Down Exit PDEX Power Down L H H X X X X X X 9

Mode Register Set Command Truth Table

Note : 6. Refer to "Mode Register Table".

Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes

RDA (1st) L H X X X X X

MRS (2nd) L X V L L V V 6

Function Truth Table (Continued)

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Function Truth Table (Continued)

Notes : 10. Illegal if any bank is not idle.

11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).

12. Illegal if tFPDL is not Stisfied.

Current State PD CS FN Address Command Action Notes

n-1 n

Idle

H H H X X DESL NOP

H H L H BA, UA RDA Row activate for Read

H H L L BA, UA WRA Row acti vate for Write

H L H X X PDEN Power Down Entry 10

H L L X X - Illegal

L X X X X - Refer to Power Down state

Row Active for Read

H H H X LA LAL Begin read

H H L X Op-Code MRS/EMRS Access to Mode Register

H L H X X PDEN Illegal

H L L X X MRS/EMRS Illegal

L X X X X - Invalid

Row Active for Write

H H H X LA LAL Begin Write

H H L X X REF Auto-Refresh

H L H X X PDEN Illegal

H L L X X REF (Self) Self-Refresh entry

L X X X X - Invalid

Read

H H H X X DESL Continue burst read to end

H H L H BA, UA RDA Illegal 11

H H L L BA, UA WRA Illegal 11

H L H X X PDEN Illegal

H L L X X - Illegal

L X X X X - Invalid

Write

H H H X X DESL Data write & continue burst write to end

H H L H BA, UA RDA Illegal 11

H H L L BA, UA WRA Illegal 11

H L H X X PDEN Illegal

H L L X X - Illegal

L X X X X - Invalid

Auto-Refreshing

H H H X X DESL NOP-> Idle after IREFC

H H L H BA, UA RDA Illegal

H H L L BA, UA WRA Illegal

H L H X X PDEN Self-Refresh entry 12

H L L X X - Illegal

L X X X X - Refer to Self-Refreshing state

Mode Register Accessing

H H H X X DESL Nop-> Idle after IRSC

H H L H BA, UA RDA Illegal

H H L L BA, UA WRA Illegal

H L H X X PDEN Illegal

H L L X X - Illegal

L X X X X - Invalid

Power Down

H X X X X - Invalid

L L X X X - Maintain Power Down Mode

L H H X X RDEX Exit Power Down Mode->Idle after tPDEX

L H L X X - Illegal

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Mode Register Table

Regular Mode Register (Notes : 1)

Address BA1*1 BA0*1 A14-A8 A7*3 A6-A4 A3 A2-A0

A7 Test Mode (TE)

0 Regular (Default)

1 Test Mode Entry

A3 Burst Type (BT)

0 Sequential

1 Interleave

A6 A5 A4 CAS Latency (CL)

00X Reserved *2

010 Reserved *2

011 Reserved *2

100 4

101 5

110 6

111 Reserved *2

A2 A1 A0 Burst Length (BL)

000 Reserved *2

001

010 4

011 Reserved *2

1XX

Extended Mode Register (Notes : 4)

Address BA1*4 BA0*4 A14-A7 A6~A5 A4-A3 A2~A1 A0*5

QS DQ Output Driver Impedance Control

(DIC)

A4 A3 A2 A1

0000 Normal Output Driver

0101 Strong Output Driver

1010 Weak Output Driver

1111 Reserved

A0 DLL Switch (DS)

0 DLL Enab le

1 DLL Disable

Note : 1 . Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0.

2. "Reserved" places in Regular Mode Register should not be set.

3. A7 in Regular Mode Register must be set to "0"(Low state).

Because Test Mode is specific mode for supplier.

4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.

5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.

A6 A5 Strobe Select

00 Reserved*2

01 Reserved*2

1 0 Unidirectional DS/QS

1 1 Unidirectional DS/Free Running QS

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State Diagram

Power

Down

Standby

(Idle)

Mode

Auto-

Refresh

Active

(Restore) Active

Write

(Buffer) Read

PDEX

(PD = H)

PD = H

LALLAL

REF MRS

RDAWRA

PDEN

(PD = L)

The second command at Active

state must be issued 1clock after

RDA or WRA command input

Command Input

Automatic Return

- 25 -

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Timing Diagrams

Single Bank Read Timing (CL=4)

CLK

Command

Address

RDA DESLLAL RDA DESLLAL RDA DESLLAL RDA

LAUA LAUA LAUA UA

#0 #0 #0 #0

Unidirectional DS/QS mode

Bank Add.

(Output)

(Input)

Unidirectional DS/Free Running QS mode

(Output)

(Input)

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0

lRC=5cycles lRC=5cycles lRC=5cycles

lRCD=1cycle lRAS=4cycles lRCD=1cycle lRAS=4cycles lRCD=1cycle lRAS=4cycles

Low

CL=4

Hi-Z

CL=4 CL=4

CL=4

Hi-Z

CL=4 CL=4

- 26 -

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Single Bank Read Timing (CL=5)

Command

Address

RDA DESLLAL

Unidirectional DS/QS mode

Bank Add.

(Output)

(Input)

Unidirectional DS/Free Running QS mode

(Output)

(Input)

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

lRC=6cycles

Low

Hi-Z

RDA DESLLAL

lRC=6cycles

RDA DESLLAL

UA LA

lRAS=5cycleslRCD=1cycle lRAS=5cycleslRCD=1cycle

UA LA

lRCD=1cycle

UA LA

#0 #0

CL=5 CL=5

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

Hi-Z

CL=5 CL=5

CLK

- 27 -

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Single Bank Read Timing (CL=6)

Command

Address

RDA DESLLAL

Unidirectional DS/QS mode

Bank Add.

(Output)

(Input)

Unidirectional DS/Free Running QS mode

(Output)

(Input)

Q0 Q1 Q2 Q3 Q0 Q1 Q2

lRC=7cycles

Low

Hi-Z

UA LA

lRAS=6cycleslRCD=1cycle

CL=6 CL=6

RDA DESLLAL

lRC=7cycles

RDA LAL

UA LA

lRAS=6cycleslRCD=1cycle

UA LA

#0 #0

Q0 Q1 Q2 Q3 Q0 Q1 Q2

Hi-Z

CL=6 CL=6

lRCD=1cycle

CLK

- 28 -

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Single Bank Write Timing (CL=4)

Command

Address

WRA DESLLAL WRA DESLLAL WRA DESLLAL WRA

LAUA LAUA LAUA UA

#0 #0 #0 #0

Unidirectional DS/QS mode

Bank Add.

Unidirectional DS/Free Running QS mode

(Output)

(Input)

lRC=5cycles lRC=5cycles lRC=5cycles

lRCD=1cycle lRAS=4cycles lRCD=1cycle lRAS=4cycles lRCD=1cycle lRAS=4cycles

(Output)

(Input)

D0 D1

Low

WL=3 WL=3

D2 D3 D0 D1 D2 D3

WL=3

D0 D1 D2 D3

D0 D1

WL=3 WL=3

D2 D3 D0 D1 D2 D3

WL=3

D0 D1 D2 D3

CLK

- 29 -

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Single Bank Write Timing (CL=5)

Command

Address

WRA DESLLAL

LAUA

Unidirectional DS/QS mode

Bank Add.

Unidirectional DS/Free Running QS mode

(Output)

(Input)

lRC=6cycles

lRCD=1cycle lRAS=5cycles

(Output)

(Input)

D0 D1

Low

D2 D3

WRA DESLLAL

lRC=6cycles

WRA DESLLAL

LAUA

lRCD=1cycle lRAS=5cycles

LAUA

lRCD=1cycle

#0 #0

D0 D1 D2 D3

WL=4 WL=4

D0 D1 D2 D3 D0 D1 D2 D3

WL=4 WL=4

CLK

- 30 -

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Single Bank Write Timing (CL=6)

Command

Address

WRA DESLLAL

LAUA

Unidirectional DS/QS mode

Bank Add.

Unidirectional DS/Free Running QS mode

(Output)

(Input)

lRC=7cycles

lRCD=1cycle lRAS=6cycles

(Output)

(Input)

D0 D1

Low

D2 D3

WRA DESLLAL

LAUA

lRC=7cycles

lRCD=1cycle lRAS=6cycles

WRA LAL

LAUA

lRCD=1cycle

#0 #0

D0 D1 D2 D3

WL=5 WL=5

D0 D1 D2 D3 D0 D1 D2 D3

WL=5 WL=5

CLK

- 31 -

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Single Bank Read-Write Timing (CL=4)

Command

Address

RDA DESLLAL WRA DESLLAL RDA DESLLAL WRA

LAUA LAUA LAUA UA

#0 #0 #0 #0

Unidirectional DS/QS mode

Bank Add.

Unidirectional DS/Free Running QS mode

(Output)

(input)

lRC=5cycles lRC=5cycles lRC=5cycles

(Output)

(input)

Q0 Q1 Q2 Q3

CL=4 CL=4WL=3

Low

D0 D1 D2 D3 Q0

Q0 Q1 Q2 Q3

CL=4 CL=4WL=3

D0 D1 D2 D3 Q0

Hi-Z

CLK

- 32 -

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Single Bank Read-Write Timing (CL=5)

Unidirectional DS/QS mode

Bank Add.

Unidirectional DS/Free Running QS mode

(Output)

(input)

(Output)

(input)

Q0 Q1 Q2 Q3

Low

D0 D1 D2 D3

Hi-Z

Command

Address

RDA DESLLAL

LAUA

lRC=6cycles

WRA DESLLAL

lRC=6cycles

RDA DESLLAL

LAUA LAUA

#0 #0 #0

CL=5 WL=4

Q0 Q1 Q2 Q3 D0 D1 D2 D3

Hi-Z

CL=5 WL=4

Read data Write data

CLK

- 33 -

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Single Bank Read-Write Timing (CL=6)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Q0 Q1 Q2 Q3

Low

D0 D1 D2 D3

Hi-Z

CL=6 WL=5

Read data Write data

Command

Address

RDA DESLLAL

LAUA

Bank Add.

lRC=7cycles

WRA DESLLAL

LAUA

lRC=7cycles

RDA LAL

LAUA

#0 #0

(Output)

(input)

(Output)

(input)

Q0 Q1 Q2 Q3 D0 D1 D2 D3

Hi-Z

CL=6 WL=5

CLK

- 34 -

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Multiple Bank Read Timing (CL=4)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

RDA LAL

LAUA

Bank

Bank Add.

RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA

LAUA LAUA LAUA LAUA LAUA LAUA UA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a" Bank

"b"

lRBD=2cycles

Qa0Qa1

CL=4

Low

Hi-Z

(Output)

(input)

Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0 Qc1

CL=4

(Output) Qa2Qa3 Qb2Qb3 Qa2 Qa3 Qb2Qb3 Qc2

Qa0Qa1

CL=4

Hi-Z

(Output)

(input)

Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0 Qc1

CL=4

(Output) Qa2Qa3 Qb2Qb3 Qa2 Qa3 Qb2Qb3 Qc2

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=5cycles

lRC(Bank"b")=5cycles

CLK

Note : lRC to the same bank must be satisfied

- 3 5 -

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Multiple Bank Read Timing (CL=5)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

RDA LAL

LAUA

Bank

Bank Add.

RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL

LAUA LAUA LAUA LAUA LAUA LAUA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a"

lRBD=2cycles

Qa0Qa1

Low

Hi-Z

(Output)

(input)

Qb0Qb1 Qa0Qa1 Qb0Qb1

(Output) Qa2Qa3 Qb2 Qb3 Qa2 Qa3 Qb2

(Output)

(input)

(Output)

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=6cycles

lRC(Bank"6")=6cycles

CL=5

Qa0Qa1

Hi-Z Qb0Qb1 Qa0Qa1 Qb0Qb1Qa2Qa3 Qb2Qb3 Qa2Qa3 Qb2

CL=5

CLK

Note : lRC to the same bank must be satisfied

- 36 -

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Multiple Bank Read Timing (CL=6)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

RDA LAL

LAUA

Bank

Bank Add.

RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA

LAUA LAUA LAUA LAUA LAUA UA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a"

lRBD=2cycles

Qa0 Qa1

Low

Hi-Z

(Output)

(input)

Qb0Qb1 Qa0Qa1

(Output) Qa2Qa3 Qb2 Qb3 Qa2

(Output)

(input)

(Output)

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=7cycles

lRC(Bank"b")=7cycles

CL=6

Qa0 Qa1

Hi-Z Qb0Qb1 Qa0Qa1Qa2Qa3 Qb2 Qb3 Qa2

CL=6

CLK

Note : lRC to the same bank must be satisfied

- 37 -

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Multiple Bank Write T iming (CL=4)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

WRA LAL

LAUA

Bank

Bank Add.

WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA

LAUA LAUA LAUA LAUA LAUA LAUA UA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a" Bank

"b"

lRBD=2cycles

Da0 Da1

Low

(Output)

(input)

Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1

(Input) Da2 Da3 Db2 Db3 Da2 Da3 Db2 Db3 Dc2

(Output)

(input)

(Input)

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=5cycles

lRC(Bank"b")=5cycles

Dc3 Dd0 Dd1

WL=3

Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1Da2 Da3 Db2 Db3 Da2 Da3 Db2 Db3 Dc2 Dc3 Dd0 Dd1

WL=3

CLK

Note : lRC to the same bank must be satisfied

- 38 -

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Multiple Bank Write T iming (CL=5)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

Bank Add.

Da0 Da1

Low

(Output)

(input)

Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1

(input) Da2 Da3 Db2 Db3 Da2 Da3 Db2 Db3

(Output)

(input)

WRA LAL

LAUA

Bank

WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL

LAUA LAUA LAUA LAUA LAUA LAUA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a"

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=6cycles

lRC(Bank"b")=6cycles

WL=4

Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1Da2 Da3 Db2 Db3 Da2 Da3 Db2 Db3

WL=4

Note :IRC to the same bank must be satisf ie d.

CLK

- 39 -

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Multiple Bank Write T iming (CL=6)

Unidirectional DS/QS mode

Unidirectional DS/Free Running QS mode

Command

Address

Bank Add.

Da0 Da1

Low

(Output)

(input)

Db0 Db1 Da0 Da1 Db0 Db1

(input) Da2 Da3 Db2 Db3 Da2 Da3

(Output)

(input)

WL=5

Note :IRC to the same bank must be satisfied.

WRA LAL

LAUA

Bank

WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA

LAUA LAUA LAUA LAUA LAUA UA

"a" Bank

"b" Bank

"a" Bank

"b" Bank

"c" Bank

"d" Bank

"a"

lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles lRBD=2cycles

lRC(Bank"a")=7cycles

Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1Da2 Da3 Db2 Db3 Da2 Da3

WL=5

CLK

- 40 -

K4C89093AF

0 234567891011112 13 14 15

REV. 0.6 Jan. 2005

WL=3 CL=4

Low

Unidirectional DS/QS mode

Da0 Da1 Qb0Qb1

Hi-Z Da2 Da3 Qb2Qb3 Da0 Da1 Qb0Qb1Da2 Da3 Qb2Qb3

Low

Da0 Da1 Qb0Qb1

Hi-Z Da2 Da3 Qb2Qb3 Da0 Da1 Qb0Qb1Da2 Da3 Qb2Qb3

Low

Da0 Da1 Qb0 Qb1

Hi-Z Da2 Da3 Qb2Qb3 Da0 Da1 Qb0Qb1

Da2 Da3

WL=4 CL=5

WL=5 CL=6

CL =4

(Output)

(Input)

(Output)

CL =5

(Output)

(Input)

(Output)

CL =6

(Output)

(Input)

(Output)

Multiple Bank Read-Write Timing (BL=4)

Command

Address

WRA LAL

LAUA

Bank

Bank Add.

RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL

LAUA LAUA LAUA UA UALA LA

"a" Bank

"b" Bank

"c" Bank

"d"

lRBD=2cycles

Bank

"a" Bank

"b"

lRC(Bank"a")

lWRD=1cycle lRWD=3cycles lWRD=1cycle lRWD=3cycles lWRD=1cycle

Note :IRC to the same bank must be satisfied.

CLK

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K4C89093AF

0 234567891011112 13 14 15

REV. 0.6 Jan. 2005

Multiple Bank Read-Write Timing (BL=4)

Command

Address

WRA LAL

LAUA

Bank

Bank Add.

RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL

LAUA LAUA LAUA UA UALA LA

"a" Bank

"b" Bank

"c" Bank

"d"

lRBD=2cycles

Bank

"a" Bank

"b"

lRC(Bank"a")

Unidirectional DS/Free Running QS mode

lWRD=1cycle lRWD=3cycles lWRD=1cycle lRWD=3cycles lWRD=1cycle

WL=3 CL=4

Da0 Da1 Qb0 Qb1

Hi-Z Da2 Da3 Qb2 Qb3 Da0 Da1 Qb0 Qb1Da2 Da3 Qb2 Qb3

Da0 Da1 Qb0Qb1

Hi-Z Da2 Da3 Qb2Qb3 Da0 Da1 Qb0Qb1Da2 Da3 Qb2Qb3

Da0 Da1 Qb0 Qb1

Hi-Z Da2 Da3 Qb2Qb3 Da0 Da1 Qb0Qb1Da2 Da3

WL=4 CL=5

WL=5 CL=6

Note :IRC to the same bank must be satisfied.

CLK

CL =4

(Output)

(Input)

(Output)

CL =5

(Output)

(Input)

(Output)

CL =6

(Output)

(Input)

(Output)

K4C89093AF

- 42 - REV. 0.6 Jan. 2005

Write with Variable Write Length (VW) Control(CL=4)

Command WRA LAL DESL WRA LAL

BL=2, SEQUENTIAL MODE

DESL

Address UA LA=#3 UA

VW=All LA=#1

VW=1

Bank Add. Bank Bank

"a"

(Input)

D0 D1 D0

Lower Address #3 #2 #1 (#0)

Last one data is masked.

Command WRA LAL DESL WRA LAL

BL=4, SEQUENTIAL MODE

DESL

Address UA LA=#3 UA

VW=All LA=#1

VW=1

Bank Add. Bank

"a"

(Input)

D0 D1 D0

Lower Address #3 #0 #1 #2 #1 (#2) (#3) (#0)

Last three data are masked.

Bank

"a"

DESL WRA LAL

UA LA=#2

VW=2

Bank

"a"

D2 D3 D0 D1

#2 #3 (#0) (#1)

Last two data are masked.

Note : DS input must be continued till end of burst count even if some of laster data is masked.

0 234567891011112 13 14 15

CLK

VW0 = Low

VW1 = don’t care VW0 = High

VW1 = don’t care

"a"

VW0 = High

VW1 = Low VW0 = High

VW1 = High VW0 = Low

VW1 = High

K4C89093AF

- 43 - REV. 0.6 Jan. 2005

Power Down Timing (CL=4, BL=4)

Command RDA LAL RDA

BL=2, SEQUENTIAL MODE

Address UA UA

DESL or

WRA

Unidirectional DS/Free Running QS mode

Unidirectional DS/QS mode

tIH

tQPDH tPDEX

tIS IPD=2 cycle

IRC(min), tREFI(max)

Q0 Q1

Low

Hi-Z

(Output)

(input)

(Output)

CL=4

Q2 Q3

Q0 Q1

Hi-Z

(Output)

(input)

(Output)

CL=4

Q2 Q3

Hi-Z

PD must be kept "High" level until end of Burst data output.

PD should be brought to "High" within t REFI(max.) to maintain the data written into cell.

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied IPDA cycles later.

Note :

Power Down Entry Power Down Exit

∼

0 2345678910n-11nn+1n+2n+3

∼

∼∼

∼

∼∼

∼

∼∼

∼

CLK

Read cycle to Power Down Mode

DESL

IPDA

K4C89093AF

- 44 - REV. 0.6 Jan. 2005

Power Down Timing (CL=4, BL=4)

Command WRA LAL

Address UA

DESL

Unidirectional DS/Free Running QS mode

Unidirectional DS/QS mode

tIH

tPDEX

tIS IPD=2 cycle

IRC(min), tREFI(max)

Low

(Output)

(input)

(Output)

WL=3

(Output)

(input)

(Output)

D0 D1 D2 D3

WL=3 IPD=2 cycle

D0 D1 D2 D3

WL=3

PD must be kept "High" level until end of Burst data output.

PD should be brought to "High" within t REFI(max.) to maintain the data written into cell.

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied IPDA cycles later.

Note :

0 2345678910n-11nn+1n+2n+3

IPDA

∼

∼∼

∼

∼∼

∼

Write cycle to Power Down Mode

CLK

RDA

WRA

DESL

K4C89093AF

- 45 - REV. 0.6 Jan. 2005

0 234567891011112 13 14 15

Mode Register Set Timing (CL=4, BL=4)

Command

A14~A0

WRA DESLLAL

LAUA

BA0, BA1

RDA DESLMRS

lRC=7cycles

LAL

LAUA

BA1="0" BA

RDA

WRA

BA0="0"

(opcode)

Valid

From Write operation to Mode Register Set operation

Unidirectional DS/Free Running QS mode

(Output)

(input)

(Output)

(input)

Low

(Output)

(input)

(Output)

(input)

D0 D1 D2 D3

Unidirectional DS/QS mode

(input)

Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.

CLK

WL + BL/2

K4C89093AF

- 46 - REV. 0.6 Jan. 2005

Extended Mode Register Set Timing (CL=4, BL=4)

Command

A14~A0

WRA DESLLAL

LAUA

BA0, BA1

RDA DESLMRS

lRC=7cycles

LAL

LAUA

BA1="0" BA

RDA

WRA

BA0="0"

(opcode)

Valid

From Write operation to Extended Mode Register Set operation

When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period.

DLL switch in Extended Mode Register must be set to enable mode for normal operation.

DLL lock-on time is ne ed ed after initi al EMR S ope ration. See Power Up Sequen ce .

Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.

Note :

Unidirectional DS/Free Running QS mode

(Output)

(input)

(Output)

(input)

Low

(Output)

(input)

(Output)

(input)

D0 D1 D2 D3

Unidirectional DS/QS mode

(input)

0 234567891011112 13 14 15

CLK

WL + BL/2

K4C89093AF

- 47 - REV. 0.6 Jan. 2005

0 234567n-1nn+1n+21

Auto-Refresh Timing (CL=4, BL=4)

RDA LAL DESL WRA REF DESL RDA

Bank, LA

Command

Bank, Address

WRA LAL or

MRS or

REF

Q0 Q1 Q2 Q3

(output)

Unidirectional DS/Free Running QS mode

CL=4

lRC=5cycles lREFC=19cycles

lRCD=1cycle lRAS=4cycles lRCD=1cycle

Low

Hi-Z

Low

Hi-Z

∼

RDA LAL DESL WRA REF DESL RDA

Bank, LA

Command

Bank, Address

WRA LAL or

MRS or

REF

Q0 Q1 Q2 Q3

(output)

CL=4

lRC=5cycles lREFC=19cycles

lRCD=1cycles lRAS=4cycles lRCD=1cycles

Hi-Z Hi-Z

∼

∼∼

∼

In case of CL=4, IREFC must be meet 19 clock cycles.

When the Auto-Refresh operation is perfomed, the synthetic average interva l of Auto-Refresh command

specified by tREFI must be satisfied.

tREFI is average interval time in 8 Refresh cycles that is sampled randomly.

Note :

Unidirecti ona l DS /Q S mode

WRA REF

∼

WRA REF

∼

WRA REF

∼

WRA REF

∼

WRA REF

t1t2t3t7t8

8 Refresh cycle

Total time of 8 Refresh cycle

t1+t2+t3+t4+t5+t6+t7+t8

tREFI =

tREFI is specified to avoid partly concentrated current of Refresh operation that is acivated

larger are than Read/Write operation.

CLK

K4C89093AF

REV. 0.6 Jan. 2005

- 48 -

Function Description

Network - DRAM

Network - DRAM is an acronym of Double Data Rate Network - DRAM.

Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.

Pin Functions

Clock Inputs : CLK & CLK

The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all

address input signals are sampled on the crossing of the positive edge of CLK and th e negative edge of CLK. The QS and DQ output

data are aligned to the crossing point of CLK and CLK. The timing reference poin t for the differential clock is when the CLK and CLK

signals cross during a transition.

Power Down : PD

The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like

a CKE input of a standard SDRAMs, therefore it is illega l to bring PD pin into low state if any Read or Write operation is being per-

formed.

Chip Select & Function Control : CS & FN

The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided

by the combination of the two consecutive operation commands using the CS and FN inputs.

Bank Addresses : BA0 & BA1

The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for

the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).

Address Inputs : A0 to A14

Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank

address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs

are also used for setting the data in the Regular or Extended Mode Register set cycle.

BA0 BA1

Bank #0 0 0

Bank #1 1 0

Bank #2 0 1

Bank #3 1 1

Upper Address Lower Address

K4C89093AF A0 to A14 A0 to A7

K4C89093AF

REV. 0.6 Jan. 2005

- 49 -

Functional Description (Continued)

Data Input/Output : DQ0 ~ DQ8

The input data of DQ0 to DQ8 are taken in synchronizing with the both edges of DS input signal.

The output data of DQ0 to DQ8 are outputted synchronizing with the both edges of QS output signal.

Data Strobe : DS or QS

Method of data strobe is chosen by Extended mode register.

(1) Unidirectional DS/QS mode

DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS

are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low"

level. QS is Hi-Z in Self-Refresh mode.

(2) Unidirectional DS/Free running QS mode

DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS

are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe

type is easy to use for pin to pin connect application.

Power Supply : VDD, VDDQ, VSS, VSSQ

VDD and VSS are supply pins for memory core and peripheral circuits.

VDDQ and VSSQ are power supply pins for the output buffer.

Reference Voltage : VREF

VREF is reference voltage for all input signals.

K4C89093AF

REV. 0.6 Jan. 2005

- 50 -

Command Functions and Operations

K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation

mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.

Read Operation (1st command + 2nd command = RDA + LAL)

Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in

a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out

sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after

CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank

goes back automatically to the idle state after IRC.

Write Operation (1st command + 2nd command = WRA + LAL)

Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in

a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is

latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be

asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst

length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-

ically to the idle state after IRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.

Auto-Refresh Operation (1st command + 2nd command = WRA + REF)

K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to

the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In

a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of

the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is

specified by IREFC. However , about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-

uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random

distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,

the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.

Power Down Mode( PD="L" )

When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89093AF become Power Down Mode by asserting

PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,

the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued

for IPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.

Mode Register Set (1st command + 2nd command = RDA + MRS)

When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a

point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the

RDA command instead of the LAL command. The data to be set in the Mode Reg ister is transferred using A0 to A14, BA0 and BA1

address inputs. The K4C89093AF have two mode registers. These are Regular and Extended Mode Register . The Regular or Extended

Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read

or write cycle. The Regular Mode Register has four function fields.

K4C89093AF

REV. 0.6 Jan. 2005

- 51 -

The four fields are as follows :

(R-1) Burst Length field to set the length of burst data

(R-2) Burst Type field to designate the lower address access sequence in a burst cycle

(R-3) CAS Latency field to set the access time in clock cycle

(R-4) Test Mode field to use for supplier only.

The Extended Mode Register has two function fields.

The two fields are as follows:

(E-1) DLL Switch field to choose either DLL enable or DLL disable

(E-2) Output Driver Impedance Control field.

(E-3) Data Strobe Select

Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by

another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-

fined, therefore the Mode Register Set command must be issued before proper operation.

• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)

These bits are used to choose either Regular MRS or Extended MRS

Regular Mode Register Fields

(R-1) Burst Length field (A2 to A0)

This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 4 words.

(R-2) Burst Type field (A3)

This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is

selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.

• Addressing sequence of Sequential mode (A3)

A column access is started from the inputted lower address and is performed by incrementing the lower address input to

the device.

BA1 BA0 A14~A0

0 0 Regular MRS cycle

0 1 Extended MRS cycle

1XReserved

A2 A1 A0 Burst Length

000Reserved

001Reserved

010 4 words

011Reserved

1 X X Reserved

A3 Burst Type

0 Sequential

1 Interleave

K4C89093AF

REV. 0.6 Jan. 2005

- 52 -

RDA LAL

Data 0 Data 1 Data 2 Data 3

Addressing sequence for Sequential mode

Data Access Address Burst Length

Data 0 n

4 words(Address bits is LA1, LA0)

not carried from LA1~LA2

Data 1 n + 1

Data 2 n + 2

Data 3 n + 3

CAS Latency = 4 (Free Running QS mode)

Command

Functional Description (Continued)

• Addressing sequence of Inteleave mode

A column access is started from the inputted lower address and is performed by interleaving the address bits in the

sequence shown as the following.

Addressing sequence for Interleave mode

(R-3) CAS Latency field (A6 to A4)

This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to

the first dat a read. The min imum value s of CAS Lat ency depen ds on the frequ ency of CL K. In a write mode , the pla ce of

clock which shou ld input write data is CAS Latency cycles - 1.

Data Access Address Burst Length

Data 0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0

4 words

Data 1 ...A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2 ...A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 3 ...A8 A7 A6 A5 A4 A3 A2 A1 A0

Addressing sequence for Interleave mode

A6 A5 A4 CAS Latency

000 Reserved

001 Reserved

010 Reserved

011 Reserved

100 4

101 5

110 6

111 7

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(R-4) Test Mode field (A7)

This bit is used to en ter Test Mode for supplier only and must be set to "0" for normal operation.

(R-5) Reserved field in the Regular Mode Register

• Reserved bits (A8 to A14)

These bits are reserved for future operations. They must be set to "0" for normal operation.

Extended Mode Register Fields

(E-1) DLL Switch field (A0)

This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.

(E-2) Output Driver Impedance Control field (A1 to A4)

This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver

Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.

(E-3) Strobe Select (A6/A5)

Two types of strobe are supported. This field is used to choose the type of data strobe.

(1) Unidirectional DS/QS mode

Data strobe is separated DS for wr ite strobe and QS for read strobe.

DS is used to sample write data at write operation. QS is aligned with read data at Read operation.

(2) Unidirectional DS/F ree running QS mode

Data strobe is separated DS for wr ite strobe and QS for read strobe.

DS is used to sample write data at write operation. QS is aligned with read data and always clocking

(E-4)Reserved fied (A7 to A14)

These bits are reserved for future operations and must be set to "0" for normal operation.

QS DQ Output Driver Impedance Control

A4 A3 A2 A1

0000 Normal Output Driver

0101 Strong Output Driver

1010 Weaker Output Driver

1111 Reserved

A6 A5 Strobe Select

00 Reserved

01 Reserved

1 0 Unidirectional DS/QS mode

1 1 Unidirectional DS/Free running QS mode

K4C89093AF

REV. 0.6 Jan. 2005

- 54 -

Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm)

10.50

0.10

15.50 ± 0.10

15.50

0.10

0.10 Max

0.5 ± 0.05

0.35

0.05

1.10

0.10

Window Mold Area

TOP VIEW

10.50

0.10

7.00

1.00 x 14 = 14.00

15.50

0.10

7.00

1.00 x 5 = 5.00

BOTTOM VIEW

1.00 1.00

1.50 1.50

1.00

60 -

∅

0.45 solder ball

2.50

#A1 Mark (Option)

#A1

K4C89093AF

REV. 0.6 Jan. 2005

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General Information

A : 60 FBGA

G : 144 FBGA

F6 : 667Mbps/pin (333MHz, CL=6)

FB : 533Mbps /pin (266MHz, CL=5)

F5 : 400Mbps/pin (200MHz, CL=4)

36 : x36

89 : 288M 8K/32ms

C : Network-DRAM

F : 7th Generation

K 4 C XX XX X X X - X X

Memory

DRAM

Small Classification

Density and Refresh

Temperature & Power

Package

Organization Version

Interface (VDD & VDDQ)

1. SAMSUNG Memory : K

2. DRAM : 4

3. Small Classification

4. Density & Refresh

5. Organization

8. Version

9. Package

11. Speed

3 : 4 Bank

6. Bank

1 2 3 4 5 6 7 8 9 10 11

A: SSTL-2(2.5V, 1.8V)

7. Interface (VDD & VDDQ)

Speed

Bank

Organization F6 (667Mbps@CL6) FB (600Mbps@CL6 ) F5 (500Mbps@CL6 )

288M(x9) K4C89093AF-ACF6 K4C89093AF-ACFB K4C89093AF-AC(I)F5

288M(x18) K4C89183AF-ACF6 K4C89183AF-ACFB K4C89183AF-AC(I)F5

288M(x36) K4C89363AF-GCF6 K4C89363AF-GCFB K4C89363AF-GC(I)F5

C : (Commercial, Normal)

I : (Industrial, Normal)

10. Temperature & Power