LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 LM56 Dual Output Low Power Thermostat Check for Samples: LM56 FEATURES DESCRIPTION * * * * * The LM56 is a precision low power thermostat. Two stable temperature trip points (VT1 and VT2) are generated by dividing down the LM56 1.250V bandgap voltage reference using 3 external resistors. The LM56 has two digital outputs. OUT1 goes LOW when the temperature exceeds T1 and goes HIGH when the the temperature goes below (T1-THYST). Similarly, OUT2 goes LOW when the temperature exceeds T2 and goes HIGH when the temperature goes below (T2-THYST). THYST is an internally set 5C typical hysteresis. 1 2 Digital Outputs Support TTL Logic Levels Internal Temperature Sensor 2 Internal Comparators with Hysteresis Internal Voltage Reference Available in 8-pin SOIC and VSSOP Packages APPLICATIONS * * * * * * * * Microprocessor Thermal Management Appliances Portable Battery Powered 3.0V or 5V Systems Fan Control Industrial Process Control HVAC Systems Remote Temperature Sensing Electronic System Protection The LM56 is available in an 8-lead VSSOP surface mount package and an 8-lead SOIC. Table 1. Key Specifications VALUE UNIT Power Supply Voltage 2.7V-10 V Power Supply Current 230 A (max) 1.250 V 1% (max) 5 C (+6.20 mV/C x T) + 395 mV mV VREF Hysteresis Temperature Internal Temperature Sensor Output Voltage Table 2. Temperature Trip Point Accuracy LM56BIM LM56CIM +25C 2C (max) 3C (max) +25C to +85C 2C (max) 3C (max) -40C to +125C 3C (max) 4C (max) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com Simplified Block Diagram and Connection Diagram Block Diagram Typical Application VT1 = 1.250V x (R1)/(R1 + R2 + R3) VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3) where: (R1 + R2 + R3) = 27 k and VT1 or T2 = [6.20 mV/C x T] + 395 mV therefore: R1 = VT1/(1.25V) x 27 k R2 = (VT2/(1.25V) x 27 k) - R1 R3 = 27 k - R1 - R2 Figure 1. Microprocessor Thermal Management These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 Absolute Maximum Ratings (1) Input Voltage 12V Input Current at any pin (2) 5 mA Package Input Current (2) 20 mA Package Dissipation at TA = 25C (3) 900 mW Human Body Model - Pin 3 Only 800V All other pins ESD Susceptibility (4) 1000V Machine Model 125V -65C to + 150C Storage Temperature (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. When the input voltage (VI) at any pin exceeds the power supply (VI < GND or VI > V+), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), JA (junction to ambient thermal resistance) and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PD = (TJmax-TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 125C. For this device the typical thermal resistance (JA) of the different package types when board mounted follow: The human body model is a 100 pF capacitor discharge through a 1.5 k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Operating Ratings (1) (2) (3) TMIN TA TMAX Operating Temperature Range -40C TA +125C LM56BIM, LM56CIM Positive Supply Voltage (V+) +2.7V to +10V Maximum VOUT1 and VOUT2 (1) (2) (3) +10V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging. Reflow temperature profiles are different for lead-free and non-lead-free packages. Package Type JA D0008A 110C/W DGK0008A 250C/W Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 3 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com LM56 Electrical Characteristics The following specifications apply for V+ = 2.7 VDC, and VREF load current = 50 A unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C unless otherwise specified. Symbol Parameter Conditions Typical (1) LM56BIM Limits (2) LM56CIM Limits (2) Units (Limits) Temperature Sensor Trip Point Accuracy (Includes VREF, Comparator Offset, and Temperature Sensitivity errors) Trip Point Hysteresis 2 3 C (max) +25C TA +85C 2 3 C (max) -40C TA +125C 3 4 C (max) 3 3 C (min) 6 6 C (max) 3.5 3.5 C (min) 6.5 6.5 C (max) 4.5 4.5 C (min) 7.5 7.5 C (max) 4 4 C (min) 8 8 C (max) 2 3 C (max) 3 4 C (max) 1500 1500 TA = -40C 4 TA = +25C 5 TA = +85C 6 TA = +125C Internal Temperature Sensitivity 6 +6.20 mV/C Temperature Sensitivity Error Output Impedance -1 A IL +40 A Line Regulation +3.0V V+ +10V, +25 C TA +85 C -0.72/+0.3 -0.72/+0.3 6 6 mV/V (max) +3.0V V+ +10V, -40 C TA <25 C -1.14/+0.6 -1.14/+0.6 1 1 mV/V (max) +2.7V V+ +3.3V (max) 2.3 2.3 mV (max) 300 300 nA (max) VT1 and VT2 Analog Inputs IBIAS Analog Input Bias Current VIN Analog Input Voltage Range VOS Comparator Offset 150 V+ - 1 V GND 2 V 8 8 mV (max) 1 1 % (max) 12.5 12.5 mV (max) 0.25 0.25 mV/V (max) VREF Output VREF VREF Nominal 1.250V VREF Error VREF/V+ VREF/IL (1) (2) Line Regulation Load Regulation Sourcing +3.0V V+ +10V 0.13 +2.7V V+ +3.3V 0.15 +30 A IL +50 A V 1.1 1.1 mV (max) 0.15 0.15 mV/A (max) Typicals are at TJ = TA = 25C and represent most likely parametric norm. Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level). Symbol Limits (2) Units (Limits) 230 A (max) V = +2.7V 230 A (max) 1 A (max) 0.4 V (max) Parameter Conditions Typical (1) + V Power Supply IS Supply Current V+ = +10V + Digital Outputs IOUT("1") Logical "1" Output Leakage Current V+ = +5.0V VOUT("0") Logical "0" Output Voltage IOUT = +50 A (1) (2) 4 Typicals are at TJ = TA = 25C and represent most likely parametric norm. Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 Typical Performance Characteristics Quiescent Current vs Temperature VREF Output Voltage vs Load Current Figure 2. Figure 3. OUT1 and OUT2 Voltage Levels vs Load Current Trip Point Hysteresis vs Temperature Figure 4. Figure 5. Temperature Sensor Output Voltage vs Temperature Temperature Sensor Output Accuracy vs Temperature Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 5 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) 6 Trip Point Accuracy vs Temperature Comparator Bias Current vs Temperature Figure 8. Figure 9. OUT1 and OUT2 Leakage Current vs Temperature VTEMP Output Line Regulation vs Temperature Figure 10. Figure 11. VREF Start-Up Response VTEMP Start-Up Response Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 FUNCTIONAL DESCRIPTION Pin Functions V+ This is the positive supply voltage pin. This pin should be bypassed with a 0.1 F capacitor to ground. GND This is the ground pin. VREF This is the 1.250V bandgap voltage reference output pin. In order to maintain trip point accuracy this pin should source a 50 A load. VTEMP This is the temperature sensor output pin. OUT1 This is an open collector digital output. OUT1 is active LOW. It goes LOW when the temperature is greater than T1 and goes HIGH when the temperature drops below T1- 5C. This output is not intended to directly drive a fan motor. OUT2 This is an open collector digital output. OUT2 is active LOW. It goes LOW when the temperature is greater than the T2 set point and goes HIGH when the temperature is less than T2- 5C. This output is not intended to directly drive a fan motor. VT1 This is the input pin for the temperature trip point voltage for OUT1. VT2 This is the input pin for the low temperature trip point voltage for OUT2. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 7 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com VT1 = 1.250V x (R1)/(R1 + R2 + R3) VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3) where: (R1 + R2 + R3) = 27 k and VT1 or T2 = [6.20 mV/C x T] + 395 mV therefore: R1 = VT1/(1.25V) x 27 k R2 = (VT2/(1.25V) x 27 k)-R1 R3 = 27 k - R1 - R2 Application Hints LM56 TRIP POINT ACCURACY SPECIFICATION For simplicity the following is an analysis of the trip point accuracy using the single output configuration shown in Figure 14 with a set point of 82C. Trip Point Error Voltage = VTPE, Comparator Offset Error for VT1E Temperature Sensor Error = VTSE Reference Output Error = VRE Figure 14. Single Output Configuration 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 1. VTPE = VT1E - VTSE + VRE Where: 2. VT1E = 8 mV (max) 3. VTSE = (6.20 mV/C) x (3C) = 18.6 mV 4. VRE = 1.250V x (0.01) R2/(R1 + R2) Using Equations from Figure 1. VT1= 1.25V x R2/(R1 + R2) = 6.20 mV/C)(82C) + 395 mV Solving for R2/(R1 + R2) = 0.7227 then, 5. VRE = 1.250V x (0.01) R2/(R1 + R2) = (0.0125) x (0.7227) = 9.03 mV The individual errors do not add algebraically because, the odds of all the errors being at their extremes are rare. This is proven by the fact the specification for the trip point accuracy stated in the LM56 Electrical Characteristics for the temperature range of -40C to +125C, for example, is specified at 3C for the LM56BIM. Note this trip point error specification does not include any error introduced by the tolerance of the actual resistors used, nor any error introduced by power supply variation. If the resistors have a 0.5% tolerance, an additional error of 0.4C will be introduced. This error will increase to 0.8C when both external resistors have a 1% tolerance. BIAS CURRENT EFFECT ON TRIP POINT ACCURACY Bias current for the comparator inputs is 300 nA (max) each, over the specified temperature range and will not introduce considerable error if the sum of the resistor values are kept to about 27 k as shown in the typical application of Figure 1. This bias current of one comparator input will not flow if the temperature is well below the trip point level. As the temperature approaches trip point level the bias current will start to flow into the resistor network. When the temperature sensor output is equal to the trip point level the bias current will be 150 nA (max). Once the temperature is well above the trip point level the bias current will be 300 nA (max). Therefore, the first trip point will be affected by 150 nA of bias current. The leakage current is very small when the comparator input transistor of the different pair is off (see Figure 15). The effect of the bias current on the first trip point can be defined by the following equations: (1) where IB = 300 nA (the maximum specified error). The effect of the bias current on the second trip point can be defined by the following equations: (2) where IB = 300 nA (the maximum specified error). The closer the two trip points are to each other the more significant the error is. Worst case would be when VT1 = VT2 = VREF/2. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 9 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com Figure 15. Simplified Schematic MOUNTING CONSIDERATIONS The majority of the temperature that the LM56 is measuring is the temperature of its leads. Therefore, when the LM56 is placed on a printed circuit board, it is not sensing the temperature of the ambient air. It is actually sensing the temperature difference of the air and the lands and printed circuit board that the leads are attached to. The most accurate temperature sensing is obtained when the ambient temperature is equivalent to the LM56's lead temperature. As with any IC, the LM56 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit operates at cold temperatures where condensation can occur. Printed-circuit coatings are often used to ensure that moisture cannot corrode the LM56 or its connections. 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 VREF AND VTEMP CAPACITIVE LOADING Figure 16. Loading of VREF and VTEMP The LM56 VREF and VTEMP outputs handle capacitive loading well. Without any special precautions, these outputs can drive any capacitive load as shown in Figure 16. NOISY ENVIRONMENTS Over the specified temperature range the LM56 VTEMPoutput has a maximum output impedance of 1500. In an extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 F be added from V+ to GND to bypass the power supply voltage, as shown in Figure 16. In a noisy environment it may be necessary to add a capacitor from the VTEMP output to ground. A 1 F output capacitor with the 1500 output impedance will form a 106 Hz lowpass filter. Since the thermal time constant of the VTEMP output is much slower than the 9.4 ms time constant formed by the RC, the overall response time of the VTEMP output will not be significantly affected. For much larger capacitors this additional time lag will increase the overall response time of the LM56. APPLICATIONS CIRCUITS Figure 17. Reducing Errors Caused by Bias Current Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 11 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com The circuit shown in Figure 17 will reduce the effective bias current error for VT2 as discussed in Section 3.0 to be equivalent to the error term of VT1. For this circuit the effect of the bias current on the first trip point can be defined by the following equations: (3) where IB = 300 nA (the maximum specified error). Similarly, bias current affect on VT2 can be defined by: (4) where IB = 300 nA (the maximum specified error). The current shown in Figure 18 is a simple overtemperature detector for power devices. In this example, an audio power amplifier IC is bolted to a heat sink and an LM56 Celsius temperature sensor is mounted on a PC board that is bolted to the heat sink near the power amplifier. To ensure that the sensing element is at the same temperature as the heat sink, the sensor's leads are mounted to pads that have feed throughs to the back side of the PC board. Since the LM56 is sensing the temperature of the actual PC board the back side of the PC board also has large ground plane to help conduct the heat to the device. The comparator's output goes low if the heat sink temperature rises above a threshold set by R1, R2, and the voltage reference. This fault detection output from the comparator now can be used to turn on a cooling fan. The circuit as shown in design to turn the fan on when heat sink temperature exceeds about 80C, and to turn the fan off when the heat sink temperature falls below approximately 75C. Figure 18. Audio Power Amplifier Overtemperature Detector 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 LM56 www.ti.com SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 Figure 19. Simple Thermostat Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 13 LM56 SNIS120G - APRIL 2000 - REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY Changes from Revision F (February 2013) to Revision G * 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM56 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM56BIM NRND SOIC D 8 95 Non-RoHS & Non-Green Call TI Call TI -40 to 125 LM56 BIM LM56BIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM56 BIM LM56BIMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T02B LM56BIMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T02B LM56BIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM56 BIM LM56CIM NRND SOIC D 8 95 Non-RoHS & Non-Green Call TI Call TI -40 to 125 LM56 CIM LM56CIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM56 CIM LM56CIMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T02C LM56CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T02C LM56CIMX NRND SOIC D 8 2500 Non-RoHS & Non-Green Call TI Call TI -40 to 125 LM56 CIM LM56CIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM56 CIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM56BIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM56BIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM56BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM56CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM56CIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM56CIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM56CIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM56BIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM56BIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM56BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM56CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM56CIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM56CIMX SOIC D 8 2500 367.0 367.0 35.0 LM56CIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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