12-Bit, Integrated, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
Data Sheet
ADV7403
FEATURES
4 Noise Shaped Video (NSV)® 12-bit analog-to-digital
converters (ADCs) sampling up to 140 MHz (140 MHz
speed grade only)
Mux with 12 analog input channels
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p/625p component progressive scan support
720p/1080i component HDTV support
Digitizes RGB graphics up to 1280 × 1024 at 75 Hz (SXGA)
(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI
receiver IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range: −40°C to +85°C
12-bit 4:4:4 and 10-/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
Vertical blanking interval (VBI) data slicer, including teletext
APPLICATIONS
LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receivers
GENERAL DESCRIPTION
The ADV7403 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder supports
the conversion of PAL, NTSC, and SECAM standards in the
form of composite or S-Video into a digital ITU-R BT.656 format.
The ADV7403 also supports the decoding of a component
RGB/YPrPb video signal into a digital YCrCb or RGB pixel output
stream. The support for component video includes standards
such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many
other HD and SMPTE standards. Graphic digitization is also
supported by the ADV7403; it is capable of digitizing RGB
graphics signals from VGA to SXGA rates and converting them
into a digital RGB or YCrCb pixel output stream. SCART and
overlay functionality are enabled by the ability of the ADV7403
to simultaneously process CVBS and standard definition RGB
signals. The fast blank pin controls the mixing of these signals.
The ADV7403 contains two main processing sections. The first
is the standard definition processor (SDP), which processes all
PAL, NTSC, and SECAM signal types, and the second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For additional
descriptions of the features of the ADV7403, see the Functional
Overview and the Theory of Operation sections.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADV7403 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Video Specifications ..................................................................... 5
Timing Characteristics ................................................................ 6
Analog Specifications ................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Package Thermal Performance ................................................... 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Functional Overview ...................................................................... 12
Analog Front End ....................................................................... 12
Standard Definition Processor (SDP) Pixel Data Output
Modes ........................................................................................... 12
Component Processor (CP) Pixel Data Output Modes ........ 12
Composite and S-Video Processing ......................................... 12
Component Video Processing .................................................. 12
RGB Graphics Processing ......................................................... 13
Digital Video Input Port ............................................................ 13
General Features ......................................................................... 13
Theory of Operation ...................................................................... 14
Analog Front End ....................................................................... 14
Standard Definition Processor (SDP) ...................................... 14
Component Processor (CP) ...................................................... 14
Pixel Input/Output Formatting .................................................... 16
Recommended External Loop Filter Components .................... 18
Typical Connection Diagram........................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/13—Revision B: Initial Version
Rev. B | Page 2 of 20
Data Sheet ADV7403
FUNCTIONAL BLOCK DIAGRAM
INPUT
MUX
DATA
PREPROCESSOR
DECIMATION
AND
DOWNSAMPLING
FILTERS
STANDARD DE FI NIT ION P ROCES S OR
LUMA
FILTER
OUTPUT FIFOAND FO RMATTER
AIN1
TO
AIN12
ADV7403
SERIAL INTERFACE
CONTROLAND V BI D ATA
SCLK1
SDA1
ALSB
SYNC
EXTRACT
20
CS/HS
8
8P29 TO P20
P19 TO P10
P9 TO P0
PIXEL
DATA
VS
FIELD/DE
LLC1
SFL/
SYNCOUT
CVBS
S-VIDEO
YPrPb
SCART–
(RGB + CV BS )
GRAPHICS RGB
12
CHROMA
FILTER
CHROMA
DEMOD
fSC
RECOVERY
INT
LUMA
RESAMPLE LUMA
2D COMB
(5H MAX)
RESAMPLE
CONTROL
CHROMA
RESAMPLE CHROMA
2D COMB
(4H MAX)
FAST
BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
FB
Y
Cb
Cr
VBI DATA RECOVERY
MACROVISION
DETECTION STANDARD
AUTODETECTION
CVBS/Y
C
Cb
Cr
Cb
Y
COLORSPACE
CONVE RS IO N
CVBS
Cr
8
COMPONENT PROCESSOR
SCLK2
SDA2
SSPD STDI
SYNC PROCESSING AND
CLO CK GENE R ATION
DCLK_IN
DE_IN
HS_IN/CS_IN
VS_IN
SOG
SOY
DIGITAL INP UT
PORT
DVI or HDMI
XTAL XTAL1
24
8
8
8
DIGITAL
FINE
CLAMP
GAIN
CONTROLOFFSET
CONTROLAV CODE
INSERTION
30
12
12
12
12
12
12
12
ACTIVE PEAK
AND
AGC MACROVISION
DETECTION CGMS DATA
EXTRACTION
P40 TO P31
P29 TO P20
P11 TO P10
P1 TO P0
12
A/DCLAMPANTI-
ALIAS
FILTER
12
A/D
CLAMPANTI-
ALIAS
FILTER
12
A/D
CLAMPANTI-
ALIAS
FILTER
12
A/DCLAMPANTI-
ALIAS
FILTER
05431-001
Figure 1.
Rev. B | Page 3 of 20
ADV7403 Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
To obtain all specifications the following write sequence must be included in the programming scripts: Address 0x0E to Data 0x80, Address 0x54
to Data 0x00, and Address 0x0E to Data 0x00.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
STATIC PERFORMANCE1
Resolution (Each ADC) N 122 Bits
Integral Nonlinearity INL Best straight line (BSL) at 27 MHz at
a 12-bit level
±2.0 ±8.02 LSB
BSL at 54 MHz at a 12-bit level −2.0/+2.5 LSB
BSL at 74 MHz at a 10-bit level ±1.0 LSB
BSL at 110 MHz at a 10-bit level
−3.0/+3.0
LSB
BSL at 135 MHz at an 8-bit level3 ±1.3 LSB
Differential Nonlinearity DNL At 27 MHz at a 12-bit level −0.7/+0.85 −0.99/+2.52 LSB
At 54 MHz at a 12-bit level −0.75/+0.9 LSB
At 74 MHz at a 10-bit level ±0.75 LSB
At 110 MHz at a 10-bit level −0.7/+5.0 LSB
At 135 MHz at an 8-bit level3 −0.8/+2.5 LSB
DIGITAL INPUTS
Input High Voltage4 VIH 2 V
Input Low Voltage5 VIL 0.8 V
Input High Voltage VIH HS_IN, VS_IN low trigger mode 0.7 V
Input Low Voltage VIL HS_IN, VS_IN low trigger mode 0.3 V
Input Current IIN P20 to P29, P31 to P40, SCLK2, SDA2,
DCLK_IN, DE_IN, RESET
−60 +60 µA
All other input pins −10 +10 µA
Input Capacitance6 CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage
7
V
OH
I
SOURCE
= 0.4 mA
2.4
V
Output Low Voltage7 VOL ISINK = 3.2 mA 0.4 V
High Impedance Leakage Current ILEAK INT, P20 to P29, SDA2 60 µA
All other output pins 10 µA
Output Capacitance6 COUT 20 pF
POWER REQUIREMENTS6
Digital Core Power Supply DVDD 1.65 1.8 2 V
Digital Input/Output Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply
PVDD
1.71
1.8
1.89
V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA
Graphics RGB sampling at 135 MHz 137 mA
SCART RGB FB sampling at 54 MHz 106 mA
Digital Input/Output Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA
Graphics RGB sampling at 135 MHz 19 mA
PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA
Graphics RGB sampling at135 MHz 12 mA
Rev. B | Page 4 of 20
Data Sheet ADV7403
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Analog Supply Current8 IAVDD CVBS input sampling at 54 MHz 99 mA
Graphics RGB sampling at 135 MHz 242 mA
SCART RGB FB sampling at 54 MHz 269 mA
Power-Down Current IPWRDN 2.25 mA
Green Mode Power-Down
I
PWRDNG
Sync bypass function
16
mA
Power-Up Time TPWRUP 20 ms
1 All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.
2 Maximum INL and DNL specifications obtained with device configured for component video input.
3 This specification is for the ADV7403KSTZ-140 only.
4 To obtain specified VIH level on the XTAL pin (Pin 38), program Subaddress 0x13 (write only) with 0x04 value. When Subaddress 0x13 is set to 0x00 value, VIH level on
the XTAL pin = 1.2 V.
5 To obtain specified VIL level on the XTAL pin (Pin 38), program Subaddress 0x13 (write only) with 0x04 value. When Subaddress 0x13 is set to 0x00 value, VIL level on
the XTAL pin (Pin 38) = 0.4 V.
6 Guaranteed by characterization.
7 VOH and VOL levels obtained using default drive strength value (0xD5) in Subaddress 0xF4.
8 Analog current measurements for CVBS made with only ADC0 are powered up; for RGB, only ADC0, ADC1, and ADC2 are powered up; and for SCART FB, all ADCs
powered up.
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by
characterization.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated 5 step 0.4 Degrees
Differential Gain DG CVBS input, modulated 5 step 0.4 %
Luma Nonlinearity LNL CVBS input, 5 step 0.4 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 61 64 dB
Luma flat field 64 65 dB
Analog Front End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40 70 Hz
fSC Subcarrier Lock Range ±1.3 kHz
Color Lock in Time 60 Lines
Sync Depth Range1 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time
2
Fields
Horizontal Lock Time 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 Degrees
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.4 %
Chroma Phase Error 0.3 Degrees
Chroma Luma Intermodulation 0.1 %
LUMA SPECIFICATIONS
Luma Accuracy
Brightness CVBS, 1 V input 1 %
Contrast CVBS, 1 V input 1 %
1 Nominal sync depth is 300 mV at 100% sync depth range.
Rev. B | Page 5 of 20
ADV7403 Data Sheet
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by
characterization.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
Horizontal Sync Input Frequency 14.8 110 kHz
LLC1 Frequency Range1 12.825 140 MHz
I2C PORT2
SCLK Frequency
400
kHz
SCLK Minimum Pulse Width High t1 0.6 µs
SCLK Minimum Pulse Width Low t2 1.3 µs
Hold Time (Start Condition) t3 0.6 µs
Setup Time (Start Condition) t4 0.6 µs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Time t6 300 ns
SCLK and SDA Fall Time t7 300 ns
Setup Time for Stop Condition t8 0.6 µs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)
3
t
11
Negative clock edge to start
of valid data
3.6
ns
t12 End of valid data to negative
clock edge
2.4 ns
Data Output Transition Time SDR (CP)4 t13 End of valid data to negative
clock edge
2.8 ns
t14 Negative clock edge to start
of valid data
0.1 ns
Data Output Transition Time DDR (CP)4, 5 t15 Positive clock edge to end of
valid data
−4 + TLLC1/4 ns
t16 Positive clock edge to start of
valid data
0.25 + TLLC1/4 ns
t17 Negative clock edge to end
of valid data
−2.95 + TLLC1/4 ns
t18 Negative clock edge to start
of valid data
−0.5 + TLLC1/4 ns
DATA and CONTROL INPUTS2
Input Setup Time (Digital Input Port) t19 HS_IN, VS_IN 9 ns
DE_IN, data inputs 2.2 ns
Input Hold Time (Digital Input Port) t20 HS_IN, VS_IN 7 ns
DE_IN, data inputs 2 ns
1 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
2 TTL input values are 0 V to 3 V with rise/fall times ≥ 3 ns measured between the 10% and 90% points.
3 SDP timing figures obtained using default drive strength value (0xD5) in Subaddress 0xF4.
4 CP timing figures obtained using maximum drive strength value (0xFF) in Subaddress 0xF4.
5 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. B | Page 6 of 20
Data Sheet ADV7403
Timing Diagram
SDA1/SDA2
SCLK1/SCLK2
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
05431-003
Figure 2. I2C Timing
05431-004
LLC1
P0 TO P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
t9t10
t12
t11
Figure 3. Pixel Port and Control SDR Output Timing (SD Core)
LLC1
P0 TO P29, VS,
HS, FIELD/DE
t14
t9
t13
t10
05431-005
Figure 4. Pixel Port and Control SDR Output Timing (CP Core)
05431-006
LLC1
P6 TO P9,
P10 TO P19
t16 t18
t15 t17
Figure 5. Pixel Port and Control DDR Output Timing (CP Core)
t
9
t
10
t
20
t
19
DCLK_IN
DE_IN
HS_IN
VS_IN
CONTROL
INPUTS
05431-007
P0 TO P1, P 10 TO P11,
P20 TO P21, P22 TO P29,
P31 TO P32, P33 TO P40
Figure 6. Digital Input Port and Control Input Timing
Rev. B | Page 7 of 20
ADV7403 Data Sheet
ANALOG SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Recommended analog input
video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Guaranteed by characterization.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance (Except the FB Pin, Pin 51) Clamps switched off 10 MΩ
Input Impedance of Pin 51 (FB) 20 kΩ
CML 1.86 V
ADC Full-Scale Level CML + 0.8 V
ADC Zero-Scale Level CML − 0.8 V
ADC Dynamic Range 1.6 V
Clamp Level (When Locked) CVBS input CML − 0.292 V
SCART RGB input (R, G, B signals)
CML − 0.4
V
S-Video input (Y signal) CML − 0.292 V
S-Video input (C signal) CML − 0 V
Component input (Y, Pr, Pb signals) CML − 0.3 V
PC RGB input (R, G, B signals) CML − 0.3 V
Large Clamp SDP only
Source Current 0.75 mA
Sink Current 0.9 mA
Fine Clamp SDP only
Source Current 17 µA
Sink Current 17 µA
Rev. B | Page 8 of 20
Data Sheet ADV7403
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD
−0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V
Digital Outputs Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V
Analog Inputs to AGND
AGND − 0.3 V to AVDD + 0.3 V
Maximum Junction
Temperature (TJ MAX)
125°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering
(20 sec)
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the device, the user
is advised to turn off any unused ADCs.
Keep the junction temperature less than the maximum junction
temperature (TJ MAX) of 125°C. The junction temperature is
calculated by
TJ = TA MAX + (θJA × WMAX)
where:
TA MAX = 85°C.
θJA = 30°C/W.
WMAX = ((AV D D × IAV D D )+(DVDD × IDVDD)+ (DVDDIO ×
IDVDDIO) + (PVDD × IPVDD)).
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6.
Package Type
θ
JA1
θ
JC2
Unit
100-Lead LQFP
30
7
°C/W
1 It is a 4-layer printed circuit board (PCB) with a solid ground plane (still air).
2 It is a 4-layer PCB with a solid ground plane.
ESD CAUTION
Rev. B | Page 9 of 20
ADV7403 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
26
P6
27
P5
28
P4
29
P26
30
P25
31
P24
32
P23
33
P22
34
P21
35
DCLK_IN
36
LLC1
37
XTAL1
38
XTAL
39
DVDD
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
17
18
19
20
2
1
22
23
24
25
11
74
73
72
69
70
71
75
68
67
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
65
40
DGND
41
P3
42
P2
43
P1
44
P0
45
P20
46
ELPF
47
PVDD
48
PVDD
49
AGND
50
AGND
05431-002
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
ADV7403
LQFP
TOP VIEW
(Not to Scale)
P11
P32
P31
INT
CS/HS
DGND
DVDDIO
P15
P14
P13
P12
DGND
DVDD
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P10
P9
P8
P27
P7
AIN2
AIN8
AIN1
AIN7
SOG
AIN9
AIN3
TEST1
AGND
CAPY1
CAPY2
AVDD
REFOUT
CML
AGND
BIAS
CAPC1
CAPC2
TEST0
AIN10
AIN4
AIN11
AIN5
AIN12
FB
FIELD/DE
DE_IN
SOY
AIN6
ALSB
SDA1
SCLK1
P40
P39
VS_IN
HS_IN/CS_IN
P38
P37
DGND
DVDD
P19
P17
P16
P36
P35
P34
VS
P33
P18
RESET
Figure 7. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
1, 2, 83, 84, 87, 88,
95 to 97, 100
P31 to P40 I Video Pixel Input Port.
3 INT O Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin triggers. The set of events that triggers an interrupt is under user control.
4 CS/HS O Digital Composite Synchronization Signal (CS). The CS pin can be selected while in CP
mode.
Horizontal Synchronization Output Signal (HS). The HS pin can be selected while in
SDP or CP modes.
5, 11, 17, 40, 89 DGND G Digital Ground.
6, 18 DVDDIO P Digital Input/Output Supply Voltage (3.3 V).
7 to 10, 22, 23,
25 to 28, 41, 42,
91 to 94
P2 to P9, P12 to P19 O Video Pixel Output Port.
12, 39, 90 DVDD P Digital Core Supply Voltage (1.8 V).
13, 14, 20, 21, 24,
29 to 34, 43 to 45
P0 to P1, P10 to P11,
P20 to P29
I/O Video Pixel Input/Output Port.
Rev. B | Page 10 of 20
Data Sheet ADV7403
Pin No. Mnemonic Type 1 Description
15 SFL/SYNC_OUT O Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when the decoder is connected to any Analog
Devices, Inc., digital video encoder.
Sliced Sync Output Signal (SYNC_OUT). This pin is only available in CP mode.
16, 82
SCLK1, SCLK2
I
I
2
C Port Serial Clock Input (Maximum Clock Rate of 400 kHz) Pins. SCLK1 is the clock
line for the control port, and SCLK2 is the clock line for the VBI data readback port.
19, 81 SDA1, SDA2 I/O I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port, and
SDA2 is the data line for the VBI readback port.
35 DCLK_IN I Clock Input Signal. This pin is used in 24-bit digital input mode (for example, processing
24-bit RGB data from a DVI receiver IC) and also in digital CVBS input mode.
36 LLC1 O Line-Locked Output Clock for Pixel Data. This pin range is 12.825 MHz to 140 MHz for
the ADV7403KSTZ-140, and 12.825 MHz to 110 MHz for the ADV7403BSTZ-110.
37 XTAL1 O Connect this pin to the 28.63636 MHz crystal, or if an external 3.3 V, 28.63636 MHz
clock oscillator source is used to clock the ADV7403, leave this pin as no connect. In
crystal mode, the crystal must be a fundamental crystal.
38 XTAL I Input Pin for 28.63636 MHz crystal. To clock the ADV7403, this pin can also be
overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source.
46 ELPF O External Loop PLL Filter. Connect the recommend external loop filter to the ELPF pin.
47, 48 PVDD P PLL Supply Voltage (1.8 V).
49, 50, 60, 66 AGND G Analog Ground.
51 FB I Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
52
SOG
I
Sync on Green Input. This pin is used in embedded sync mode.
53 to 58, 71 to 76 AIN1 to AIN12 I Analog Video Input Channels.
59 TEST1 O Leave this pin unconnected.
61, 62 CAPY1, CAPY2 I ADC Capacitor Network.
63 AVDD P Analog Supply Voltage (3.3 V).
64 REFOUT O Internal Voltage Reference Output.
65 CML O Common-Mode Level (CML) Pin for theInternal ADCs.
67 BIAS O External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between the
BIAS pin and ground.
68, 69 CAPC1, CAPC2 I ADC Capacitor Network.
70 TEST0 NC Leave this pin unconnected, or alternately, tie this pin to AGND.
77 SOY I Sync on Luma Input. This pin is used in embedded sync mode.
78 RESET I System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required
to reset the circuitry of the ADV7403.
79 DE_IN I Data Enable Input Signal. This pin is used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI receiver IC).
80 ALSB I This pin selects the I2C device address for the control and VBI readback ports of the
ADV7403. When ALSB is set to Logic 0, it sets the address for a write to the control
port to Address 0x40 and the readback address for the VBI port to Address 0x21.
When ALSB is set to Logic 1, it sets the address for a write to the control port to
Address 0x42 and the readback address for the VBI port to Address 0x23.
85 VS_IN I VS Input Signal. This pin is used in CP mode for 5-wire timing mode.
86 HS_IN/CS_IN I Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal used to extract timing in a 5-wire or 4-wire RGB mode.
98 FIELD/DE O Field Synchronization Output Signal for All Interlaced Video Modes (FIELD). This is a
multifunction pin. It can also be enabled as a data enable signal (DE) in CP mode to
allow direct connection to a HDMI/DVI transmitter IC.
99
VS
O
Vertical Synchronization Output Signal (SDP and CP Modes).
1 G = ground, P = power, I = input, O = output, I/O = input/output, and NC = no connect.
Rev. B | Page 11 of 20
ADV7403 Data Sheet
FUNCTIONAL OVERVIEW
The following overview provides a brief description of the
functionality of the ADV7403. More details are available in the
Theory of Operation section.
ANALOG FRONT END
The analog front end of the ADV7403 provides four 140 MHz
(ADV7403KSTZ-140), NSV, 12-bit ADCs to enable 10-bit video
decoding, a multiplexer with 12 analog input channels to enable
multisource connection without the requirement of an external
multiplexer, and four current and voltage clamp control loops to
ensure that dc offsets are removed from the video signal.
SCART functionality and standard definition RGB overlay with
CVBS are controlled by the fast blank input. This front end also
features four antialias filters to remove out-of-band noise on
standard definition input video signals.
STANDARD DEFINITION PROCESSOR (SDP) PIXEL
DATA OUTPUT MODES
The ADV7403 features the following SDP output modes:
• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
• 16-/20-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
• 24-/30-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
COMPONENT PROCESSOR (CP) PIXEL DATA
OUTPUT MODES
The ADV7403 features two single data rate (SDR) outputs:
16-/20-bit 4:2:2 YCrCb for all standards, and 24-/30-bit 4:4:4
YCrCb/RGB for all standards. The ADV7403 also features two
double data rate (DDR) outputs: 8-/10-bit 4:2:2 YCrCb for all
standards, and 12-bit 4:4:4 YCrCb/RGB for all standards.
COMPOSITE AND S-VIDEO PROCESSING
The ADV7403 supports NTSC (J, M, 4.43), PAL (B, D, I, G, H,
M, N, Nc, 60), and SECAM (B, D, G, K, L) standards for CVBS
and S-Video formats. Superadaptive 2D, 5-line comb filters for
NTSC and PAL provide superior chrominance and luminance
separation for composite video.
The composite and S-Video processing functionalities also
include fully automatic detection of switching among worldwide
standards (PAL/NTSC/SECAM); automatic gain control (AGC)
with white peak mode to ensure that the video is processed
without compromising the video processing range; adaptive
digital line length tracking (ADLLT™); and proprietary architecture
for locking to weak, noisy, and unstable sources from VCRs and
tuners. The IF filter block compensates for high frequency luma
attenuation due to the tuner SAW filter.
The ADV7403 also features chroma transient improvement
(CTI) and luminance digital noise reduction (DNR), as well as
teletext, closed captioning (CC), extended data service (EDS),
and wide-screen signaling (WSS). It offers certified Macrovision®
copy protection detection on composite and S-Video for all
worldwide formats (PAL/NTSC/SECAM), and a copy
generation management system (CGMS). Other features
include 4× oversampling (54 MHz) for CVBS, S-Video, and
YUV modes; line-locked clock output (LLC); vertical interval
time codes (VITC); support for letterbox detection; a free-run
output mode for stable timing when no video input is present;
clocking from a single 28.63636 MHz crystal; Gemstar™ 1×/2×
electronic program guide compatible; and subcarrier frequency
lock (SFL) output for downstream video encoders.
In addition, the device has color controls for hue, brightness,
saturation, and contrast and controls for Cr and Cb offsets. The
ADV7403 also incorporates a vertical blanking interval data
processor and a video programming system (VPS) on the device.
The differential gain of the ADV7403 is 0.4% typical, and the
differential phase is 0.4° typical.
COMPONENT VIDEO PROCESSING
The ADV7403 supports 525i, 625i, 525p, 625p, 720p, 1080i,
1080p, and many other HDTV formats. It provides automatic
adjustments for gain (contrast) and offset (brightness), as well
as manual adjustment controls. Furthermore, the ADV7403 not
only supports analog component YPrPb/RGB video formats
with embedded synchronization or with separate HS, VS, and CS,
but also supports YCrCb-to-RGB and RGB-to-YCrCb conversions
by any-to-any, 3 × 3 color-space conversion matrices.
Standard identification (STDI) enables detection of the component
format at the system level, and a synchronization source polarity
detector (SSPD) determines the source and polarity of the
synchronization signals that accompany the input video.
Certified Macrovision copy protection detection is available on
component formats (525i, 625i, 525p, and 625p).
When no video input is present, free-run output mode provides
stable timing.
The ADV7403 also supports arbitrary pixel sampling for
nonstandard video sources.
Rev. B | Page 12 of 20
Data Sheet ADV7403
RGB GRAPHICS PROCESSING
The ADV7403 provides 140 MSPS conversion rate support of
RGB input resolutions up to 1280 × 1024 at 75 Hz (SXGA) and
110 MSPS conversion rate for the ADV7403BSTZ-110. It also
provides automatic or manual clamp and gain controls for
graphics modes.
The RGB graphics processing functionality features contrast
and brightness controls, automatic detection of synchronization
source and polarity by the SSPD block, standard identification
enabled by the STDI block, and arbitrary pixel sampling
support for nonstandard video sources.
Additional RGB graphics processing features of the ADV7403
include the following:
• 32-phase DLL support of optimum pixel clock sampling.
• Color-space conversion of RGB to YCrCb and decimation
to a 4:2:2 format for videocentric back-end IC interfacing.
• Data enable (DE) output signal supplied for direct
connection to the HDMI/DVI transmitter IC.
DIGITAL VIDEO INPUT PORT
The ADV7403 supports raw 8-/10-bit CVBS data from a digital
tuner and 24-bit RGB input data from a DVI receiver chip,
output converted to YCrCb 4:2:2. It also supports 24-bit 4:4:4,
16-/20-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, VGA to
SXGA at 60 Hz input data from HDMI receiver chip, output
converted to 16-bit 4:2:2 YCrCb.
GENERAL FEATURES
The ADV7403 features HS, VS, and FIELD output signals with
programmable position, polarity, and width. It also includes a
programmable interrupt request output pin (INT), signals
SDP/CP status changes, and supports two I2C host port
interfaces (control and VBI).
The ADV7403 offers low power consumption: 1.8 V digital
core, 3.3 V analog and digital input/output, low power power-
down mode, and green PC mode.
The ADV7403BSTZ-110 operates over the industrial temperature
range (−40°C to +85°C) and is available in a 100-lead, 14 mm ×
14 mm, RoHS-compliant LQFP.
It is also available in a 140 MHz speed grade (ADV7403KST-140).
Rev. B | Page 13 of 20
ADV7403 Data Sheet
THEORY OF OPERATION
ANALOG FRONT END
The ADV7403 analog front end comprises four noise shaped
video (NSV®), 12-bit ADCs that digitize the analog video signal
before applying it to the standard definition processor (SDP) or
component processor (CP). See Table 8 for the maximum sampling
rates. The analog front end uses differential channels to each
ADC to ensure high performance in a mixed signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7403. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping either in the CP or SDP.
Optional antialiasing filters are positioned in front of each
ADC. These filters can be used to band-limit standard
definition video signals, removing spurious, out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
The ADV7403 can support simultaneous processing of CVBS and
RGB standard definition signals to enable SCART compatibility
and overlay functionality. A combination of CVBS and RGB
inputs can be mixed and output under control of I2C registers
and the fast blank pin.
Table 8. Maximum ADC Sampling Rates
Model Maximum ADC Sampling Rate (MHz)
ADV7403BSTZ-110 110
ADV7403KSTZ-140 140
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-Video and YUV formats.
The video standards supported by the SDP include PAL (B, D, I,
G, H, M, N, Nc, 60), NTSC (J, M, 4.43), and SECAM (B, D, G,
K, L). The ADV7403 can automatically detect the video standard
and process it accordingly.
The SDP has a super adaptive 2-D, 5-line comb filter that gives
superior chrominance and luminance separation when decoding a
composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to video standard and
signal quality with no user intervention required. The SDP has
an IF filter block that compensates for attenuation in the high
frequency luma spectrum due to the tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7403 implements a patented adaptive digital line length
tracking (ADLLT™) algorithm to track varying video line lengths
from sources such as a VCR. ADLLT enables the ADV7403 to
track and decode poor quality video sources such as VCRs, noisy
sources from tuner outputs, VCD players, and camcorders. The
SDP also contains a chroma transient improvement (CTI)
processor. This processor increases the edge rate on chroma
transitions, resulting in a sharper video image.
The SDP can process a variety of VBI data services, such as
TeleText, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), Gemstar
1×/2×, and extended data service (XDS). The ADV7403 SDP
section has a Macrovision 7.1 detection circuit that allows it to
detect Types I, II, and III protection levels. The decoder is also
fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA at 75 Hz (ADV7403KSTZ-140
only), and many other standards not listed here.
The CP section of the ADV7403 contains an AGC block. When
no embedded sync is present, the video gain can be set manually.
The AGC section is followed by a digital clamp circuit that
ensures that the video signal is clamped to the correct blanking
level. Automatic adjustments within the CP include gain (contrast)
and offset (brightness); manual adjustment controls are also
supported.
A fully programmable any-to-any, 3 × 3 color space conversion
matrix is placed between the analog front end and the CP section.
This enables YPrPb-to-RGB and RGB-to-YCrCb conversions.
Many other standards of color space can be implemented using
the color space converter.
The output section of the CP is highly flexible. It can be configured
in SDR with one data packet per clock cycle or in a DDR mode
where data is presented on the rising and falling edges of the
clock. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output
is possible. In these modes, HS, VS, and FIELD/DE (where
applicable) timing reference signals are provided. In DDR mode,
the ADV7403 can be configured in an 8-/10-bit 4:2:2 YcrCb or
12-bit 4:4:4 Yc r C b /RGB pixel output interface with corresponding
timing signals.
Rev. B | Page 14 of 20
Data Sheet ADV7403
The ADV7403 is capable of supporting an external DVI/HDMI
receiver. The digital interface expects 24-bit 4:4:4 or 16-/20-bit
4:2:2 bit data (either graphics RGB or component video YcrCb),
accompanied by HS, VS, DE, and a fully synchronous clock
signal. The data is processed in the CP and output as 16-bit
4:2:2 YcrCb data.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section of
the ADV7403 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the I2C
interface. For more detailed product information, see the
ADV7403 product page.
Rev. B | Page 15 of 20
ADV7403 Data Sheet
PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Pixel Port Pins P[19:0]
Processor Mode Format 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDP Video out, 8-bit, 4:2:2 YcrCb[7:0]OUT
SDP Video out, 10-bit, 4:2:2 YcrCb[9:0]OUT
SDP
Video out, 16-bit, 4:2:2
Y[7:0]
OUT
CrCb[7:0]
OUT
SDP Video out, 20-bit, 4:2:2 Y[9:0]OUT CrCb[9:0]OUT
SDP Video out, 24-bit, 4:4:4 Y[7:0]OUT Cb[7:0]OUT
SDP Video out, 30-bit, 4:4:4 Y[9:0]OUT Cb[9:0]OUT
SM-SDP Digital tuner input[1] Output choices are the same as video out 16-/20-bit or pseudo 8-/10-bit DDR
CP 8-bit, 4:2:2, DDR D7 D6 D5 D4 D3 D2 D1 D0
CP
10-bit, 4:2:2, DDR
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CP 12-bit, 4:4:4, RGB DDR D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8
CP Video out, 16-bit, 4:2:2 CHA[7:0]OUT (for example, Y[7:0]) CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
CP
Video out, 20-bit, 4:2:2
CHA[9:0]
OUT
(for example, Y[9:0])
CHB/C[9:0]
OUT
(for example, Cr/Cb[9:0])
CP Video out, 24-bit, 4:4:4 CHA[7:0]OUT (for example, G[7:0]) CHB[7:0]OUT (for example, B[7:0])
CP Video out, 30-bit, 4:4:4 CHA[9:0]OUT (for example, G[9:0]) CHB[9:0]OUT (for example, B[9:0])
SM-CP HDMI receiver support,
24-bit, 4:4:4 input
CHA[7:0]OUT (for example, Y[7:0]) R[5:4]IN CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) R[1:0]IN
SM-CP
HDMI receiver support
16-bit pass through
CHA[7:0]
OUT
(for example, Y[7:0])
CHB/C[7:0]
OUT
(for example, Cr/Cb[7:0])
SM-CP HDMI receiver support,
20-bit, pass through
CHA[9:0]OUT (for example, Y[9:0]) CHB/C[9:0]OUT (for example, Cr/Cb[9:0])
Rev. B | Page 16 of 20
Data Sheet ADV7403
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
Pixel Port Pins P[40:31], P[29:20]
Processor Mode Format 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20
SDP Video out, 8-bit, 4:2:2
SDP Video out, 10-bit, 4:2:2
SDP Video out, 16-bit, 4:2:2
SDP Video out, 20-bit, 4:2:2
SDP
Video out, 24-bit, 4:4:4
Cr[7:0]
OUT
SDP Video out, 30-bit, 4:4:4 Cr[9:0]OUT
SM-SDP Digital tuner input[1] DCVBS[9:0]IN
CP 8-bit, 4:2:2, DDR
CP 10-bit, 4:2:2, DDR
CP 12-bit, 4:4:4, RGB DDR
CP Video out, 16-bit, 4:2:2
CP Video out, 20-bit, 4:2:2
CP Video out, 24-bit, 4:4:4
input
CHC[7:0]OUT (for example, R[7:0])
CP Video out, 30-bit, 4:4:4
input
CHC[9:0]OUT (for example, R[9:0])
SM-CP HDMI receiver support,
24-bit, 4:4:4 input
G[7:0]IN R[7:6]IN B[7:0]IN R[3:2]IN
SM-CP HDMI receiver support,
16-bit, pass through
CHA[7:0]IN(for example, Y[7:0]) CHB/C[7:0]IN(for example, Cr/Cb[7:0])
SM-CP HDMI receiver support,
20-bit, pass through
CHA[9:0]IN(for example, Y[9:0]) CHB/C[9:0]IN(for example, Cr/Cb[9:0])
Rev. B | Page 17 of 20
ADV7403 Data Sheet
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
Place the external loop filter components for the ELPF pin as
close as possible to the respective pins. Figure 8 shows the
recommended component values.
05431-008
1.69kΩ
82nF
10nF
PVDD = 1.8V
PIN 46–E LPF
Figure 8. ELPF Components
Rev. B | Page 18 of 20
Data Sheet ADV7403
TYPICAL CONNECTION DIAGRAM
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
56
Ω
AGND
10nF
0.1
µ
F
10nF
0.1
µ
F
10nF
0.1
µ
F
DVDD_1.8V
DGND
U1 BYPASS CAPACITO RS
10nF
0.1
µ
F
10nF
0.1
µ
F
DVDDIO
DGND
U1 BYPASS CAPACITO RS
10nF
0.1
µ
F
AGND
PVDD_1.8V
10nF
0.1
µ
F
AGND
AVDD_3.3V
75
Ω
GREEN
BLUE
RED
RGB
GRAPHICS
P5–2
P5–3
P5–1
P5–13
P5–14
P6–5
P6–6
P5–7
P5–8
P5–10
HS_IN
VS_IN
1
3
5
21
2
4
6
P4
SCART_21_PIN
20 19
18 17
16 15
14 13
12 11
10 9
87
65
43
21
4
3
2
1
P8
MINI-DIN-4
S-VIDEO
SOG
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SOY
AIN10
AIN11
AIN12
AIN7
AIN8
AIN9
CAPC2
CAPC1
CAPY2
CAPY1
CML
REFOUT
BIAS
XTAL
XTAL1
ELPF
SDA
SCLK
SDA2
SCLK2
ALSB
RESET
1
3
2
4
19Ω
19Ω
20 CVBS/Y
CVBS
P9
AGND
19Ω
56Ω
0.1µF
PVDD
PVDD
AVDD
DVDD
DVDD
DVDD
DVDDIO
DVDDIO
DE_IN
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
INT
DCLK_IN
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
LLC1
CS/HS
VS
FIELD
HS_IN/CS_IN
VS_IN
SFL/SYNC_OUT
FB
TEST1
TEST0
AGND
AGND
PVSS
PVSS
DGND
DGND
DGND
DGND
DGND
ADV7403
33ΩVP4179 33ΩVP4083 33ΩVP39
84 33ΩVP3887 33ΩVP3788 33ΩVP36
95 33ΩVP35
96 33ΩVP34
97 33ΩVP33
100 33ΩVP32133ΩVP31
233ΩVP303
33ΩVP29
13 33ΩVP2814 33ΩVP27
24 33ΩVP26
29 33ΩVP2530 33ΩVP24
31 33ΩVP2332 33ΩVP22
33 33ΩVP2134 33ΩVP20
45
33ΩVP19
91 33ΩVP18
92 33ΩVP17
93 33ΩVP1694 33ΩVP15733ΩVP14833ΩVP13933ΩVP1210 33ΩVP11
20 33ΩVP1021 33ΩVP09
22 33ΩVP0823 33ΩVP07
25 33ΩVP0626 33ΩVP05
27 33ΩVP0428
VP[00:41]
INT
DCLCK_IN
33ΩVP0341 33ΩVP02
42 33ΩVP01
43 33ΩVP00
44
100Ω4100Ω
99 100Ω
98 100Ω
86 100Ω85
33Ω
15
HS
VS
FIELD
HS_IN
VS_IN
SFL/SYNC_OUT
100Ω36
10nF
0.1
µ
F
10
µ
F
0.1
µ
F
AGND
10nF
0.1
µ
F10
µ
F
0.1
µ
F
AGND 0.1
µ
F10
µ
F
10
µ
F
0.1
µ
F
2.7k
Ω
2.7k
Ω
Y2
28.63636MHz
1MΩ
47pF
1
47pF
1
DGND
10nF
82nF
PVDD_1.8V
1.69kΩ
100Ω
100Ω
5.6kΩ
SDA
SCLK
RESET
DVDDIO
K1
K2
BAT54C DVDDIO
PVDD_1.8V DVDD_1.8V
AVDD_3.3V
DVDDIO
U1
47
48
63
12
39
90
6
18
C22 1nF
C94 1nF
D1
BZX399-C3V3
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
Y
C
AGND
1
LO AD CAP V ALUES ARE DE P E NDANT ON CRY S TAL ATTRIBUTE S
AGND
Pr/Pb
Pb/Pr
Y
RED/C
GREEN
F_BLNK
BLUE
PHONO3
AGND
05431-009
U1 BYPASS CAPACITO RS
10k
Ω
35
70
66
60
49
50
5
17
11
40
89
LLC1
52
54
56
58
72
74
76
77
71
73
75
53
55
57
69
68
62
61
65
64
67
38
37
46
81
82
19
16
80
78
51
59
AGND
+
+
P7
16
2
11
15
AGND DGND
Figure 9. ADV7403 Typical Connection Diagram
Rev. B | Page 19 of 20
ADV7403 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS-026-BE D
TOP VIEW
(PINS DOW N)
1
25 26 51
50
75
76100
0.50
BSC
LEAD P IT CH
0.27
0.22
0.17
1.60 M AX
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08
COPLANARITY
VIEW A
ROTAT E D 90° CCW
SEATING
PLANE
7°
3.5°
0°
14.20
14.00 SQ
13.80
16.20
16.00 SQ
15.80
051706-A
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
ADV7403BSTZ-110 −40°C to +85°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
ADV7403KSTZ-140 0°C to 70°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
EVAL-ADV7403EBZ Evaluation Board
1 The ADV7403 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition,
it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at
conventional reflow temperatures of 220°C to 235°C.
2 Z = RoHS Compliant Part.
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05431-0-9/13(B)
Rev. B | Page 20 of 20
