© Semiconductor Components Industries, LLC, 2010
August, 2020 − Rev. 4
1Publication Order Number:
FAN4860/D
Synchronous Regulator,
TINYBOOST), 3 MHz
FAN4860
Description
The FAN4860 is a low−power boost regulator designed to provide a
regulated 3.3 V, 5.0 V or 5.4 V output from a single cell Lithium or
Li−Ion battery. Output voltage options are fixed at 3.3 V, 5.0 V, or
5.4 V with a guaranteed maximum load current of 200 mA at
VIN = 2.3 V and 300 mA at VIN = 3.3 V. Input current in Shutdown
Mode is less than 1 μA, which maximizes battery life.
Light−load PFM operation is automatic and “glitch−free”. The
regulator maintains output regulation at no−load with as low as 37 μA
quiescent current.
The combination of built−in power transistors, synchronous
rectification, and low supply current make the FAN4860 ideal for
battery powered applications.
The FAN4860 is available in 6−bump 0.4 mm pitch Wafer−Level
Chip Scale Package (WLCSP) and a 6−lead 2 x 2 mm ultra−thin MLP
package.
Features
•Operates with Few External Components:
1 μH Inductor and 0402 Case Size Input and Output Capacitors
•Input Voltage Range from 2.3 V to 5.4 V
•Fixed 3.3 V, 5.0 V, or 5.4 V Output Voltage Options
•Maximum Load Current >150 mA at VIN = 2.3 V
•Maximum Load Current 300 mA at VIN = 3.3 V, V OUT = 5.4 V
•Maximum Load Current 300 mA at VIN = 3.3 V, VOUT = 5.0 V
•Maximum Load Current 300 mA at VIN = 2.7 V, VOUT = 3.3 V
•Up to 92% Efficient
•Low Operating Quiescent Current
•True Load Disconnect During Shutdown
•Variable On−time Pulse Frequency Modulation (PFM) with
Light−Load Power−Saving Mode
•Internal Synchronous Rectifier
(No External Diode Needed)
•Thermal Shutdown and Overload Protection
•6−Pin 2 ×2 mm UMLP
•6−Bump WLCSP, 0.4 mm Pitch
Applications
•USB “On the Go” 5 V Supply
•5 V Supply – HDMI, H−Bridge Motor Drivers
•Powering 3.3 V Core Rails
•PDAs, Portable Media Players
•Cell Phones, Smart Phones, Portable Instruments
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WLCSP6 1.23 x 0.88 x 0.586
CASE 567RP
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
UDFN6 2 x 2, 0.65P
CASE 517DS
EN
SW
L1
GNDVIN
FB
VOUT
C2
C1
B2
B1
A2A1
VIN CIN 2.2 μF
1 μH
4.7 μF
COUT
TYPICAL APPLICATION
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Table 1. ORDERING INFORMATION
Part Number Operating Temperature Range Package Packing Method
FAN4860UC5X −40°C to 85°CWLCSP, 0.4 mm Pitch Tape and Reel
FAN4860UMP5X −40°C to 85°CUMLP−6, 2 x 2 mm Tape and Reel
FAN4860UC33X* −40°C to 85°CWLCSP, 0.4 mm Pitch Tape and Reel
FAN4860UC54X* −40°C to 85°CWLCSP, 0.4 mm Pitch Tape and Reel
*This device is End of Life. Please contact sales for additional information and assistance with replacement devices.
BLOCK DIAGRAMS
Figure 1. IC Block Diagram
EN
VOUT
Q2
Q1
Modulator Logic
and Control
Q3
VIN
SW
Synchronous
Rectifier
Control
GND
FB
L1
EN
VOUT
Q2
Q1
Modulator Logic
and Control
Q3
VIN
SW
Synchronous
Rectifier
Control
GND
FB
L1
VIN
CIN
COUT
PIN CONFIGURATIONS
Figure 2. WLCSP (Top View)
VIN
SW
EN
GND
VOUT
FB
C2C1
B2
B1
A2 VIN
SW
EN
GND
VOUT
FB C1C2
B1B2
A1
FB
SW
VINGND
EN
1 6
2 5
3 4
P1
(GND)
Figure 3. WLCSP (Bottom View) Figure 4. 2y2 mm UMLP (Top View)
A2
A1
VOUT
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Table 2. PIN DEFINITIONS
Pin #
Name Description
WLCSP UMLP
A1 6 VIN Input Voltage. Connect to Li−Ion battery input power source and input capacitor (CIN)
B1 5 SW Switching Node. Connect to inductor
C1 4 EN Enable. When this pin is HIGH, the circuit is enabled. This pin should not be left floating
C2 3 FB Feedback. Output voltage sense point for VOUT
. Connect to output capacitor (COUT)
B2 2 VOUT Output Voltage. This pin is both the output voltage terminal as well as an IC bias supply
A2 1, P1 GND Ground. Power and signal ground reference for the IC. All voltages are measured with
respect to this pin
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min. Max. Units
VIN VIN Pin −0.3 5.5 V
VOUT VOUT Pin –2 6 V
VFB FB Pin –2 6 V
VSW SW Node DC −0.3 5.5 V
Transient: 10 ns, 3 MHz −1.0 6.5
VEN EN Pin −0.3 5.5 V
ESD Electrostatic Discharge Protection Level Human Body Model per JESD22−A114 2kV
Charged Device Model per
JESD22−C101
1
TJJunction Temperature –40 +150 °C
TSTG Storage Temperature –65 +150 °C
TLLead Soldering Temperature, 10 Seconds +260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Units
VIN Supply Voltage 5.4 VOUT 2.3 4.5 V
5.0 VOUT 2.3 4.5
3.3 VOUT 2.5 3.2
IOUT Output Current 200 mA
TAAmbient Temperature –40 +85 °C
TJJunction Temperature –40 +125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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Table 5. THERMAL PROPERTIES
Symbol Parameter Typical Units
θJA Junction−to−Ambient Thermal Resistance WLCSP 130 °C/W
UMLP 57 °C/W
1. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards
in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient
temperate TA.
Table 6. ELECTRICAL SPECIFICATIONS
(Minimum and maximum values are at VIN = VEN = 2.3 V to 4.5 V (2.5 to 3.2 VIN for 3.3 VOUT option), TA = −40°C to +85°C; circuit of
Typical Application, unless otherwise noted. Typical values are at TA = 25°C, VIN = VEN = 3.6 V for VOUT = 5.0 V / 5.4 V,
and VIN = VEN = 2.7 V for VOUT = 3.3 V)
Symbol Parameter Conditions Min Typ Max Units
IIN VIN Input Current 5.4 VOUT Quiescent: VIN = 3.6 V, IOUT = 0, EN = VIN 37 45 μA
Shutdown: EN = 0, VIN = 3.6 V 0.5 1.5 μA
5.0 VOUT Quiescent: VIN = 3.6 V, IOUT = 0, EN = VIN 37 45
Shutdown: EN = 0, VIN = 3.6 V 0.5 1.5
3.3 VOUT Quiescent: VIN = 2.7 V, IOUT = 0, EN = VIN 50 65
Shutdown: EN = 0, VIN = 2.7 V 0.5 1.5
ILK_OUT VOUT Leakage Current VOUT = 0, EN = 0, VIN ≥3 V 10 nA
ILK_RVSR VOUT to VIN Reverse
Leakage
VOUT = 5.4 V, VIN = 3.6 V, EN = 0 2.5 μA
VOUT = 5.0 V, VIN = 3.6 V, EN = 0
VOUT = 3.3 V, VIN = 3.0 V, EN = 0
VUVLO Under−Voltage Lockout VIN Rising 2.2 2.3 V
VUVLO_HYS Under−Voltage Lockout
Hysteresis
190 mV
VENH Enable HIGH Voltage 1.05 V
VENL Enable LOW Voltage 0.4 V
ILK_EN Enable Input Leakage
Current
0.01 1.00 μA
VOUT Output Voltage Accuracy
(Note 2)
VIN from 2.3 V to 4.5 V, IOUT ≤200 mA 5.15 5.40 5.50 V
VIN from 2.7 V to 4.5 V, IOUT ≤200 mA 5.20 5.40 5.50
VIN from 3.3 V to 4.5 V, IOUT ≤300 mA 5.15 5.40 5.50
VIN from 2.3 V to 4.5 V, IOUT ≤200 mA 4.80 5.05 5.15
VIN from 2.7 V to 4.5 V, IOUT ≤200 mA 4.85 5.05 5.15
VIN from 3.3 V to 4.5 V, IOUT ≤300 mA 4.85 5.05 5.15
VIN from 2.5 V to 3.2 V, IOUT ≤200 mA 3.17 3.33 3.41
vref Reference Accuracy Referred to VOUT = 5.4 V 5.325 5.400 5.475 V
Referred to VOUT = 5.0 V 4.975 5.050 5.125
Referred to VOUT = 3.3 V 3.280 3.330 3.380
tOFF Off Time VIN = 3.6 V, VOUT = 5.4 V, IOUT = 200 mA 185 230 255 ns
VIN = 3.6 V, VOUT = 5.0 V, IOUT = 200 mA 195 240 265
VIN = 2.7 V, VOUT = 3.3 V, IOUT = 200 mA 240 290 350
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Table 6. ELECTRICAL SPECIFICATIONS (continued)
(Minimum and maximum values are at VIN = VEN = 2.3 V to 4.5 V (2.5 to 3.2 VIN for 3.3 VOUT option), TA = −40°C to +85°C; circuit of
Typical Application, unless otherwise noted. Typical values are at TA = 25°C, VIN = VEN = 3.6 V for VOUT = 5.0 V / 5.4 V,
and VIN = VEN = 2.7 V for VOUT = 3.3 V)
Symbol UnitsMaxTypMinConditionsParameter
IOUT Maximum Output
Current
(Note 2)
5.4 VOUT VIN = 2.3 V 200 mA
VIN = 3.3 V 300
VIN = 3.6 V 400
5.0 VOUT VIN = 2.3 V 200
VIN = 3.3 V 300
VIN = 3.6 V 400
3.3 VOUT VIN = 2.5 V 250
VIN = 2.7 V 300
ISW SW Peak Current
Limit
5.4 VOUT VIN = 3.6 V, VOUT > VIN 1000 1400 1500 mA
5.0 VOUT VIN = 3.6 V, VOUT > VIN 930 1100 1320
3.3 VOUT VIN = 2.7 V, VOUT > VIN 650 800 950
ISS Soft−Start Input
Peak Current
Limit
(Note 3)
5.4 VOUT VIN = 3.6 V, VOUT < VIN 900 mA
5.0 VOUT VIN = 3.6 V, VOUT < VIN 850
3.3 VOUT VIN = 2.7 V, VOUT < VIN 700
tSS Soft−Start Time
(Note 4)
5.4 VOUT VIN = 3.6 V, IOUT = 200 mA 270 400 μs
5.0 VOUT VIN = 3.6 V, IOUT = 200 mA 100 300
3.3 VOUT VIN = 2.7 V, IOUT = 200 mA 250 750
RDS(ON) N−Channel Boost Switch VIN = 3.6 V 300 mΩ
P−Channel Sync Rectifier VIN = 3.6 V 400
TTSD Thermal Shutdown ILOAD = 10 mA 150 °C
TTSD_HYS Thermal Shutdown
Hysteresis
30 °C
2. ILOAD from 0 to IOUT
; also includes load transient response. VOUT measured from mid−point of output voltage ripple.
Effective capacitance of COUT > 1.5 μF.
3. Guaranteed by design and characterization; not tested in production.
4. Elapsed time from rising EN until regulated VOUT
.
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5.4 VOUT TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA = 25°C.
80,00%
82,00%
84,00%
86,00%
88,00%
90,00%
92,00%
94,00%
96,00%
0 50 100 150 200 250 300
Load Current (mA)
4.5 VIN
3.6 VIN
3.2 VIN
2.5 VIN
82,00%
84,00%
86,00%
88,00%
90,00%
92,00%
94,00%
0 50 100 150 200 250 300
5,24
5,26
5,28
5,3
5,32
5,34
5,36
5,38
5,4
5,42
5,44
0 50 100 150 200 250 300
VOUT (V)
ILOAD (mA)
Iout (mA) @Vin = 4.5 V
Iout (mA) @Vin = 3.6 V
Iout (mA) @Vin = 3.2 V
Iout (mA) @ Vin = 2.5 V
20
30
40
50
60
70
80
90
100
2 2,5 3 3,5 4 4,5 5
Quiescent current (μA)
Input Voltage (V)
200
300
400
500
600
700
800
900
1000
2 2,5 3 3,5 4 4,5
Load Current, max, (mA)
Input voltage (V)
1000
1100
1200
1300
1400
1500
1600
1700
1800
2 2,5 3 3,5 4 4,5
Peak Inductor Current (mA)
Input Voltage (V)
Efficiency (%)
Efficiency (%)
Load Current (mA)
Figure 5. Efficiency vs. VIN
+25°C
−40°C
+85°C
Figure 6. Efficiency vs. Temperature, 3.6 VIN
Figure 7. Line and Load Regulation Figure 8. Quiescent Current
Figure 9. Maximum DC Load Current Figure 10. Peak Inductor Current
+25°C
−40°C
+85°C
+25°C
−40°C
+85°C
+25°C
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5.4 VOUT TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA=25°C.
Figure 11. 0−50 mA Load Transient, 100 ns Step Figure 12. 50−200 mA Load Transient, 100 ns Step
Figure 13. Line Transient, 5 mA Load, 10 s Step Figure 14. Line Transient, 200 mA Load, 10 s Step
5.0 VOUT TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA = 25°C.
Figure 15. Efficiency vs. VIN Figure 16. Efficiency vs. Temperature, 3.6 VIN
75
80
85
90
95
100
0 50 100 150 200 250
Efficiency (%)
Load Current (mA)
300
Efficiency (%)
Load Current (mA)
80
83
86
89
92
95
0 50 100 150 200 250 300
2.5 Vin
3.3 Vin
3.6 Vin
4.5 Vin
+25°C
−40°C
+85°C
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5.0 VOUT TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA = 25°C.
Figure 17. Line and Load Regulation Figure 18. Load Regulation vs. Temperature, 3.6 VIN
Figure 19. Switching Frequency Figure 20. Quiescent Current
0
800
1600
2400
3200
4000
0 50 100 150 200 250
Frequency (KHz)
Load Current (mA)
300
2.5 Vin
3.6 Vin
4.5 Vin 25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Quiescent Current (uA)
Input Voltage(V)
−40C
+25C
+85C
−100
−75
−50
−25
0
25
50
0 50 100 150 200 250
Load Current (mA)
300
2.5 Vin
3.3 Vin
3.6 Vin
4.5 Vin
VOUT − 5.05 V (mV)
VOUT − 5.05 V (mV)
−100
−75
−50
−25
0
25
50
0 50 100 150 200 250
Load Current (mA)
300
Load Current, max. (mA)
Peak Inductor Current (mA)
Input Voltage (V) Input Voltage (V)
Figure 21. Maximum DC Load Current Figure 22. Peak Inductor Current
+25°C
−40°C
+85°C
+25°C
−40°C
+85°C
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5.0 VOUT TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA = 25°C.
Figure 23. Output Ripple, 10 mA PFM Load Figure 24. Output Ripple, 200 mA PWM Load
Figure 25. 0−50 mA Load Transient, 100 ns Step Figure 26. 50−200 mA Load Transient, 100 ns Step
Figure 27. Line Transient, 5 mA Load, 10 s Step Figure 28. Line Transient, 200 mA Load, 10 s Step
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5.0 VOUT TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified; circuit per Typical Application, 3.6 VIN, and TA = 25°C.
Figure 29. Start Up, No load Figure 30. Start Up, 33 Load
Figure 31. Shutdown, 1 k Load Figure 32. Shutdown, 33 Load
Figure 33. Overload Protection Figure 34. Short−Circuit Response
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3.3 VOUT TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application, 3.0 VIN, and TA = 25°C.
Figure 35. Efficiency vs. VIN Figure 36. Efficiency vs. Temperature, 3.0 VIN
Figure 37. Line and Load Regulation Figure 38. Load Regulation vs. Temperature,
3.0 VIN
Figure 39. Quiescent Current Figure 40. Maximum DC Load Current
75
80
85
90
95
100
0 50 100 150 200 250 300
Efficiency (%)
Load Current (mA)
2.5 Vin
2.7 Vin
3.0 Vin
3.2 Vin 83
86
89
92
95
98
0 50 100 150 200 250 300
Efficiency (%)
Load Current (mA)
−40C
+25C
+85C
0
20
40
0 50 100 150 200 250 300
Load Current (mA)
2.5 Vin
2.7 Vin
3.0 Vin
3.2 Vin
−80
−40
−20
0
20
40
0 50 100 150 200 250 300
Load Current (mA)
−40C
+25C
+85C
200
300
400
500
600
700
2.0 2.3 2.6 2.9 3.2 3.5
Maximum DC Load Current (mA)
Input Voltage(V)
−40C
+25C
+85C
30
35
40
45
50
55
2.0 2.3 2.6 2.9 3.2 3.5
Quiescent Current (uA)
Input Voltage(V)
−40C
+25C
+85C
VOUT − 3.33 V (mV)
VOUT − 3.33 V (mV)
−60
−80
−40
−20
−60
+25°C
−40°C
+85°C
+25°C
−40°C
+85°C
+25°C
−40°C
+85°C
+25°C
−40°C
+85°C
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FUNCTIONAL DESCRIPTION
Circuit Description
The FAN4860 is a synchronous boost regulator, typically
operating at 3 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
low VIN voltages.
At light−load currents, the converter switches
automatically to power−saving PFM Mode. The regulator
automatically and smoothly transitions between
quasi−fixed−frequency continuous conduction PWM Mode
and variable−frequency PFM Mode to maintain the highest
possible efficiency over the full range of load current and
input voltage.
PWM Mode Regulation
The FAN4860 uses a minimum on−time and computed
minimum off−time to regulate VOUT. The regulator achieves
excellent transient response by employing current mode
modulation. This technique causes the regulator output to
exhibit a load line. During PWM Mode, the output voltage
drops slightly as the input current rises. With a constant VIN,
this appears as a constant output resistance.
The “droop” caused by the output resistance when a load
is applied allows the regulator to respond smoothly to load
transients with negligible overshoot.
100
200
300
400
500
600
700
2.0 2.5 3.0 3.5 4.0 4.5
Output Resistance (mA)
Input Voltage (V)
5.0
Figure 45. Output Resistance (ROUT)
3.3
5.0
VOUT
VOUT
When the regulator is in PWM CCM Mode and the target
VOUT = 5.05 V, VOUT is a function of ILOAD and can be
computed as:
VOUT +5.05 *ROUT ILOAD (eq. 1)
For example, at VIN = 3.3 V, and ILOAD = 200 mA, VOUT
drops to:
VOUT +5.05 *0.38 0.2 +4.974 V (eq. 2)
At VIN = 2.3 V, and ILOAD = 200 mA, VOUT drops to:
VOUT +5.05 *0.68 0.2 +4.914 V (eq. 3)
PFM Mode
If VOUT > VREF when the minimum off−time has ended,
the regulator enters PFM Mode. Boost pulses are inhibited
until VOUT < VREF. The minimum on−time is increased to
enable the output to pump up sufficiently with each PFM
boost pulse. Therefore, the regulator behaves like a constant
on−time regulator, with the bottom of its output voltage
ripple at 5.05 V in PFM Mode.
Table 7. OPERATING STATES
Mode Description Invoked When:
LIN Linear Startup VIN > VOUT
SS Boost Soft−Start VOUT < VREG
BST Boost Operating
Mode VOUT = VREG
Shutdown and Startup
If EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, true load disconnect
between battery and load prevents current flow from VIN to
VOUT, as well as reverse flow from VOUT to VIN.
LIN State
When EN rises, if VIN > UVLO, the regulator first
attempts to bring VOUT within about 1V of VIN by using the
internal fixed current source from VIN (ILIN1). The current
is limited to about 630 mA during LIN1 Mode.
If VOUT reaches VIN−1V during LIN1 Mode, the SS state
is initiated. Otherwise, LIN1 times out after 16 clock counts
and the LIN2 Mode is entered.
In LIN2 Mode, the current source is incremented to
850 mA. If VOUT fails to reach VIN−1 V after 64 clock
counts, a fault condition is declared.
SS State
Upon the successful completion of the LIN state (VOUT >
VIN − 1 V), the regulator begins switching with boost pulses
current limited to about 50% of nominal level, incrementing
to full scale over a period of 32 clock counts.
If the output fails to achieve 90% of its set point within 96
clock counts at full−scale current limit, a fault condition is
declared.
BST State
This is the normal operating mode of the regulator. The
regulator uses a minimum tOFF−minimum tON modulation
scheme. Minimum tOFF is proportional to VIN / VOUT,
which keeps the regulator’s switching frequency reasonably
constant in CCM. tON(MIN) is proportional to VIN and is
higher if the inductor current reaches 0 before tOFF(MIN)
during the prior cycle.
To ensure that VOUT does not pump significantly above
the regulation point, the boost switch remains off as long as
FB > VREF.
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Fault State
The regulator enters the FAULT state under any of the
following conditions:
•VOUT fails to achieve the voltage required to advance
from LIN state to SS state
•VOUT fails to achieve the voltage required to advance
from SS state to BST state
•Sustained (32 CLK counts) pulse−by−pulse current
limit during the BST state
•The regulator moves from BST to LIN state due to a
short circuit or output overload (VOUT < VIN−1 V)
Once a fault is triggered, the regulator stops switching and
presents a high−impedance path between VIN and VOUT.
After waiting 480 CLK counts, a restart is attempted.
Soft−Start and Fault Timing
The soft−start timing for each state, and the fault times, are
determined by the fault clock, whose period is inversely
proportional to VIN. This allows the regulator more time to
charge larger values of COUT when VIN is lower. With higher
VIN, this also reduces power delivered to VOUT during each
cycle in current limit.
Figure 46. Fault Response into Short Circuit
ILIN2
VOUT
0
6416
ILIN1
EN
0 V
480
8
The fault clock period as a function of VIN is shown in
Figure 47.
Figure 47. Fault Clock Period vs. VIN
The VIN−dependent LIN Mode charging current is
illustrated in Figure 48.
Figure 48. LIN Mode Current vs. VIN
Over−Temperature Protection (OTP)
The regulator shuts down when the thermal shutdown
threshold is reached. Restart, with soft−start, occurs when
the IC has cooled by about 30°C.
Over−Current Protection (OCP)
During Boost Mode, the FAN4860 employs a
cycle−by−cycle peak current limit to protect switching
elements. Sustained current limit, for 32 consecutive fault
clock counts, initiates a fault condition.
During an overload condition, as VOUT collapses to
approximately VIN-1 V, the synchronous rectifier is
immediately switched off and a fault condition is declared.
Automatic restart occurs once the overload/short is
removed and the fault timer completes counting.
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APPLICATION INFORMATION
External Component Selection
Table 8 shows the recommended external components for
the FAN4860:
Table 8. EXTERNAL COMPONENTS
REF Description Manufacturer
L1 1.0 μH, 0.8 A,
190 mΩ, 0805
Murata
LQM21PN1R0MC0,
or equivalent
CIN 2.2 μF, 6.3 V, X5R, 0402 Murata
GRM155R60J225M
TDK C1005X5R0J225M
COUT 4.7 μF, 10 V, X5R, 0603
(Note 5)
Kemet
C0603C475K8PAC
TDK C1608X5R1A475K
5. A 6.3 V−rated 0603 capacitor may be used for COUT
, such as
Murata GRM188R60J225M. All datasheet parameters are valid
with the 6.3 V−rated capacitor. Due to DC bias effects, the 10 V
capacitor offers a performance enhancement; particularly output
ripple and transient response, without any size increase.
Output Capacitance (COUT)
Stability
The effective capacitance (CEFF) of small, high−value,
ceramic capacitors decrease as their bias voltage increases,
as shown in Figure 49.
Figure 49. CEFF for 4.7 F, 0603, X5R, 6.3 V
(Murata GRM188R60J475K)
FAN4860 is guaranteed for stable operation with the
minimum value of CEFF (CEFF(MIN)) outlined in Table 9.
Table 9. MINIMUM CEFF REQUIRED FOR STABILITY
Operating Conditions
CEFF(MIN) (F)
VIN (V) ILOAD (mA)
2.3 to 4.5 0 to 200 1.5
2.7 to 4.5 0 to 200 1.0
2.3 to 4.5 0 to 150 1.0
CEFF varies with manufacturer, dielectric material, case
size, and temperature. Some manufacturers may be able to
provide an X5R capacitor in 0402 case size that retains CEFF
> 1.5 μF with 5 V bias; others may not. If this CEFF cannot
be economically obtained and 0402 case size is required, the
IC can work with the 0402 capacitor as long as the minimum
VIN is restricted to > 2.7 V.
For best performance, a 10 V−rated 0603 output capacitor
is recommended (Kemet C0603C475K8PAC, or
equivalent). Since it retains greater CEFF under bias and over
temperature, output ripple can is reduced and transient
capability enhanced.
Output Voltage Ripple
Output voltage ripple is inversely proportional to COUT.
During tON, when the boost switch is on, all load current is
supplied by COUT.
VRIPPLE(P*P) +tON
lLOAD
COUT (eq. 4)
and
tON +tSW D+tSW (1 *
VIN
VOUT
)(eq. 5)
Therefore:
VRIPPLE(P*P) +tSW (1 *
VIN
VOUT
)
ILOAD
COUT (eq. 6)
Where:
tSW +1
fSW (eq. 7)
As can be seen from Equation 6, the maximum VRIPPLE
occurs when VIN is minimum and ILOAD is maximum.
Startup
Input current limiting is in effect during soft−start, which
limits the current available to charge COUT. If the output
fails to achieve regulation within the time period described
in the soft−start section above; a FAULT occurs, causing the
circuit to shut down, then restart after a significant time
period. If COUT is a very high value, the circuit may not start
on the first attempt, but eventually achieves regulation if no
load is present. If a high−current load and high capacitance
are both present during soft−start, the circuit may fail to
achieve regulation and continually attempt soft−start, only
to have COUT discharged by the load when in the FAULT
state.
The circuit can start with higher values of COUT under full
load if VIN is higher, since:
IOUT +(ILIM(PK) *
IRIPPLE
2)
VIN
VOUT (eq. 8)
Generally, the limitation occurs in BST Mode.
FAN4860
www.onsemi.com
16
The FAN4860 starts on the first pass (without triggering
a FAULT) under the following conditions for CEFF(MAX):
Table 10. MAXIMUM CEFF FOR FIRST−PASS
STARTUP
Operating Conditions
CEFF(MAX)
(F)
VIN (V)
RLOAD(MIN) ()
5.4 VOUT 5.0 VOUT 3.3 VOUT
> 2.3 27 25 16 10
> 2.7 27 25 16 15
> 2.7 37 33 20 22
CEFF values shown in Table 10 typically apply to the
lowest VIN. The presence of higher VIN enhances ability to
start into larger CEFF at full load.
Transient Protection
To protect against external voltage transients caused by
ESD discharge events, or improper external connections,
some applications employ an external transient voltage
suppressor (TVS) and Schottky diode (D1 in Figure 50).
Figure 50. FAN4860 with External
Transient Protection
CIN
EN
SW
L1 GNDVIN
FB
VOUT D1 Connector
TVS
C2
C1
B2
B1
A2A1
VIN
COUT2
1 μH
4.7 μF
COUT
2.2 μF
The TVS is designed to clamp the FB line (system VOUT)
to +10 V or –2 V during external transient events. The
Schottky diode protects the output devices from the positive
excursion. The FB pin can tolerate up to 14 V of positive
excursion, while both the FB and VOUT pins can tolerate
negative voltages.
The FAN4860 includes a circuit to detect a missing or
defective D1 by comparing VOUT to FB. If VOUT – FB >
about 0.7 V, the IC shuts down. The IC remains shut down
until VOUT < UVLO and VIN < UVLO + 0.7 or EN is
toggled.
COUT2 may be necessary to preserve load transient
response when the Schottky is used. When a load is applied
at the FB pin, the forward voltage of the D1 rapidly increases
before the regulator can respond or the inductor current can
change. This causes an immediate drop of up to 300 mV,
depending on D1’s characteristics if COUT2 is absent. COUT2
supplies instantaneous current to the load while the regulator
adjusts the inductor current. A value of at least half of the
minimum value of COUT should be used for COUT2. COUT2
needs to withstand the maximum voltage at the FB pin as the
TVS is clamping.
The maximum DC output current available is reduced
with this circuit, due to the additional dissipation of D1.
LAYOUT GUIDELINE
Figure 51. WLCSP Suggested Layout (Top View)
Figure 52. UMLP Suggested Layout (Top View)
PRODUCT−SPECIFIC DIMENSIONS
Product D E X Y
FAN4860UC5X 1.230mm ±0.030 mm 0.880 mm ±0.030 mm 0.240 mm 0.215 mm
FAN4860UC33X
TINYBOOST is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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