1/63May 2003
M58BW016BT, M58BW016BB
M58BW016DT, M58BW016DB
16 Mbi t ( 512 Kb x32, B oot Block, B urst)
3V Supply Flash Memories
PE 4 FEATURES SUMMA R Y
■SUPPLY VOLTAGE
–V
DD = 2.7V to 3.6V for Program, Erase and
Read
–V
DDQ = VDDQIN = 2.4V to 3.6V for I/O Buff ers
–V
PP = 12V for fast Program (optional)
■HIGH PERFORMA NCE
– Access Time: 80, 90 and 100ns
– 56MHz Effective Zero Wait-State Burst Read
– Synchronous B urst Reads
– Async hronous Pa ge Reads
■HARDW ARE BL OCK PROTECTION
–W
P pin Lock Program and E rase
■SOFTWARE BLOCK PROTECTION
– Tuning Protection to Lock Program and
Erase with 64 bit User Programmable Pass-
word (M58BW016B v ersion only)
■OPTIMIZED for FDI DRIVERS
– Fast Program / Erase su spend latenc y
time < 6µs
– Comm on Fla sh Interface
■MEMORY BLOCKS
– 8 Parameters Blocks (Top or Bottom)
– 31 Main Blocks
■LOW POWER CONSUMPTION
– 5µA Typic al Deep Power Down
– 60µA Typi cal Standby
– Automatic Standby after Asynchronous Read
■ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M58 BW 016xT: 8836h
– Bottom Device Code M5 8BW 016xB : 8835h
Figure 1. Packages
BGA
LBGA80 (ZA)
10 x 8 ball array
PQFP80 (T)
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
2/63
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Nam es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. LBGA Conn ections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PQFP Connections (Top view through packag e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Tuning Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Top Boot Block Addresses, M58BW0 16B T, M58BW016DT . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bottom Boot Block Addres ses, M58 BW 016BB , M58B W016DB . . . . . . . . . . . . . . . . . . . 12
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
D ata Inputs/Ou tputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chip En able (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable (GD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
W rite Enable (W ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Latch Enable (L).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Burst Address Ad vance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Suppl y Vo ltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Out put Suppl y Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inpu t Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program /Era se Supply Voltage (VPP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BUS OPERAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Async hronou s Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Async hronou s Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Async hronou s Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Async hronou s Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Async hronou s Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Asynchronous Read Electronic Signature Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Synchronous Bu s Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Sy nchronous Burst Read Bus Operat ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Burst Config uration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
R ead Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
X-Latency Bi ts (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Y-Latency Bi t (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Burst Type Bit (M7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Wrap Burst Bit (M3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Table 7. Burst Configurati on Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Burst Type D efin ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
R ead Memory Array Com man d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
R ead Electroni c Signature Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
R ead Query Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
R ead Status Register Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Clear Status Reg ister Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program /Era se Suspend Com m and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Set Burst Configuration Register Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tuning Protection Unlock Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Tuning Protection Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 27
STATUS REGIST ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program/Erase Controller Status (Bi t 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Erase S uspend S tatus (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Status, Tuning Protection Unlock Status (Bit 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Susp end Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Ab solute Maximum Ra tings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
4/63
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Operating and AC Measuremen t Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. AC Meas urement Input Outpu t Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. AC Meas urement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. DC Ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Asynchronous B us Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Asynchrono us Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Asynchrono us Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 34
Figure 11. Asynchronou s Page Read AC Wav efo rms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Asynchrono us Page Read AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Asynchronous Latch Controlled Write AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Asynchrono us Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . 38
Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 39
Table 20. Synchronous Burst Read AC Characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 40
Figure 16. Synchronous Burst Read - C ontinuous - Valid Data Ready Output. . . . . . . . . . . . . . . 41
Figure 17. Synchronous Burst Read - Burst Address Advanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. Reset, Power-Down a nd Power-up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Reset, Power-Down and Pow er-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
PAC KAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. LBGA80 10x12m m - 8x10 ball array, 1mm pitch, Bottom View Package Outlin e . . . . 43
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Pack age Mecha nical Data. . . . . . . . 43
Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package O utline. . . . . . . . . . . . . . . . . . . . 44
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Pack age Mecha nical Data. . . . . . . . . . . . . 44
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. COMMO N FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26 . CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27 . CFI - Device Vo ltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
APPENDIX B. F LOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. Program Flowchart and Ps eudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. Program Suspend & Resume Flowch art and Pseudo Code . . . . . . . . . . . . . . . . . . . . 50
Figure 23. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. Unlock De vice and Change Tuning Protect ion Code Flowc hart . . . . . . . . . . . . . . . . . 53
5/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 26. Unlock Dev ice and Program a Tuning Protected Block Flowchart. . . . . . . . . . . . . . . . 54
Figure 27. Unlock Dev ice and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . 55
Figure 28. Pow er-u p Sequ ence to Burst the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 29. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 57
Figure 30. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 58
Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 59
Figure 32. Command Interface and Program Erase Controller Flowchart (d). . . . . . . . . . . . . . . . 60
Figure 33. Command Interface and Program Erase Controller Flowchart (e). . . . . . . . . . . . . . . . 61
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 30 . Document Revisio n History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
6/63
SUMMARY DESCRIPTION
The M58BW016B/D is a 16Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Double-
Word basis using a 2.7V to 3.6V VDD supply for the
circuit and a VDDQ su pply down to 2.4V for the In-
put and Output buffers. Optionally a 12V VPP sup-
ply can be used to provide fast program and erase
for a limited time and number of program/erase cy-
cles.
The devices support Asynchronous (Latch Con-
trolled and Page Read) and Synchronous Bus op-
erations. The Synchronous Burst Read Interface
allows a high data transfer rate controlled by the
Burst Clock, K, signal. It is capable of bursting
fixed or unlimited lengths of data. The burst type,
latency and length are configurable and can be
easily adapted to a large variety of system clock
frequencies and microprocessors. All Writes are
Asynchronous. On power-up the memory defaults
to Read mode with a n Asynchronous B us.
The device has a boot block architecture with an
array of 8 parameter block of 64Kb each and 31
main blocks of 512Kb each. The parameter blocks
can be located at the top of the address space,
M58BW016BT, M58BW016DT or at the bottom,
M58BW 016BB , M58B W016DB.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Prog ram can be suspended to Read dat a
in any ot her block and then res umed. E ach block
can be programmed and eras ed over 100,0 00 cy-
cles.
All blocks are protected during power-up. The
M58BW016B features four different levels of block
protection to avoid unwanted program/erase oper-
ations. The W P pin offers an hardware prot ection
on two of the parameter blocks and all of the main
blocks. The Program and Erase commands can
be password protected by the Tuning Protection
command. All Program or Erase operations are
blocked when Reset, RP, is held low. The
M58BW016D o ffers the same protection features
with the exception of the Tuning Block Protection
which is disabled in the fact ory.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is lower than in the normal standby mode, the
device is write protected a nd bo th the Sta tus and
the Burst Configuration Registers are cleared. A
recovery time is requi red when th e RP in put goes
High.
The memory is offered in PQFP80 (14 x 20mm)
and LBGA80 (1.0mm pitch) packages and it is
supplied with all the bits erased (set to ’1’).
7/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 2. Logic Diagram Table 1. Signal Names
AI04155
A0-A18
L
DQ0-DQ31
VDD
M58BW016DT
M58BW016DB
E
VSS
RP
G
GD
VDDQ
W
WP
R
K
VPP
B
VSSQ
VDDQIN
M58BW016BT
M58BW016BB
A0-A18 Address inputs
DQ0-DQ7 Data Input/Output, Command Input
DQ8-DQ15 Data Input/Output, Burst Configuration
Register
DQ16-DQ31 Data Input/Output
BBurst Address Advance
EChip Enable
GOutput Enable
K Burst Clock
LLatch Enable
R Valid Data Ready (open drain output)
RP Reset/Power-down
WWrite Enable
GD Output Disable
WP Write Protect
VDD Supply Voltage
VDDQ Power Supply for Output Buffers
VDDQIN Power Supply for Input Buffers only
VPP Optional Supply Voltage for Fast
Program and Fast Erase Operations
VSS Ground
VSSQ Input/Output Ground
NC Not Connected Internally
DU Don’t Use as Internally Connected
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
8/63
Figu re 3. LBGA Co nnecti ons (Top v i ew t hro ugh package)
AI04151b
B
DQ24DQ7VSSQ
F
VDDQ
DQ26DQ4VDDQ
E
DQ29
VSS
DQ0DQ3D
A0
DUA7A11A18A17C
A1
A4A5A8
RP
E
A13A16B
A2
A3A6
VDD
VPP
VDD
A14A
87654321
DQ20DQ18DQ19DQ17DQ11DQ12DQ13
VDDQ
DQ23DQ8VDDQ
H
G
DU
GDW
VDDQIN
DQ16RGLDQ14DQ15
K
J
A15 VSS
A12 A9
A10 NC
DU DU DQ31 DQ30
DQ2 DQ28
DQ6 DQ25 VSSQ
DQ10 DQ9 DQ21
WP
K
DU
DQ1 DQ27
DQ5 NC
DQ22
9/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 4. PQFP Connections (Top view through package)
AI04152b
12
1
73
M58BW016BT
M58BW016BB 53
VDDQ
DQ24
DQ25
DQ18
DQ17
DQ16
DQ19
DQ20
DQ21
DQ22
DQ23
VDDQ
DQ29
DQ26
DQ30
DU
DQ31
DQ28
DQ27
A2
A5
A3
A4
A0
A1
A11
VSS
A12
A13
A14
A10
GD
WP
W
DU
G
VSS
E
K
L
NC
B
RP
VDDQ
DQ7
DQ6
DQ13
DQ14
DQ15
DQ12
DQ11
DQ10
DQ9
VSSQ
DQ8
DQ2
DQ5
DQ0
NC
A18
A16
A17
DQ3
DQ4
VSSQ
VSSQ
A8
A6
A7
VPP
VDD
A9
A15
DQ1
VDDQ
VSSQ
R
VDD
NC
VDDQIN
24
25
32
40
41
64
65
80
M58BW016DT
M58BW016DB
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
10/63
Block Protection
The M58BW 016B features four different levels of
block protection . The M5 8BW016D h as the same
block protection with the exception of the Tuning
Block Protection , which is d isabled in the factory.
■Write Protect Pin, WP, - When WP is low , VIL,
all the lockable parameter blocks (two upper
(Top ) or lower (Bottom)) and all t he main blocks
are protected. When WP is high (VIH) all the
locka ble p ar ame ter blo cks and all th e main
blocks are unprotected.
■Reset/Power-Down Pin, RP, - I f the device is
held in reset mode (RP at VIL), no program or
erase operations can be perform ed on any
block.
■Tuning Block Protection: M58BW016B
features a 64 bit password protection for
program and erase operations for a fixed
number of blocks After power-up or reset the
device is tuning protected. An Unlock command
is provided to allow program or erase operations
in all the blocks.
A ft er a de v i ce r es et t h e f i r st t w o k i nds of bl ock p r o-
tection (WP, RP ) can be com bin ed t o give a flexi-
ble block protection. They do not affect the Tuning
Block Protection. When the two protections are
disabled, W P and RP at VIH, the blo cks locked by
the Tuning Block Protection cannot be modified.
All blocks a re protect ed during power-up.
Tuni ng B l oc k P rot ection . The Tuning Block
Protection is a software feature to protect certain
blocks fro m program or erase operat ions. It allo ws
the user to lock program and erase operations with
a user definable 64 bit code. It is only av ailable on
the M58BW016B version.
The code is writ ten once in t he Tuning Protection
Register and cannot be erased. When s hipped the
flash memory will have the Tuning Protection
Code bits set to ‘1'. T he user can program a ‘0’ in
any of the 64 pos itions. Onc e programmed it is not
possible to reset a bit t o ‘ 1’ a s the c ells can not be
erased. The Tuning Protection Register can be
programmed at any moment (after providing the
correct code), however once all bits are set to ‘0’
the Tuning Protection Code can no longer be al-
tered.
The Tuning Protection Code locks the program
and erase operations of 2 parameter and 24 m ain
blocks, blocks 0, 1 and 15-38 for the bottom con-
figuration and the blocks 0-23, 37 and 38 for the
top configuration.
The tuning b locks ar e "lo cked" if th e tuni ng pr otec-
tion code has not been provided, and “unlocked"
once the correct code has been provided. The tun-
ing blocks a re locked afte r re set o r power-up . The
tuning protection status can be monitored in the
Status Register. R efer to the Sta tus Reg ister sec-
tion.
Refer to the Command Interface section for the
Tuning Protection Block Unlock and Tuning Pro-
tection Program commands. See A ppendix B, Fig-
ure 25, 26 and 27 for suggested flowcharts for
using the Tuning Block Protection commands. For
further information on the Tuning Block Protection
refer to Application Note, AN1361.
11/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Table 2. Top Boot Block Addresses,
M58BW016BT, M58BW016DT
Note: 1. TP = Tuning Protected Block, only available for the
M58BW016B.
# Size (Kbit) Address Range TP(1)
38 64 7F800h-7FFFFh yes
37 64 7F000h-7F7FFh yes
36 64 7E800h-7EFFFh no
35 64 7E000h-7E7FFh no
34 64 7D800h-7DFFFh no
33 64 7D000h-7D7FFh no
32 64 7C800h-7CFFFh no
31 64 7C000h-7C7FFh no
30 512 78000h-7BFFFh no
29 512 74000h-77FFFh no
28 512 70000h-73FFFh no
27 512 6C000h-6FFFFh no
26 512 68000h-6BFFFh no
25 512 64000h-67FFFh no
24 512 60000h-63FFFh no
23 512 5C000h-5FFFFh yes
22 512 58000h-5BFFFh yes
21 512 54000h-57FFFh yes
20 512 50000h-53FFFh yes
19 512 4C000h-4FFFFh yes
18 512 48000h-4BFFFh yes
17 512 44000h-47FFFh yes
16 512 40000h-43FFFh yes
15 512 3C000h-3FFFFh yes
14 512 38000h-3BFFFh yes
13 512 34000h-37FFFh yes
12 512 30000h-33FFFh yes
11 512 2C000h-2FFFFh yes
10 512 28000h-2BFFFh yes
9 512 24000h-27FFFh yes
8 512 20000h-23FFFh yes
7 512 1C000h-1FFFFh yes
6 512 18000h-1BFFFh yes
5 512 14000h-17FFFh yes
4 512 10000h-13FFFh yes
3 512 0C000h-0FFFFh yes
2 512 08000h-0BFFFh yes
1 512 04000h-07FFFh yes
0 512 00000h-03FFFh yes
# Size (Kbit) Address Range TP(1)
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
12/63
Table 3. Bottom Boo t Block Addresses,
M58BW016B B, M58BW016 DB
Note: 1. TP = Tuning Protected Block, only available for the
M58BW016B.
# Size (Kbit) Address Range TP(1)
38 512 7C000h-7FFFFh yes
37 512 78000h-7BFFFh yes
36 512 74000h-77FFFh yes
35 512 70000h-73FFFh yes
34 512 6C000h-6FFFFh yes
33 512 68000h-6BFFFh yes
32 512 64000h-67FFFh yes
31 512 60000h-63FFFh yes
30 512 5C000h-5FFFFh yes
29 512 58000h-5BFFFh yes
28 512 54000h-57FFFh yes
27 512 50000h-53FFFh yes
26 512 4C000h-4FFFFh yes
25 512 48000h-4BFFFh yes
24 512 44000h-47FFFh yes
23 512 40000h-43FFFh yes
22 512 3C000h-3FFFFh yes
21 512 38000h-3BFFFh yes
20 512 34000h-37FFFh yes
19 512 30000h-33FFFh yes
18 512 2C000h-2FFFFh yes
17 512 28000h-2BFFFh yes
16 512 24000h-27FFFh yes
15 512 20000h-23FFFh yes
14 512 1C000h-1FFFFh no
13 512 18000h-1BFFFh no
12 512 14000h-17FFFh no
11 512 10000h-13FFFh no
10 512 0C000h-0FFFFh no
9 512 08000h-0BFFFh no
8 512 04000h-07FFFh no
7 64 03800h-03FFFh no
6 64 03000h-037FFh no
5 64 02800h-02FFFh no
4 64 02000h-027FFh no
3 64 01800h-01FFFh no
2 64 01000h-017FFh no
1 64 00800h-00FFFh yes
0 64 00000h-007FFh yes
# Size (Kbit) Address Range TP(1)
13/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
SIGNA L DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18). The Address Inputs
are used to select the c ells to acc ess in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Comman d Interface of the internal state m achine.
Chip Enable must be low when selecting the ad-
dresses.
The address inpu ts are latched on the rising edge
of Latch Enable L or Burst Clock K , whichever oc-
curs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Latch Enable, whichever occurs
first in a Write operation. The address latch is
transparent when Latch Enable is low, VIL. The ad-
dress is internally latc hed in a n E rase or P rogram
operation.
Data Inputs/Output s (DQ0-DQ31). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data dur ing a program operation. Dur-
ing Bus Wri te op erations they repres ent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occu rs first.
When Chip Enable and Output Enable are both
low, VIL, and Output Disable is at VIH, the data bus
outputs data from the memory array, the Electron-
ic Signature, the CFI Information or the contents of
the Status Register. The data bus is high imped-
ance when the device is deselected with Chip En-
able at VIH, Out put E na ble at VIH, O utp u t Di sabl e
at VIL or Reset/Power-Down at VIL. The Status
Register content is output on DQ0-DQ7 and DQ8-
DQ31 are at VIL.
Chip Enable (E). The Chip Enable, E, input a cti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumpt ion to the Standby level.
Output Enable (G). The Output Enable, G , gates
the outputs through the data output buffers during
a read operation, when Output Disable GD is at
VIH. Wh en Output Enable G is a t VIH, the ou tp uts
are high im pedance in dependently of Output Dis-
able.
Outp ut Disabl e (G D ). The Output Disable, GD,
deactivates the dat a output buffers. When Ou tput
Disable, GD, is at VIH, the outputs are driven by
the Output Enable. When Output Disable, GD, is at
VIL, the outputs are high impedance independent-
ly of Output Enabl e. The Output Disable pin m ust
be connected to an external pull-up resistor as
there is no internal pull-up resistor to drive the pin.
Write Enable (W). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Wri te En-
able (also see Latch Enable, L).
Reset/Power-Dow n (RP). The Reset/Power-
Down, RP, is used to apply a hardware reset to the
memory. A hardware reset is achie ved by hold ing
Reset/Power-Down Low, VIL, for at least tPLPH.
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are re-
set. The Status Register information is cleared and
power consumption is reduced to deep power-
down level. The device acts as deselected , that is
the data outputs are high impedance .
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read operations af-
ter a delay of tPHEL or Bus W rite operations after
tPHWL.
If Reset/Power-Down goes low, VIL, during a Block
Erase, a Program or a Tuning Protection Program
the operation is aborted, in a time of tPLRH maxi-
mum, and data is altered and may be corrupted.
During Power-up power should be applied simulta-
neously to VDD a nd VDDQ(IN) wi th RP held at VIL.
When the supplies are stable RP is taken to VIH.
Output E nable, G, Chi p Enab le, E , and Write En-
able, W, should be held at VIH during power-up.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
erase or program operation, the memory may out-
put the Stat us Register information inst ead of be-
ing initialized to the default Asynchronous
Random Read.
See T able 21 a nd F igure 18, Reset , Po wer-Down
and Power-up Characteristics, for more details.
Latch Enable (L). The Bu s Interface can be c on-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L, for Asynchronous Latch
Enable Cont rolled R ead or W rite or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the ac-
tive edge of t he Clock whe n Lat ch E na ble is Low,
VIL. Once latched, the addresses may change
without affecting the address used by the memory.
When Latch E nabl e is Low, V IL, the latch is trans-
parent. Latch Enable, L, can remain at VIL for
Asynchronous Random Read and Write opera-
tions.
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus dur-
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
14/63
ing S ynchronous Burs t Read ope rations. Bus sig-
nals are latched on the active edge of the Clock.
The Clock can be configured to have an active ris-
ing or falling edge. In Synchronous Burst Read
mode the address is latched on the first active
clock edge when Latch Enable is low, VIL, or on
the rising edge of Latch Enable, whichever occurs
first.
During Asynchronous bus operation s the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the adv ancing of the address
by the internal address counter during Synchro-
nous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-lat ency
time has expired. If Burst Address Advance is
Low, VIL, t he internal address counter advances. If
Burst Address Advance is High, VIH, the internal
address count er does not change ; the same dat a
remains on the Data Inputs/Outputs and Burst Ad-
dress Advance is not sampled until the Y-latency
expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be
used, during Synchronous Burst Read operations,
to identify if the me mory is ready to output data or
not. The Valid Data Ready output can be config-
ured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data
Ready, at VIH, ind ic ates that ne w da ta is or w ill be
available. When Valid Dat a Ready is Low, VIL, the
previous data outputs remain active.
In all As ynchronous operations, Valid Dat a Ready
is high-impedanc e. It may be tied to other compo-
nents with the same Valid Data Ready signal to
create a unique system Ready signal. The Valid
Data Ready output has an int ernal pull-up r esistor
of around 1 MΩ powered from VDDQ, designers
should use an ex ternal pull-up res istor o f the cor-
rect value to meet the external timing require-
ments for Valid Data Ready going to VIH.
Write Protect (WP). The Write Protect , WP, pro-
vides protection against program or erase opera-
tions. When Write Protect, WP, is at VIL the first
two (in the bottom configuration) or las t two (i n the
top configuration) parameter blocks and all main
blocks are locked. When Write Protect WP is at
VIH all the blocks can be programmed or erased, if
no other protection is used.
Supply Voltage (VDD). The Supply Voltage, VDD,
is the core power s upp ly. Al l internal c ircuits draw
their current from the VDD pin, including the Pro-
gram/Erase Controller.
Output Supply Voltage (VDDQ). The Output Sup-
ply Voltage, VDDQ, is the output buffer power supply
for all operations (Read, Program and Era se) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (VDDQIN). The Input Sup-
ply Vo ltage, VDDIN, is the power supply for all input
signal. Input signals ar e: K, B, L, W, GD, G, E, A0 -
A18 and D0-D31, when used as inputs.
Program /Era se Supp ly Voltage (VPP). T he P ro-
gram/Erase S upply V oltage, VPP, is used for pro-
gram and erase operations. The memory normally
executes program and erase operations at VPP1
voltage levels. In a manufacturing environment,
programming may be speeded up by applying a
higher voltage level, VPPH, to th e VPP pin.
The voltag e level VPPH may be app lied for a t otal
of 80 hours over a maximum of 1000 cycles.
Stressing the device beyond these limits could
damage the device .
Ground (VSS and VSSQ). The Ground VSS is the
reference for the inte rnal supply voltage V DD. The
Ground VSSQ is the reference for the output and
input supplies VDDQ, and VDDQIN. It is es s e nt ia l t o
connect VSS and VSSQ toge ther.
Note: A 0.1µF capacitor should be connected
between the Supply Voltages, VDD, VDDQ and
VDDIN and the Grounds, VSS and VSSQ to decou-
ple the current surges from the power supp ly.
The PCB track widths must be sufficient to car-
ry the currents required during all operations
of the parts, see Table 15, DC Chara cteristics,
for maximum cur rent suppl y requir ements.
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be be-
tween VSS and V DDQ or leave it un connecte d.
Not Connected (NC). This pin is not physically
connected to the device.
15/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
BUS OPERATIONS
Each bus operations that controls the memory is
described in this section, see Tables 4, 5 and 6
Bus Operations, for a summary. The bus operation
is selected through the Burst Configuration Regis-
ter; the bits in this register are described at the end
of this sect ion.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write, no other bus operation can
be performed unt il the B urst Control Register has
been configured.
The Electronic Signature, CFI or Status Register
will be read in asynchronous mode regardless of
the Burst Control Register settings.
Typically glitches of less than 5ns on Chi p Enable
or Write Enable are ignored by the memory and do
not affec t bus operations.
Asynchro no us Bus Operati ons
For asynchronou s bus operations ref er to Tabl e 4
together with the following text.
Asynchro nous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Burst Configuration Register) in
the Command Interface. A valid bus ope ration in-
volves setting the desired address on the Address
Inputs, appl ying a Low s ig nal, V IL, to Chip Enable
and Output Enable and keeping Write E nable and
Output Disable High, VIH. The Data Inputs/Out-
puts will output the value, see Figure 9, Asynchro-
nous Bus Read AC Waveforms, and Table 16,
Asynchronous Bus Read AC Characteristics, for
details of when the o utput becom es valid.
Asynchronous Read is the default read mode
which the device enters on power-up or on return
from Reset/Power-Down.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from t he memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
t he me mo r y u s es.
A valid bus operation i nvolves set ting the d esired
address on the Address Inputs, setting Chip En-
able and Latc h E nable Low, VIL and keeping Write
Enable High, VIH; the address is latched on the ris-
ing edge of Latch Enable. Once latched, the Ad-
dress Inputs ca n change. Set Output Enabl e Low,
VIL, to read the data on the Data Inputs/Outputs;
see Figure 1, Asynchronous Latch Control led Bus
Read AC Waveforms and Table 17, Asynchro-
nous Latch Cont rolled Bus Read AC Charac teris-
tics for details on when the output becom es valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchro nous P age R e ad. Asynchronous
Page Read operations are used to read from sev-
eral addresses within the same memory page.
Each m emo ry page i s 4 Do uble-Words and is ad-
dressed by the address input s A0 and A1.
Data is read i nternally and stored in the Page Buff-
er. Valid bus operations are the same as Asyn-
chronous Bus Read operations but with different
timings. The first read operation within the page
has identical timings, subsequent reads within the
sam e page have much shorter acce ss ti mes. If the
page changes then the normal, longer timings ap-
ply again. Page Read does not support Latched
Controlled Read.
See Figure 11, Asynchronous Page Read AC
Waveforms and Table 18, Asynchronous Page
Read AC Characteristics for details on when the
outputs become va lid.
Asynchro nous Bus Wr ite. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write oper ations.
A valid Asy nchronous Bus Write operation b egins
by setti ng the desired address on the Addres s I n-
puts, and setting Chip Enable, Write Enable and
Latch Enable Low, VIL, and Output Enable High,
VIH, or Output Disable Low, VIL. The Address In-
puts are latched by the Command Interface on the
rising edge of Chip Enable or Write Enable, which-
ever occurs first. Commands and Input Data are
latched on the rising edge of Chip Enable, E, or
Write Enable, W, whichever occurs first. Output
Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write
operation.
See Figure 12, Asynchronous Write AC Wave-
forms, and Table 19, Asynchronous Write and
Latch Controlled Write A C Charact eristics, for de-
tails of the timing requirem ents .
Asynchronous Latch Controlled Bus Write.
Asynchronous Latch Controlled Bus W rite opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data t o p rogram. Bus W rite op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
16/63
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Com-
mand Interface on the rising edge of Latch Enable,
Write Enable or Chip Enable, whichever occurs
first. Commands and I nput Data are latched on the
rising edge of Chip Enable, E, or Write Enable, W,
whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole
Asynchronous Bus Write oper ation.
See Figure 13, Asynchronous Latch Controlled
Write AC Waveforms, and Table 19, Asynchro-
nous Write and Latch Controlled Write AC Charac-
teristics, for det ails of the timing requirements.
Outp ut Disabl e. The data outputs are high im-
pedance when the Output Enable, G, is at VIH or
Output Disable, GD, i s a t VIL.
Standby. When Chip Enable is High, VIH, and the
Program/Eras e Controller is idle, t he memory en-
ters Standby mode, the power consu mption is re-
duced to the standby level and the Data Inputs/
Outputs pins are placed in the high impedance
state regardless of Output Enable, Write Enable or
Output Disable inputs.
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current. The Data Inputs/Outputs will still
output data if a Bus Read operation is in progress.
Automatic Low Power is only available in Asyn-
chronous Read modes .
Power -D own . The memory is in Power-down
when Reset/Power-Down, RP, is at VIL. The pow-
er cons umption is reduced to the power-down lev-
el and the outputs are high impedance,
independent of the Chip Enable, E, Output Enable,
G, Ou t put D i sa b l e, GD , or Wri te Enable, W, inputs.
Electronic Sign atur e. Two codes identifying the
manufacturer and the device can be read from the
memory allowing programming equipment or ap-
plications to aut om at ically match their interfac e to
the characteristics of the memory. The Electronic
Signature is output by giving the Read Electronic
Signature command. The manufacturer code is
output when all the Address inputs are at VIL. The
device code is output when A1 is at VIH and all the
other address pins are at VIL. See Table 5. Issue
a Read Memory Array command to return to Read
mode.
Table 4. Asynchronous Bus Operations
No te: X = Don’t C are
Bus Operation Step E G GD W RP L A0-A18 DQ0-DQ31
Asynchronous Bus Read VIL VIL VIH VIH VIH VIL Address Data Output
Asynchronous Latch
Controlled Bus Read Address Latch VIL VIH VIH VIL VIH VIL A ddre ss High Z
Read VIL VIL VIH VIH VIH VIH X Data Output
Asynchronous Page
Read VIL VIL VIH VIH VIH X Address Data Output
Asynchronous Bus Write VIL VIH XVIL VIH VIL Address Data Input
Asynchronous Latch
Controlled Bus Write Address Latch VIL VIL VIH VIH VIH VIL Addre ss High Z
Write VIL VIH XVIL VIH VIH X Data Input
Output Disable, G VIL VIH VIH VIH VIH X X High Z
Output Disable, GD VIL VIL VIL VIH VIH X X High Z
Standby VIH XXX
V
IH X X High Z
Reset/Power-Down X X X X VIL X X High Z
17/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Table 5. Asynchronous Read El ectronic Signature Operation
Note: 1. x= B or D version of the d evice .
2. BCR= Burst Configuration Register.
Synchronous Bus Operations
For synchronous bus operations refer to Table 6
together with the following text.
Sync h ronou s Bu rst R ea d. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external r ef-
erence clock. The burst type, length and latency
can be configured. The different configurati ons for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion. Refer to Figures 5 and 6 for examples of
synchronous burst operations.
In continuous burst r ead, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B at VIL for
the appropriate number of clock cycles. At the end
of the memory address space the burst read re-
starts from the b eginni ng at address 000000h .
A valid Synchronous Burst Read operation begins
when the Burst Clock is active and Chip Enable
and Latch Enable are Low, VIL. The burs t start ad-
dress is latched and lo aded i nto the interna l Burst
Address Counte r on the valid Burst Clock K edge
(rising or falling depe nding on the value of M6) or
on the rising ed ge of Lat ch Ena ble, whichev er oc-
curs fi rst.
After an initial memory latency time, the memory
outputs data e ach clock cycl e (or two clock cycles
depending on the value of M9). The Burst Address
Advance B input controls the memory burst output.
The second burst output is on the nex t clock valid
edge after the Burst A ddress A dvance B has been
pulled Low.
Valid Data Ready, R, monitors if the memory burst
boundary is e xcee ded and the Burst Cont roller of
the microprocessor needs to insert wait states.
When Valid Data Ready is Low on the active clock
edge, no new data is available and the memory
does not increment t he internal address counter at
the active clock edge even if Burst Address Ad-
vance, B, is Low.
Valid Data Ready may be confi gured (by bit M8 of
Burst Configuration R egister) to be valid immedi-
ately at the valid clock edge or one data cycle be-
fore the val id clock edge.
Synchronous Burst Read will be suspended if
Burst Address Adv ance, B, goes High, VIH.
If Output En able is at VIL and Out put Disable is at
VIH, t he last data is still valid.
If Output Enable, G, is at VIH or Output Disable,
GD, is at VIL, but the Burst Address Advance, B, is
at VIL the internal Bu rst Address Cou nter is incre-
mented at each Burst Clock K valid edge.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 14 , 15,
16 and 17, and Table 20.
Synchronou s Burst Read Suspend . During a
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, V IH. The Burst Address
Advance goin g High, VIH, stops the burst count er
and the Output Enable going High, VIH, inh ibits the
data outputs. The Sync hronous Burst Read oper-
ation can be resumed by setting Output Enable
Low.
Code Device E G GD W A18-A0 DQ31-DQ0
Manufacturer All VIL VIL VIH VIH 00000h 00000020h
Device M58BW016xT(1) VIL VIL VIH VIH 00001h 00008836h
M58BW016xB(1) VIL VIL VIH VIH 00001h 00008835h
Burst Configur ation
Register VIL VIL VIH VIH 00005h BCR (2)
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
18/63
Table 6. Synchronous Bu rst Read Bus Operation s
Note: 1. X = Don't Care, VIL or VIH.
2. M15 = 0, Bit M15 i s in the Bu rst Conf i guration Reg i st er.
3. T = transi tion, see M6 in the Bu rst Conf i guration Reg i st er for details on the act i ve edge of K.
Bus Operation Step E G GD RP K(3) L B A0-A18
DQ0-DQ31
Synchronous Burst
Read
Address Latch VIL VIH XVIH TVIL X Address Input
Read VIL VIL VIH VIH TVIH VIL Data Output
Read Suspend VIL VIH XVIH XVIH VIH High Z
Read Resume VIL VIL VIH VIH TVIH VIL Data Output
Burst Address Advance VIL VIH XVIH TVIH VIL High Z
Read Abort, E VIH XX
V
IH X X X High Z
Read Abort, RP XXX
V
IL X X X High Z
19/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Burst Configuration Register
The Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform.
The Burst Configuration Register is set through
the Command Interface and will retain it s informa-
tion until it is re-c onfigured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register bits are de-
scribed in Table 7. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation. Refer to Figures 5
and 6 for exam ples of sy nchronous bu rst conf igu-
rations.
Read Select Bit (M 15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1 ’, B us Read operat ions
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operat ions are synchronous.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous accesses.
X-Latency Bits (M14-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assum e the values in Table 7,
Burst Configuration Register. The X-Latency bits
should also be selected in conjunction with Table ,
Burst Performance to ensure valid settings.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table 7,
Burst Configuration Register and Table , Burst
Performance, for valid combinations of the Y-La-
tency, the X-Latency and the Cloc k frequency.
Valid Data Ready Bit (M8). The Valid Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. Whe n the Val id Data Ready
bit is ’0’ the Valid Data Ready o utput pin is driven
Low for the active clock edge when inval id data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Burs t Ty pe Bit ( M7 ). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’ 1’ the memory
outputs f rom sequential addresses. See Tables 8,
Burst Type Definition, for the sequence of ad-
dresses output from a given starting address in
each mode.
Valid Clock Edge Bit (M6). The Valid Clock
Edge bit, M6, is used to configu re the active e dge
of the Clock, K, during Synchronous Burst Read
operations. When the Valid Clock Edge bit is ’0’
the falling edge of the Clock is the active edge;
when the Valid Clock Edge bit is ’1’ the rising edge
of the Clock is active.
Wrap Burst Bit (M3). The burst reads can be
confined inside the 4 or 8 Double-Word boundary
(wrap) or overcome the bounda ry (no wra p). The
Wrap Burst bit i s used to select between wrap and
no wrap. When the Wr ap Burst bit is set to ‘0’ the
burst read wraps; when it is set to ‘1’ the burst read
does not wrap.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Double-Words that
can be output during a Synchronous Burst Read
operation before the address wraps. Burst lengths
of 4 or 8 are available for both the S equent ial and
Interleaved burst types, and a continuous burst is
available for the Sequential type.
Table 7, Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Table 8, Burst Type Definition,
gives the sequence of addresses output from a
given starting address for each length.
If either a Continuous or a No Wrap Burst Read
has been initiated the device will output data syn-
chronously. Depending on the starting address,
the device activates the Valid Data Ready output
to indicate that a delay is necessary before the
data is out put. If the s t arting a ddres s is aligned to
an 8 Double Word boundary, the continuous burst
mode will run without activating the Valid Data
Ready output. If the start ing address is not aligned
to an 8 Double Word boundary, Valid Data Ready
is activated to indicate that the device needs an in-
ternal delay to read the successive words in the ar-
ray.
M10 , M5 and M4 are reserved fo r future use.
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
20/63
Table 7. Burst Configuration Register
No te: 1. 4 - 2 - 2 - 2 is not a l l owed.
2. X latenc i es can be cal culated as: (tAVQV – tLLKH + tQVKH) + t SYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK
is the clock period) .
3. Y lat encie s c an be calc ul ated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.
4. tSYSTEM MARGIN is the t ime margin requir ed for the c al culat i on.
Bit Description Value Description
M15 Read Select 0 Synchronous Burst Read
1 Asynchronous Read (Default at power-on)
M14 Reserved
M13-M11 X-Latency (2)
001 Reserved
010 4, 4-1-1-1 (1)
011 5, 5-1-1-1, 5-2-2-2
100 6, 6-1-1-1, 6-2-2-2
101 7, 7-1-1-1, 7-2-2-2
110 8, 8-1-1-1, 8-2-2-2
M10 Reserved
M9 Y-Latency (3) 0 One Burst Clock cycle
1 Two Burst Clock cycles
M8 Valid Data Ready 0 R valid Low during valid Burst Clock edge
1 R valid Low one data cycle before valid Burst Clock edge
M7 Burst Type 0 Interleaved
1 Sequential
M6 Valid Clock Edge 0 Falling Burst Clock edge
1 Rising Burst Clock edge
M5-M4 Reserved
M3 Wrapping 0 Wrap
1 No wrap
M2-M0 Burst Length
001 4 Double-Words
010 8 Double-Words
111 Continuous
21/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Table 8. Burst Type Definition
M 3 Starting
Address x4
Sequential x4
Interleaved x8
Sequential x8
Interleaved Continuous
0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10..
0 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11..
0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12..
0 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13..
0 4 – – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14..
0 5 – – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14..
0 6 – – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15..
0 7 – – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16..
0 8 – – – – 8-9-10-11-12-13-14-15-16-17..
1 0 0-1-2-3 – 0-1-2-3-4-5-6-7 – 0-1-2-3-4-5-6-7-8-9-10..
1 1 1-2-3-4 – 1-2-3-4-5-6-7-8 – 1-2-3-4-5-6-7-8-9-10-11..
1 2 2-3-4-5 – 2-3-4-5-6-7-8-9 – 2-3-4-5-6-7-8-9-10-11-12..
1 3 3-4-5-6 – 3-4-5-6-7-8-9-10 – 3-4-5-6-7-8-9-10-11-12-13..
1 4 4-5-6-7 – 4-5-6-7-8-9-10-
11 – 4-5-6-7-8-9-10-11-12-13-14..
1 5 5-6-7-8 – 5-6-7-8-9-10-11-
12 – 5-6-7-8-9-10-11-12-13-14..
1 6 6-7-8-9 – 6-7-8-9-10-11-
12-13 – 6-7-8-9-10-11-12-13-14-15..
1 7 7-8-9-10 – 7-8-9-10-11-12-
13-14 – 7-8-9-10-11-12-13-14-15-16..
1 8 8-9-10-11 – 8-9-10-11-12-13-
14-15 – 8-9-10-11-12-13-14-15-16-17..
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
22/63
Figure 5. Example Burst Configuration X-1-1-1
Figure 6. Example Burst Configuration X-2-2-2
AI03841
K
DQ
L
ADD VALID
DQ
DQ
DQ
DQ
4-1-1-1
5-1-1-1
6-1-1-1
7-1-1-1
8-1-1-1
0123456789
VALIDVALIDVALIDVALID
VALIDVALIDVALIDVALID
VALID
VALID
VALIDVALIDVALID
VALID
VALID
VALID
VALID
VALIDVALID
VALID
AI04406b
K
L
ADD
DQ VALID
DQ
DQ
DQ
5-2-2-2
6-2-2-2
7-2-2-2
8-2-2-2
0123456789
VALID
VALID VALID
VALID
VALID
VALID
VALID
VALID
NV
NV
NV
NV
NV
NV
NV NV
NVNV
NV=NOT VALID
23/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
COMMAND INTERFACE
All Bus Write operations t o the memory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
9, Commands. Refer to Table 9 in conjunction with
the text descriptions below.
Read Memory Array Comman d
The Read Memory Array command returns the
memory to Read mode. One Bus Write cycle is re-
quired to issue t he Read Memory Array command
and return the memory to Read mode. Subse-
quent read operations will output the addressed
memory array data. Once the command is issued
the memory remains in Read mode until another
command is issued. From Read mode Bu s Read
commands will access the memory array.
Read Electronic Signature Command
The Read Electronic Signature command i s used
to read the Manufacturer Code, the Device Code
or the Burst Configuration Register. One Bus Write
cycle is required to issue the Read Electroni c Sig-
nature command. Once the command is issued
subsequent Bus Read operations, depending on
the address specified, read the Manufacturer
Code, the Device Code or the Burs t Configuration
Register until another command is issued; see Ta-
ble 5, Read Electronic Signature.
Read Query Com m and .
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area. One Bus Write cycle is required to issue the
Read Query Com mand. O nce t he com ma nd is is-
sued subsequent Bus Read operations, depend-
ing on the address specified, read from the
Common Flash Interface Memory Area. See Ap-
pendix A, T ables 25, 26, 27 , 28 an d 29 for det ails
on the information contained in the Common Flash
Interface (CFI) memory area.
Read Status Register Command
The Read Status Register command is used to
read the Status Register. One Bus Write cycle is
required to issue the Read Status Register com-
mand. Once the command is issued subsequent
Bus Read operations read the Status Register un-
til another command is issued.
The Status Register information is present on t he
output data bus (DQ1-DQ7) wh en Chip Enable E
and Output Enable G are at VIL and Output Dis-
able is at VIH.
An interactive update of t he Status Regist er bits is
possible by togglin g Output Enabl e or Output Dis-
able. It is also possible duri ng a Program or Erase
operation, by disactivating the device with Chip
Enable at VIH and then reactivating it with Chip En-
able and Output Enable at VIL and Output Disable
at VIH.
The content of the Status Register may also be
read at the completion of a Program, Erase or
Suspend operation. During a Block Erase, Pro-
gram, Tuning Protection Program or Tuning Pro-
tection Unlock command, DQ7 indicates the
Program/Erase Controller status. It is valid until
the oper ation is completed or suspended.
See the section on the Stat us Register and Table
11 for details on the def inition s of the S tatus Reg-
ister b it s
Clear Status Register Command
The Clear Status Register command c an be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register co mmand. On ce the comm and is
issued the memory returns to its previous mode,
subsequent Bu s Rea d operations co ntinue to out-
put the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Pro-
gram, Erase, Block Protect or Block Unprotect
command is issued. If any error occurs then it is
essential to clear any error bits in the S tatus Reg-
ister by issuing the Clear Status Register com-
mand before attempting a new Progra m, Erase or
Resume command.
Block Erase Command
The B lock Erase com mand can be used to erase
a block. It s ets all of th e bits in the block to ‘1’. All
previous data in the block is lost. If the block is pro-
tected then the Erase operation wi ll abort, the data
in the block will not be changed and the Status
Register will output the error.
Two Bus Write operations are required to issue the
command; the first write cycle sets up the Block
Erase command, the second write cycle confirms
the Block erase command and latches the block
address in the internal state machine and starts
the Program/Erase Controller. The sequence is
aborted if the Confirm command is not given and
the device will output the Status Register Data with
bits 4 and 5 se t to '1'.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Erase operation the memory will only accept the
Read Status Register command and the Program /
Erase Suspend command. All other commands
will be ignore d.
The command can be executed using either VDD
(for a normal erase operation) or VPP (for a fast
erase operation). I f VPP is in the VPPH range when
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
24/63
the command is issued then a fast erase operation
will be executed, o the rwise the opera tion wi ll use
VDD. If VPP goes below t he VPP Lo ckou t Voltage,
VPPLK, during a fast erase the operation aborts,
the Status Register VPP Status bit is set to ‘1’ and
the command must be re-issued.
Typical Erase times are given in Table 10.
See Appendix B, Figure 23, Block Erase Flowchart
and Pseudo Code, for a suggested flowchart on
using the Block Erase command.
Progra m Command .
The Program command is used to program the
memory array. Two Bus Write operations are re-
quired to issue the command; the first write cycle
sets up the Program command, the second write
cycle latches the address and data to be pro-
grammed in the internal state machi ne and s tarts
the Program/Erase Controller. A program opera-
tion can be aborted by writin g FFF FFFFFh to any
address after the program set-up command has
been given.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Program operation the memory will only accept
the Rea d Status Re gister com mand and the P ro-
gram/Erase Suspend command. All other com-
mands will be ignored.
If Reset/Power-down, RP, falls to VIL during pro-
gramming the operation will be aborted.
The command can be executed using either VDD
(for a normal program operation) or VPP (for a fast
program operation). If VPP is in the VPPH range
when the co mmand is issued then a fast program
operation will be executed, otherwise the opera-
tion will use VDD. If VPP goes below the VPP Lock-
out Voltage, VPPLK, during a fast program the
operation aborts and the Status Register VPP Sta-
tus bit is set to ‘1’. As data integrity cannot be guar-
anteed when the program operation is aborted, the
memory block must be erased and repro-
grammed.
See Appendix B, Figure 21, Program Flowchart
and Pseudo Code, for a suggested flowchart on
using the Program command.
Program/ Erase Suspend Command
The Program/Erase Suspend com mand is used to
pause a Program or Erase operation. The com-
mand will only be accepted during a Program or
Erase operat ion. I t can be i ssued at any t ime dur-
ing a program or erase operation. T he command
is ignored if the device is already in suspend
mode.
One B us Write cycle is required to i ssue the P ro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) i ndicates that t he Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if t he operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Tabl e 10.
During Program/Erase Suspend the Read Mem o-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Program and the
Progra m Sus pend commands will also be accep t-
ed. When a program operation is completed inside
a Block Erase Suspend the Read Memory Array
command must be issued to reset the device in
Read mode, then the Erase Resume command
can be issued to complete the whole sequence.
Only the blocks not being e rased m ay be read or
programmed correctly.
See Appen dix B, Figure 22 , Program Suspend &
Resume Flowcha rt and Pseudo Code, and Figure
24, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Su spend c ommand.
Progra m/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/E ras e Controller after
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command.
See Appen dix B, Figure 22 , Program Suspend &
Resume Flowcha rt and Pseudo Code, and Figure
24, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Resume command.
Set Burst Configuration Regi ster Command.
The Set Bu rst Configuration Register command is
used to write a new value t o the Burst Conf igura-
tion Control Register which defines the burst
length, type, X and Y latencies, Synchronous/
25/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Asynchronous Read mode and the valid Clock
edge configuration.
Two Bu s Writ e cycl es are require d to issue th e Se t
Burst Configuration Register command. The first
cycle writes t he setup command and the address
corresponding to the Set Burst Configuration Reg-
ister content. The second cycle writes the Burst
Configuration Register data and the confirm com-
mand. Once the command is issued the memory
returns to Read m ode as if a Rea d M emo ry Array
command had been issued.
The value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the othe r address bits are ignored.
Tuni ng Protectio n U nl ock Comm a nd
The Tuning Protection Unlock command unlocks
the tuning protected blocks by writing the 64bit
Tuning Protection Code (M58BW016B only). After
a reset or powe r-up the blocks are locked a nd so
a Tuning P rotection Unlock comm and must b e is-
sued to allow program or erase operations on tun-
ing protected block or to program a new Tuning
Protection Cod e. Read ope rations out put the Sta-
tus Register content after the unlock operation has
started.
The Tuning Protection Code is composed of 64
bits, but the dat a bus is 32 bits wi de so f our (2 x 2)
writ e cycles are required to unlock t he device.
■The first write cycl e issue s the Tuning
Protection Unlock Setup comm and (0x78).
■The second write cycle inputs the first 32 bit s of
the tuning protection code on the data bus, at
address 0x00000.
Bit 7 of the Status Register should now be
checked t o verif y t hat t he device has su ccessf ully
stored the first part of the code in the internal reg-
ister. If b 7 = ‘1’, the device is ready to accept the
second part of the code. This doe s not me an that
the first 32 bits match the tuning protection code,
simply that i t was correct ly st ored for the c om par-
ing. If b7 = ‘0’, the user must wait for this bit setting
(refer to write cycle AC timings).
■The third write cycle re-issues th e Tuning
Protection Unlock Setup comm and (0x78).
■The fourth wr ite cycle inputs the second 32 bits
of the code at address 0x00001.
Bit 7 of the Status Register should again be
checked t o verif y t hat t he device has su ccessf ully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’), the tuning protection status
can be monitored on Status Register bit0. If b0 =
‘0’ the device is locked; b0 = ‘1’ the device is un-
locked. If the device is still locked a Read Memory
Array comma nd must be issued before re-issuing
the Tuning Protection Unloc k comman d.
Device locked means that the 64 bit password is
wrong. If the unlock operation is attempted using a
wrong code on an already unlocked device, the
device becomes locked. Status register bit 4 i s s et
to '1' if t here has been a verify failure.
Unlocking aborts if VPP drops out of the allowed
range or RP goes to VIL.
Once the device is succes sfu lly unlocked, a Read
Memory Array comma nd must be iss ued to return
the memory to read mode before issuing any other
commands. The user can then program or erase
all blocks, depending on WP status and VPP level.
At this point, it is a lso possible to c on figure a new
protection code. To write a new protection code
into the device tuning register, the user mus t per-
form the Tuning Protection Program sequence.
The device can be re-l ocked with a reset or power-
down.
See Appendix B, Figure 25, 26 and 27 for suggest-
ed flowcha rts for us ing the T uning Prote ction Un-
lock command.
Tuni ng Protectio n Pr ogram Com m a n d.
The Tuning Protection Program command is used
to program a new Tuning Protection Code which
can be configured by the designer of the applica-
tion (M58BW016B only). The device should be un-
locked by the Tuning Protection Unlock comm and
before issuing the Tuning Protection Program
command.
Read operations output the Status Register con-
tent after the program operation has started.
The Tuning Protection Code is composed of 64
bits, but the dat a bus is 32 bits wi de so f our (2 x 2)
writ e cycles are required to program the code.
■The first write cycl e issue s the Tuning
Protection Program Setup co mmand (0x 48).
■The second write cycle inputs the first 32 bit s of
the new tuning protection code on the data bus,
at address 0x00000.
Bit 7 of the Status Register should now be
checked t o verif y t hat t he device has su ccessf ully
stored the first part of the code in the internal reg-
ister. If b 7 = ‘ 1’, the device is ready t o acc ept the
second part of the code. If b7 = ‘0’, the user must
wait for this bit setting (refer to write cycle AC tim-
ings).
■The third write cycle re-issues th e Tuning
Protection Program Setup co mmand (0x 48).
■The fourth write cycle inputs the second 32 bits
of the new code at address 0x00001.
Bit 7 of the Status Register should again be
checked t o verif y t hat t he device has su ccessf ully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’). After completion Status
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
26/63
Register bi t 4 is set to '1' if there has b een a pro-
gram failure.
Programming aborts if VPP drops out of the al-
lowed range or RP goes to VIL.
A Read Memory Array command must be issued
to return the memory to read mode before issuing
any other commands. Once the code has been
changed a device reset or power-d own will make
the protection active with the new code.
See Appendix B, Figure 25, 26 and 27 for suggest-
ed flowcharts for using the Tuning Protect ion Pro-
gram command.
Table 9. Commands
No te : 1 . X Don’t Care; RA Read Address, R D Read Data, I D Devi ce Code, SRD St atus Regis ter Data, PA P rogr am Address; PD P rogr am
Data, QA Que ry Addr es s, QD Qu ery D ata, BA A ny addr ess in the Blo ck, B CR Burst Config ur ation R egis ter v alue, TP A = Tuni ng
Prot ection A ddres s, TPC = Tun i ng P rotect i on Cod e.
2. Cy cles 1 an d 2 i nput the fi rst 32 bits of the code, c ycles 3 and 4 the second 32 bits of t he code.
Command
Cycles
Bus Operations
1st Cycle 2nd Cycle 3rd Cycle 4th Cycle
Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data
Read Memo r y Array ≥ 2 Write X FFh Read RA RD
Read Electr onic Signa ture
(Manufacturer Code) ≥ 2 Write X 90h Read 00000h 20h
Read Electr onic Signa ture
(Device Code) ≥ 2 Write X 90h Read 00001h IDh
Read Electr onic Signa ture
(Burst Configuration
Register) ≥ 2 Write X 90h Read 00005h BCRh
Read Statu s Register 2 Writ e X 70h Re ad X SRDh
Read Query ≥ 2 Write X 98h Read QAh QDh
Clear Statu s Register 1 Writ e X 50h
Block Erase 2 Write X 20h Write BAh D0h
Program 2 Write X 40h
10h Write PA PD
Program/Erase Suspend 1 Write X B0h
Program/Erase Resume 1 Write X D0h
Set Burst Configuration
Register 2 Write X 60h Write BCRh 03h
Tuning Protection(2)
Program 4 Write X 48h Write TPAh TPCh Write X 48h Write TPAh TPCh
T uning Protection Unlock(2 ) 4 Write X 78h Write TPAh TPCh Write X 78h Write TPAh TPCh
27/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Table 10. Program, Erase Times and Program Erase Endurance Cycles
Note: TA = –40 to 125°C, V DD = 2.7V to 3.6V, VDDQ = 2.4V to VDD
Parameters M58BW016B/D Unit
Min Typ Max
VPP = VDD VPP = 12V VPP = VDD VPP = 12V
Parameter Block (64Kb) Program 0.030 0.016 0.060 0.032 s
Main Block (512Kb) Program 0.23 0.13 0.46 0.26 s
Parameter Block Erase 0.8 0.64 1.8 1.5 s
Main Block Erase 1.5 0.9 3 1.8 s
Program Suspend Latency Time 3 10 µs
Erase Suspend Latency Time 10 30 µs
Program/Erase Cycles (per Block) 100,000 cycles
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
28/63
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Tuning Protection operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Regis ter t he Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Program/E rase Resume commands. The
Status Register can be re ad from any address.
The cont ents of the St atus Register can be updat-
ed during an erase or program operation by tog-
gling the Output Enable or Output Disable pin s or
by dis-activating (Chip Enable, VIH) and then reac-
tivating (Chip Enable and Ou tput Enable, VIL, and
Output Disable, VIH.) the device.
The Status Register bits are summarized in Tab le
11, Status Register Bits. Refer to Table 11 in con-
junction with the following text descriptions.
Program /Era se Contr oller Status (Bit 7)
The Program/Erase Controller Status bit indicates
whether the P rogram /Erase Con troller is act ive or
inactive. When the Program/ E rase Controller Sta-
tus bit i s s et to ‘0’ , the P rogram/Erase Controller is
active; when bit7 is set to ‘1’, the Program/Erase
Controller is inactive.
The Program/Erase Controller Status is set to ‘0’
immediately after a Program/Erase Suspend co m-
mand is issued unti l the Program/Erase Controller
pauses. After the Program/E rase Cont roller paus-
es the bit is set to ‘1’.
During Program and Erase operations the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the o perati on. The oth er bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is set to ‘1’.
After the Program/Erase Controller completes its
operation the Er ase S tatu s (bit5), Program S tatus
and Tuning Protection Unlock status (bit4) bits
should be tested for errors.
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an
Erase operatio n has been susp ended and is wait-
ing to be resumed. The Erase Suspend Status
should only be considered valid when the Pro-
gram/Erase Controller Status bit is set to ‘1’ (Pro-
gram/Erase Controller inactive); after a Program/
Erase Suspend command is issued the memory
may still complete t he operation rather than enter-
ing the Suspend mode.
When the Erase Suspend Status bit is set to ‘0’,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is set to ‘1’, a Pro-
gram/Erase Suspend command has been issued
and the memory is waiting for a Program/Erase
Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspen d Status bit returns to ‘0’.
Erase Status (Bit 5)
The E rase S tatus bit can be us ed to identify if t he
memory has failed to verify that the block has
erased correctly. The Erase Status bit should be
read once t he Program/Erase Controller Status bit
is High (Program/Erase Controller inactive).
When the Erase Status bit is set to ‘0’, the memory
has succes sfully verifi ed t hat the block has erased
correctly. When the Erase Status bit is set to ‘1’,
the Program/Erase Controller has applied the
maximum number of pulses to the block and still
failed to verify that the block has erased correctly.
Once set to ‘1’, the Erase Status bit can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If set to ‘1’ it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status, Tuning Protection Unlock
Status (Bit 4)
The Program Status and Tuning Protection Unlock
Status bit is used to identify a Program failure or a
Tuning Protection Code verify failure. Bit4 should
be read once the Program /Erase Controller Status
bit is High (Program/Erase Controller inactive).
When bit4 is set to ‘0’ the memory has successful-
ly verified that the device has programmed cor-
rectly or that the correct Tuning Protection Code
has been written. When bit 4 is set t o ‘1’ the device
has failed to verify that the data has been pro-
grammed correctly or t hat the co rrect Tu ning Pro-
tection code has been written.
Once set to 1’, the Program Status bit can only be
reset t o ‘0’ by a Clear Status Register command or
a hardware reset. If set to ‘1’ it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPP Status (Bit 3)
The VPP Status bit can be used to identify an in-
valid voltage on the VPP pin during fast program
and erase operations. The VPP pin is only sampled
at the beginning o f a program or erase operat ion.
Indeterminate resul ts can occur if VPP becomes in-
valid during a fa st Program or Erase operation.
When the VPP Status bit is set to ‘0’, the voltage on
the V PP pin was sam pled at a valid voltag e; when
the VPP Status bit is set to ‘1’, the VPP pin has a
voltage that i s below t he VPP Lockout Voltage, VP-
PLK.
Once set to ‘1’, the VPP Status bit can only be reset
to ‘0’ by a Clear Status Register command or a
hardware reset. If set to ‘1’ it should be reset be-
29/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspen d Status (Bit 2)
The Program Suspend Status bit indicates that a
Program operation has been suspended and is
waiting to be resumed. The Program Suspend
Status should only be considered valid when the
Program/Erase Controller Status bit is set to ‘1’
(Program/Erase Controller inactive); after a Pro-
gram/Erase Suspend command is issued the
memory may still complete the operation rather
than enteri ng the Suspend mode.
When the Program Suspend St atus bit is set to ‘0’ ,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is set to ‘1’, a Pro-
gram/Erase Suspend command has been issued
and the memory is waiting for a Program/Erase
Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1)
The Block Protection Status bit can be used to
identify if a Program o r Erase operation has tried
to modify the contents of a prote cted block.
When the Block Protection Status b it is set to ‘0’,
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is set to ‘1’, a
Program or Erase operation has been attempted
on a protected block.
Once set to ‘1’, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set to ‘1’ it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Tuni ng Protectio n Stat us (Bit 0)
The Tuning Protection Status bit indicates if the
device is locked (Tuning P rot ection is enabled) or
unlocked (Tuning Protect ion is disabled).
When the Tuni ng Pr otec tion S tatus bi t is set to ‘ 0’
the device is locked, when it is set to ‘1’ the device
is unlocked. After a reset or power-up the device is
locked and so bit0 is se t to ‘0’.
The Tuning Protect ion Status bit is set to ‘1’ f or the
M58BW016D v ersion.
Table 11. Status Register Bits
No te : 1 . For the M58BW016D version t he T uning Prote ct i on Stat us bit is al ways set to ‘1’ .
Bit Name Logic Level Definition
7Program/Erase Contr oller Status ’1’ Ready
’0’ Busy
6Erase Suspend Status ’1’ Suspended
’0’ In Progress or Completed
5Erase Status ’1’ Erase Error
’0’ Erase Success
4Program Status,
Tuning Protection Unlock Status ’1’ Program Error
’0’ Program Success
3VPP Status ’1’ VPP Invalid, Abort
’0’ VPP OK
2Program Suspend Status ’1’ Suspended
’0’ In Progress or Completed
1Erase/Program in a Protected
Block ’1’ Program/Erase on Protected Block,
Abort
’0’ No Operations to Protected Sectors
0Tuning Protection Status ’1’ Tuning Protection Disabled(1)
’0’ Tuning Protection Enabled
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
30/63
MAX I MUM R A TING
Stressing the device above the rat ings listed in Ta-
ble 12, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat -
ed in the Oper ati ng sections of this specification is
not impl ied. Exposure to Absol ute Max imum Ra t-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE P rogram and oth er rel-
evant quality documents.
Table 12. Absolute Maximum Ratings
Note: Cum ulat iv e t i m e at a high vol t age level of 13.5V sh oul d not exc eed 80 hours on VPP pin.
Symbol Parameter Value Unit
Min Max
TBIAS Temperature Under Bias –40 125 °C
TSTG Storage Temperature –55 155 °C
VIO Input or Output Voltage –0.6 VDDQ +0.6
VDDQIN +0.6 V
VDD, VDDQ, VDDQIN Supply Voltage –0.6 4.2 V
VPP Program Volta ge –0.6 13.5 (1) V
31/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
DC AND AC PARAME TERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the de vi ce . The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 13,
Operating and AC Measurement Conditions. De-
signers should check that the operating c onditions
in their circuit match the measurement co nditions
when relying on th e quoted parameters.
Table 13. Operating and AC Measurem en t Conditions
Figu re 7. AC Measure m ent Input Outpu t
Waveform
Note: VDD = V DDQ.
Figu re 8. AC Measure ment Load C irc ui t
Table 14. D evice Capacitance
Note: 1. TA = 25°C, f = 1 MHz
2. Sampled only, not 100% tested.
Parameter Value Units
Min Max
Supply Voltage (VDD)2.7 3.6 V
Input/Output Supply Voltage (VDDQ)2.4 VDD V
Ambient Temperature (TA)Grade 6 –40 90 °C
Grade 3 –40 125 °C
Load Capacitance (CL)60 pF
Clock Rise and Fall Times 4 ns
Input Rise and Fall Times 4 ns
Input Pulses Voltages 0 to VDDQ V
Input and Output Timing Ref. Voltages VDDQ/2 V
AI04153
VDDQ
VDDQIN
0V
VDDQ/2
VDDQIN/2
AI04154
1.3V
OUT
CL
CL includes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Symbol Parameter Test Cond ition Ty p Max Unit
CIN Input Capacitance VIN = 0V 68pF
C
OUT Output Capacitance VOUT = 0V 812pF
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
32/63
Table 15. DC Characteristics
Symb ol Parameter Test Cond ition Min Max U nit
ILI Input Leaka ge Curren t 0V≤ VIN ≤ VDDQ ±1 µA
ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±5 µA
IDD Supply Current (Random Read) E = VIL, G = VIH, fadd = 6MHz 20 mA
IDDB Supply Current (Burst Read) E = VIL, G = VIH, fclock =
56MHz 30 mA
IDD1
Supply Current (Standby) E = RP = VDD ± 0.2V 60 µA
Supply Current (Auto Low-Power) E = VSS ± 0.2V,
RP = VDD ± 0.2V 60 µA
IDD2 Supply Current (Reset/Power-down) RP = VSS ± 0.2V 60 µA
IDD3 Supply Current (Program or Erase,
Set Lock Bit, Erase Lock Bit) Program, Block Erase in
progress 30 mA
IDD4 Supply Current
(Erase/Program Suspend) E = VIH 40 µA
IPP Program Current (Read or Standby) VPP ≥ VPP1 ± 30 µA
IPP1 Program Current (Read or Standby) VPP ≤ VPP1 ± 30 µA
IPP2 Program Current (Power-down) RP = VIL ± 5 µA
IPP3 Program Current (Program)
Program in Progress VPP = VPP1 200 µA
VPP = VPPH 20 mA
IPP4 Program Current (Erase)
Erase in Progress VPP = VPP1 200 µA
VPP = VPPH 20 mA
VIL Input Low Vol tage –0.5 0.2VDDQIN V
VIH Input High Voltage (for DQ lines) 0.8VDDQIN VDDQ +0.3 V
VIH Input High Voltage (for Input only
lines) 0.8VDDQIN 3.6 V
VOL Output Low Voltage IOL = 100µA 0.1 V
VOH Output High Voltage CMOS IOH = –100µA VDDQ –0.1 V
VPP1 Program Voltage
(Program or Erase operations) 2.7 3.6 V
VPPH Program Voltage
(Program or Erase operations) 11.4 12.6 V
VLKO VDD Supply Voltage (Erase and
Program lockout) 2.2 V
VPPLK VPP Supply Voltage (Erase and
Program lockout) 11.4 V
33/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 9. Asynchrono us Bus Read AC Wavefor ms
Table 16. Asynchro nous Bus Read AC Characteristics.
No te : 1 . Output Enable G may be de l ayed up to tELQV - tGLQV after the falling edge of Chip Enable E witho ut increasing tELQV.
Symbol Parameter Test Condition M58BW016 Unit
80 90 100
tAVAV Address Valid to Address Valid E = VIL, G = VIL Min 80 90 100 ns
tAVQV Address Valid to Output Valid E = VIL, G = VIL Max 80 90 100 ns
tAXQX Address Transition to Output Transition E = VIL, G = VIL Min 0 0 0 ns
tEHLX Chip Enable High to Latch Enable Transition Min 0 0 0 ns
tEHQX Chip Enable High to Output Transition G = VIL Min 0 0 0 ns
tEHQZ Chip Enable High to Output Hi-Z G = VIL Max 20 20 20 ns
tELQV(1) Chip Enable Low to Output Valid G = VIL Max 80 90 100 ns
tELQX Chip Enable Low to Output Transition G = VIL Min 0 0 0 ns
tGHQX Output Enable High to Output Transition E = VIL Min 0 0 0 ns
tGHQZ Output Enable High to Output Hi-Z E = VIL Max 15 15 15 ns
tGLQV Output Enable Low to Output Valid E = VIL Max 25 25 25 ns
tGLQX Output Enable to Output Transition E = VIL Min 0 0 0 ns
tLLEL Latch Enable Low to Chip Enable Low Min 0 0 0 ns
AI0440 C
E
G
L
A0-A18
DQ0-DQ31
VALID
tLLEL
tAXQX
tELQX
tELQV
tAVQV
tGLQX
tGLQV tEHQX
tEHQZ
tGHQX
tGHQZ
See also Page Read
OUTPUT
tEHLX
tAVAV
GD
AI04407C
E
G
L
A0-A18
DQ0-DQ31
VALID
tLLEL
tAXQX
tELQX
tELQV
tAVQV
tGLQX
tGLQV tEHQX
tEHQZ
tGHQX
tGHQZ
See also Page Read
OUTPUT
tEHLX
tAVAV
GD
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
34/63
Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms
Table 17. A synchronous Latch Controlled Bus Read AC Charac teristics
Symb ol Parame ter Test Cond ition M58BW016 Unit
80 90 100
tAVLL Address Valid to Latch Enable Low E = VIL Min 0 0 0 ns
tEHLX Chip Enable High to Latch Enable Transition Min 0 0 0 ns
tEHQX Chip Enable High to Output Transition G = VIL Min 0 0 0 ns
tEHQZ Chip Enable High to Output Hi-Z G = VIL Max 20 20 20 ns
tELLL Chip Enable Low to Latch Enable Low Min 0 0 0 ns
tGHQX Output Enable High to Output Transition E = VIL Min 0 0 0 ns
tGHQZ Output Enable High to Output Hi-Z E = VIL Max 15 15 15 ns
tGLQV Output Enable Low to Output Valid E = VIL Max 25 25 25 ns
tGLQX Output Enable Low to Output Transition E = VIL Min 0 0 0 ns
tLHAX Latch Enable High to Address Transition E = VIL Min 5 5 5 ns
tLHLL Latch Enable High to Latch Enable Low Min 10 10 10 ns
tLLLH Latch Enable Low to Latch Enable High E = VIL Min 10 10 10 ns
tLLQV Latch Enable Low to Output Valid E = VIL, G = VIL Max 80 90 100 ns
tLLQX Latch Enable Low to Output Transition E = VIL, G = VIL Min 0 0 0 ns
AI03645
L
E
G
A0-A18
DQ0-DQ31
VALID
tEHLXtLHLL
tLHAXtAVLL
tELLL
tLLLH
tEHQX
tEHQZ
tGHQX
GHQZ
tLLQX
tLLQV
tGLQX
tGLQV
See also Page Read
OUTPUT
35/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 11. Asynchronous Page Read AC Waveforms
Table 18. Asynchro nous Pa ge Read AC Characteristics
No te : F or other timi ngs see Table 16, As ynchronous B us Read Chara ct eristi cs.
Symbol Parameter Test Condition M58BW016 Unit
80 90 100
tAVQV1 Address Valid to Output Valid E = VIL, G = VIL Max 25 25 25 ns
tAXQX Address Transition to Output Transition E = VIL, G = VIL Min666ns
AI03646
A0-A1
DQ0-DQ31
A0 and/or A1
tAVQV1
OUTPUT
tAXQX
OUTPUT + 1
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
36/63
Figure 12. Asynchrono us Write AC Waveform
AI03651
DQ0-DQ31
W
RP
A0-A18
E = L
G
INPUT
VALID VALID
tWHEH
VALID
tAVWH
tWLWH
tELWL
INPUT VALID SR
VPP
tWHAX
tWHWL
tWHDX
tDVWH
tWHGL
tWHQV
tVPHWH tQVVPL
tQVPL
tPHWH
RP = VDD
RP = VHH
Read Status RegisterWrite CycleWrite Cycle
tAVLL
37/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figu re 13. As yn c hr onous Lat ch C on t rol le d W ri te AC Waveform
AI03652
DQ0-DQ31
W
RP
A0-A18
L
G
INPUT
VALID VALID VALID
tAVLH
INPUT VALID SR
VPP
tLHAX
Read Status RegisterWrite CycleWrite Cycle
E
tLLLH
tLLWH
tWHAX
tELWL
tWLWH
tWHEH
tWHWL tWHGL
tWHQV
tDVWH
tWHDX tVPHWH tQVVPL
tQVPL
RP = VHH RP = VDD
tAVWH
tELLL
tAVLL
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
38/63
Table 19. Asynchro nous Wri te and Latch Controlled Write AC Characteristics
Symbol Parameter Test Condition M58BW016 Unit
80 90 100
tAVLL Address Valid to Latch Enable Low Min 0 0 0 ns
tAVWH Address Valid to Write Enable High E = VIL Min 50 50 50 ns
tDVWH Data Input Valid to Write Enable High E = VIL Min 50 50 50 ns
tELLL Chip Enable Low to Latch Enable Low Min 0 0 0 ns
tELWL Chip Enable Low to Write Enable Low Min 0 0 0 ns
tLHAX Latch Enable High to Address Transition Min 5 5 5 ns
tLLLH Latch Enable Low to Latch Enable High Min 10 10 10 ns
tLLWH latch Enable Low to Write Enable High E = VIL Min 50 50 50 ns
tQVVPL Output Valid to VPP Low Min 0 0 0 ns
tVPHWH VPP High to Write Enable High Min 0 0 0 ns
tWHAX Write Enable High to Address Transition E = VIL Min 0 0 0 ns
tWHDX Write Enable High to Input Transition E = VIL Min 0 0 0 ns
tWHEH Write Enable High to Chip Enable High Min 0 0 0 ns
tWHGL Write Enable High to Output Enable Low Min 150 150 150 ns
tWHQV Write Enable High to Output Valid Min 175 175 175 ns
tWHWL Write Enable High to Write Enable Low Min 20 20 20 ns
tWLWH Write Enable Low to Write Enable High E = VIL Min 60 60 60 ns
tQVPL Output Valid to Reset/Power-down Low Min 0 0 0 ns
39/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 14. Synchronous Burst Read (Data Vali d from ’n’ Clock Rising Edge)
AI04409
DQ0-DQ31
A0-A18
L
E
G
K
VALID
tKHAX
n+2n+1n
1
0
tKHLL
tLLKH
tELLL
tAVLL
tKHLX
tEHQX
tEHQZ
tGHQX
tGHQZ
tGLQV
Setup
OUTPUT
tKHQV tQVKH
tAVQV
Note: n depends on Burst X-Latency.
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
40/63
Table 20. Synchronous Burst Read AC Characteristics
No te : 1 . Data output should b e read on the valid cloc k e dge.
2. For other timin gs see T abl e 16, As ynchronou s B us Read Char acteri stics.
Figure 15. Synchronous Burst Read (Data Vali d from ’n’ Clock Rising Edge)
No te : F or se t up sign al s a nd timi ngs see Synchronous Burst Read.
Symbol Parameter Test Condition M58BW016 Unit
80 90 100
tAVLL Address Valid to Latch Enable Low E = VIL Min 0 0 0 ns
tBHKH Burst Address Advance High to Valid Clock
Edge E = VIL, G = VIL,
L = VIH Min 8 8 8 ns
tBLKH Burst Address Advance Low to Valid Clock
Edge E = VIL, G = VIL,
L = VIH Min 8 8 8 ns
tELLL Chip Enable Low to Latch Enable low Min 0 0 0 ns
tGLQV Output Enable Low to Output Valid E = VIL, L = VIH Min 25 25 25 ns
tKHAX Valid Clock Edge to Address Transition E = VIL Min 5 5 5 ns
tKHLL Valid Clock Edge to Latch Enable Low E = VIL Min 0 0 0 ns
tKHLX Valid Clock Edge to Latch Enable Transition E = VIL Min 0 0 0 ns
tKHQX Valid Clock Edge to Output Transition E = VIL, G = VIL,
L = VIH Min 3 3 3 ns
tLLKH Latch Enable Low to Valid Clock Edge E = VIL Min 6 6 6 ns
tQVKH(1) Output Valid to Valid Clock Edge E = VIL, G = VIL,
L = VIH Min 6 6 6 ns
tRLKH Valid Data Ready Low to Valid Clock Edge E = VIL, G = VIL,
L = VIH Min 6 6 6 ns
tKHQV Valid Clock Edge to Output Valid E = VIL, G = VIL,
L = VIH Max 11 11 11 ns
AI04408b
K
n+5
n+4
n+3
n+2
n+1
n
DQ0-DQ31
tQVKH
tKHQX
Q0 Q1 Q2 Q3 Q4 Q5
SETUP Burst Read
Q0 to Q3
tKHQV
Note: n depends on Burst X-Latency
41/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output
Note: Vali d Data Ready = V al i d Low du ri ng valid cloc k e dge
1. V = V a lid out put.
2. R is an open drain output with an internal pull up resistor of 1MΩ. The internal timing of R follows DQ. An external resistor, typically
300kΩ. f or a sing l e m em ory on the R bus, shou l d be used to give the dat a valid set up time required to rec ognize that vali d data is
avai l abl e on the next va l i d clock edge.
Figure 17. Synchronous Burst Read - Burst Address Advance
AI03649
K
Output (1) VVVV
tRLKH
R
V
(2)
AI03650
K
ADD Q0 Q1
L
Q2
ADD VALID
G
tGLQV
tBLKH tBHKH
B
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
42/63
Figure 18. Reset, Power-Down and Pow er-up AC Waveform
Table 21. Reset, Power-Dow n and Power-u p AC Charac teris tics
Note : 1. This time is tPHEL + tAVQV or tPHEL + tELQV.
Symbol Parameter Min Max Unit
tPHEL Reset/Power-down High to Chip Enable Low 50 ns
tPHQV (1) Reset/Power-down High to Output Valid 130 ns
tPHWL Reset/Power-down High to Write Enable Low 50 ns
tPHGL Reset/Power-down High to Output Enable Low 50 ns
tPLPH Reset/Power-down Low to Reset/Power-down High 100 ns
tPLRH Reset/Power-down Low to Valid Data Ready High 2 30 µs
tVDHPH Supply Voltages High to Reset/Power-down High 10 µs
AI03849b
W,
RP
tPHWL
tPHEL
tPHGL
E, G
VDD, VDDQ
tVDHPH
tPHWL
tPHEL
tPHGL
tPLPH
tPLRH
Power-Up Reset
R
43/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
PACKAGE MECHANICAL
Figure 19. LBGA 80 10x12 m m - 8x10 ball array, 1mm pitch , Bottom View Package Ou tline
Note: Drawing is not to scale.
Table 22. LBGA8 0 10x12mm - 8x10 ball array, 1mm pitch, Packa ge Me chanic al Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.700 0.0669
A1 0.400 0.350 0.450 0.0157 0.0138 0.0177
A2 1.100 0.0433
b 0.500 – – 0.0197 – –
D 10.000 – – 0.3937 – –
D1 7.000 – – 0.2756 – –
ddd 0.150 0.0059
E 12.000 – – 0.4724 – –
E1 9.000 – – 0.3543 – –
e 1.000 – – 0.0394 – –
FD 1.500 – – 0.0591 – –
FE 1.500 – – 0.0591 – –
SD 0.500 – – 0.0197 – –
SE 0.500 – – 0.0197 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z05
ddd
FD
FE SD
SE
e
BALL "A1"
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
44/63
Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pac k, Packag e Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.400 0.1339
A1 0.250 0.0098
A2 2.800 2.550 3.050 0.1102 0.1004 0.1201
b 0.300 0.450 0.0118 0.0177
c 0.130 0.230 0.0051 0.0091
D 23.200 22.950 23.450 0.9134 0.9035 0.9232
D1 20.000 19.900 20.100 0.7874 0.7835 0.7913
D2 18.400 – – 0.7244 – –
e 0.800 – – 0.0315 – –
E 17.200 16.950 17.450 0.6772 0.6673 0.6870
E1 14.000 13.900 14.100 0.5512 0.5472 0.5551
E2 12.000 – – 0.4724 – –
L 0.800 0.650 0.950 0.0315 0.0256 0.0374
L1 1.600 – – 0.0630 – –
α0° 7° 0° 7°
N80 80
Nd 24 24
Ne 16 16
QFP-B
D1
CP
b
e
A2
A
N
LA1 α
E1
E2
1
D
c
E
D2
L1
Nd
Ne
45/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
PART NUMBERING
Table 24. Ordering Information Scheme
Note: Devices are ship ped from the factory with the memory content bits erased to ’1’.
For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Example: M58BW016B T 80 T 3 T
Device Type
M58
Architecture
B = Burst Mode
Operating Voltage
W = VDD = 2.7V to 3.6V; VDDQ = VDDQIN =2.4 to VDD
Device Function
016B = 16 Mbit (x32), Boot Block, Burst Tuning Protection
016D = 16 Mbit (x32), Boot Block, Burst no Tuning Protection
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
80 = 80ns
90 = 90ns
100 = 100ns
Package
T = PQFP80
ZA = LBGA80: 1.0mm pitch
Temperature Range
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
46/63
APPENDIX A. COMMO N FLASH INTERFACE - CFI
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system sof tware t o query the device to det ermine
various electrical and timing parameters, density
information and functions supported by t he mem-
ory. The system can interface easily with the de-
vice, enabling the s oftware to upgrad e itse lf when
necessary.
When the CFI Query C ommand (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the m em ory. Tables 25 , 26,
27, 28 and 29 show the addresses used to retrieve
the data.
Table 25. Query Structure Overview
Note: 1. Of fs et 15h defines P w hi ch poin ts to the Primary A l gorithm Ex tended Quer y A ddress Table.
2. Of fs et 19h def i nes A whic h poi nts to the Alternate Al gorit hm E xt ended Query Address T abl e.
Table 26. CFI - Query Address and Data Output
Note: 1. The x8 or Byte Address and the x16 or Word Address mode are not available.
2. Query Dat a are alw ays presented o n DQ7-D Q0. DQ31-D Q8 are set t o ' 0' .
Offset Sub-section Name Description
00h Manufacturer Code
01h Device Code
10h CFI Query Identification String Command set ID and algorithm data offset
1Bh System Interface Information Device timing and voltage information
27h Device Geometry Definition Flash memory layout
P(h)(1) Primary Algorithm-specific Extended Query Table Additional information specific to the Primary
Algorithm (optional)
A(h)(2) Alternate Algorithm-specific Extended Query Table Additional information specific to the Alternate
Algorithm (optional)
Address A0-A18 Data Instruction
10h 51h "Q" 51h; "Q"
Query ASCII String 52h; "R"
59h; "Y"
11h 52h "R"
12h 59h "Y"
13h 03h Primary Vendor:
Command Set and Control Interface ID Code
14h 00h
15h 35h Primary algorithm extended Query Address Table: P(h)
16h 00h
17h 00h Alternate Vendor:
Command Set and Control Interface ID Code
18h 00h
19h 00h Alternate Algorithm Extended Query address Table
1Ah 00h
47/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Table 27. CFI - Device Voltage and Timing Specification
Note: 1. Bit s a re coded i n B i nary Code Deci m al , bit7 to b i t4 a re scal ed i n V ol ts and bit3 to bit0 in mV .
2. Bit 7 t o bi t4 are coded in Hexadecimal and scal ed in Volt s whi l e bit3 to bi t 0 are in B i nary Code Deci m al and scaled in 100mV .
3. Not supp ort ed.
Table 28. Device Geometry Definition
Address A0-A18 Data Description
1Bh 27h (1) VDD min, 2.7V
1Ch 36h (1) VDD max, 3.6V
1Dh B4h (2) VPP min
1Eh C6h (2) VPP max
1Fh 00h (3) 2n ms typical time-out for Word, DWord prog – Not Available
20h 00h (3) 2n ms, typical time-out for max buffer write – Not Available
21h 0Ah 2n ms, typical time-out for Erase Block
22h 00h (3) 2n ms, typical time-out for chip erase – Not Available
23h 00h (3) 2n x typical for Word Dword time-out max – Not Available
24h 00h 2n x typical for buffer write time-out max – Not Available
25h 04h 2n x typical for individual block erase time-out maximum
26h 00h (3) 2n x typical for chip erase max time-out – Not Available
Address A0-A18 Data Description
27h 15h 2n number of bytes memory size
28h 03h Device Interface Sync./Async.
29h 00h Organization Sync./Async.
2Ah 00h Page size in bytes, 2n
2Bh 00h
2Ch 02h Bit7-0 = number of Erase Block Regions in device
2Dh 1Eh Number (n-1) of blocks of identical size; n=31
2Eh 00h
2Fh 00h Erase Block region information x 256 bytes per
Erase Block (64Kby tes)
30h 01h
31h 07h Number (n-1) of blocks of identical size; n=8
32h 00h
33h 20h Erase Block region information x 256 bytes per
Erase Block (8Kbyte s)
34h 00h
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
48/63
Table 29. Extended Quer y informati on
No te : 1 . Not su pport ed.
Address
offset Address
A18-A0 Data (Hex) Description
(P)h 35h 50h "P"
Query ASCII string - Extended Table(P+1)h 36h 52h "R"
(P+2)h 37h 49h "Y"
(P+3)h 38h 31h Major version number
(P+4)h 39h 31h Minor version number
(P+5)h 3Ah 86h
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Lock/Unlock Supported (1=yes)
bit4, Queue Erase Supported (0=no)
Bit 31-5 reserved for future use
(P+6)h 3Bh 01h
Optional Features: Synchronous Read supported(P+7)h 3Ch 00h
(P+8)h 3Dh 00h
(P+9)h 3Eh 01h Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(P+A)h 3Fh 00h (1) Block Status Register Mask – Not Available
49/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
APPENDIX B. FLOW CHARTS
Figu re 21 . Program Fl ow c hart and Pseud o C ode
No te : 1 . If an er ror is f ound, the Status Register must be cleared befor e further P/E opera ti ons.
Write 40h
AI03850
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
VPP Invalid
Error (1)
Program
Error (1)
Program Command:
– write 40h
– write Address & Data
(memory enters read status
state after the Program command)
do:
– read status register
(E or G must be toggled)
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
YES
End
NO
b1 = 0 Program to Protect
Block Error If b1 = 1, Program to Protected Block Error:
– error handler
YES
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
50/63
Figure 22. Program Suspend & Resume Flowchart and Pseudo Code
Write 70h
AI00612
Read Status
Register
YES
NO
b7 = 1
YES
NO
b2 = 1
Program Continues
Write FFh
Program/Erase Suspend Command:
– write B0h
– write 70h
do:
– read status register
while b7 = 1
If b4 = 0, Program completed
Read Memory Array Command:
– write FFh
– one or more data reads
from other blocks
Write D0h Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Read data from
another block
Start
Write B0h
Program Complete
Write FFh
Read Data
51/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 23. Block Erase Flowcha rt and Pseudo Code
No te : 1 . If an er ror is f ound, the Status Register must be cleared befor e further P/E opera ti ons.
Write 20h
AI03851
Start
Write Block Address
& D0h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
YES
b4 and b5
= 1
VPP Invalid
Error (1)
Command
Sequence Error
Erase Command:
– write 20h
– write Block Address
(A11-A18) & D0h
(memory enters read status
state after the Erase command)
do:
– read status register
(E or G must be toggled)
if Erase command given execute
suspend erase loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4, b5 = 1, Command Sequence error:
– error handler
NO
NO
b5 = 0 Erase
Error (1)
YES
NO
Suspend
Suspend
Loop
If b5 = 1, Erase error:
– error handler
YES
End
YES
NO
b1 = 0 Erase to Protected
Block Error If b1 = 1, Erase to Protected Block Error:
– error handler
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
52/63
Figure 24. Erase Suspend & Resume Flow chart and Pseud o Code
Write 70h
AI00615
Read Status
Register
YES
NO
b7 = 1
YES
NO
b6 = 1
Erase Continues
Write FFh
Program/Erase Suspend Command:
– write B0h
– write 70h
do:
– read status register
while b7 = 1
If b6 = 0, Erase completed
Read Memory Array command:
– write FFh
– one or more data reads
from other blocks
Write D0h
Read data from
another block
or Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Program operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
53/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 25. Unlock Device and Change Tuning Protection Code Flowchart
AI04501
Reset
Device locked
by tuning code
1st: Write Cycle
2nd: Write Cycle
(old code,
factory setup = 0xFFFFh)
YES
3rd: Write Cycle
4th: Write Cycle
(old code,
factory setup = 0xFFFFh)
YES
YES
NO
DEVICE LOCKED
Add: don't care
Data: 0x48h 6th: Write Cycle
Add: 0x00000h
Data: First 32 bit 7th: Write Cycle
(new code)
YES
b7 = 1
Add: don't care
Data: 0x48h 8th: Write Cycle
Add: 0x00001h
Data: Second 32 bit 9th: Write Cycle
(new code)
YES
b7 = 1
DEVICE UNLOCKED
Reset
Device locked
by new code
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 0xFFh 5th: Write Cycle
Issue Read command
Issue
Read
command
Add: don't care
Data: 0x78h
Add: 0x00000h
Data: First 32 bit
b7 = 1
Add: don't care
Data: 0x78h
Add: 0x00001h
Data: Second 32 bit
b7 = 1
Read Status
Register
b0 = 1
Add: don't care
Data: 0xFFh
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
54/63
Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart
AI04502
Reset
Device locked
by tuning code
Add: don't care
Data: 0x78h 1st: Write Cycle
Add: 0x00000h
Data: First 32 bit
2nd: Write Cycle
(First part
of the tuning code)
YES
b7 = 1
Add: don't care
Data: 0x78h 3rd: Write Cycle
Add: 0x00001h
Data: Second 32 bit
4th: Write Cycle
(Second part
of the tuning code)
YES
b7 = 1
YES
NO b0 = 1
DEVICE LOCKED
Add: don't care
Data: 0x40h 6th: Write Cycle
Add: location to prog.
Data: data to prog. 7th: Write Cycle
YES
b7 = 1
DEVICE UNLOCKED
Status Register
check
Location
programmed
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 0xFFh Issue Read command
5th: Write Cycle
Add: don't care
Data: 0xFFh
Issue
Read
command
Read Status
Register
55/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 27. Unlock Device and Erase a Tuning Protec ted Block Flowchart
AI04502
Reset
Device locked
by tuning code
Add: don't care
Data: 0x78h 1st: Write Cycle
Add: 0x00000h
Data: First 32 bit
2nd: Write Cycle
(First part
of the tuning code)
YES
b7 = 1
Add: don't care
Data: 0x78h 3rd: Write Cycle
Add: 0x00001h
Data: Second 32 bit
4th: Write Cycle
(Second part
of the tuning code)
YES
b7 = 1
YES
NO b0 = 1
DEVICE LOCKED
Add: don't care
Data: 0x20h 6th: Write Cycle
Add: block to erase
Data: 0xD0h 7th: Write Cycle
YES
b7 = 1
DEVICE UNLOCKED
Status Register
check
Block
Erased
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 0xFFh Issue Read command
5th: Write Cycle
Add: don't care
Data: 0xFFh
Issue
Read
command
Read Status
Register
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
56/63
Figure 28. Power-up Sequence t o Burst the Flash
AI03834
Power-up
or Reset
Asynchronous Read
Write 60h command
Write 03h with A15-A0
BCR inputs
Synchronous Read
BCR bit 15 = '1'
Set Burst Configuration Register Command:
– write 60h
– write 03h
and BCR on A15-A0
BCR bit 15 = '0'
BCR bit 14-bit 0 = '1'
57/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 29. Comm and Interface and Prog ram E rase Cont roller Flowch art (a)
AI03835
READ ELEC.
SIGNATURE
YES
NO
90h
READ
STATUS
YES
70h NO
ERASE
SET-UP
YES
20h NO
PROGRAM
SET-UP
YES
40h NO
CLEAR
STATUS
YES
50h NO
WAIT FOR
COMMAND
WRITE
READ
STATUS
READ
ARRAY
YES
D
B
C
READ CFI
YES
98h NO
NO D0h
A
ERASE
COMMAND
ERROR E
D
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
58/63
Figure 30. Comm and Interface and Prog ram E rase Cont roller Flowch art (b)
AI03836
TP
PROGRAM
SET_UP
YES
NO
48h
SET BCR
SET_UP
YES
60h NO
D
TP
UNLOCK
SET_UP
YES
78h NO
FFh
03h
NO
YES
NO
E
F
G
YES
59/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 31. Comm and Interface and Prog ram E rase Cont roller Flowch art (c)
READ
STATUS
70h
B
ERASE
READY
NO
A
B0h NO READ
STATUS
YES READY
NO
ERASE
SUSPEND
YES
READ
ARRAY
YES
ERASE
SUSPENDED
READ
STATUS YES
NO
40h
NO
D0h
NO
PROGRAM
SET_UP
AI03837
YES
YES
NO YES READ
STATUS
C
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
60/63
Figure 32. Comm and Interface and Prog ram E rase Cont roller Flowch art (d)
READ
STATUS
70h
B
PROGRAM
READY
NO
C
B0h NO READ
STATUS
YES READY
NO
PROGRAM
SUSPEND
READ
ARRAY
YES
PROGRAM
SUSPENDED
READ
STATUS YES
NO
NO
D0h
AI03838
YES
NO YES READ
STATUS
YES
61/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
Figure 33. Comm and Interface and Prog ram E rase Cont roller Flowch art (e)
B
TP
PROGRAM
READY
F
NO READ
STATUS
AI03839
YES
B
TP
UNLOCK
READY
G
NO READ
STATUS
YES
M58BW016B T, M58BW016B B, M58BW016DT, M5 8BW016DB
62/63
RE VISION HISTORY
Table 30. D ocum ent Revision History
Date Version Revision Details
January-2001 -01 First Issue.
05-Jun-2001 -02 Major rewrite and restructure.
15-Jun-2001 -03 Nd and Ne values changed in PQFP80 Package Mechanical Table
17-Jul-2001 -04 PQFP80 Package Outline Drawing and Mechanical Data Table updated
17-Dec-2001 -05
tLEAD removed from Absolute Maximum Ratings (Table 12)
80, 90 and 100ns Speed classes defined (Tables 16, 17, 18, 19 and 20 clarified
accordingly)
Figures 14, 15, 16 and 17 clarified
Temperature range 3 and 6 added
Tables 13, 14, 15, 21 and CFI Tables 26, 27, 28, 29 clarified
Document status changed from Product Preview to Preliminary Data
17-Jan-2002 -06 DC Characteristics IPP, IPP1 and IDD1 clarified
AC Bus Read Characteristics timing tGHQZ clarified
30-Aug-2002 6.1
Revision numbering modified: a minor revision will be indicated by incrementing the
tenths digit, and a major revision, by incrementing the units digit of the previous
version (e.g. revision version 06 becomes 6.0).
References of VPP pin used for block protection purposes removed. Figure 9
modified.
4-Sep-2002 7.0 Datasheet status changed from Preliminary Data to full Datasheet.
tWLWH parameter modified in Table 19, Asynchronous Write and Latch Controlled
Write AC Characteristics.
13-May-2003 7.1 Revision History moved to end of document. VPP clarified in Program and Block
Erase commands and Status Register, VPP Status bit. VPPLK added to DC
Characteristics Table. Timing TKHQV modif ied.
63/63
M58BW016BT, M58BW016BB , M58BW016DT, M58BW016DB
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