ADP7104ACPZ-1.8-R7 - Analog Devices

20 V, 500 mA, Low Noise, CMOS LDO

Data Sheet

ADP7104

Rev. H Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Input voltage range: 3.3 V to 20 V

Maximum output current: 500 mA

Low noise: 15 µV rms for fixed output versions

PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V

Reverse current protection

Low dropout voltage: 350 mV at 500 mA

Initial accuracy: ±0.8%

Accuracy over line, load, and temperature: −2%/+1%

Low quiescent current (VIN = 5 V), IGND = 900 μA with 500 mA load

Low shutdown current: <40 µA at VIN = 12 V, stable with small

1 µF ceramic output capacitor

7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,

5 V, and 9 V

Adjustable output from 1.22 V to VIN − VDO

Foldback current limit and thermal overload protection

User programmable precision UVLO/enable

Power-good indicator

8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulation to noise sensitive applications: ADC, DAC circuits,

precision amplifiers, high frequency oscillators, clocks,

and PLLs

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

TYPICAL APPLICATION CIRCUITS

OUT

= 5V

= 8V

VOUTVIN

GND

SENSE

EN/

UVLO

COUT

1µF

CIN

1µF

OFF

09507-001

RPG

100kΩ

Figure 1. ADP7104 with Fixed Output Voltage, 5 V

OUT

= 5V

= 8V

VOUTVIN

GND

ADJ

EN/

UVLO

COUT

1µF

CIN

1µF

OFF

13kΩ

40.2kΩ

09507-002

RPG

100kΩ

Figure 2. ADP7104 with Adjustable Output Voltage, 5 V

GENERAL DESCRIPTION

The ADP7104 is a CMOS, low dropout linear regulator that oper-

ates from 3.3 V to 20 V and provides up to 500 mA of output

current. This high input voltage LDO is ideal for regulation of

high performance analog and mixed signal circuits operating

from 19 V to 1.22 V rails. Using an advanced proprietary archi-

tecture, it provides high power supply rejection, low noise, and

achieves excellent line and load transient response with just a

small 1 µF ceramic output capacitor.

The ADP7104 is available in seven fixed output voltage options

and an adjustable version, which allows output voltages that range

from 1.22 V to VIN − VDO via an external feedback divider.

The ADP7104 output noise voltage is 15 μV rms and is inde-

pendent of the output voltage. A digital power-good output

allows power system monitors to check the health of the output

voltage. A user programmable precision undervoltage lockout

function facilitates sequencing of multiple power supplies.

The ADP7104 is available in 8-lead, 3 mm × 3 mm LFCSP

and 8-lead SOIC packages. The LFCSP offers a very compact

solution and also provides excellent thermal performance for

applications requiring up to 500 mA of output current in a

small, low-profile footprint.

ADP7104 Data Sheet

Rev. H | Page 2 of 25

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor, Recommended Specifications ..... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 16

Applications Information .............................................................. 17

Capacitor Selection .................................................................... 17

Programmable Undervoltage Lockout (UVLO) .................... 18

Power-Good Feature .................................................................. 19

Noise Reduction of the Adjustable ADP7104 ............................ 19

Current Limit and Thermal Overload Protection ................. 20

Thermal Considerations ............................................................ 20

Printed Circuit Board Layout Considerations ............................ 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 25

REVISION HISTORY

10/15—Rev. G to Rev. H

Changes to Figure 59 and Figure 60 ............................................. 16

5/14—Rev. F to Rev. G

Change to UVLO Threshold Rising Parameter, Table 1 ............. 4

Change to Power-Good Feature Section ..................................... 19

11/13—Rev. E to Rev. F

Changes to Figure 53 through Figure 58 ..................................... 15

10/13—Rev. D to Rev. E

Changes to Figure 1 and Figure 2 ................................................... 1

Changes to Figure 65 ...................................................................... 18

Changes to Figure 69 ...................................................................... 19

8/13—Rev. C to Rev. D

Changes to Table 3 ............................................................................ 5

2/13—Rev. B to Rev. C

Changes to Noise Reduction of the Adjustable ADP7104

Section .............................................................................................. 19

Updated Outline Dimensions ....................................................... 25

3/12—Rev. A to Rev. B

Changes to Figure 66 ...................................................................... 18

11/11—Rev. 0 to Rev. A

Changed Low Dropout Voltage from 200 mV to 350 mV .......... 1

Changes to Dropout Voltage Parameter ........................................ 3

10/11—Revision 0: Initial Version

Data Sheet ADP7104

Rev. H | Page 3 of 25

SPECIFICATIONS

VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, T A = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN 3.3 20 V

OPERATING SUPPLY CURRENT IGND IOUT = 100 µA, VIN = 10 V 400 µA

IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C 900 µA

IOUT = 10 mA, VIN = 10 V 450 µA

IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 1050 µA

IOUT = 300 mA, VIN = 10 V 750 µA

IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 1400 µA

IOUT = 500 mA, VIN = 10 V 900 µA

OUT

= 500 mA, V

= 10 V, T

= −40°C to +125°C

1600

µA

SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 12 V 40 50 µA

EN = GND, VIN = 12 V, TJ = −40°C to +125°C 75 µA

INPUT REVERSE CURRENT IREV-INPUT EN = GND, VIN = 0 V, VOUT = 20 V 0.3 µA

EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to

+125°C

5 µA

OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy VOUT IOUT = 10 mA –0.8 +0.8 %

1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,

TJ = −40°C to +125°C

–2 +1 %

Adjustable Output Voltage

Accuracy

VADJ IOUT = 10 mA 1.21 1.22 1.23 V

1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,

TJ = −40°C to +125°C

1.196 1.232 V

LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −0.015 +0.015 %/V

LOAD REGULATION

∆V

OUT

/∆I

OUT

= 1 mA to 500 mA

0.2

%/A

IOUT = 1 mA to 500 mA, TJ = −40°C to +125°C 0.75 %/A

ADJ INPUT BIAS CURRENT ADJI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,

ADJ connected to VOUT

10 nA

SENSE INPUT BIAS CURRENT SENSEI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,

SENSE connected to VOUT, VOUT = 1.5 V

1 μA

DROPOUT VOLTAGE1F

2 VDROPOUT IOUT = 10 mA 20 mV

IOUT = 10 mA, TJ = −40°C to +125°C 40 mV

OUT

= 150 mA

100

IOUT = 150 mA, TJ = −40°C to +125°C 175 mV

IOUT = 300 mA 200 mV

IOUT = 300 mA, TJ = −40°C to +125°C 325 mV

IOUT = 500 mA 350 mV

OUT

= 500 mA, T

= −40°C to +125°C

550

START-UP TIME2F

3 tSTART-UP VOUT = 5 V 1000 µs

CURRENT-LIMIT THRESHOLD3F

4 ILIMIT 625 775 1000 mA

PG OUTPUT LOGIC LEVEL

PG Output Logic High

HIGH

< 1 µA

1.0

PG Output Logic Low PGLOW IOL < 2 mA 0.4 V

PG OUTPUT THRESHOLD

Output Voltage Falling PGFALL −9.2 %

Output Voltage Rising PGRISE −6.5 %

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD TJ rising 150 °C

Thermal Shutdown Hysteresis TSSD-HYS 15 °C

ADP7104 Data Sheet

Rev. H | Page 4 of 25

Parameter Symbol Conditions Min Typ Max Unit

PROGRAMMABLE EN/UVLO

UVLO Threshold Rising UVLORISE 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 1.18 1.22 1.28 V

UVLO Threshold Falling UVLOFALL 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in

series with the enable pin

1.13 V

UVLO Hysteresis Current UVLOHYS VEN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 µA

Enable Pull-Down Current IEN-IN EN = VIN 500 nA

Start Threshold VSTART TJ = −40°C to +125°C 3.2 V

Shutdown Threshold VSHUTDOWN TJ = −40°C to +125°C 2.45 V

Hysteresis 250 mV

OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 15 µV rms

10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 15 µV rms

10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 15 µV rms

10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 15 µV rms

10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V,

adjustable mode

18 µV rms

10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V,

adjustable mode

30 µV rms

10 Hz to 100 kHz, VIN = 20 V, VOUT = 15 V,

adjustable mode

65 µV rms

POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.3 V, VOUT = 3.3 V 50 dB

100 kHz, VIN = 6 V, VOUT = 5 V 50 dB

10 kHz, V

= 4.3 V, V

OUT

= 3.3 V

10 kHz, VIN = 6 V, VOUT = 5 V 60 dB

100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 50 dB

100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 60 dB

100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 60 dB

10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 60 dB

10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 80 dB

10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 80 dB

1 Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.

2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 3.0 V.

3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

Minimum Input and Output Capacitance4F

1 CMIN TA = −40°C to +125°C 0.7 µF

Capacitor ESR RESR TA = −40°C to +125°C 0.001 0.2 Ω

1 The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;

Y5V and Z5U capacitors are not recommended for use with any LDO.

Data Sheet ADP7104

Rev. H | Page 5 of 25

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND −0.3 V to +22 V

VOUT to GND

−0.3 V to +20 V

EN/UVLO to GND −0.3 V to VIN

PG to GND −0.3 V to VIN

SENSE/ADJ to GND −0.3 V to VOUT

Storage Temperature Range −65°C to +150°C

Operating Junction Temperature Range −40°C to +125°C

Soldering Conditions JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADP7104 can be damaged when the junction

temperature limit is exceeded. Monitoring ambient temperature

does not guarantee that TJ is within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

In applications with moderate power dissipation and low PCB

thermal resistance, the maximum ambient temperature can

exceed the maximum limit as long as the junction temperature

is within specification limits. The junction temperature (TJ) of

the device is dependent on the ambient temperature (TA), the

power dissipation of the device (PD), and the junction-to-ambient

thermal resistance of the package (θJA).

Maximum junction temperature (TJ) is calculated from the

ambient temperature (TA) and power dissipation (PD) using the

formula

TJ = TA + (PD × θJA)

Junction-to-ambient thermal resistance (θJA) of the package is

based on modeling and calculation using a 4-layer board. The

junction-to-ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The value of θJA may vary, depending

on PCB material, layout, and environmental conditions. The

specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit

board. See JESD51-7 and JESD51-9 for detailed information on

the board construction. For additional information, see the

AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale

Package, available at www.analog.com.

ΨJB is the junction-to-board thermal characterization parameter

with units of °C/W. The package’s ΨJB is based on modeling and

calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. ΨJB measures the component power

flowing through multiple thermal paths rather than a single

path as in thermal resistance, θJB. Therefore, ΨJB thermal paths

include convection from the top of the package as well as

radiation from the package, factors that make ΨJB more useful

in real-world applications. Maximum junction temperature (TJ)

is calculated from the board temperature (TB) and power

dissipation (PD) using the formula

TJ = TB + (PD × ΨJB)

See JESD51-8 and JESD51-12 for more detailed information

about ΨJB.

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a

device soldered in a circuit board for surface-mount packages. θJC

is a parameter for surface-mount packages with top mounted

heatsinks. θJC is presented here for reference only.

Table 4. Thermal Resistance

Package Type θJA θJC ΨJB Unit

8-Lead LFCSP 40.1 27.1 17.2 °C/W

8-Lead SOIC 48.5 58.4 31.3 °C/W

ESD CAUTION

ADP7104 Data Sheet

Rev. H | Page 6 of 25

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNE

T. DO NOT CONNECT TO

THIS PIN.

. IT IS HIGHLY RECOMMENDED THAT THE

EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE BE CONNECTED TO THE GROUND

PLANE ON THE BOARD.

3GND

4NC

1VOUT

2SENSE/ADJ

6GND

5 EN/UVLO

8VIN

7PG

ADP7104

TOP VIEW

(Not to Scale)

09507-003

Figure 3. LFCSP Package

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.

2. IT IS HIGHLY RECOMMENDED THAT THE

EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE BE CONNECTED TO THE GROUND

PLANE ON THE BOARD.

VOUT

SENSE/ADJ

GND

VIN

GND

EN/UVLO

ADP7104

TOP VIEW

(Not to Scale)

09507-004

Figure 4. Narrow Body SOIC Package

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.

2 SENSE/ADJ

Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier.

Connect SENSE as close as possible to the load to minimize the effect of IR drop between the

regulator output and the load. This function applies to fixed voltages only.

Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to

adjustable voltages only.

3 GND Ground.

4 NC Do Not Connect to this Pin.

5 EN/UVLO

Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.

For automatic startup, connect EN to VIN.

Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,

the upper and lower thresholds are determined by the programming resistors.

6 GND Ground.

7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the

part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output

voltage, PG immediately transitions low. If the power-good function is not used, the pin may be

left open or connected to ground.

8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.

EPAD

Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal

performance and is electrically connected to GND inside the package. It is highly recommended

that the EPAD be connected to the ground plane on the board.

Data Sheet ADP7104

Rev. H | Page 7 of 25

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 7.5 V, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.

3.25

3.27

3.29

3.31

3.33

3.35

VOUT (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

–40°C –5°C 25°C 85°C 125°C

TJ (

°C

)

09507-005

Figure 5. Output Voltage vs. Junction Temperature

3.25

3.27

3.29

3.31

3.33

3.35

0.1 110 100 1000

OUT

(V)

LOAD

(mA)

09507-006

Figure 6. Output Voltage vs. Load Current

3.25

3.27

3.29

3.31

3.33

3.35

46810 12 14 16 18 20

VOUT (V)

VIN (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

09507-007

Figure 7. Output Voltage vs. Input Voltage

200

400

600

800

1000

1200

GRO UND CURRE NT (µA)

–40°C –5°C 25°C 85°C 125°C

(

°C

)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

09507-008

Figure 8. Ground Current vs. Junction Temperature

100

200

300

400

500

600

700

800

0.1 110 100 1000

LOAD

(mA)

GRO UND CURRE NT (µA)

09507-009

Figure 9. Ground Current vs. Load Current

200

400

600

800

1000

1200

46810 12 14 16 18 20

GRO UND CURRE NT (µA)

(V)

LO AD = 100µA

LO AD = 1mA

LO AD = 10mA

LO AD = 100mA

LO AD = 300mA

LO AD = 500mA

09507-010

Figure 10. Ground Current vs. Input Voltage

ADP7104 Data Sheet

Rev. H | Page 8 of 25

SHUT DO WN CURRENT (µA)

100

120

140

160

–50 –25 025 50 75 100 125

TEMPERAT URE ( °C)

3.3V

4.0V

6.0V

8.0V

12.0V

20.0V

09507-011

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

100

150

200

250

300

350

110 100 1000

DROPOUT ( mV )

LOAD

(mA)

OUT

= 3.3V

= 25° C

09507-012

Figure 12. Dropout Voltage vs. Load Current

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.1 3.2 3.3 3.4 3.5 3.6 3.7

VOUT (V)

VIN (V)

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

LOAD = 500mA

09507-013

Figure 13. Output Voltage vs. Input Voltage (in Dropout)

200

400

600

800

1000

1200

1400

3.1 3.2 3.3 3.4 3.5 3.6 3.7

GRO UND CURRE NT (µA)

VIN (V)

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

LOAD = 500mA

09507-014

Figure 14. Ground Current vs. Input Voltage (in Dropout)

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

OUT

(V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

–40°C –5°C 25°C 85°C 125°C

(

°C

)

09507-015

Figure 15. Output Voltage vs. Junction Temperature, VOUT = 5 V

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

0.1 110 100 1000

OUT

(V)

LOAD

(mA)

09507-016

Figure 16. Output Voltage vs. Load Current, VOUT = 5 V

Data Sheet ADP7104

Rev. H | Page 9 of 25

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

6 8 10 12 14 16 18 20

OUT

(V)

LO AD = 100µA

LO AD = 1mA

LO AD = 10mA

LO AD = 100mA

LO AD = 300mA

LO AD = 500mA

09507-017

Figure 17. Output Voltage vs. Input Voltage, VOUT = 5 V

100

200

300

400

500

600

700

800

900

1000

25°C 85°C 125°C

GRO UND CURRE NT (µA)

TJ (° C)

–40°C –5°C

LO AD = 100µA

LO AD = 1mA

LO AD = 10mA

LO AD = 100mA

LO AD = 300mA

09507-118

Figure 18. Ground Current vs. Junction Temperature, VOUT = 5 V

100

200

300

400

500

600

700

0.1 110 100 1000

GRO UND CURRE NT (µA)

ILOAD (mA)

09507-119

Figure 19. Ground Current vs. Load Current, VOUT = 5 V

100

150

200

250

300

110 100 1000

DROPOUT ( mV )

ILOAD (mA)

VOUT = 5V

TA = 25° C

09507-018

Figure 20. Dropout Voltage vs. Load Current, VOUT = 5 V

4.55

4.60

4.65

4.70

4.75

4.80

4.85

4.90

4.95

5.00

5.05

4.8 4.9 5.0 5.1 5.2 5.3 5.4

OUT

(V)

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

LOAD = 500mA

09507-019

Figure 21. Output Voltage vs. Input Voltage (in Dropout)

–500

500

1000

1500

2000

2500

4.80 4.90 5.00 5.10 5.20 5.30 5.40

GRO UND CURRE NT (µA)

VIN (V)

LOAD = 5mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 300mA

LOAD = 500mA

09507-020

Figure 22. Ground Current vs. Input Voltage (in Dropout), VOUT = 5 V

ADP7104 Data Sheet

Rev. H | Page 10 of 25

1.75

1.77

1.79

1.81

1.83

1.85

VOUT (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

–40°C –5°C 25°C 85°C 125°C

TJ (

°C

)

09507-021

Figure 23. Output Voltage vs. Junction Temperature, VOUT = 1.8 V

OUT

(V)

1.75

1.77

1.79

1.81

1.83

1.85

0.1 110 100 1000

LOAD

(mA)

09507-022

Figure 24. Output Voltage vs. Load Current, VOUT = 1.8 V

1.75

1.77

1.79

1.81

1.83

1.85

2 4 6810 12 14 16 18 20

OUT

(V)

LO AD = 100µA

LO AD = 1mA

LO AD = 10mA

LO AD = 100mA

LO AD = 300mA

LO AD = 500mA

09507-023

Figure 25. Output Voltage vs. Input Voltage, VOUT = 1.8 V

100

200

300

400

500

600

700

800

900

25°C 85°C 125°C

GRO UND CURRE NT (µA)

TJ (° C)

–40°C –5°C

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

09507-126

Figure 26. Ground Current vs. Junction Temperature, VOUT = 1.8 V

100

200

300

400

500

600

700

0.1 110 100 1000

GRO UND CURRE NT (µA)

ILOAD (mA)

09507-127

Figure 27. Ground Current vs. Load Current, VOUT = 1.8 V

200

400

600

800

1000

1200

2 4 6 8 10 12 14 16 18 20

GRO UND CURRE NT (µA)

VIN (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

09507-024

Figure 28. Ground Current vs. Input Voltage, VOUT = 1.8 V

Data Sheet ADP7104

Rev. H | Page 11 of 25

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

VOUT (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

–40°C –5°C 25°C 85°C 125°C

TJ (

°C

)

09507-025

Figure 29. Output Voltage vs. Junction Temperature, VOUT = 5 V, Adjustable

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

0.1 110 100 1000

OUT

(V)

LOAD

(mA)

09507-026

Figure 30. Output Voltage vs. Load Current, VOUT = 5 V, Adjustable

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

6810 12 14 16 18 20

VOUT (V)

VIN (V)

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 300mA

LOAD = 500mA

09507-027

Figure 31. Output Voltage vs. Input Voltage, VOUT = 5 V, Adjustable

0.5

1.0

1.5

2.0

–40 –20 020 40 60 80 100 120 140

OUT

SHUT DO WN CURRENT ( µA)

TEMPERAT URE ( °C)

3.3V

10V

12V

15V

18V

20V

09507-054

Figure 32. Reverse Input Current vs. Temperature, VIN = 0 V, Different

Voltages on VOUT

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR ( dB)

FREQUENCY (Hz)

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

09507-028

Figure 33. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, VIN = 3.3 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR ( dB)

FREQUENCY (Hz)

09507-029

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.8 V

ADP7104 Data Sheet

Rev. H | Page 12 of 25

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY (Hz)

09507-030

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY (Hz)

09507-031

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

09507-032

Figure 37. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6.5 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M

09507-033

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 38. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

09507-034

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 39. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.5 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

09507-035

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 40. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.3 V

Data Sheet ADP7104

Rev. H | Page 13 of 25

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

09507-036

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

09507-037

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V

Adjustable

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

PSRR (dB)

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

09507-038

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

Figure 43. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V

Adjustable With Noise Reduction Circuit

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

00.25 0.50 0.75 1.00 1.25 1.50

PSRR (dB)

HEADROOM V OLTAGE (V)

09507-039

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 44. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz,

VOUT = 5 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

00.25 0.50 0.75 1.00 1.25 1.50

PSRR (dB)

HEADROOM V OLTAGE (V)

09507-040

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz,

VOUT = 5 V

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

00.25 0.50 0.75 1.00 1.25 1.50

PSRR (dB)

HEADROOM V OLTAGE (V)

09507-041

LOAD = 500mA

LOAD = 300mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz,

VOUT = 5 V

ADP7104 Data Sheet

Rev. H | Page 14 of 25

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

00.25 0.50 0.75 1.00 1.25 1.50

PSRR (dB)

HEADROOM V OLTAGE (V)

LO AD = 500mA

LO AD = 300mA

LO AD = 100mA

LO AD = 10mA

LO AD = 1mA

09507-042

Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz,

VOUT = 5 V

0.01

0.0010.00010.00001 0.1 1

NOISE (µV rms)

LO AD CURRE NT (A)

3.3V

1.8V

5VADJ

5VADJ NR

09507-043

Figure 48. Output Noise vs. Load Current and Output Voltage,

COUT = 1 μF

FREQUENCY (Hz)

0.01

0.1

10 100 1k 10k 100k

NOISE (µV/√Hz)

3.3V

5VADJ

5VADJ NR

09507-044

Figure 49. Output Noise Spectral Density, ILOAD = 10 mA, COUT = 1 μF

CH2 50mVCH1 500mA M 20µs A CH1 270mA

T10%

Ω

LOAD CURRENT

OUTPUT VOLTAGE

09507-045

Figure 50. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 500 mA,

VOUT = 1.8 V, VIN = 5 V

CH2 50mVCH1 500mAM 20µs A CH1 280mA

T10.2%

Ω

LOAD CURRENT

OUTPUT VOLTAGE

09507-046

Figure 51. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 500 mA,

VOUT = 3.3 V, VIN = 5 V

CH2 50mVCH1 500mAM 20µs A CH1 300mA

T10.2%

Ω

LOAD CURRENT

OUTPUT VOLTAGE

09507-047

Figure 52. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 500 mA,

VOUT = 5 V, VIN = 7 V

Data Sheet ADP7104

Rev. H | Page 15 of 25

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-048

Figure 53. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 500 mA,

VOUT = 1.8 V

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-049

Figure 54. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 500 mA,

VOUT = 3.3 V

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-050

Figure 55. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 500 mA,

VOUT = 5 V

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-051

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

Figure 56. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA,

VOUT = 1.8 V

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-052

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

Figure 57. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA, VOUT = 3.3 V

CH2 10mVCH1 1V M 4µs A CH4 1.56V

T9.8%

INPUT VOLTAGE

OUTPUT VOLTAGE

09507-053

Figure 58. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA,

VOUT = 5 V

ADP7104 Data Sheet

Rev. H | Page 16 of 25

THEORY OF OPERATION

The ADP7104 is a low quiescent current, low-dropout linear

regulator that operates from 3.3 V to 20 V and provides up to

500 mA of output current. Drawing a low 1 mA of quiescent

current (typical) at full load makes the ADP7104 ideal for

battery-operated portable equipment. Typical shutdown

current consumption is 40 μA at room temperature.

Optimized for use with small 1 µF ceramic capacitors, the

ADP7104 provides excellent transient performance.

SHUTDOWN

VIN

GND

EN/

UVLO

VOUT

REFERENCE

VREG PGOOD PG

SENSE

SHORT-CIRCUIT,

THERMAL

PROTECT

10µA

09507-056

Figure 59. Fixed Output Voltage Internal Block Diagram

SHUTDOWN

VIN

GND

EN/

UVLO

VOUT

1.22V

REFERENCE

VREG PGOOD PG

ADJ

SHORT-CIRCUIT,

THERMAL

PROTECT

10µA

09507-156

Figure 60. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7104 consists of a reference, an error amplifier, a

feedback voltage divider, and a PMOS pass transistor. Output

current is delivered via the PMOS pass device, which is controlled

by the error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the reference

voltage, the gate of the PMOS device is pulled lower, allowing

more current to pass and increasing the output voltage. If the

feedback voltage is higher than the reference voltage, the gate

of the PMOS device is pulled higher, allowing less current to

pass and decreasing the output voltage.

The ADP7104 is available in seven fixed output voltage options,

ranging from 1.5 V to 9 V and in an adjustable version with an

output voltage that can be set to between 1.22 V and 19 V by an

external voltage divider. The output voltage can be set according

to the following equation:

VOUT = 1.22 V(1 + R1/R2)

VOUT = 5V

VIN = 8V

VOUTVIN

GND

ADJ

EN/

UVLO RPG

100kΩ

COUT

1µF

CIN

1µF

OFF R2

13kΩ

+R1

40.2kΩ

09507-075

Figure 61. Typical Adjustable Output Voltage Application Schematic

The value of R2 should be less than 200 kΩ to minimize errors

in the output voltage caused by the ADJ pin input current. For

example, when R1 and R2 each equal 200 kΩ, the output voltage

is 2.44 V. The output voltage error introduced by the ADJ pin input

current is 2 mV or 0.08%, assuming a typical ADJ pin input

current of 10 nA at 25°C.

The ADP7104 uses the EN/UVLO pin to enable and disable

the VOUT pin under normal operating conditions. When

EN/UVLO is high, VOUT turns on, when EN is low, VOUT

turns off. For automatic startup, EN/UVLO can be tied to VIN.

The ADP7104 incorporates reverse current protections circuitry

that prevents current flow backwards through the pass element

when the output voltage is greater than the input voltage. A

comparator senses the difference between the input and output

voltages. When the difference between the input voltage and

output voltage exceeds 55 mV, the body of the PFET is switched

to VOUT and turned off or opened. In other words, the gate is

connected to VOUT.

Data Sheet ADP7104

Rev. H | Page 17 of 25

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP7104 is designed for operation with small, space-saving

ceramic capacitors but functions with most commonly used

capacitors as long as care is taken with regard to the effective series

resistance (ESR) value. The ESR of the output capacitor affects the

stability of the LDO control loop. A minimum of 1 µF capacitance

with an ESR of 1 Ω or less is recommended to ensure the stability

of the ADP7104. Transient response to changes in load current is

also affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADP7104 to

large changes in load current. Figure 62 shows the transient

responses for an output capacitance value of 1 µF.

CH2 50mVCH1 500mA M 20µs A CH1 270mA

T10%

Ω

LOAD CURRENT

OUTPUT VOLTAGE

09507-057

Figure 62. Output Transient Response, VOUT = 1.8 V, COUT = 1 µF

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces

the circuit sensitivity to printed circuit board (PCB) layout,

especially when long input traces or high source impedance

are encountered. If greater than 1 µF of output capacitance is

required, the input capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7104, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufac-

tured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over

the necessary temperature range and dc bias conditions. X5R

or X7R dielectrics with a voltage rating of 6.3 V to 25 V are

recommended. Y5V and Z5U dielectrics are not recommended,

due to their poor temperature and dc bias characteristics.

Figure 63 depicts the capacitance vs. voltage bias characteristic

of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is ~±15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

0246810

CAPACITANCE (µF )

VOLTAGE (V)

09507-058

Figure 63. Capacitance vs. Voltage Characteristic

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

CBIAS is 0.94 μF at 1.8 V, as shown in Figure 63.

Substituting these values in Equation 1 yields

CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO overtemper-

ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7104, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

ADP7104 Data Sheet

Rev. H | Page 18 of 25

PROGRAMMABLE UNDERVOLTAGE LOCKOUT

(UVLO)

The ADP7104 uses the EN/UVLO pin to enable and disable the

VOUT pin under normal operating conditions. As shown in

Figure 64, when a rising voltage on EN crosses the upper threshold,

VOUT turns on. When a falling voltage on EN/ UVLO crosses

the lower threshold, VOUT turns off. The hysteresis of the

EN/UVLO threshold is determined by the Thevenin equivalent

resistance in series with the EN/UVLO pin.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.001.00

VOUT, E N RISE

VOUT, EN FALL

09507-060

Figure 64. Typical VOUT Response to EN Pin Operation

The upper and lower thresholds are user programmable and can

be set using two resistors. When the EN/UVLO pin voltage is

below 1.22 V, the LDO is disabled. When the EN/UVLO pin

voltage transitions above 1.22 V, the LDO is enabled and 10 µA

hysteresis current is sourced out the pin raising the voltage, thus

providing threshold hysteresis. Typically, two external resistors

program the minimum operational voltage for the LDO. The

resistance values, R1 and R2 can be determined from:

R1 = VHYS/10 μA

R2 = 1.22 V × R1/(VIN − 1.22 V)

where:

VIN is the desired turn-on voltage.

VHYS is the desired EN/UVLO hysteresis level.

Hysteresis can also be achieved by connecting a resistor in

series with EN/UVLO pin. For the example shown in Figure 65,

the enable threshold is 2.44 V with a hysteresis of 1 V.

OUT

= 5V

= 8V

VOUTVIN

GND

SENSE

EN/

UVLO

RPG

100kΩ

COUT

1µF

CIN

1µF

OFF

09507-059

Figure 65. Typical EN Pin Voltage Divider

Figure 64 shows the typical hysteresis of the EN/UVLO pin.

This prevents on/off oscillations that can occur due to noise

on the EN pin as it passes through the threshold points.

The ADP7104 uses an internal soft-start to limit the inrush current

when the output is enabled. The start-up time for the 3.3 V option

is approximately 580 μs from the time the EN active threshold is

crossed to when the output reaches 90% of its final value. As

shown in Figure 66, the start-up time is dependent on the

output voltage setting.

TIME (µs)

0500 1000 1500 2000

VOUT (V)

3.3V

ENABLE

09507-061

Figure 66. Typical Start-Up Behavior

Data Sheet ADP7104

Rev. H | Page 19 of 25

POWER-GOOD FEATURE

The ADP7104 provides a power-good pin (PG) to indicate

the status of the output. This open-drain output requires an

external pull-up resistor to VIN or VOUT. If the part is in

shutdown mode, current-limit mode, or thermal shutdown, or

if it falls below 90% of the nominal output voltage, the power-

good pin (PG) immediately transitions low. During soft-start,

the rising threshold of the power-good signal is 93.5% of the

nominal output voltage.

The open-drain output is held low when the ADP7104 has suffi-

cient input voltage to turn on the internal PG transistor. The PG

transistor is terminated via a pull-up resistor to VOUT or VIN.

Power-good accuracy is 93.5% of the nominal regulator output

voltage when this voltage is rising, with a 90% trip point when

this voltage is falling. Regulator input voltage brownouts or

glitches trigger power no good signals if VOUT falls below 90%.

A normal power-down causes the power-good signal to go low

when VOUT drops below 90%.

Figure 67 and Figure 68 show the typical power-good rising and

falling threshold over temperature.

4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

PG (V)

OUT

(V)

PG –4 0°C

PG –5°C

PG +25°C

PG +85°C

PG + 12 5°C

09507-062

Figure 67. Typical Power-Good Threshold vs. Temperature, VOUT Rising

4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

PG (V)

VOUT (V)

PG –4 0°C

PG –5°C

PG +25°C

PG +85°C

PG + 12 5°C

09507-063

Figure 68. Typical Power-Good Threshold vs. Temperature, VOUT Falling

NOISE REDUCTION OF THE ADJUSTABLE ADP7104

The ultralow output noise of the fixed output ADP7104 is

achieved by keeping the LDO error amplifier in unity gain

and setting the reference voltage equal to the output voltage.

This architecture does not work for an adjustable output

voltage LDO. The adjustable output ADP7104 uses the more

conventional architecture where the reference voltage is fixed

and the error amplifier gain is a function of the output voltage.

The disadvantage of the conventional LDO architecture is that

the output voltage noise is proportional to the output voltage.

The adjustable LDO circuit may be modified slightly to reduce

the output voltage noise to levels close to that of the fixed

output ADP7104. The circuit shown in Figure 69 adds two

additional components to the output voltage setting resistor

divider. CNR and RNR are added in parallel with RFB1 to reduce

the ac gain of the error amplifier. RNR is chosen to be equal to

RFB2, this limits the ac gain of the error amplifier to approxi-

mately 6 dB. The actual gain is the parallel combination of RNR

and RFB1 divided by RFB2. This ensures that the error amplifier

always operates at greater than unity gain.

CNR is chosen by setting the reactance of CNR equal to RFB1 −

RNR at a frequency between 50 Hz and 100 Hz. This sets the

frequency where the ac gain of the error amplifier is 3 dB

down from its dc gain.

OUT

= 5V

= 8V

VOUTVIN

GND

ADJ

EN/

UVLO

COUT

1µF

CIN

1µF

OFF

13kΩ

FB2

13kΩ

FB1

40.2kΩC

100nF

09507-064

RPG

100kΩ

Figure 69. Noise Reduction Modification to Adjustable LDO

The noise of the adjustable LDO is can be found by using the

formula below assuming the noise of a fixed output LDO is

approximately 15 μ V.













Ω













Ω+Ω

+× k13/

k2.

40/1k13/

1μV15

Based on the component values shown in Figure 69, the

ADP7104 has the following characteristics:

• DC gain of 4.09 (12.2 dB)

• 3 dB roll off frequency of 59 Hz

• High frequency ac gain of 1.76 (4.89 dB)

• Noise reduction factor of 1.33 (2.59 dB)

• RMS noise of the adjustable LDO without noise reduction

of 27.8 µV rms

• RMS noise of the adjustable LDO with noise reduction

(assuming 15 µV rms for fixed voltage option) of

19.95 µV rms

ADP7104 Data Sheet

Rev. H | Page 20 of 25

CURRENT LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7104 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7104 is designed to current limit when the

output load reaches 600 mA (typical). When the output load

exceeds 600 mA, the output voltage is reduced to maintain a

constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts to

rise above 150°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

135°C, the output is turned on again, and output current is

restored to its operating value.

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7104 current limits, so that only 600 mA

is conducted into the short. If self heating of the junction is

great enough to cause its temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to zero. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

600 mA into the short, again causing the junction temperature

to rise above 150°C. This thermal oscillation between 135°C

and 150°C causes a current oscillation between 600 mA and

0 mA that continues as long as the short remains at the output.

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For reliable

operation, device power dissipation must be externally limited

so the junction temperature does not exceed 125°C.

THERMAL CONSIDERATIONS

In applications with low input-to-output voltage differential, the

ADP7104 does not dissipate much heat. However, in applications

with high ambient temperature and/or high input voltage, the

heat dissipated in the package may become large enough that

it causes the junction temperature of the die to exceed the

maximum junction temperature of 125°C.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the tempera-

ture rise of the package due to the power dissipation, as shown

in Equation 2.

To guarantee reliable operation, the junction temperature of

the ADP7104 must not exceed 125°C. To ensure that the

junction temperature stays below this maximum value, the

user must be aware of the parameters that contribute to

junction temperature changes. These parameters include

ambient temperature, power dissipation in the power device,

and thermal resistances between the junction and ambient air

(θJA). The θJA number is dependent on the package assembly

compounds that are used and the amount of copper used to

solder the package GND pins to the PCB.

Table 6 shows typical θJA values of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes. Table 7 shows

the typical ΨJB values of the 8-lead SOIC and 8-l e a d L F C SP.

Table 6. Typical θJA Values

Copper Size (mm2)

θJA (°C/W)

LFCSP SOIC

251 165.1 167.8

100 125.8 111

500 68.1 65.9

1000 56.4 56.1

6400 42.1 45.8

1 Device soldered to minimum size pin traces.

Table 7. Typical ΨJB Values

Model ΨJB (°C/W)

LFCSP 15.1

SOIC 31.3

The junction temperature of the ADP7104 is calculated from the

following equation:

TJ = TA + (PD × θJA) (2)

where:

TA is the ambient temperature.

PD is the power dissipation in the die, given by

PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)

where:

ILOAD is the load current.

IGND is the ground current.

VIN and VOUT are input and output voltages, respectively.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to the following:

TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB

to ensure that the junction temperature does not rise above 125°C.

Figure 70 to Figure 77 show junction temperature calculations

for different ambient temperatures, power dissipation, and areas

of PCB copper.

Data Sheet ADP7104

Rev. H | Page 21 of 25

105

115

125

135

145

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

JUNCTION TEMP E R ATURE (° C)

TOTAL POWER DISSIPATION (W)

6400mm

500mm

25mm

MAX

09507-065

Figure 70. LFCSP, TA = 25°C

JUNCTI ON T E M P E R ATURE (° C)

100

110

120

130

140

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TOTAL POWER DISSIPATION (W)

6400mm

500mm

25mm

MAX

09507-066

Figure 71. LFCSP, TA = 50°C

JUNCTION TEMP E R ATURE (° C)

105

115

125

135

145

00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

6400mm

500mm

25mm

MAX

09507-067

Figure 72. LFCSP, TA = 85°C

105

115

125

135

145

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

JUNCTION TEMP E R ATURE (° C)

6400mm

500mm

25mm

MAX

09507-068

Figure 73. SOIC, TA = 25°C

100

110

120

130

140

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TOTAL POWER DISSIPATION (W)

JUNCTI ON T E M P E R ATURE (° C)

6400mm2

500mm2

25mm2

TJMAX

09507-069

Figure 74. SOIC, TA = 50°C

105

115

125

135

145

00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

JUNCTI ON T E M P E R ATURE (° C)

6400mm

500mm

25mm

MAX

09507-070

Figure 75. SOIC, TA = 85°C

ADP7104 Data Sheet

Rev. H | Page 22 of 25

In the case where the board temperature is known, use the

thermal characterization parameter, ΨJB, to estimate the

junction temperature rise (see Figure 76 and Figure 77).

Maximum junction temperature (TJ) is calculated from

the board temperature (TB) and power dissipation (PD)

using the following formula:

TJ = TB + (PD × ΨJB) (5)

The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP package

and 31.3°C/W for the 8-lead SOIC package.

TOTAL POWER DISSIPATION (W)

JUNCTIO N TEMP E R ATURE ( T

)

100

120

140

00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

TB = 25° C

TB = 50° C

TB = 65° C

TB = 85° C

TJMAX

09506-071

Figure 76. LFCSP

TOTAL POWER DISSIPATION (W)

JUNCTION TEM P E R ATURE ( T

)

100

120

140

00.5 1.0 1.5 2.0 2.5 3.0 3.5

TB = 25° C

TB = 50° C

TB = 65° C

TB = 85° C

TJMAX

09507-072

Figure 77. SOIC

Data Sheet ADP7104

Rev. H | Page 23 of 25

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP7104.

However, as listed in Table 6, a point of diminishing returns

is eventually reached, beyond which an increase in the copper

size does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0805 or 0603 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

09507-073

Figure 78. Example LFCSP PCB Layout

09507-074

Figure 79. Example SOIC PCB Layout

ADP7104 Data Sheet

Rev. H | Page 24 of 25

OUTLINE DIMENSIONS

PIN 1

INDICATOR

(R 0. 2)

BOTTOM VIEW

TOP VIEW 1

INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

0.30

0.25

0.18

0.05 M AX

0.02 NO M

0.80 M AX

0.55 NO M

0.20 REF

0.50 BSC

COPLANARITY

0.08

2.48

2.38

2.23

1.74

1.64

1.49

0.50

0.40

0.30

COMPLIANT

JEDEC STANDARDS M O-229-WEE D- 4

FO R P ROPE R CONNECT ION OF

THE EXPOSED PAD, REFER TO

THE P IN CO NFIGURAT ION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

02-05-2013-B

0.20 M I N

EXPOSED

PAD

3.10

3.00 SQ

2.90

Figure 80. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-5)

Dimensions shown in millimeters

COMPLIANT TO JEDE C S TANDARDS MS-012-AA

06-03-2011-B

1.27

0.40

1.75

1.35

2.41

0.356

0.457

4.00

3.90

3.80

6.20

6.00

5.80

5.00

4.90

4.80

0.10 M AX

0.05 NO M

3.81 REF

0.25

0.17

8°

0°

0.50

0.25

45°

COPLANARITY

0.10

1.04 REF

1.27 BSC

SEATING

PLANE

FO R P ROPE R CONNECT IO N O F

THE EXPOSED PAD, REFER TO

THE P IN CO NFIGURAT ION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.51

0.31

1.65

1.25

3.098

Figure 81. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

Data Sheet ADP7104

Rev. H | Page 25 of 25

ORDERING GUIDE

Model5F

Temperature

Range

Output

Voltage (V)6F

Package

Description

Package

Option Branding

ADP7104ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LH1

ADP7104ACPZ-1.5-R7 −40°C to +125°C 1.5 8-Lead LFCSP_WD CP-8-5 LK6

ADP7104ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-5 LK7

ADP7104ACPZ-2.5-R7 −40°C to +125°C 2.5 8-Lead LFCSP_WD CP-8-5 LKJ

ADP7104ACPZ-3.0-R7 −40°C to +125°C 3.0 8-Lead LFCSP_WD CP-8-5 LKK

ADP7104ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-5 LKL

ADP7104ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP_WD CP-8-5 LKM

ADP7104ACPZ-9.0-R7 −40°C to +125°C 9 8-Lead LFCSP_WD CP-8-5 LLD

ADP7104ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-1.5-R7

−40°C to +125°C

1.5

8-Lead SOIC_N_EP

RD-8-2

ADP7104ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-2.5-R7 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-3.0-R7 −40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2

ADP7104ARDZ-9.0-R7 −40°C to +125°C 9 8-Lead SOIC_N_EP RD-8-2

ADP7104CP-EVALZ 3.3 LFCSP Evaluation Board

ADP7104RD-EVALZ 3.3 SOIC Evaluation Board

ADP7104CPZ-REDYKIT LFCSP REDYKIT

ADP7104RDZ-REDYKIT SOIC REDYKIT

1 Z = RoHS Compliant Part.

2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

3 The ADP7104CP-EVALZ and ADP7104RD-EVALZ evaluation boards are preconfigured with a 3.3 V ADP7104.

registered trademarks are the property of their respective owners.

D09507-0-10/15(H)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Analog Devices Inc.:

ADP7104ARDZ-R7 ADP7104ACPZ-5.0-R7 ADP7104ARDZ-5.0-R7 ADP7104ARDZ-1.8-R7 ADP7104ACPZ-3.3-R7

ADP7104ACPZ-R7 ADP7104ARDZ-3.3-R7 ADP7104ACPZ-3.0-R7 ADP7104ACPZ-2.5-R7 ADP7104ACPZ-9.0-R7

ADP7104ARDZ-1.5-R7 ADP7104ACPZ-1.8-R7 ADP7104ARDZ-9.0-R7 ADP7104ARDZ-3.0-R7 ADP7104ACPZ-1.5-

R7 ADP7104ARDZ-2.5-R7