SI8900EDB-T1 - Vishay / Siliconix

Vishay Siliconix

Si8900EDB

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Bi-Directional N-Channel 20-V (D-S) MOSFET

FEATURES

• TrenchFET® Power MOSFET

• Ultra-Low RSS(on)

• ESD Protected: 4000 V

• MICRO FOOT® Chipscale Packaging

Reduces Footprint Area Profile (0.62 mm)

and On-Resistance Per Footprint Area

APPLICATIONS

• Battery Protection Circuit

- 1-2 Cell Li+/LiP Battery Pack for Portable Devices

PRODUCT SUMMARY

VS1S2 (V) RS1S2(on) (Ω)I

S1S2 (A)

0.024 at VGS = 4.5 V 7

0.026 at VGS = 3.7 V 6.8

0.034 at VGS = 2.5 V 5.0

0.040 at VGS = 1.8 V 5.5

MICRO FOOT

Device Marking:

8900E = P/N Code

xxx = Date/Lot Traceability Code

Bump Side View

G2G1

S1S1

310

S1S1

Backside View

8900E

xxx

Pin 1 Identifier

Ordering Information:

Si8900EDB-T2-E1 (Lead (Pb)-free)

N-Channel

4 kΩ

Notes:

a. Surface Mounted on 1" x 1" FR4 board.

b. The foot is defined as the top surface of the package.

c. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering.

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Source1- Source2 Voltage VS1S2 20 V

Gate-Source Voltage VGS ± 12

Continuous Source1- Source2 Current (TJ = 150 °C)aTA = 25 °C IS1S2

75.4

TA = 85 °C 5.1 3.9

Pulsed Source1- Source2 Current ISM 50

Maximum Power DissipationaTA = 25 °C PD

1.8 1 W

TA = 85 °C 0.9 0.5

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

Package Reflow ConditionscIR/Convection 260

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientat ≤ 5 s RthJA

55 70

°C/W

Steady State 95 120

Maximum Junction-to-FootbSteady State RthJF 12 15

RoHS

COMPLIANT

www.vishay.com

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

Vishay Siliconix

Si8900EDB

Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage VGS(th) VSS = VGS, ID = 1.1 mA 0.45 1.0 V

Gate-Body Leakage IGSS

VSS = 0 V, VGS = ± 4.5 V ± 4 µA

VSS = 0 V, VGS = ± 12 V ± 10 mA

Zero Gate Voltage Drain Current IS1S2

VSS = 20 V, VGS = 0 V 1µA

VSS = 20 V, VGS = 0 V, TJ = 85 °C 5

On-State Drain CurrentaIS(on) V

SS = 5 V, VGS = 4.5 V 5A

Source1- Source2 On State ResistanceaRS1S2(on)

VGS = 4.5 V, ISS = 1 A 0.020 0.024

VGS = 3.7 V, ISS = 1 A 0.022 0.026

VGS = 2.5 V, ISS = 1 A 0.026 0.034

VGS = 1.8 V, ISS = 1 A 0.032 0.040

Forward Transconductanceagfs VSS = 10 V, ISS = 1 A 31 S

Dynamicb

Tur n - O n D e l ay Time td(on)

VSS = 10 V, RL = 10 Ω

ISS ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω

µs

Rise Time tr4.5 7

Turn-Off Delay Time td(off) 55 85

Fall Time tf15 25

Gate-Current vs. Gate-Source Voltage

0 3 6 9 12 15

VGS

- Gate-to-Source Voltage (V)

- Gate Current (mA)IGSS

IGSS at 25 °C (mA)

Gate Current vs. Gate-Source Voltage

0.01

100

10 000

0.1

1000

VGS

- Gate-to-Source Voltage (V)

- Gate Current (I

GSS

µA)

0369 15

TJ = 25 °C

TJ = 150 °C

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Vishay Siliconix

Si8900EDB

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Output Characteristics

On-Resistance vs. Drain Current

On-Resistance vs. Gate-to-Source Voltage

01234

VGS = 5 thru 1.5 V

VDS

- Drain-to-Source Voltage (V)

- Drain Current (A)ID

1 V

0.00

0.01

0.02

0.03

0.04

0.05

0246810

- On-Resistance (Ω)R

DS(on)

- Drain Current (A)

VGS = 4.5 V

VGS = 2.5 V

VGS = 1.8 V

VGS = 3.7 V

0.00

0.02

0.04

0.06

0.08

0.10

012345

- On-Resistance (Ω)R

DS(on)

VGS

- Gate-to-Source Voltage (V)

IS1S2 = 1 A

IS1S2 = 5 A

Transfer Characteristics

On-Resistance vs. Junction Temperature

Threshold Voltage

0.0 0.2 0.4 0.6 0.8 1.0 1.2

25 °C

TC = 125 °C

- 55 °C

VGS

- Gate-to-Source Voltage (V)

- Drain Current (A)ID

0.6

0.8

1.0

1.2

1.4

1.6

- 50 - 25 0 25 50 75 100 125 150

TJ - Junction Temperature (°C)

VGS = 4.5 V

IS1S2 = 1 A

RDS(on) - On-Resistance

(Normalized)

- 0.4

- 0.3

- 0.2

- 0.1

0.0

0.1

0.2

- 50 - 25 0 25 50 75 100 125 150

Variance (V)VGS(th)

TJ - Temperature (°C)

IS1S2 = 1.1 mA

www.vishay.com

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

Vishay Siliconix

Si8900EDB

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Single Pulse Power, Junction-to-Ambient

Power (W)

Time (s)

1 1000100.10.01

100

Normalized Thermal Transient Impedance, Junction-to-Ambient

10-310-21 10 60010-1

10-4100

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 95 °C/W

3. T JM - TA = PDMZthJA(t)

Notes:

4. Surface Mounted

PDM

Normalized Thermal Transient Impedance, Junction-to-Foot

10-310-2110-1

10-4

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Vishay Siliconix

Si8900EDB

PACKAGE OUTLINE

MICRO FOOT: 10-BUMP (2 x 5, 0.8 mm PITCH)

Notes (Unless Otherwise Specified):

1. Laser mark on the silicon die back, coated with a thin metal.

2. Bumps are 95.5Sn/3.8Ag/0.7Cu.

3. Non-solder mask defined copper landing pad.

Notes:

a. Use millimeters as the primary measurement.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see http://www.vishay.com/ppg?71830.

Recommended Land

Mark on Backside of Die

10 x ∅ 0.30 ~ 0.31

Note 3

Solder Mask ∅ ~ 0.40

8900E

xxx

b Diamerter

S1e

Bump Note 2

Silicon

Dim. MillimetersaInches

Min. Max. Min. Max.

A 0.600 0.650 0.0236 0.0256

A1 0.260 0.290 0.102 0.0114

A2 0.340 0.360 0.0134 0.0142

b 0.370 0.410 0.0146 0.0161

D 4.050 4.060 0.1594 0.1598

E 1.980 2.000 0.0780 0.0787

e 0.750 0.850 0.0295 0.0335

S10.430 0.450 0.0169 0.0177

S2 0.580 0.600 0.0228 0.0236

Legal Disclaimer Notice

www.vishay.com Vishay

Revision: 08-Feb-17 1Document Number: 91000

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