SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 – JUNE 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D
Extended Temperature Performance of
–55°C to 125°C
D
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
Enhanced Product-Change Notification
D
Qualification Pedigree
D
EPIC (Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
description/ordering information
The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance
memory-decoding and data-routing applications that require very short propagation-delay times. In
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
55
°
Cto125
°
C
SOIC – D Tape and reel SN74AHCT138MDREP AHCT138MEP
55°C
to
125°C
TSSOP – PW Tape and reel SN74AHCT138MPWREP AT138EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
D OR PW PACKAGE
(TOP VIEW)
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
H L L H H H H H H H H H H L
logic symbols (alternatives)
BIN/OCT
1
1
A
2
2
B
4
3
C
4
5
6
G1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
DMUX
0
1
A2
B
2
3
C
4
5
6
G1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
G7
0
G2A
G2B
G2A
G2B
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
G1
G2B
G2A
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
4
5
6
15
14
13
12
11
10
9
7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
IOH High-level output current 8 mA
IOL Low-level output current 8 mA
t/vInput transition rise or fall rate 20 ns/V
TAOperating free-air temperature 55 125 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX
MIN
MAX
UNIT
VOH
IOH = 50
m
A
45V
4.4 4.5 4.4
V
V
OH IOH = 8 mA
4
.
5
V
3.94 3.8
V
VOL
IOL = 50
m
A
45V
0.1 0.1
V
V
OL IOL = 8 mA
4
.
5
V
0.36 0.5
V
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1
m
A
ICC VI = VCC or GND, IO = 0 5.5 V 4 40
m
A
ICCOne input at 3.4 V,
Other inputs at VCC or GND 5.5 V 1.35 1.5 mA
CiVI = VCC or GND 5 V 2 10 pF
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX
MIN
MAX
UNIT
tPLH
ABC
Any Y
CL=15
p
F
7.6 10.4 1 12
ns
tPHL
A
,
B
,
C
Any
Y
C
L =
15
pF
7.6 10.4 1 12
ns
tPLH
G1
Any Y
CL=15
p
F
6.6 9.1 1 10.5
ns
tPHL
G1
Any
Y
C
L =
15
pF
6.6 9.1 1 10.5
ns
tPLH
G2A G2B
Any Y
CL=15
p
F
7 9.6 1 11
ns
tPHL
G2A
,
G2B
Any
Y
C
L =
15
pF
7 9.6 1 11
ns
tPLH
ABC
Any Y
CL=50
p
F
8.1 11.4 1 13
ns
tPHL
A
,
B
,
C
Any
Y
C
L =
50
pF
8.1 11.4 1 13
ns
tPLH
G1
Any Y
CL=50
p
F
7.1 10.1 1 11.5
ns
tPHL
G1
Any
Y
C
L =
50
pF
7.1 10.1 1 11.5
ns
tPLH
G2A G2B
Any Y
CL=50
p
F
7.5 10.6 1 12
ns
tPHL
G2A
,
G2B
Any
Y
C
L =
50
pF
7.5 10.6 1 12
ns
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC VOL + 0.3 V
50% VCC 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
BIN/OCT
1
1
A0
2
2
A1
4
3
A3
4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHCT138
VCC
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHCT138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHCT138
A2
A4
Figure 2. 24-Bit Decoding Scheme
SN74AHCT138-EP
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCLS491 JUNE 2003
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
VCC
BIN/OCT
1
1
A0
2
2
A1
4
3
A3 4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHCT138
A2
A4
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHCT138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHCT138
BIN/OCT
1
1
2
2
4
3
4
5
6
24
15
0
&
EN
25
14
1
26
13
2
27
12
3
28
11
4
29
10
5
30
9
6
31
7
7
SN74AHCT138
Figure 3. 32-Bit Decoding Scheme
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHCT138MDREP SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AHCT138MPWREP TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT138MDREP SOIC D 16 2500 333.2 345.9 28.6
SN74AHCT138MPWREP TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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SN74AHCT138MDREP SN74AHCT138MPWREP V62/03655-01XE V62/03655-01YE