1/37October 2005
M25PE20
M25PE10
1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories
with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out
FEATURES SUMMARY
■Industrial Standard SPI Pin-out
■1 or 2 Mbit of Page-Erasable Flash Memory
■Page Write (up to 256 Byt es) in 11ms (typica l)
■Page Program (up to 256 Bytes) in 1.2ms
(typical)
■Page Erase (256 By tes) in 10 m s (typical)
■Sector Erase (512 Kbit)
■2.7 to 3.6V Single Supply Voltage
■SPI Bus Compatible Serial Interface
■33MHz Clock Rate (maximum)
■Deep Power-down Mode 1µA (typical)
■Electronic Signature
– JEDEC Standard Two-Byte Signature
(8012h for M25PE20
8011h for M25PE10)
■More than 100,000 Write Cycles
■More than 20 Year Data Retention
■Hardware Write Protection of the Top Sector
(64KB)
■Packages
– ECOPACK® (RoHS compliant)
Figure 1. Pack ag e s
VDFPN8 (MP)
6x5mm (MLP8)
8
1
SO8N (MN)
150 mil width
M25PE10, M25PE20
2/37
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/37
M25PE10, M25PE20
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
M25PE10, M25PE20
4/37
SUMMARY DESCRIPTION
The M25PE20 and M2 5PE10 are 2 Mbit (256 K x 8
bit) and 1 Mbit (128K x8 bit) Serial Paged Flash
Memories, respectively. They are accessed by a
high speed SPI- co m pa tib le bu s.
The memories can be written or programmed 1 to
256 Bytes at a time, u sing the Page Wr ite or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle fol-
lowed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors,
each containing 256 pages. Each page is 256
Bytes wide. Thus, the whole memory can be
viewed as consisting of 1024 pages, or 262,144
Bytes.
The M25PE10 memory is organized as 2 sectors,
each containing 256 pages. Each page is 256
Bytes wide. Thus, the whole memory can be
viewed as consisting of 512 pages, or 131, 072
Bytes.
The memories can be erased a p age at a time, us-
ing the Page Erase instruction, or a sector at a
time, using the Sector Erase instruction.
The top sector of the memories can be Write Pro-
tected by Hardwa re (TSL).
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
Table 1. Signal Names
Figure 3. VDFPN AND SO Connections
Note: 1. There is an exposed die p addle on the unde rside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be al lowed to be connecte d to any oth er voltage
or signal li ne on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
Reset
AI09713
S
VCC
M25PE20
M25PE10
VSS
TSL
Q
C
D
C Serial Clock
D Serial Data Input
Q Serial Data Output
SChip Select
TSL Top Sector Lock
Reset Reset
VCC Supply Voltage
VSS Ground
1
AI09715
2
3
4
8
7
6
5DVSS C
ResetQ
SV
CC
TSL
M25PE20
M25PE10
5/37
M25PE10, M25PE20
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data ser ially into the device. It rece ives in-
structions, addresses, and the data to be pro-
grammed. Values a re latched on the rising e dge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high imped ance. Unless an internal Read ,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is
not the Deep Power-down mode). Driving Chip
Select (S) Low selects the device, placing it in the
Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory.
When Reset ( Reset) is driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter the Reset
mode. In this mode, the o utput is high impedance.
Driving Reset (Reset) Low while an internal oper-
ation is in progress will affect this operation (write,
program or erase cycle) and data may be lost.
Top Sector Lo c k (TSL). This input signal puts
the device in the Har dware Protected mode, when
Top Sector Lock ( TSL) is connecte d to VSS, caus-
ing the top 256 pages (upper addresses) of the
memory to become read-only (protected from
write, program and erase operations).
When Top Sector Lock (TSL ) is connected to VCC,
the top 256 pages of memory behave like the other
pages of memory.
M25PE10, M25PE20
6/37
SPI MODES
These de vices can be driv en by a micro controller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference bet ween th e two mod es, as shown
in Figure 5., is the clock polarity when the bus
master is in Standby mode and not transferring da-
ta:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
Note: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
AI10741B
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
TSL RP TSL RP TSL RP
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
7/37
M25PE10, M25PE20
OPERATING FEATURES
Sharing the Overhead of Modifying Data
To write or prog ram one (or more) dat a Bytes, two
instructions are required: Write Enable (WREN),
which is one Byte, and a Page Writ e (PW) or Page
Program (PP) sequence, which consists of four
Bytes plus data. This is followed by the internal cy-
cle (of duration tPW or tPP).
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
Bytes to be programmed (changing bits from 1 to
0) or written (changing bits to 0 or 1) at a time, pro-
vided that they lie in consecutive addresses on the
same page of memory.
An Easy Way to Modify Data
The Page Write (PW) instruction provides a con-
venient way of modifying data (up to 256 contigu-
ous Bytes at a time), and simply requires the start
address, and the new data in the instruction se-
quence.
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, and then transmitting
the instruction Byte, thr ee address Bytes (A23-A0)
and at least one data Byte, and then driving Chip
Select (S) High. While Chip Select (S) is being
held Low, the data Bytes are written to the data
buffer, star ting at the ad dress given in the th ird ad-
dress Byte (A7-A0). When Chip Select (S) is driv-
en High, the Write cycle starts. The remaining,
unchanged, Bytes of the data buffer are automati-
cally loaded with the values of the corresponding
Bytes of the addressed memory page. The ad-
dressed memory page then automatically put into
an Erase cycle. Finally, the addressed memory
page is programmed with the contents of the data
buffer.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of being able to alter the contents of the
memory on a Byte-by-Byte basis.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes (see Page
Write (PW) and AC Characteristics (33MHz oper-
ation)).
A Fast Way to Modify Data
The Page Program (PP) instruction provides a fast
way of modif ying data (up to 256 co ntiguous Bytes
at a time), provided that it only involves resetting
bits to 0 that had previously been set to 1.
This might be:
– when the designer is programming the device
for the first time
– when the designer knows that the page has
already been erased by an earlier Page Erase
(PE) or Sector Erase (SE) instruction. This is
useful, for example, when storing a fast
stream of data, having first performed the
erase cycle when time was availabl e
– when the designer knows that the only
changes involve resetting bits to 0 that are still
set to 1. When this method is possible , it has
the additional advantage of minimising the
number of unnecessary erase operations, and
the extra stress incurred by each page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Page Program (PP) and AC Characteristics
(33MHz operation)).
Polling Durin g a Write, Program or Erase Cyc le
A further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (tPW, tPP, tPE, or tSE). The Write
In Progress (WIP) bit is provided in the Status
Register so that th e application pro gram can mon-
itor its value, polling it to establish when the previ-
ous cycle is complete.
Reset
An internal Power-On Reset circuit helps protect
against inadvertent data writes. Addition protec-
tion is provided by driving Reset (Reset) Low dur-
ing the Power-on process, and only driving it High
when VCC has reached the correct voltage level,
VCC(min).
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode.
When Chip Select (S) is High, the device is dese-
lected, but could r emain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) in-
struction) is executed. The device consumption
drops further to ICC2. The device remains in this
mode until the Release from Deep Power-down in-
struction is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in a ctive use , to pro tect the
M25PE10, M25PE20
8/37
device from inadvertent Write, Program or Erase
instructions.
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the me mory is busy with a Write, Program
or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the st atus of the internal Writ e Enable Latch.
Table 2. Status Register Format
Note: WEL and WIP are volatile read -o nly bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correc tly in the presence of excessive
noise. To help combat this, the M25PE10 and
M25PE20 feature the following data protection
mechanisms:
■Power On Reset and an internal timer (tPUW)
can provide protection ag ainst inadvertent
changes while the power supply is outside the
operating specification.
■Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution.
■All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set th e Writ e En ab le La tc h
(WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Reset (RESET) driven Low
– Write Disable (WRDI) instruction comple-
tion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
■The Hardware Prot ected mode is entere d
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory
■The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time , not just during Power-up and
Power-down.
■In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software prot ection from inadvertent
Write, Program and Erase instructions while
the device is not in active use.
b7 b0
0 0 0 0 0 0 WEL WIP
9/37
M25PE10, M25PE20
MEMORY ORGANIZATION
The M25PE20 memory is organized as:
■1024 pages (256 Bytes each).
■262,144 Bytes (8 bits each)
■4 sectors (512 Kbits, 65536 Bytes each)
The M25PE10 memory is organized as:
■512 pages (256 Bytes each).
■131,074 Bytes (8 bits each)
■2 sectors (512 Kbits, 65536 Bytes each)
In the M25PE20 an d M25PE10, each page can be
individually:
– programmed (bits are programmed from 1 to
0)
– erased (bits are erased from 0 to 1)
– written (bits are changed to either 0 or 1)
The device is Page or Sector Erasable (bits are
erased from 0 to 1).
Table 3. M25PE20 Memory Organization
Table 4. M25PE10 Memory Organization
Sector Address Range
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
Sector Address Range
1 10000h 1FFFFh
0 00000h 0FFFFh
M25PE10, M25PE20
10/37
Figure 6. M25PE20 Block Diagram
AI07402
S
TSL Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
3FFFFh
000FFh
Reset
2FFFFh
Top 256 Pages can
be made read-only
3FF00h
11/37
M25PE10, M25PE20
Figure 7. M25PE10 Block Diagram
AI10814
S
TSL Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
1FFFFh
000FFh
Reset
FFFFh
Top 256 Pages can
be made read-only
1FF00h
M25PE10, M25PE20
12/37
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significan t bi t firs t.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-Byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-Byte
instruction code. Depending on the instruction,
this might be followed by address Bytes, or by data
Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast _Read) or Re ad
Status Register (RDSR) in struction, the shifted-in
instruction sequence is followed by a da ta-ou t se-
quence. Chip Select (S) can be driven High after
any bit of the data-out sequence is being shifted
out.
In the case of a Page Write (PW), Page Program
(PP), Page Erase (PE), Sector Erase (SE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven High exactly at a Byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses afte r Chip Select (S) b eing
driven Low is an exact multiple of eight.
All attempts to ac cess the memory arr ay during a
Write cycle, Program cycle or Erase cycle are ig-
nored, and th e internal Wr ite cycle, Progr am cycle
or Erase cycle continues unaffected.
Table 5. Instruction Set
Instruction Description One-Byte Instruction Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PW Page Write 0000 1010 0Ah 3 0 1 to 256
PP Page Program 0000 0010 02h 3 0 1 to 256
PE Page Erase 1101 1011 DBh 3 0 0
SE Sector Erase 1101 1000 D8h 3 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDP Release from Deep Power-down 1010 1011 ABh 0 0 0
13/37
M25PE10, M25PE20
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable La tch (WEL) bit.
The Write Enable La tch ( WEL) bit must be set pri-
or to every Page Wr ite ( PW) , Page Pr ogr am (PP),
Page Erase (PE), and Sector Erase (SE) instruc-
tion.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 8. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and th en driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–Power-up
– Write Disable (WRDI) instruction completion
– Page Writ e (PW) instruction comple tio n
– Page Program (PP) instr uction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
Figure 9. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25PE10, M25PE20
14/37
Read Identification (RDID)
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two Bytes of device identification. The
manufacturer identifica tion is assigned by JEDEC,
and has the va lue 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first Byte (80h), and the memory capacity of
the device in the second Byte (12h for the
M25PE20 and 11h for the M25PE10).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
The device is first select ed by driving Chip Select
(S) Low. Then, t he 8-bit instruct ion code for t he in-
struction is shifted in. This is followed by the 24-bit
device identification, stored in the memory, being
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 10..
The Read Identification (RDID) instruction is termi-
nated by driving Chip Select (S) High at any time
during data output.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Table 6. Read Identification (RDID) Data-Out Sequence
Figure 10. Read Identificat ion (RDID) Instruction Sequence and Data-Out Sequence
Manufacturer Identification Device Identification
Memory Type Memory Capacity
20h 80h 12h (M25PE20)
20h 80h 11h (M25PE10)
C
D
S
21 3456789101112131415
Instruction
0
AI06809
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 16 18 28 29 30 31
15/37
M25PE10, M25PE20
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 11.
The status bits of the Status Register are as fol-
lows:
WIP bit. The Write In Progress (WIP) bit indicat es
whether the m emory is busy with a Write, Prog ram
or Erase cycle. When set to 1, such a cycle is in
progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status o f the internal Write Enable Lat ch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write, Program or Erase instruction
is accepted.
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequ ence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M25PE10, M25PE20
16/37
Read Data Bytes (READ)
The device is first selec ted by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-Byte
address (A23-A0) , each bit being latched-in d uring
the rising edge o f Serial Clock (C). Then t he mem-
ory contents, at that addr ess, is sh ift ed out on Se -
rial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first Byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each Byte of data is shift-
ed out. The wh ole memory can, therefore, be r ead
with a single Read Data Bytes (READ) instruction.
When the highe st address is reached, the addr ess
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time dur ing data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any e ffects on
the cycle that is in prog re ss .
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bit s A23 to A17 are Don’t Care in the M25 P E10.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
17/37
M25PE10, M25PE20
Read Data Bytes at Higher Speed
(FAST_READ)
The device is first selec ted by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-Byte address (A23-A0) and a
dummy Byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each Byte of data is shift-
ed out. The wh ole memory can, therefore, be r ead
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is termin at ed b y driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Seque nce
and Data-Out Sequence
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bit s A23 to A17 are Don’t Care in the M25 P E10.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
M25PE10, M25PE20
18/37
Page Write (PW)
The Page Write (PW) instruction allows Bytes to
be written in th e memo ry. Bef ore it can be accept -
ed, a Write Enable (WREN) instructio n must previ-
ously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable La tch (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Dat a Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
The Page Write (PW) instruction performs a page
erase cycle even if only one Byte is updated.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitt ed data exceeding the ad-
dressed page boundary roll over, and are written
from the start address of the same page (the one
whose 8 least significant address bits (A7-A0) are
all zero). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 Byt es are sent to t he device, pre-
viously latched data are discarded and the last 256
data Bytes are guaranteed to be written correctly
within the sam e pa ge . If less th an 25 6 Data Bytes
are sent to device, they are corre ctly writt en at the
requested addresses without having any effects
on the other Bytes of the same page.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes (see AC
Characteristics (33MHz operation)).
Chip Select (S) must be driven High after the
eighth bit of the last da ta Byte has been latched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Write cycle (whose duration is tPW) is
initiated. While the Page Write cycle is in progress,
the Status Register may be read to check the val-
ue of the Write In Prog re ss ( WIP) bit . The Wr ite In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecifie d time before the cycle is com plete, the
Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Write (PW) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figure 14. Page Write (PW) Instruction Sequence
Note: 1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
2. 1 ≤ n ≤ 256
C
D
AI04045
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte n
765432 0
1
MSB MSB
MSB MSB MSB
19/37
M25PE10, M25PE20
Page Program (PP)
The Page Program (PP) instruction allows Bytes
to be programmed in the memory (changing bits
from 1 to 0, only). Before it can be accepted, a
Write Enable (WREN) instruction must previously
have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable La tch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are pro-
grammed from th e start address of the sam e page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration o f the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 Byt es are sent to t he device, pre-
viously latched data are discarded and the last 256
data Bytes are guar anteed to be program med cor-
rectly within the same page. If less than 256 Data
Bytes are sent to device, they are correctly pro-
grammed at the r equested addresses without hav-
ing any effects on the other Bytes of the same
page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see AC Characteristics (33MHz operation)).
Chip Select (S) must be driven High after the
eighth bit of the last da ta Byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of t he Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effe cts on the cycle th at
is in progress.
Figure 15. Page Program (PP) Instruction Sequence
Note: 1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
2. 1 ≤ n ≤ 256
C
D
AI04044
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte n
765432 0
1
MSB MSB
MSB MSB MSB
M25PE10, M25PE20
20/37
Page Erase (PE)
The Page Erase (PE) instr uction sets to 1 (FFh) all
bits inside the chosen page. Before it can be ac-
cepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address Bytes on Serial
Data Input (D). Any address inside the Page is a
valid addres s for the Pa ge Er ase (PE) in structio n.
Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
latched in, otherwise t he Page Erase (PE) instruc-
tion is not executed. As so on as Ch ip Select ( S ) is
driven High, the self-timed Page Erase cycle
(whose duration is tPE) is initiated. While the Page
Erase cycle is in progress, the Status Register
may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Page Erase cycle, and
is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Erase (PE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figure 16. Page Erase (PE) Instruction Sequence
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bit s A23 to A17 are Don’t Care in the M25 P E10.
24 Bit Address
C
D
AI04046
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
21/37
M25PE10, M25PE20
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instr uction has been decod-
ed, the device sets the Write Enab le Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address Bytes on Serial
Data Input (D). Any address inside the Sector ( see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the se quence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
latched in, otherwise the Sector Erase (SE) in-
struction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Sector Erase cy-
cle (whose duration is tSE) is initiated. While the
Sector Erase cycle is in progress, the Status Reg-
ister may be read to check the value of th e Write
In Progress (WIP) bit . The Write In Progress (WIP)
bit is 1 during the self-timed Sector Erase cycle,
and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Sector Erase (SE) instru ction applied to a sector
that contains a pa ge that is Hardware Protected is
not executed.
Any Sector Erase (SE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figure 17. Sector Erase (SE) Instruction Sequence
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bit s A23 to A17 are Don’t Care in the M25 P E10.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25PE10, M25PE20
22/37
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only wa y to put the device in the lowe st con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, w hile the device is not in active us e,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in Standby Power mode (if
there is no internal cycle currently in progress). But
this mode is n ot the Deep Po wer-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
ICC1 to ICC2, as specified in Tabl e 12.).
Once the device has entered the Deep Power-
down mode, all instruction s are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. This relea se s th e de vice fro m this mo d e.
The Deep Power-down mode automatically stops
at Power-do wn, and the device always Power s-up
in Standby Power mod e.
The Deep Power-do wn (DP) in structio n is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 18.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise th e Deep Power-down (DP) instruc-
tion is not executed. As so on as Ch ip Select ( S ) is
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effe cts on the cycle th at
is in progress.
Figure 18. Deep Power-down (DP) Instruction Sequence
C
D
AI03753D
S
21 345670t
DP
Deep Power-down Mode
Standby Power Mode
Instruction
23/37
M25PE10, M25PE20
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-
down mode, all instruction s are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. Executing this instruction takes the device out
of the Deep Power-down mode.
The Release from Deep Power-down (RDP) in-
struction is entered by driving Chip Select (S) Low,
followed by the instruct ion code on Serial Data In-
put (D). Chip Select (S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 19.
The Release from Deep Power-down (RDP) in-
struction is terminated by driving Chip Select (S)
High. Sending additional clock cycles on Serial
Clock (C), while Chip Select (S) is driven Low,
cause the instruction to be rejected, and not exe-
cuted.
After Chip Select (S) has been driven High,
followed by a delay, tRDP, the device is put in
Standby Power mode. Chip Select (S) must
remain High at least until this period is over. The
device waits to be selected, so that it can receive,
decode and execute inst ructions.
Any Release from Deep Power-down (RDP) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 19. Release from Deep Power-down (RDP) Instruction Sequence
C
D
AI06807
S
21 345670tRDP
Standby Power Mode
Deep Power-down Mode
QHigh Impedance
Instruction
M25PE10, M25PE20
24/37
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selecte d (that is Chip Select (S) must follow
the voltage applied on VCC) until VCC reaches the
correct value:
–V
CC(min) at Power-up, and t hen for a further
delay of tVSL
–V
SS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption an d inadve rtent writ e op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while VCC is less than the Power
On Reset (POR) threshold value, VWI – all opera-
tions are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
tions until a time delay of tPUW has elapsed after
the moment that VCC rises above the VWI thresh-
old. However, the correct operation of the device
is not guaranteed if, by this time, VCC is still below
VCC(min). No Write, Program or Erase instructions
should be sent until the later of:
–t
PUW after VCC passed the VWI threshold
–t
VSL after VCC passed the VCC(min) level
These values are specified in Table 7.
If the delay, tVSL, has elapsed, aft er VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
As an extra protection, the Reset (Reset) signal
could be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the device is in the following state:
– The device is in the Standby Power mode (not
the Deep Power-down mode).
– The Write Enab le La tc h (WE L) bit is rese t.
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Each de-
vice in a system should have th e VCC rail dec ou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1 µF).
At Power-down , when VCC drops from the opera t-
ing voltage, to below the Power On Reset (POR)
threshold voltage, VWI, all operations are disa bled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 20. Power-up Timing
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
25/37
M25PE10, M25PE20
Table 7. Power-Up Timing and VWI Threshold
Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each Byte contains
FFh). All usable Status Register bits are 0.
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Rat ings
Note: 1. Compliant wi th JED EC St d J-STD -020 C (for smal l body , Sn- Pb or Pb as sembl y), the ST E COPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
tVSL1VCC(min) to S low 30 µs
tPUW1Time delay before the first Write, Program or Erase instruction 1 10 ms
VWI1Write Inhibit Voltage 1.5 2.5 V
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
M25PE10, M25PE20
26/37
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the devices. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions
Table 10. AC Measurement Conditions
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC Measurement I/O Waveform
Table 11. Capacitance
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Temperature –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V
Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
27/37
M25PE10, M25PE20
Table 12. DC Characteristics
Symbol Parameter Test Condition
(in addition to those in Table 9.)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current
(Standby and Reset modes) S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA
ICC3 Operating Current (FAST_READ) C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open 6mA
C = 0.1VCC / 0.9.VCC at 33 MHz, Q = open 8
ICC4 Operating Current (PW) S = VCC 15 mA
ICC5 Operating Current (SE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µAV
CC–0.2 V
M25PE10, M25PE20
28/37
Table 13. AC Characteristics (25MHz operation)
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256)
Test conditions specified in Table 9. and Table 10.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Frequency for the following
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
RDSR
D.C. 25 MHz
fRClock Frequency for READ
instructions D.C. 20 MHz
tCH (1) tCLH Clock High Time 18 ns
tCL (1) tCLL Clock Low Time 18 ns
Clock Slew Rate 2 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 5 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 10 ns
tSHCH S Not Activ e Setup Time (relativ e to C) 10 ns
tSHSL tCSH S Deselect Time 200 ns
tSHQZ (2) tDIS Output Disable Time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold Time 0 ns
tTHSL Top Sector Lock Setup Time 50 ns
tSHTL Top Sector Lock Hold Time 100 ns
tDP (2) S to Deep Power-down 3 µs
tRDP (2) S High to Standby Power Mode 30 µs
tPW (3) Page Write Cycle Time (256 Bytes) 11 25 ms
Page Write Cycle Time (n Bytes) 10.2 +
n*0.8/256
tPP (3) P age Program Cycle Time (256 Bytes) 1.2 5ms
Page Program Cycle Time (n Bytes) 0.4 +
n*0.8/256
tPE Page Erase Cycle Time 10 20 ms
tSE Sector Erase Cycle Time 1 5 s
29/37
M25PE10, M25PE20
Table 14. AC Characteristics (33MHz operation)
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256)
4. Details of how to find the date of marking are given in Application Note, AN1995.
33MHz only available for products marked since week 40 of 2005(4)
Test conditions specified in Table 9. and Table 10.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Frequency for the following
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
RDSR
D.C. 33 MHz
fRClock Frequency for READ
instructions D.C. 20 MHz
tCH (1) tCLH Clock High Time 13 ns
tCL (1) tCLL Clock Low Time 13 ns
Clock Slew Rate 2 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 3 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 n s
tSHCH S Not Activ e Setup Time (relativ e to C) 5 ns
tSHSL tCSH S Deselect Time 200 ns
tSHQZ (2) tDIS Output Disable Time 12 ns
tCLQV tVClock Low to Output Valid 12 ns
tCLQX tHO Output Hold Time 0 ns
tTHSL Top Sector Lock Setup Time 50 ns
tSHTL Top Sector Lock Hold Time 100 ns
tDP (2) S to Deep Power-down 3 µs
tRDP (2) S High to Standby Power mode 30 µs
tPW (3) Page Write Cycle Time (256 Bytes) 11 25 ms
Page Write Cycle Time (n Bytes) 10.2+
n*0.8/256
tPP (3) Page Program Cycle Time (256 Bytes) 1.2 5ms
Page Program Cycle Time (n Bytes) 0.4+
n*0.8/256
tPE Page Erase Cycle Time 10 20 ms
tSE Sector Erase Cycle Time 1 5 s
M25PE10, M25PE20
30/37
Figure 22. Serial Input Timing
Figure 23. Top Sector Lock Setup and Hold Timing
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
TSL
tTHSL tSHTL
AI07439c
31/37
M25PE10, M25PE20
Figure 24. Output Timing
C
Q
AI01449D
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25PE10, M25PE20
32/37
Table 15. Reset Timings
Note: 1. Value guaranteed by characterization, not 100% tested in production.
Figure 25. Reset AC Waveforms
Test conditions specified in Table 9. and Table 10.
Symbol Alt. Parameter Conditions Min. Typ. Max. Unit
tRLRH (1) tRST Reset Pulse Width 10 µs
tRHSL tREC Reset Recovery Time
after any oper ation except
for PW, PP, PE and SE 30 µs
After PW, PP and PE
operations 25 ms
After SE operations 5 s
tSHRH Chip Select High to
Reset High
Chip should have been
deselected before Reset is
de-asserted 10 ns
AI06808
Reset tRLRH
S
tRHSLtSHRH
33/37
M25PE10, M25PE20
PACKAGE MECHANICAL
Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline
Note: Drawing is not to scale.
Table 16. MLP8, 8-lead Very thin Dual Flat Package No lea d , 6x5mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ12° 12°
D
E
VDFPN-01
A2
A
A3
A1
E1
D1
eE2
D2
L
b
θ
M25PE10, M25PE20
34/37
Figure 27. SO8 Narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
Note: Drawing is not to scale.
Table 17. SO8 Narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
ddd 0.10 0.004
E 3.80 4.00 0.150 0.157
e1.27– –0.050– –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
a0808
N8 8
SO-A
E
8
ddd
Be
A
D
C
LA1 α
1
H
h x 45˚
A2
35/37
M25PE10, M25PE20
PART NUMBERING
Table 18. Ordering Information Scheme
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
The category of second Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standar d JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
Example: M25PE20 – V MP 6 T G
Device Type
M25PE = Page-Erasable Serial Flash Memory
Device Function
10 = 1 Mbit (128K x 8)
20 = 2 Mbit (256K x 8)
Operating Vo ltage
V = VCC = 2.7 to 3.6V
Package
MN = SO8N (150 mil width)
MP = VDFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
M25PE10, M25PE20
36/37
REVISION HISTORY
Table 19. Document Revision History
Date Version Description of Revision
07-Dec-2004 0.1 Document written
21-Dec-2004 0.2 Notes 1 and 2 remov ed from Table 18., Ordering Information Scheme. S08N silhouette
corrected in Figure 1., Packages.
6-Oct-2005 1.0
Added Table 14., AC Characteristics (33MHz operation). Document status promoted
to full Datasheet. An Easy Way to Modify Data, A Fast Way to Modify Data, Page Write
(PW) and Page Program (PP) sections updated to explain optimal use of Page Write
and Page Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated Table 18., Ordering Information Scheme. Added Ecopack® information.
37/37
M25PE10, M25PE20
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of use of su ch information nor for an y infringement of patents or other rights of third parties which may result f rom its use. No lic ense is granted
by implicatio n o r otherwise u nder any patent or pa ten t r ig hts o f STMicroelectron ics . Sp ec ifications mentio ne d in this public at ion are subject
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