EVALUATION KIT AVAILABLE MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access General Description Benefits and Features The MAX11321-MAX11328 are 12-/10-bit with external reference and 500kHz, full-linear-bandwidth, high-speed, low-power, serial-output successive approximation register (SAR) analog-to-digital converters (ADCs). The MAX11321-MAX11328 provide external access to the output of the integrated mux and ADC input, to simplify conditioning. The MAX11321-MAX11328 include both internal and external clock modes. These devices feature scan mode in both internal and external clock modes. The internal clock mode features internal averaging to increase SNR. The external clock mode features the SampleSetK technology, a user-programmable analog input channel sequencer. The SampleSet approach provides greater sequencing flexibility for multichannel applications while alleviating significant microcontroller or DSP (controlling unit) communication overhead. S Scan Modes, Internal Averaging, and Internal Clock S 16-Entry First-In/First-Out (FIFO) S SampleSet: User-Defined Channel Sequence with Maximum Length of 256 S Input Pins Any Combination of Single-Ended, Differential and Pseudo-Differential Pairs Allowed S Analog Multiplexer with True Differential Track/Hold 16-/8-/4-Channel Single-Ended 12-/8-/4-Channel Fully-Differential Pairs 15-/8-/4-Channel Pseudo-Differential Relative to a Common Input S Externally Accessible Multiplex Output and ADC Input S Two Software-Selectable Bipolar Input Ranges QVREF+/2, QVREF+ S Flexible Input Configuration Across All Channels S High Accuracy Q1 LSB INL, Q1 LSB DNL, No Missing Codes S 70dB SINAD Guaranteed at 100kHz Input Frequency S 1.5V to 3.6V Digital I/O Supply Voltage S 2.35V to 3.6V Supply Voltage S Extended Battery Life for Portable Applications 5.4mW at 1Msps with 3V Supplies 2A Full-Shutdown Current S External Differential Reference (1V to VDD) S 16MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSPCompatible Serial Interface S Wide -40NC to +125NC Operation S Space-Saving, 32-Pin, 5mm x 5mm TQFN Packages S 1Msps Conversion Rate, No Pipeline Delay External pins provide access to the output of the multiplexer and ADC inputs to simplify multichannel signal conditioning. The internal clock mode features an integrated FIFO allowing data to be sampled at high speeds and then held for readout at any time or at a lower clock rate. Internal averaging is also supported in internal clock mode improving SNR for noisy input signals. The devices feature analog input channels that can be configured to be single-ended inputs, fully differential pairs, or pseudodifferential inputs with respect to one common input. The MAX11321-MAX11328 operate from a 2.35V to 3.6V supply and consume only 5.4mW at 1Msps. The MAX11321-MAX11328 include AutoShutdownK, fast wake-up, and a high-speed 3-wire serial interface. The devices feature full power-down mode for optimal power management. The 48MHz, 3-wire serial interface directly connects to SPI, QSPIK, and MICROWIREM devices without external logic. Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and small space. Applications High-Speed Data Acquisition Systems The MAX11321-MAX11328 are available in 32-pin, 5mm x 5mm, TQFN packages and operate over the -40NC to +125NC temperature range. High-Speed Closed-Loop Systems SampleSet and AutoShutdown are trademarks of Maxim Battery-Powered Instruments Integrated Products, Inc. QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. Ordering Information appears at end of data sheet. Industrial Control Systems Medical Instrumentation Portable Systems For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX11321-MAX11328.related. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 19-6467; Rev 0; 9/12 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ABSOLUTE MAXIMUM RATINGS VDD to GND..............................................................-0.3V to +4V AOP, AON, AIP, AIN, OVDD, AIN0-AIN13, CNVST/AIN14, REF+, REF-/AIN15 to GND........................................ -0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, DIN, DOUT, EOC TO GND........-0.3V to the lower of (VOVDD + 0.3V) and +4V DGND to GND.......................................................-0.3V to +0.3V Input/Output Current (all pins)............................................50mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 34.4mW/NC above +70NC)..................2758mW Operating Temperature Range......................... -40NC to +125NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (BJA)............29NC/W Junction-to-Case Thermal Resistance (BJC)................1.7NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1.0 LSB DC ACCURACY (Notes 3 and 4) Resolution RES Integral Nonlinearity INL Differential Nonlinearity DNL 12 bit 12 No missing codes Offset Error Gain Error Bits (Note 5) Q1.0 LSB 1.2 Q3.0 LSB 0.02 Q5.5 LSB Offset Error Temperature Coefficient OETC Q2 ppm/NC Gain Temperature Coefficient GETC Q0.8 ppm/NC Channel-to-Channel Offset Matching Line Rejection LSB Q0.5 PSR (Note 6) 0.3 Q2 LSB/V DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7) Signal-to-Noise Plus Distortion SINAD 70 71.9 dB Signal-to-Noise Ratio SNR 70 72.3 dB Total Harmonic Distortion (Up to the 5th Harmonic) THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Maxim Integrated IMD -83 77 -76 dB 84 dB f1 = 99.2432kHz, f2 = 69.2139kHz -85 dB -3dB 30 -0.1dB 5 SINAD 70dB 0.5 MHz MHz 2 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN -0.5dB below full-scale of 99.2432kHz sine wave input to the channel being sampled, apply full-scale 69.2139kHz sine wave signal to all 15 nonselected input channels. Crosstalk TYP MAX -88 UNITS dB CONVERSION RATE Power-Up Time tPU Acquisition Time tACQ Conversion Time tCONV External Clock Frequency fSCLK Conversion cycle, external clock 2 Internally clocked (Note 8) Externally clocked, fSCLK = 16MHz, 16 cycles (Note 8) Aperture Jitter ns 5.9 s 1000 ns 0.16 Aperture Delay RMS Cycles 156 16 MHz 8 ns 30 ps ANALOG INPUT Input Voltage Range VINA Absolute Input Voltage Range Static Input Leakage Current Input Capacitance Unipolar, (single ended and pseudodifferential) Bipolar (Note 9) Range bit set to 0 -VREF+/2 Range bit set to 1 -VREF+ AIN+, AIN- relative to GND IILA CAIN 0 -0.1 VREF+ VREF+/2 VREF+ VREF+ + 0.1 -0.1 VAIN = VDD, GND V During acquisition time; RANGE bit = 0 (Note 10) 15 During acquisition time; RANGE bit = 1 (Note 10) 7.5 Q1.5 V FA pF EXTERNAL REFERENCE INPUT REF- Input Voltage Range VREF- -0.3 REF+ Input Voltage Range VREF+ 1 REF+ Input Current IREF+ +1 VDD + 50mV VREF+ = 2.5V, fSAMPLE = 1Msps 36.7 VREF+ = 2.5V, fSAMPLE = 0Msps 0.1 V V FA DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low VIL Input Voltage High VIH Input Hysteresis Maxim Integrated VHYST VOVDD O 0.25 VOVDD O 0.75 V V VOVDD O 0.15 mV 3 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL Input Leakage Current IIN Input Capacitance CIN CONDITIONS MIN VAIN = 0V or VDD TYP MAX UNITS Q0.09 Q1.0 FA 3 pF DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low VOL ISINK = 200FA Output Voltage High VOH ISOURCE = 200FA Three-State Leakage Current Three-State Output Capacitance VOVDD O 0.15 VOVDD O 0.85 V V IL CS = VDD -0.3 COUT CS = VDD 4 Q1.5 FA pF POWER REQUIREMENTS Positive Supply Voltage Digital I/O Supply Voltage VDD VOVDD 2.35 3.0 3.6 V 1.5 3.0 3.6 V 1.8 2.5 fSAMPLE = 1Msps Positive Supply Current IDD fSAMPLE = 0Msps (1Msps devices) 1 Full shutdown Normal mode (External Reference) Power Dissipation AutoStandby Full/ AutoShutdown 0.0015 VDD = 3V, fSAMPLE = 1Msps 5.4 VDD = 2.35V, fSAMPLE = 1Msps 3.8 VDD = 3V, fSAMPLE = 1Msps 2.6 VDD = 2.35V, fSAMPLE = 1Msps 1.6 VDD = 3V 4.5 VDD = 2.35V 2.1 mA 0.006 mW FW TIMING CHARACTERISTICS (Figure 1) (Note 11) SCLK Clock Period tCP SCLK Duty Cycle tCH SCLK Fall to DOUT Transition tDOT CLOAD = 10pF 16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns CLOAD = 10pF, channel ID off 16 ns CLOAD = 10pF 14 ns 14th SCLK Fall to DOUT Disable SCLK Fall to DOUT Enable tDOE Externally clocked conversion 62.4 ns 40 60 VOVDD = 1.5V to 2.35V 4 16.5 VOVDD = 2.35V to 3.6V 4 15 % ns DIN to SCLK Rise Setup tDS 4 ns SCLK Rise to DIN Hold tDH 1 ns Maxim Integrated 4 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Fall to SCLK Fall Setup tCSS 4 ns SCLK Fall to CS Fall Hold tCSH 1 ns CNVST Pulse Width tCSW 5 ns CS or CNVST Rise to EOC Low (Note 6) CS Pulse Width See Figure 6 tCNV_INT See Figure 7, fSAMPLE = 1Msps tCSBW 5.3 6.2 5 Fs ns ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Notes 3 and 4) Resolution RES Integral Nonlinearity INL Differential Nonlinearity DNL 10 bit 10 0.4 LSB 0.4 LSB 0.7 1.2 LSB 0 1.5 LSB No missing codes Offset Error Gain Error Bits (Note 5) Offset Error Temperature Coefficient OETC 2 ppm/NC Gain Temperature Coefficient GETC 0.8 ppm/NC 0.5 LSB Channel-to-Channel Offset Matching Line Rejection PSR (Note 6) 0.2 1.0 LSB/V DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7) Signal-to-Noise Plus Distortion SINAD 61 61.5 dB Signal-to-Noise Ratio SNR 61 61.5 dB Total Harmonic Distortion (Up to the 5th Harmonic) THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Maxim Integrated IMD -82.5 76 83.4 -75 dB dB f1 = 99.2432kHz, f2 = 69.2139kHz -83 dB -3dB 30 MHz -0.1dB 5 MHz 0.5 MHz SINAD 61dB 5 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN -0.5dB below full-scale of 99.2432kHz sine-wave input to the channel being sampled; apply full-scale 69.2139kHz sine wave signal to all 15 nonselected input channels Crosstalk TYP MAX -88 UNITS dB CONVERSION RATE Power-Up Time tPU Acquisition Time tACQ Conversion Time External Clock Frequency tCONV Conversion cycle, external clock 2 Internally clocked, fSAMPLE = 1Msps, (Note 8) Externally clocked, fSCLK = 16MHz, 16 cycles (Note 8) fSCLK Aperture Jitter 156 ns 5.9 s 1000 ns 0.16 Aperture Delay RMS Cycles 16 MHz 8 ns 30 ps ANALOG INPUT Unipolar (single-ended and pseudo differential) Input Voltage Range VINA Bipolar (Note 9) Absolute Input Voltage Range Static Input Leakage Current Input Capacitance 0 VREF+ RANGE bit set to 0 -VREF+ /2 +VREF+ /2 RANGE bit set to 1 -VREF+ +VREF+ -0.1 VREF+ + 0.1 V 1.5 FA AIN+, AIN- relative to GND IILA CAIN -0.1 VAIN_ = VDD, GND During acquisition time, RANGE bit = 0 (Note 10) 15 During acquisition time, RANGE bit = 1 (Note 10) 7.5 V pF EXTERNAL REFERENCE INPUT REF- Input Voltage Range VREF- REF+ Input Voltage Range VREF+ REF+ Input Current IREF+ -0.3 +1 V 1 VDD +50mV V VREF+ = 2.5V, fSAMPLE = 1Msps 36.7 FA VREF+ = 2.5V, fSAMPLE = 0Msps 0.1 FA DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low Maxim Integrated VIL VOVDD O 0.25 V 6 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Input Voltage High Input Hysteresis SYMBOL CONDITIONS MIN VIH IIN Input Capacitance CIN MAX VAIN_ = 0V or VDD UNITS V VOVDD O 0.15 VHYST Input Leakage Current TYP VOVDD O 0.75 0.09 mV 1.0 3 FA pF DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low VOL ISINK = 200FA Output Voltage High VOH ISOURCE = 200FA Three-State Leakage Current Three-State Output Capacitance VOVDD O 0.15 VOVDD O 0.85 V V IL CS = VDD -0.3 COUT CS = VDD 4 1.5 FA pF POWER REQUIREMENTS Positive Supply Voltage Digital I/O Supply Voltage VDD VOVDD 2.35 3.0 3.6 V 1.5 3.0 3.6 V 1.8 2.5 fSAMPLE = 1Msps Positive Supply Current IDD fSAMPLE = 0Msps (1Msps devices) 1 Full shutdown Normal mode (external reference) Power Dissipation AutoStandby Full/ AutoShutdown 0.0015 VDD = 3V, fSAMPLE = 1Msps 5.4 VDD = 2.35V, fSAMPLE = 1Msps 3.8 VDD = 3V, fSAMPLE = 1Msps 2.6 VDD = 2.35V, fSAMPLE = 1Msps 1.6 VDD = 3V 4.5 VDD = 2.35V 2.1 mA 0.006 mW FW TIMING CHARACTERISTICS (Figure 1) (Note 11) SCLK Clock Period tCP SCLK Duty Cycle tCH SCLK Fall to DOUT Transition tDOT CLOAD = 10pF 16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns CLOAD = 10pF, channel ID off 16 ns CLOAD = 10pF 14 ns 14th SCLK Fall to DOUT Disable SCLK Fall to DOUT Enable Maxim Integrated tDOE Externally clocked conversion 62.4 ns 40 60 VOVDD = 1.5V to 2.35V 4 16.5 VOVDD = 2.35V to 3.6V 4 15 % ns 7 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to SCLK Rise Setup tDS 4 ns SCLK Rise to DIN Hold tDH 1 ns CS Fall to SCLK Fall Setup tCSS 4 ns SCLK Fall to CS Fall Hold tCSH 1 ns CNVST Pulse Width tCSW 5 ns CS or CNVST Rise to EOC Low (Note 7) tCNV_INT See Figure 6 See Figure 7, fSAMPLE = 1Msps 5.3 tCSBW CS Pulse Width 5 6.2 Fs ns Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Parts are tested with MUX externally connected to the ADC input. Note 3: Channel ID disabled. Note 4: Tested in single-ended mode. Note 5: Offset nulled. Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V. Note 7: Tested and guaranteed with fully differential input. Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle. Maximum conversion time: 4.73Fs + N x 16 x tOSC_MAX tOSC_MAX = 88.2ns, tOSC_TYP = 75ns. Note 9: The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+. Note 10: See Figure 3 (Equivalent Input Circuit). Note 11: Guaranteed by characterization. tCSBW CS tCSS SCLK tCH 1ST CLOCK tCP tCSH 16TH CLOCK tDH tDS tDOT DIN tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram Maxim Integrated 8 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Typical Operating Characteristics (MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, TA = +25C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.5 DNL (LSB) INL (LSB) 0.4 0.2 0 -0.2 fSAMPLE = 1Msps -0.4 3 0 MAX11321 toc03 0.6 1.0 2 OFFSET ERROR (LSB) fSAMPLE = 1Msps 0.8 MAX11321 toc01 1.0 OFFSET ERROR vs. TEMPERATURE MAX11321 toc02 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 1 0 -1 -0.5 -0.6 -2 -0.8 -1.0 1024 0 2048 3072 1024 2048 3072 4096 -40 -25 -10 5 20 35 50 65 80 95 110 125 DIGITAL OUTPUT CODE (DECIMAL) DIGITAL OUTPUT CODE (DECIMAL) TEMPERATURE (C) GAIN ERROR vs. TEMPERATURE HISTOGRAM FOR 30,000 CONVERSIONS SNR AND SINAD vs. ANALOG INPUT FREQUENCY -1 -2 30,000 CODE HITS 25,000 20,000 15,000 10,000 73.5 73.0 SNR 72.5 72.0 SINAD 71.5 5,000 0 -3 fSAMPLE = 1Msps 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2046 2047 2048 2049 71.0 2050 20 0 40 OUTPUT CODE (DECIMAL) TEMPERATURE (C) THD vs. ANALOG INPUT FREQUENCY fSAMPLE = 1Msps 80 100 SFDR vs. ANALOG INPUT FREQUENCY 96 MAX11321 toc07 -80 60 fIN (kHz) 92 SFDR (dB) -85 THD (dB) fSAMPLE = 1Msps 94 MAX11321 toc08 0 30,000 74.0 SNR AND SINAD (dB) 1 fSAMPLE = 1Msps MAX11321 toc05 2 35,000 NUMBER OF OCCURENCES MAX11321 toc04 3 GAIN ERROR (LSB) -3 0 4096 MAX11321 toc06 -1.0 90 88 86 -90 84 82 -95 80 0 20 40 60 fIN (kHz) Maxim Integrated 80 100 0 20 40 60 80 100 fIN (kHz) 9 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Typical Operating Characteristics (continued) (MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, TA = +25C, unless otherwise noted.) SINAD vs. INPUT RESISTANCE 72.5 -70 MAX11321 toc10 MAX11321 toc09 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN THD vs. INPUT RESISTANCE 73 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN fSAMPLE = 1Msps fIN = 100kHz AOP SHORTED TO AIP AON SHORTED TO AIN -75 AOP SHORTED TO AIP AON SHORTED TO AIN THD (dB) 72.0 SINAD (dB) -80 AOP SHORTED TO AIP AON SHORTED TO AIN 71 71.5 BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN -85 fSAMPLE = 1Msps fIN = 100kHz fSAMPLE = 1Msps fIN = 100kHz 70 71.0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 500 1000 1500 2000 2500 3000 3500 4000 4500 0 5000 500 1000 1500 2000 2500 3000 3500 4000 RIN (I) RIN (I) RIN (I) SFDR vs. INPUT RESISTANCE 100kHz SINE-WAVE INPUT (8192 POINT FFT PLOT) REFERENCE CURRENT vs. SAMPLING RATE AOP SHORTED TO AIP AON SHORTED TO AIN 80 75 500 1500 2000 2500 3000 3500 4000 4500 40 -40 AHD3 = -86.69dB f = 300kHz -60 AHD2 = -102.99dB f = 200kHz -80 5000 30 20 0 500 0 50 100 150 200 250 300 350 400 450 500 1000 fSAMPLE (ksps) FREQUENCY (kHz) SUPPLY CURRENT vs. TEMPERATURE SNR vs. REFERENCE VOLTAGE MAX11321 toc16 74 MAX11321 toc15 2.5 5000 0 -120 fSAMPLE = 1Msps VDD = 3.0V 4500 10 RIN (I) 3.0 50 -100 fSAMPLE = 1Msps fIN = 100kHz 1000 -20 AMPLITUDE (dB) SFDR (dB) 85 fSAMPLE = 1Msps fIN = 100kHz IREF (A) BUFFER BETWEEN AOP AND AIP BUFFER BETWEEN AON AND AIN 0 MAX11321 toc13 90 0 -90 0 MAX11321 toc12 0 MAX11321 toc14 SNR (dB) 72 MAX11321 toc11 SNR vs. INPUT RESISTANCE 73.0 73 SNR (dB) IVDD (mA) 72 2.0 71 70 1.5 69 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Maxim Integrated fSAMPLE = 1Msps fIN = 100kHz 68 1.0 1.4 1.8 2.2 2.6 3.0 3.4 VREFP (V) 10 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access VDD GND REF+ GND DIN CS SCLK VDD VDD GND REF+ GND 23 SCLK 24 VDD CS TOP VIEW DIN Pin Configurations 22 21 20 19 18 17 24 23 22 21 20 19 18 17 DGND 25 16 REF- DGND 25 16 REF- OVDD 26 15 CNVST OVDD 26 15 CNVST DOUT 27 14 AIN DOUT 27 14 AIN 13 AIP EOC 28 13 AIP 12 AON AIN0 29 12 AON 11 AOP AIN1 30 11 AOP 10 GND AIN2 31 10 GND 9 GND AIN3 32 9 GND EOC 28 MAX11321 MAX11322 AIN0 29 AIN1 30 AIN2 31 + 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 GND GND GND GND GND GND GND AIN4 AIN5 AIN6 AIN7 GND GND GND GND + GND AIN3 32 MAX11324 MAX11325 SCLK VDD VDD GND REF+ GND TOP VIEW DIN TQFN 8 CHANNEL CS TQFN 4 CHANNEL 24 23 22 21 20 19 18 17 DGND 25 16 REF-/AIN15 OVDD 26 15 CNVST/AIN14 DOUT 27 14 AIN 13 AIP 12 AON 11 AOP 10 AIN13 9 AIN12 EOC 28 MAX11327 MAX11328 AIN0 29 AIN1 30 AIN2 31 + 4 5 6 7 8 AIN8 AIN9 AIN10 AIN11 AIN5 3 AIN7 2 AIN6 1 AIN4 AIN3 32 TQFN 16 CHANNEL Maxim Integrated 11 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Pin Description MAX11321 MAX11322 (4 CHANNEL) MAX11324 MAX11325 (8 CHANNEL) MAX11327 MAX11328 (16 CHANNEL) NAME 1-10, 17, 19 5-10, 17, 19 17, 19 GND Ground 11 11 11 AOP Positive Output from the Multiplexer 12 12 12 AON Negative Output from the Multiplexer 13 13 13 AIP Positive Input to the ADC 14 14 14 AIN Negative Input to the ADC 15 15 -- CNVST 16 16 -- REF- External Differential Reference Negative Input 18 18 18 REF+ External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47FF capacitor. 20, 21 20, 21 20, 21 VDD Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF capacitors. 22 22 22 SCLK Serial Clock Input. Clocks data in and out of the serial interface. 23 23 23 CS Active-Low Chip Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance or three-state. 24 24 24 DIN Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 25 25 25 DGND Digital I/O Ground 26 26 26 OVDD Digital Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF capacitors. 27 27 27 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. When CS is high, DOUT is high impedance or threestate. 28 28 28 EOC 29-32 -- -- AIN0-AIN3 -- -- 29-32 , 1-10 -- 29-32, 1-4 -- AIN0-AIN7 CNVST/ AIN14 -- -- 15 -- -- 16 -- -- -- Maxim Integrated FUNCTION Active-Low Conversion Start Input End of Conversion Output. Data is valid after EOC is driven low (internal clock mode only). Analog Inputs AIN0-AIN13 Analog Inputs Analog Inputs Active-Low Conversion Start Input/Analog Input 14 REF-/AIN15 External Differential Reference Negative Input /Analog Input 15 EP Exposed Pad. Connect EP directly to GND plane for guaranteed performance. 12 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Functional Diagrams HIGH-INPUT IMPEDANCE PGA/FILTER/BUFFER AOP AON AIN AIP REF+ REF- AIN0 REF+ REF- AIN1 ADC AIN2 AIN3 I/P MUX SINGLEENDED/ DIFFERENTIAL BUS CS SCLK OSCILLATOR CS SCLK AIN(N-1) CONTROL LOGIC AND SEQUENCER AIN(N) DIN DOUT CNVST EOC MAX11321-MAX11328 Maxim Integrated 13 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Functional Diagrams (continued) AOP AON AIN AIP REF+ REF- AIN0 REF+ REF- AIN1 ADC AIN2 CS AIN3 I/P MUX SINGLEENDED/ DIFFERENTIAL BUS SCLK OSCILLATOR CS SCLK AIN(N-1) CONTROL LOGIC AND SEQUENCER AIN(N) DIN DOUT CNVST EOC MAX11321-MAX11328 Detailed Description The MAX11321-MAX11328 are 12-/10-bit with external reference and industry-leading 500kHz, full linear bandwidth, high-speed, low-power, serial output successive approximation register (SAR) analog-to-digital converters (ADC). These devices feature scan mode, internal averaging to increase SNR, and AutoShutdown. The external clock mode features the SampleSet technology, a user-programmable analog input channel sequencer. The user may define and load a unique sequencing pattern into the ADC allowing both high- and low-frequency inputs to be converted without interface activity. This feature frees the controlling unit for other tasks while lowering overall system noise and power consumption. The MAX11321-MAX11328 include internal clock. The internal clock mode features an integrated FIFO, allowing data to be sampled at high speed and then held for readout at any time or at a lower clock rate. Internal averaging Maxim Integrated is also supported in this mode improving SNR for noisy input signals. All input channels are configurable for single-ended, fully differential or pseudo-differential inputs in unipolar or bipolar mode. The MAX11321-MAX11328 operate from a 2.35V to 3.6V supply and consume only 5.4mW at 1Msps. The MAX11321-MAX11328 include AutoShutdown, fast wake-up, and a high-speed 3-wire serial interface. The devices feature full power-down mode for optimal power management. Data is converted from analog voltage sources in a variety of channel and data-acquisition configurations. Microprocessor (FP) control is made easy through a 3-wire SPI-/QSPI-/MICROWIRE-compatible serial interface. AOP and AON are the output pins of the internal multiplexer while AIP and AIN are the ADC inputs which are all accessible externally through pins. This allows flexibility to the system designer to process all signals through one PGA (programmable gain amplifier), filter or gain stage 14 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access in single-ended or differential configuration. The external buffering stage should be designed to properly drive the input sampling network of the ADC. The external buffer should also have very high input impedance (low-leakage current) to ensure best linearity. If additional signal processing is not required, connect AOP to AIP and AON to AIN. It is recommended to limit the source impedance to not affect the sampling accuracy of the ADC causing degradation in linearity and total harmonic distortion. See the SINAD vs. Input Resistance graph in the Typical Operating Characteristics. Input Bandwidth The ADC's input-tracking circuitry features a 500MHz small-signal full-linear bandwidth to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. Anti-alias filtering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. 3-Wire Serial Interface The MAX11321-MAX11328 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode to generate the serial clock signal. Select the SCLK frequency of 48MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the control registers to the same value. The MAX11321-MAX11328 operate with SCLK idling high, and thus operate with CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. A high-to-low transition on CS samples the analog inputs and initiates a new frame. A frame is defined as the time between two falling edges of CS. There is a minimum of 16 bits per frame. The serial data input, DIN, carries data into the control registers clocked in by the rising edge of SCLK. The serial data output, DOUT, delivers the conversion results and is clocked out by the falling edge of SCLK. DOUT is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the MSB when CHAN_ID is set to 1 in the ADC Mode Control register (Figure 2a). When CHAN_ID is set to 1 keep the SCLK high for at least 25ns before the CS falling edge (Figure 2b). When CHAN_ID is set to 0 (external clock mode only), the 16-bit data word includes a leading zero and the 12-bit conversion result is followed by 3 trailing zeros (Figure 2c). In the 10-bit conversion result is followed by 5 trailing zeros. CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DI[15] DI[14] DIN DOUT Ch[3] Ch[2] 15 16 DI[0] DI[1] Ch[1] Ch[0] MSB MSB-1 LSB+1 LSB Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1 CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tQUIET > tSCLK DIN DOUT DI[15] Ch[3] DI[1] Ch[2] Ch[1] Ch[0] MSB MSB-1 LSB+1 DI[0] LSB Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance Maxim Integrated 15 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access CS SCLK DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DI[15] DI[14] 0 16 DI[1] MSB] MSB-1 MSB-2 LSB DI[0] 0 Figure 2c. External Clock Mode Timing Diagram with CHAN_ID=0 Single-Ended, Differential, and Pseudo-Differential Input The MAX11321-MAX11328 include up to 16 analog input channels that can be configured on a pin-by-pin basis to 16 single-ended inputs, 8 fully differential pairs, or 15 pseudo-differential inputs with respect to one common input (REF-/AIN15 is the common input). The analog input range is 0V to VREF+ in single-ended and pseudo-differential mode (unipolar) and QVREF+/2 or QVREF+ in fully differential mode (bipolar) depending on the RANGE register settings. See Table 7 for the RANGE register settings. Unipolar mode sets the differential input range from 0 to VREF+. If the positive analog input swings below the negative analog input in unipolar mode, the digital output code is zero. Selecting bipolar mode sets the differential input range to QVREF+/2 or QVREF+ depending on the RANGE register settings (Table 7). In single-ended mode, the ADC always operates in unipolar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0V to VREF+. Single-ended conversions are internally referenced to GND (Figure 3). The MAX11321-MAX11328 feature up to 15 pseudo differential inputs by setting the PDIFF_COM bits in the Unipolar register to 1 (Table 10). The 15 analog input signals inputs are referenced to a DC signal applied to the REF-/AIN15. Fully Differential Reference (REF+, REF-) When the reference is used in fully differential mode (REFSEL = 1), the full-scale range is set by the difference between REF+ and REF-. The output code reaches its Maxim Integrated DAC COMPARATOR AIP HOLD AIN (GND) DAC Figure 3. Equivalent Input Circuit maximum value if the input signal exceeds this reference range. ADC Transfer Function The output format of the MAX11321-MAX11328 is straight binary in unipolar mode and two's complement in bipolar mode. The code transitions midway between successive integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure 4 and Figure 5 show the unipolar and bipolar transfer function, respectively. Output coding is binary, with for example, 1 LSB = VREF+/4096 in the 12-bit devices such as the MAX11322/MAX11325/MAX11328. Internal FIFO The MAX11321-MAX11328 contain a FIFO buffer that can hold up to 16 ADC results. This allows the ADC to handle multiple internally clocked conversions without tying up the serial bus. If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each 16 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access OUTPUT CODE (hex) OUTPUT CODE (hex) FFF FS = VREF+ 7FF FFE ZS = 0 7FE FFD 1 LSB = VREF+ 4096 FFC 001 FFB VREF+ 2 ZS = 0 -VREF+ -FS = 2 VREF+ 1 LSB = 4096 +FS = 000 FFF 004 FFE 003 002 801 001 800 000 0 1 2 3 4 FS -1.5 LSB FS INPUT VOLTAGE (LSB) Figure 4. Unipolar Transfer Function for 12-Bit Resolution result contains 2 bytes, with the MSB preceded by four leading channel address bits. After each falling edge of CS, the oldest available byte of data is available at DOUT. When the FIFO is empty, DOUT is zero. External Clock Apply a soft reset when changing from internal to external clock mode: RESET [1:0] = 10. The detailed operation of external clock mode is dependent on the mode of operation selected for the device using SCAN[3:0] bit settings (see Table 3). In external clock mode the analog inputs are sampled at the falling edge of CS. Serial clock (SCLK) is used to perform the conversion. Depending on the mode selected, the sequencer reads in the channel to be converted from the serial data input (DIN) at each frame (e.g. manual mode). The conversion results are sent to the serial output (DOUT) at the next frame. In other external clocked modes the sequence of channel to be converted is determined by the mode (SCAN[3:0]) selected in Table 3. See the Applications Information for more detail on programming modes. Maxim Integrated -FS 0 -FS +0.5 LSB +FS -1.5 LSB INPUT VOLTAGE (LSB) +FS Figure 5. Bipolar Transfer Function for 12-Bit Resolution Internal Clock Apply a soft reset when changing from internal to external clock mode: RESET [1:0] = 10. The MAX11321- MAX11328 operate from an internal oscillator, which is accurate within Q15% of the 13.33MHz nominal clock rate. Request internally timed conversions by writing the appropriate sequence to the ADC Mode Control register (Table 2). The wake-up, acquisition, conversion, and shutdown sequences are initiated through CNVST and are performed automatically using the internal oscillator. Results are added to the internal FIFO. With CS high, initiate a scan by setting CNVST low for at least 5ns before pulling it high (Figure 6). Then, the MAX11321-MAX11328 wake up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. Do not initiate a second CNVST before EOC goes low; otherwise, the FIFO may become corrupted. 17 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access UP TO N INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS CNVST tCSW CS EOC tCNV_INT SCLK 1 16 1 16 SET MODE REG SET MODE REG READ DATA FROM FIFO READ DATA FROM FIFO DIN DOUT INTERNAL OSCILLATOR ON SCAN OPERATION AND RESULTS STORED IN FIFO Figure 6. Internal Conversions with CNVST UP TO N INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS tCNV_INT (N = 1) CS EOC SCLK 1 17 SET MODE REG 1 16 SET MODE REG SWCNV = 1 DIN DOUT MODE CONTROL INTERNAL OSCILLATOR ON READ DATA FROM FIFO SCAN OPERATION AND RESULTS STORED IN FIFO Figure 7. Internal Conversions with SWCNV Maxim Integrated 18 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Alternatively, set SWCNV to 1 in the ADC Mode Control register (Figure 4) to initiate conversions with CS rising edge instead of cycling CNVST (Table 2). For proper operation, CS must be held low for 17 clock cycles to guarantee that the device interprets the SWCNV setting. Wait until EOC goes low before pulling CS low to communicate with the serial interface. Upon completing the conversion, SWCNV is reset to 0 (Figure 7). Analog Input The MAX11321-MAX11328 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within the specified operating range. Internal protection diodes confine the analog input voltage within the region of the analog power input rails (VDD, GND) and allow the analog input voltage to swing from GND - 0.3V to VDD + 0.3V without damaging the device. Input voltages beyond GND - 0.3V and VDD + 0.3V forward bias the internal protection diodes. Limit the forward diode current to less than 50mA to avoid damage to the MAX11321-MAX11328. ECHO When writing to the ADC Configuration register, set ECHO to 1 in ADC Configuration register to echo back the configuration data onto DOUT at time n+1 (Figure 8, Table 6). Scan Modes The MAX11321-MAX11328 feature nine scan modes (Table 3). Manual Mode The next channel to be selected is identified in each SPI frame. The conversion results are sent out in the next frame. The manual mode works with the external clock only. The FIFO is unused. Repeat Mode Repeat scanning channel N for number of times and store all the conversion results in the FIFO. The number of scans is programmed in the ADC Configuration register. The repeat mode works with the internal clock only. Custom_Int and Custom_Ext In Custom_Int and Custom_Ext modes, the device scans preprogrammed channels in ascending order. The channels to be scanned in sequence are programmed in the Custom Scan0 or Custom Scan1 registers (see Table 12 and Table 13). A new I/P MUX is selected every frame on the thirteenth falling edge of SCLK. Custom_Int works with the internal clock. Custom_Ext works with the external clock. Standard_Int and Standard_Ext In Standard_Int and Standard_Ext modes, the device scans channels 0 through N in ascending order where N is the last channel specified in the ADC Mode Control register. A new I/P MUX is selected every frame on the thirteenth falling edge of SCLK. Standard_Int works with the internal clock. Standard_Ext works with the external clock. Upper_Int and Upper_Ext In Upper_Int and Upper_Ext modes, the device scans channels N through 15/11/7/3 in ascending order where N is the first channel specified in the ADC Mode Control register. A new I/P MUX is selected every frame on the thirteenth falling edge of SCLK. Upper_Int works with the internal clock. Upper_Ext works with the external clock. SampleSet The SampleSet mode of operation allows the definition of a unique channel sequence combination with maximum length of 256. SampleSet is supported only in the external clock mode. SampleSet is ideally suited for multichannel measurement applications where some analog inputs must be converted more often than others. t = n-1 t=n t = n+1 t = n+2 TURN ON ECHO CONFIGURATION DATA CONFIGURATION DATA CONFIGURATION DATA CONFIGURATION DATA CONFIGURATION DATA CS DIN DOUT Figure 8. Echo Back the Configuration Data Maxim Integrated 19 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access The SampleSet approach provides greater sequencing flexibility for multichannel applications while alleviating significant microcontroller communication overhead. SampleSet technology allows the user to exploit available ADC input bandwidth without need for constant communication between the ADC and controlling unit. The user may define and load a unique sequencing pattern into the ADC allowing both high- and low-frequency inputs to be converted appropriately without interface activity. With the unique sequence loaded into ADC memory, the pattern may be repeated indefinitely or changed at any time. For example, the maximum throughput of MAX11321- MAX11328 is 1Msps. Traditional ADC scan modes allow SampleSet REPEATS: LENGTH = 256 SAMPLE SET (DEPTH = 256) 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE 7TH CYCLE 8TH CYCLE 9TH CYCLE POTENTIAL SampleSet PATTERN CHANNEL: AIN2/ AIN3 AIN0 AIN1 AIN0 AIN1 AIN0 AIN1 AIN2/ AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN2/ AIN3 AIN0 AIN1 AIN0 AIN1 AIN2/ AIN3 ENTRY NO.: 1 2 3 4 5 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 254 255 256 120 CONVERSIONS: AIN0 AND AIN1 120 CONVERSIONS: AIN0 AND AIN1 ANALOG INPUTS AIN0 100kHz 100 CYCLES AIN1 135 10kHz 10 CYCLES 1 FULLY DIFFERENTIAL 122 1kHz 1 CYCLES 256 AIN2 AIN3 123 AIN4 124 AIN5 125 AIN6 tS = 1/fS = 1/3Msps = 333.33ns AIN7 CS 10 8 AIN0 AIN8 12 6 14 4 AIN9 16 2 32 18 TS 5s 10s 30 20 28 22 fin = 100kHz AIN10 26 24 AIN11 AIN1 7 9 11 5 3 TS AIN12 13 15 17 5s AIN13 31 19 29 21 23 25 10s 27 Figure 9. SampleSet Use-Model Example Maxim Integrated 20 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access up to 16-channel conversions in ascending order. In this case, the effective throughput per channel is 1Msps/16 channel or 62.5ksps. The maximum input frequency that the ADC can resolve (Nyquist Theorem) is 31.25kHz. If all 16 channels must be measured, with some channels having greater than 31.25kHz input frequency, the user must revert back to manual mode requiring constant communication on the serial interface. SampleSet technology solves this problem. Figure 9 provides a SampleSet use-model example. Averaging Mode In averaging mode, the device performs the specified number of conversions and returns the average for each requested result in the FIFO. The averaging mode works with internal clock only. Scan Modes and Unipolar/Bipolar Setting When the Unipolar or Bipolar registers are configured as pseudo-differential or fully differential, the analog input pairs are repeated in this automated mode. For example, if N is set to 15 to scan all 16 channels and all analog input pairs are configured for fully-differential conversion, the ADC converts the channels twice. In this case, the user may avoid dual conversions on input pairs by implementing Manual mode or using Custom_Int or Custom_Ext scan modes and only scan even (or odd) channels (e.g. 0, 2, 4). Table 1. Register Access and Control REGISTER IDENTIFICATION CODE REGISTER NAME DIN DATA INPUTS BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 ADC Mode Control 0 DIN DIN DIN DIN BIT [10:0] DIN ADC Configuration 1 0 0 0 0 DIN Unipolar 1 0 0 0 1 DIN Bipolar 1 0 0 1 0 DIN RANGE 1 0 0 1 1 DIN Custom Scan0 1 0 1 0 0 DIN Custom Scan1 1 0 1 0 1 DIN SampleSet 1 0 1 1 0 DIN Reserved. Do not use. 1 1 1 1 1 DIN Table 2. ADC Mode Control Register BIT NAME BIT DEFAULT STATE FUNCTION REG_CNTL 15 0 SCAN[3:0] 14:11 0001 ADC Scan Control register (Table 3) CHSEL[3:0] 10:7 0000 Analog Input Channel Select register (Table 4). See Table 3 to determine which modes use CHSEL[3:0] for the channel scan instruction. RESET[1:0] Maxim Integrated 6:5 00 Set to 0 to select the ADC Mode Control register RESET1 RESET0 FUNCTION 0 0 No reset 0 1 Reset the FIFO only (resets to zero) 1 0 Reset all registers to default settings (includes FIFO) 1 1 Unused 21 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 2. ADC Mode Control Register (continued) BIT NAME BIT DEFAULT STATE PM[1:0] 4:3 00 Power Management Modes (Table 5). In external clock mode, PM[1:0] selects between normal mode and various power-down modes of operation. CHAN_ID 2 0 External Clock Mode. Channel address is always present in internal clock mode. Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the MSB. FUNCTION SWCNV 1 0 Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST (internal clock mode only). This bit is used for the internal clock mode only and must be reasserted in the ADC mode control, if another conversion is desired. -- 0 0 Unused Table 3. ADC Scan Control SCAN3 0 SCAN2 0 SCAN1 0 SCAN0 0 MODE NAME Null FUNCTION Continue to operate in the previously selected mode. Ignore data on bits [10:0]. This feature is provided so that DIN can be held low when no changes are required in the ADC Mode Control register. Bits [6:3, 1] can be still written without changing the scan mode properties. The next channel to be selected is identified in each SPI frame. The conversion results are sent out in the next frame. 0 0 0 1 Manual Clock mode: External clock only Channel scan/sequence: Single channel per frame Channel selection: See Table 4, CHSEL[3:0] Averaging: No Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16 conversion results for channel N. 0 0 1 0 Repeat Clock mode: Internal clock only Channel scan/sequence: Single channel per frame Channel selection: See Table 4, CHSEL[3:0] Averaging: Can be enabled Scans channels 0 through N. The FIFO stores N conversion results. Clock mode: Internal clock 0 0 1 1 Standard_Int Channel scan/sequence: N channels in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: Can be enabled Maxim Integrated 22 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 3. ADC Scan Control (continued) SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION Scans channels 0 through N Clock mode: External clock only 0 1 0 0 Standard_Ext Channel scan/sequence: N channels in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: No Scans channel N through the highest numbered channel. The FIFO stores X conversion results where: 0 1 0 1 Upper_Int X = Channel 16-N 16-channel devices X = Channel 8-N 8-channel devices Clock mode: Internal clock only Channel scan/sequence: Channel N through the highest numbered channel in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: Can be enabled Scans channel N through the highest numbered channel Clock mode: External clock only 0 1 1 0 Upper_Ext Channel scan/sequence: Channel N through the highest numbered channel in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: No Scans preprogrammed channels in ascending order. The FIFO stores conversion results for this unique channel sequence. Clock mode: Internal clock only 0 1 1 1 Custom_Int Channel scan/sequence: Unique ascending channel sequence Maximum depth: 16 conversions Channel selection: See Table 12, Custom Scan0 register and Table 13, Custom Scan1 register Averaging: Can be enabled Scans preprogrammed channels in ascending order Clock mode: External clock only Channel scan/sequence: Unique ascending channel sequence 1 0 0 0 Custom_Ext Maximum depth: 16 conversions Channel selection: See Table 12, Custom Scan0 register and Table 13, Custom Scan1 register Averaging: No Maxim Integrated 23 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 3. ADC Scan Control (continued) SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION Scans preprogrammed channel sequence with maximum length of 256. There is no restriction on the channel pattern. Clock mode: External clock only 1 0 0 1 SampleSet Channel scan/sequence: Unique channel sequence Maximum depth: 256 conversions Channel Selection: See Table 4 Averaging: No 1 0 1 0 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. 1 0 1 1 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. 1 1 0 0 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. 1 1 0 1 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. 1 1 1 0 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. 1 1 1 1 Null Continue to operate in the previously selected mode. Ignore data on bits [10:0]. Table 4. Analog Input Channel Select CHSEL3 CHSEL2 CHSEL1 CHSEL0 SELECTED CHANNEL (N) 0 0 0 0 AIN0 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AIN8 1 0 0 1 AIN9 1 0 1 0 AIN10 1 0 1 1 AIN11 1 1 0 0 AIN12 1 1 0 1 AIN13 1 1 1 0 AIN14 1 1 1 1 AIN15 Maxim Integrated 24 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Register Descriptions The MAX11321-MAX11328 communicate between the internal registers and the external circuitry through the SPI-/QSPI-compatible serial interface. Table 1 details the register access and control. Table 2 through Table 14 detail the various functions and configurations. For ADC mode control, set bit 15 of the register code identification to zero. The ADC Mode Control register determines when and under what scan condition the ADC operates. U Full shutdown where all circuitry is shutdown. U Partial shutdown where all circuitry is powered down except for the internal bias generator. AutoShutdown with External Clock Mode When the PM_ bits in the ADC Mode Control register are asserted (Table 5), the device shuts down at the rising edge of CS in the next frame. The device powers up again at the following falling edge of CS. There are two available options: U AutoShutdown where all circuitry is shutdown. To set the ADC data configuration, set the bit 15 of the register code identification to one. U AutoStandby where all circuitry are powered down except for the internal bias generator. Power-Down Mode AutoShutdown with Internal Clock Mode The device shuts down after all conversions are completed. The device powers up again at the next falling edge of CNVST or at the rising edge of CS after the SWCNV bit is asserted. The MAX11321-MAX11328 feature three power-down modes. Static Shutdown The devices shut down when the SPM bits in the ADC Configuration register are asserted (Table 6). There are two shutdown options: Table 5. Power Management Modes PM1 PM0 MODE 0 0 Normal FUNCTION 0 1 AutoShutdown 1 0 AutoStandby 1 1 -- All circuitry is fully powered up at all times. The device enters full shutdown mode at the end of each conversion. All circuitry is powered down. The device powers up following the falling edge of CS. It takes 2 cycles before valid conversions take place. The information in the registers is retained. The device powers down all circuitry except for the internal bias generator. The part powers up following the falling edge of CS. It takes 2 cycles before valid conversions take place. The information in the registers is retained. Unused. Table 6. ADC Configuration Register BIT NAME BIT DEFAULT STATE CONFIG_SETUP 15:11 N/A REFSEL AVGON Maxim Integrated 10 9 0 0 FUNCTION Set to 10000 to select the ADC Configuration register. REFSEL VOLTAGE REFERENCE REF- CONFIGURATION 0 External single-ended AIN15 (for the 16-channel devices) 1 External differential REF- Set to 1 to turn averaging on. Valid for internal clock mode only. Set to 0 to turn averaging off. 25 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 6. ADC Configuration Register (continued) BIT NAME BIT DEFAULT STATE FUNCTION Valid for internal clock mode only. AVGON NAVG[1:0] 8:7 NAVG1 NAVG0 FUNCTION 0 X X Performs 1 conversion for each requested result. 1 0 0 Performs 4 conversions and returns the average for each requested result. 1 0 1 Performs 8 conversions and returns the average for each requested result. 1 1 0 Performs 16 conversions and returns the average for each requested result. 1 1 1 Performs 32 conversions and returns the average for each requested result. 00 Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only. NSCAN[1:0] 6:5 NSCAN1 NSCAN0 0 0 Scans channel N and returns 4 results. 0 1 Scans channel N and returns 8 results. 1 0 Scans channel N and returns 12 results. 1 1 Scans channel N and returns 16 results. 00 FUNCTION Static power-down modes SPM[1:0] 4:3 00 SPM1 SPM0 MODE 0 0 Normal FUNCTION 0 1 Full Shutdown All circuitry is powered down. The information in the registers is retained. 1 0 Partial Shutdown All circuitry is powered down except for the reference and reference buffer. The information in the registers is retained. 1 1 -- All circuitry is fully powered up at all times. Reserved ECHO 2 0 Set to 0 to disable the instruction echo on DOUT. Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8). -- 1:0 0 Unused Maxim Integrated 26 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 7. RANGE Register (RANGE Settings Only Applies to Bipolar Fully Differential Analog Input Configurations) BIT NAME BIT DEFAULT STATE RANGE_SETUP 15:11 N/A RANGE0/1 10 0 Set to 0 for AIN0/1: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN0/1: +VREF+, fS = 2(VREF+ - VREF-) RANGE2/3 9 0 Set to 0 for AIN2/3: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN2/3: +VREF+, fS = 2(VREF+ - VREF-) RANGE4/5 8 0 Set to 0 for AIN4/5: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN4/5: +VREF+, fS = 2(VREF+ - VREF-) RANGE6/7 7 0 Set to 0 for AIN6/7: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN6/7: +VREF+, fS = 2(VREF+ - VREF-) RANGE8/9 6 0 Set to 0 for AIN8/9: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN8/9: +VREF+, fS = 2(VREF+ - VREF-) RANGE10/11 5 0 Set to 0 for AIN10/11: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN10/11: +VREF+, fS = 2(VREF+ - VREF-) RANGE12/13 4 0 Set to 0 for AIN12/13: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN12/13: +VREF+, fS = 2(VREF+ - VREF-) RANGE14/15 3 0 Set to 0 for AIN14/15: +VREF+/2, fS = VREF+ - VREFSet to 1 for AIN14/15: +VREF+, fS = 2(VREF+ - VREF-) -- 2:0 000 FUNCTION Set to 10011 to select the RANGE register Unused ADC Output as a Function of Unipolar and Bipolar Modes The ADC Scan Control register (Table 3) determines the ADC mode of operation. The Unipolar and Bipolar registers in Table 10 and Table 11 determine output coding and whether input configuration is single-ended or fully differential. Table 9 details the conversion output for analog inputs, AIN0 and AIN1. The truth table is consistent for any other valid input pairs (AINn/AINn+1). Table 8 shows the applicable input signal format with respect to analog input configurations. CHSEL[3:0] is used for MANUAL, REPEAT, STANDARD_EXT, STANDARD_INT, UPPER_EXT, UPPER_INT modes of operation. CHSCAN[15:0] is used for CUSTOM_EXT and CUSTOM_INT modes of operation. SampleSet Mode of Operation The SampleSet register stores the unique channel sequence length. The sequence pattern is comprised of up to 256 unique single-ended and/or differential conversions with any order or pattern. Maxim Integrated Patterns are assembled in 4-bit channel identifier nibbles as described in Table 4. Figure 10 presents the SampleSet timing diagram. Note that two CS frames are required to configure the SampleSet functionality. The first frame indicates the sequence length. The second frame is used to encode the channel sequence pattern. After the SampleSet register has been coded (Table 14), by the next falling edge of CS, the new SampleSet pattern is activated (Figure 10). If the pattern length is less than SEQ_LENGTH, the remaining channels default to AIN0. If the select pattern length is greater than SEQ_LENGTH, the additional data is ignored as the ADC waits for the rising edge of CS. If CS is asserted in the middle of a nibble, the full nibble defaults to AIN0. Upon receiving the SampleSet pattern, the user can set the ADC Mode Control register to begin the conversion process where data readout begins with the first SampleSet entry. While the last conversion result is read, the ADC can be instructed to enter AutoShutdown, if desired. If the user wishes to change the SampleSet length, a new pattern must be loaded into the ADC as described in Figure 10. 27 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 8. Analog Input Configuration and Unipolar/Bipolar Waveforms SUPPORTED WAVEFORMS ANALOG INPUT CONFIGURATION REFSEL = 0 VIN+ Unipolar (Binary Coding) REF+ RANGE: 1V TO VDD REF+ VIN+ REF+ 1V GND, AIN15 PDIFF_COM = 1 0V -0.3V REF+ RANGE: 1V TO VDD REF+ RANGE: 1V TO VDD VIN(DC OFFSET OR SINUSOID) VIN- REF+ 2 VIN- VFS = 2REF+ RANGE = 1 REF+ VFS = REF+ RANGE = 0 Bipolar (2's Complement) VIN(DC OFFSET OR SINUSOID) REF+ RANGE: 1V TO VDD VIN+ Table 10. Unipolar Register: Set desired channel(s) to 0 or PDIFF_COM to 1. Counterpart Register Table 11. Bipolar Register: Set desired channel(s) to 0. Table 10. Unipolar Register: Set desired channel(s) to 1. REF+ VIN+ REF+ VIN- 1V 0V -0.3V REF- REF+ RANGE: 1V TO VDD VFS = 2REF+ RANGE = 1 REF+ GND Fully Differential VIN+ REF- VIN+ Unipolar (Binary Coding) Fully Differential REF+ RANGE: 1V TO VDD VFS = REF+ RANGE = 0 SingleEnded UNIPOLAR/BIPOLAR REGISTER SETTING REFSEL = 1 1V GND 0V -0.3V REF- Counterpart Register Table 11. Bipolar Register: Set desired channel(s) to 0. Table 11. Bipolar Register: Set desired channel(s) to 1. Counterpart Register Table 10. Unipolar Register: Set desired channel(s) to 0. Table 9. ADC Output as a Function of Unipolar/Bipolar Register Settings CHANNEL SELECTION BIT NAME AIN0 Selection: CHSEL[3:0] = 0000 CHSCAN0 = 1 AIN1 Selection: CHSEL[3:0] = 0001 CHSCAN1 = 1 Maxim Integrated UNIPOLAR REGISTER BIPOLAR REGISTER FUNCTION UCH0/1 PDIFF_COM BCH0/1 0 0 0 AIN0 (binary, unipolar) 0 0 1 AIN0/1 pair (two's complement, bipolar) 1 0 0 AIN0/1 pair (binary, unipolar) 1 0 1 AIN0/1 pair (binary, unipolar); Unipolar register takes precedence X 1 X AIN0 referred to REF-/AIN15 (binary, unipolar) 0 0 0 AIN1 (binary, unipolar) 0 0 1 AIN0/1 pair (two's complement, bipolar) 1 0 0 AIN0/1 pair (binary, unipolar) 1 0 1 AIN0/1 pair (binary, unipolar), Unipolar register takes precedence X 1 X AIN1 referred to REF-/AIN15 (binary, unipolar) 28 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 10. Unipolar Register BIT NAME BIT DEFAULT STATE UNI_SETUP 15:11 -- UCH0/1 10 0 UCH2/3 9 0 UCH4/5 8 0 UCH6/7 7 0 UCH8/9 6 0 UCH10/11 5 0 UCH12/13 4 0 UCH14/15 3 0 PDIFF_COM 2 0 -- 1:0 000 FUNCTION Set to 10001 to select the Unipolar register. Set to 1 to configure AIN0 and AIN1 for pseudo-differential conversion. Set to 0 to configure AIN0 and AIN1 for single-ended conversion. Set to 1 to configure AIN2 and AIN3 for pseudo-differential conversion. Set to 0 to configure AIN2 and AIN3 for single-ended conversion. Set to 1 to configure AIN4 and AIN5 for pseudo-differential conversion. Set to 0 to configure AIN4 and AIN5 for single-ended conversion. Set to 1 to configure AIN6 and AIN7 for pseudo-differential conversion. Set to 0 to configure AIN6 and AIN7 for single-ended conversion. Set to 1 to configure AIN8 and AIN9 for pseudo-differential conversion. Set to 0 to configure AIN8 and AIN9 for single-ended conversion. Set to 1 to configure AIN10 and AIN11 for pseudo-differential conversion. Set to 0 to configure AIN10 and AIN11 for single-ended conversion. Set to 1 to configure AIN12 and AIN13 for pseudo-differential conversion. Set to 0 to configure AIN12 and AIN13 for single-ended conversion. Set to 1 to configure AIN14 and AIN15 for pseudo-differential conversion. Set to 0 to configure AIN14 and AIN15 for single-ended conversion. Set to 1 to configure AIN0-AIN14 to be referenced to one common DC voltage on the REF-/AIN15. Set to 0 to disable the 15:1 pseudo differential mode. Unused. Table 11. Bipolar Register BIT NAME BIT DEFAULT STATE BIP_SETUP 15:11 -- Set to 10010 to select the Bipolar register. BCH0/1 10 0 Set to 1 to configure AIN0 and AIN1 for bipolar fully differential conversion. Set to 0 to configure AIN0 and AIN1 for unipolar conversion mode. BCH2/3 9 0 Set to 1 to configure AIN2 and AIN3 for bipolar fully differential conversion. Set to 0 to configure AIN2 and AIN3 for unipolar conversion mode. BCH4/5 8 0 Set to 1 to configure AIN4 and AIN5 for bipolar fully differential conversion. Set to 0 to configure AIN4 and AIN5 for unipolar conversion mode. BCH6/7 7 0 Set to 1 to configure AIN6 and AIN7 for bipolar fully differential conversion. Set to 0 to configure AIN6 and AIN7 for unipolar conversion mode. BCH8/9 6 0 Set to 1 to configure AIN8 and AIN9 for bipolar fully differential conversion. Set to 0 to configure AIN8 and AIN9 for unipolar conversion mode. BCH10/11 5 0 Set to 1 to configure AIN10 and AIN11 for bipolar fully differential conversion. Set to 0 to configure AIN10 and AIN11 for unipolar conversion mode. BCH12/13 4 0 Set to 1 to configure AIN12 and AIN13 for bipolar fully differential conversion. Set to 0 to configure AIN12 and AIN13 for unipolar conversion mode. BCH14/15 3 0 Set to 1 to configure AIN14 and AIN15 for bipolar fully differential conversion. Set to 0 to configure AIN14 and AIN15 for unipolar conversion mode. -- 2:0 000 Maxim Integrated FUNCTION Unused. 29 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Table 12. Custom Scan0 Register BIT NAME BIT DEFAULT STATE CUST_SCAN0 15:11 -- Set to 10100 to select the Custom Scan0 register. CHSCAN15 10 0 Set to 1 to scan AIN15. Set to 0 to omit AIN15. CHSCAN14 9 0 Set to 1 to scan AIN14. Set to 0 to omit AIN14. CHSCAN13 8 0 Set to 1 to scan AIN13. Set to 0 to omit AIN13. CHSCAN12 7 0 Set to 1 to scan AIN12. Set to 0 to omit AIN12. CHSCAN11 6 0 Set to 1 to scan AIN11. Set to 0 to omit AIN11. CHSCAN10 5 0 Set to 1 to scan AIN10. Set to 0 to omit AIN10. CHSCAN9 4 0 Set to 1 to scan AIN9. Set to 0 to omit AIN9. CHSCAN8 3 0 Set to 1 to scan AIN8. Set to 0 to omit AIN8. -- 2:0 000 FUNCTION Unused. Table 13. Custom Scan1 Register BIT NAME BIT DEFAULT STATE CUST_SCAN1 15:11 -- Set to 10101 to select the Custom Scan1 register. CHSCAN7 10 0 Set to 1 to scan AIN7. Set to 0 to omit AIN7. CHSCAN6 9 0 Set to 1 to scan AIN6. Set to 0 to omit AIN6. CHSCAN5 8 0 Set to 1 to scan AIN5. Set to 0 to omit AIN5. CHSCAN4 7 0 Set to 1 to scan AIN4. Set to 0 to omit AIN4. CHSCAN3 6 0 Set to 1 to scan AIN3. Set to 0 to omit AIN3. CHSCAN2 5 0 Set to 1 to scan AIN2. Set to 0 to omit AIN2. CHSCAN1 4 0 Set to 1 to scan AIN1. Set to 0 to omit AIN1. Set to 1 to scan AIN0. Set to 0 to omit AIN0. CHSCAN0 3 0 -- 2:0 000 FUNCTION Unused. Table 14. SampleSet Register BIT NAME BIT DEFAULT STATE SMPL_SET 15:11 -- SEQ_LENGTH 10:3 00000000 -- 2:0 -- Maxim Integrated FUNCTION Set to 10110 to select the SampleSet register. 8-bit binary word indicating desired sequence length. The equation is: Sequence length = SEQ_LENGTH + 1 00000000 = Sequence length = 1 11111111 = Sequence length = 256 Coding: Straight binary Maximum length: 256 ADC conversions Unused. 30 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access CS SCLK 1 16 1 1 DIN ENTRY 1 DOUT WRITE SampleSet REGISTER DEFINE SEQ_LENGTH ENTRY 2 ENTRY N = (SEQ_LENGTH) LOAD SampleSet PATTERN TIME BETWEEN CS FALLING AND RISING EDGE DEPENDS IN SEQ_LENGTH WRITE ADC MODE CONTROL OR CONTINUE WITH ADDITIONAL CONFIGURATION SETTINGS Figure 10. SampleSet Timing Diagram Applications Information How to Program Modes 1) Configure the ADC (set the MSB on DIN to 1). 2) Program ADC mode control (set the MSB on DIN to 0) to begin the conversion process or to control power management features. * If ADC mode control is written during a conversion sequence, the ADC finishes the present conversion and at the next falling edge of CS initiates its new instruction. * If configuration data (MSB on DIN is a 1) is written during a conversion sequence, the ADC finishes the present conversion in the existing scan mode. However, data on DOUT is not valid in following frames until a new ADC mode control instruction is coded. Programming Sequence Flow Chart See Figure 11 for programming sequence. Layout, Grounding, and Bypassing For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD, Maxim Integrated OVDD, and REF affects the ADC's performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. Choosing an Input Amplifier It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conver sion results are accurate when the ADC samples the input signal for an interval longer than the input signal's worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. Figure 13 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16-bit resolution, is an excellent choice for this application. Table 15 lists serveral recommended operational amplifiers for MAX11321-MAX11328. 31 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access SELECT REFERENCE EXTERNAL SINGLE-ENDED EXTERNAL DIFFERENTIAL SINGLE-ENDED OR DIFFERENTIAL SELECT ADC CONFIGURATION REGISTER SET REFSEL BIT TO 1 SELECT ADC CONFIGURATION REGISTER SET REFSEL BIT TO 0 FIGURE OUT NUMBER OF CHANNELS TO USE (N) FOR EACH ADC CHANNEL SINGLE-ENDED PSEUDODIFFERENTIAL PSEUDO-DIFFERENTIAL SELECT UNIPOLAR AND REGISTER SET BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION SINGLE-ENDED PSEUDODIFFERENTIAL FULLYDIFFERENTIAL SE, PsD/FD SINGLE-ENDED UNIPOLAR OR BIPOLAR BIPOLAR SELECT UNIPOLAR AND BIPOLAR REGISTER SET PER CHANNEL UCH{X}/{X+1} AND BCH{X}/{X+1} TO 0 FOR SINGLE-ENDED SELECTION SELECT BIPOLAR REGISTER SET PER CHANNEL BCH{X}/{X+1} TO 1 FOR BIPOLAR FULLY DIFFERENTIAL SELECT RANGE REGISTER SET PER CHANNEL PAIR RANGE{X}/{X+1} TO 1 QVREF+ 1 UNIPOLAR SELECT UNIPOLAR REGISTER SET PER CHANNEL UCH{X}/{X+1} TO 1 FOR UNIPOLAR RANGE SELECT 0 FOR EACH ADC CHANNEL SELECT RANGE REGISTER SET PER CHANNEL PAIR RANGE{X}/{X+1} TO 0 QVREF+/2 NEXT CHANNEL SEE FIGURE 12 Figure 11. ADC Programming Sequence Maxim Integrated 32 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access INTERNAL YES REPEAT AVERAGE INTERNAL/EXTERNAL CLOCK NO EXTERNAL ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0001 SET CHSEL[3:0] TO CHANNEL NUMBER SELECT THE PM[1:0] BITS YES YES NO MANUAL NO ADC CONFIGURATION REGISTER SET AVG ON BIT TO 1 SET NAVG[1:0] TO N ADC CONFIGURATION REGISTER SET NSCAN[1:0] FOR SCAN COUNT ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0010 SET CHSEL[3:0] TO CHANNEL NUMBER SELECT THE RIGHT SWCNV BIT ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0100 SET CHSEL[3:0] TO CHANNEL NUMBER STANDARD-EXT YES NO YES AVERAGE STANDARD-INT NO YES NO ADC CONFIGURATION REGISTER SET AVG ON BIT TO 1 SET NAVG[1:0] TO N ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0011 SET CHSEL[3:0] TO CHANNEL NUMBER SELECT THE RIGHT SWCNV BIT UPPER-INT YES AVERAGE ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0110 SET CHSEL[3:0] TO CHANNEL NUMBER UPPER-EXT YES NO NO YES NO ADC CONFIGURATION REGISTER SET AVG ON BIT TO 1 SET NAVG[1:0] TO N ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0101 SET CHSEL[3:0] TO CHANNEL NUMBER SELECT THE RIGHT SWCNV BIT CUSTOM-INT NO YES AVERAGE NO SET CUSTOM Scan0 REGISTER SET CUSTOM Scan1 REGISTER CUSTOM-EXT YES NO ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 1000 SET CHSEL[3:0] TO CHANNEL NUMBER YES ADC CONFIGURATION REGISTER SET AVGON BIT TO 1 SET NAVG[1:0] TO N SET CUSTOM Scan0 REGISTER SET CUSTOM Scan1 REGISTER ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 0111 SET CHSEL[3:0] TO CHANNEL NUMBER SELECT THE RIGHT SWCNV BIT SampleSet REGISTER SET SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH SampleSet YES FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH ADC MODE CONTROL REGISTER SET SCAN[3:0] TO 1001 SET CHSEL[3:0] TO CHANNEL NUMBER Figure 12. ADC Mode Select Programming Sequence Maxim Integrated 33 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Choosing a Reference For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. The following parameters need to be considered in selecting a reference: U Initial voltage accuracy U Temperature drift U Current source capability U Current sink capability U Quiescent current U Noise. See Table 16. +5V 0.1F 10F VDD 100pF VOVDD VDD 0.1F 500I 500I INPUT 1 0.1F AGND 4 5 3 2 AIP AIN AIN0 COG CAPACITOR -5V 0.1F 470pF AIN1 10F COG 470pF CAPACITOR INPUT 2 10F 0.1F SCLK SCLK DOUT MISO CPU AIN15 REF +5V 10F AOP AON MAX11321-MAX11328 10I 1 MAX4430 VDC OVDD 10F GND CS SS DIN MOSI 10F +5V 100pF 7 6 500I 500I INPUT 2 4 0.1F 5 MAX4430 VDC 3 2 10I 1 4 3 IN OUTF 2 1F OUTS GNDS GND MAX6126 NR 0.1F 1 0.1F -5V 0.1F 10F Figure 13. Typical Application Circuit Maxim Integrated 34 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nulled. The static linearity parameters for the MAX11321-MAX11328 are measured using the end-points method. In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Total Harmonic Distortion Total harmonic distortion (THD) is expressed as: THD = Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB or less guarantees no missing codes and a monotonic transfer function. Signal-to-Noise Ratio Signal-to-noise ratio is the ratio of the amplitude of the desired signal to the amplitude of noise signals at a given point in time. The larger the number, the better. The theoretical minimum analog-to-digital noise is caused by quantization error and results directly from the ADC's resolution (N bits): V 2 + V32 + V42 + V52 20 x log 2 V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component. Full-Power Bandwidth Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. SNR = (6.02 x N + 1.76) dB Table 15. Recommended Input Amplifiers REFERENCE CHANNELS TYPICAL APPLICATION MAX4430 1 Dual supply, low noise, low distortion, high bandwidth MAX4432 2 Dual supply, low noise, low distortion, high bandwidth MAX4454 4 Low power, single, supply, low cost MAX4418 4 Low noise, low power, high bandwidth MAX44263 2 Low power, precision, CMOS input, rail-to-rail I/O Table 16. Recommended References REFERENCE TYPICAL APPLICATION MAX6126 Ultra-high precision, ultra-low noise, wide temperature range MAX6033 Ultra-high precision, low noise, low power, wide temperature range MAX6043 High precision, wide temperature range MAX6129B MAX6003 Maxim Integrated Low cost, ultra-low power Low cost, low power 35 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Full-Linear Bandwidth Full-linear bandwidth is the frequency at which the signal-to-noise plus distortion (SINAD) is more than 70dB (MAX11322/MAX11325/MAX11328). Intermodulation Distortion Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are input into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. Ordering Information PIN-PACKAGE BITS SPEED (Msps) NO. OF CHANNELS MAX11321ATJ+ PART 32 TQFN-EP* 10 1 4 MAX11322ATJ+ 32 TQFN-EP* 12 1 4 MAX11324ATJ+ 32 TQFN-EP* 10 1 8 MAX11325ATJ+ 32 TQFN-EP* 12 1 8 MAX11327ATJ+ 32 TQFN-EP* 10 1 16 MAX11328ATJ+ 32 TQFN-EP* 12 1 16 Note: All devices are specified over the -40C to +125C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Maxim Integrated PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 TQFN-EP T3255+5 21-0140 90-0013 36 MAX11321-MAX11328 1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access Revision History REVISION NUMBER REVISION DATE 0 9/12 DESCRIPTION Initial release PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2012 Maxim Integrated 37 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.