MAX11322ATJ+ - Hytronics

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

19-6467; Rev 0; 9/12

Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part,

refer to www.maximintegrated.com/MAX11321-MAX11328.related.

General Description

The MAX11321–MAX11328 are 12-/10-bit with external

reference and 500kHz, full-linear-bandwidth, high-speed,

low-power, serial-output successive approximation reg-

ister (SAR) analog-to-digital converters (ADCs). The

MAX11321–MAX11328 provide external access to the

output of the integrated mux and ADC input, to simplify

conditioning. The MAX11321–MAX11328 include both

internal and external clock modes. These devices feature

scan mode in both internal and external clock modes. The

internal clock mode features internal averaging to increase

SNR. The external clock mode features the SampleSetK

technology, a user-programmable analog input channel

sequencer. The SampleSet approach provides greater

sequencing flexibility for multichannel applications while

alleviating significant microcontroller or DSP (controlling

unit) communication overhead.

External pins provide access to the output of the

multiplexer and ADC inputs to simplify multichannel sig-

nal conditioning. The internal clock mode features an inte-

grated FIFO allowing data to be sampled at high speeds

and then held for readout at any time or at a lower clock

rate. Internal averaging is also supported in internal clock

mode improving SNR for noisy input signals. The devices

feature analog input channels that can be configured to

be single-ended inputs, fully differential pairs, or pseudo-

differential inputs with respect to one common input. The

MAX11321–MAX11328 operate from a 2.35V to 3.6V sup-

ply and consume only 5.4mW at 1Msps.

The MAX11321–MAX11328 include AutoShutdownK,

fast wake-up, and a high-speed 3-wire serial interface.

The devices feature full power-down mode for optimal

power management. The 48MHz, 3-wire serial interface

directly connects to SPI, QSPIK, and MICROWIREM

devices without external logic.

Excellent dynamic performance, low voltage, low power,

ease of use, and small package size make these convert-

ers ideal for portable battery-powered data-acquisition

applications, and for other applications that demand low

power consumption and small space.

The MAX11321–MAX11328 are available in 32-pin, 5mm

x 5mm, TQFN packages and operate over the -40NC to

+125NC temperature range.

Benefits and Features

S Scan Modes, Internal Averaging, and Internal Clock

S 16-Entry First-In/First-Out (FIFO)

S SampleSet: User-Defined Channel Sequence with

Maximum Length of 256

S Input Pins

Any Combination of Single-Ended, Differential

and Pseudo-Differential Pairs Allowed

S Analog Multiplexer with True Differential

Track/Hold

 16-/8-/4-Channel Single-Ended

 12-/8-/4-Channel Fully-Differential Pairs

 15-/8-/4-Channel Pseudo-Differential Relative to

a Common Input

S Externally Accessible Multiplex Output and

ADC Input

S Two Software-Selectable Bipolar Input Ranges

 QVREF+/2, QVREF+

S Flexible Input Configuration Across All Channels

S High Accuracy

 Q1 LSB INL, Q1 LSB DNL, No Missing Codes

S 70dB SINAD Guaranteed at 100kHz Input

Frequency

S 1.5V to 3.6V Digital I/O Supply Voltage

S 2.35V to 3.6V Supply Voltage

S Extended Battery Life for Portable Applications

 5.4mW at 1Msps with 3V Supplies

 2µA Full-Shutdown Current

S External Differential Reference (1V to VDD)

S 16MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSP-

Compatible Serial Interface

S Wide -40NC to +125NC Operation

S Space-Saving, 32-Pin, 5mm x 5mm TQFN Packages

S 1Msps Conversion Rate, No Pipeline Delay

Applications

High-Speed Data Acquisition Systems

High-Speed Closed-Loop Systems

Industrial Control Systems

Medical Instrumentation

Battery-Powered Instruments

Portable Systems

SampleSet and AutoShutdown are trademarks of Maxim

Integrated Products, Inc.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National Semiconductor

Corp.

EVALUATION KIT AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

2Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

VDD to GND .............................................................-0.3V to +4V

AOP, AON, AIP, AIN, OVDD, AIN0–AIN13, CNVST/AIN14, REF+,

REF-/AIN15 to GND ....................................... -0.3V to the lower of

(VDD + 0.3V) and +4V

CS, SCLK, DIN, DOUT, EOC TO GND .......-0.3V to the lower of

(VOVDD + 0.3V) and +4V

DGND to GND ...................................................... -0.3V to +0.3V

Input/Output Current (all pins) ...........................................50mA

Continuous Power Dissipation (TA = +70NC)

TQFN (derate 34.4mW/NC above +70NC)..................2758mW

Operating Temperature Range ........................ -40NC to +125NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

TQFN

Junction-to-Ambient Thermal Resistance (BJA) ........... 29NC/W

Junction-to-Case Thermal Resistance (BJC) ...............1.7NC/W

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-

tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Notes 3 and 4)

Resolution RES 12 bit 12 Bits

Integral Nonlinearity INL Q1.0 LSB

Differential Nonlinearity DNL No missing codes Q1.0 LSB

Offset Error 1.2 Q3.0 LSB

Gain Error (Note 5) 0.02 Q5.5 LSB

Offset Error Temperature Coefficient OETC Q2 ppm/NC

Gain Temperature Coefficient GETC Q0.8 ppm/NC

Channel-to-Channel Offset Matching Q0.5 LSB

Line Rejection PSR (Note 6) 0.3 Q2 LSB/V

DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)

Signal-to-Noise Plus Distortion SINAD 70 71.9 dB

Signal-to-Noise Ratio SNR 70 72.3 dB

Total Harmonic Distortion

(Up to the 5th Harmonic) THD -83 -76 dB

Spurious-Free Dynamic Range SFDR 77 84 dB

Intermodulation Distortion IMD f1 = 99.2432kHz, f2 = 69.2139kHz -85 dB

Full-Power Bandwidth -3dB 30 MHz

-0.1dB 5

Full-Linear Bandwidth SINAD ≥ 70dB 0.5 MHz

3Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Crosstalk

-0.5dB below full-scale of 99.2432kHz

sine wave input to the channel being

sampled, apply full-scale 69.2139kHz

sine wave signal to all 15 nonselected

input channels.

-88 dB

CONVERSION RATE

Power-Up Time tPU Conversion cycle, external clock 2 Cycles

Acquisition Time tACQ 156 ns

Conversion Time tCONV

Internally clocked (Note 8) 5.9 µs

Externally clocked, fSCLK = 16MHz,

16 cycles (Note 8) 1000 ns

External Clock Frequency fSCLK 0.16 16 MHz

Aperture Delay 8 ns

Aperture Jitter RMS 30 ps

ANALOG INPUT

Input Voltage Range VINA

Unipolar, (single ended and pseudo-

differential) 0 VREF+

Bipolar

(Note 9)

Range bit set to 0 -VREF+/2 VREF+/2

Range bit set to 1 -VREF+ VREF+

Absolute Input Voltage Range AIN+, AIN- relative to GND -0.1 VREF+ + 0.1 V

Static Input Leakage Current IILA VAIN = VDD, GND -0.1 Q1.5 FA

Input Capacitance CAIN

During acquisition time;

RANGE bit = 0 (Note 10) 15

During acquisition time;

RANGE bit = 1 (Note 10) 7.5

EXTERNAL REFERENCE INPUT

REF- Input Voltage Range VREF- -0.3 +1 V

REF+ Input Voltage Range VREF+ 1 VDD + 50mV V

REF+ Input Current IREF+

VREF+ = 2.5V, fSAMPLE = 1Msps 36.7 FA

VREF+ = 2.5V, fSAMPLE = 0Msps 0.1

DIGITAL INPUTS (SCLK, DIN, CS, CNVST)

Input Voltage Low VIL VOVDD

O 0.25 V

Input Voltage High VIH VOVDD

O 0.75 V

Input Hysteresis VHYST VOVDD

O 0.15 mV

4Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage Current IIN VAIN = 0V or VDD Q0.09 Q1.0 FA

Input Capacitance CIN 3 pF

DIGITAL OUTPUTS (DOUT, EOC)

Output Voltage Low VOL ISINK = 200FAVOVDD

O 0.15 V

Output Voltage High VOH ISOURCE = 200FAVOVDD

O 0.85 V

Three-State Leakage Current ILCS = VDD -0.3 Q1.5 FA

Three-State Output Capacitance COUT CS = VDD 4 pF

POWER REQUIREMENTS

Positive Supply Voltage VDD 2.35 3.0 3.6 V

Digital I/O Supply Voltage VOVDD 1.5 3.0 3.6 V

Positive Supply Current IDD

fSAMPLE = 1Msps 1.8 2.5

mAfSAMPLE = 0Msps (1Msps devices) 1

Full shutdown 0.0015 0.006

Power Dissipation

Normal mode

(External

Reference)

VDD = 3V,

fSAMPLE = 1Msps 5.4

VDD = 2.35V,

fSAMPLE = 1Msps 3.8

AutoStandby

VDD = 3V,

fSAMPLE = 1Msps 2.6

VDD = 2.35V,

fSAMPLE = 1Msps 1.6

Full/

AutoShutdown

VDD = 3V 4.5 FW

VDD = 2.35V 2.1

TIMING CHARACTERISTICS (Figure 1) (Note 11)

SCLK Clock Period tCP Externally clocked conversion 62.4 ns

SCLK Duty Cycle tCH 40 60 %

SCLK Fall to DOUT Transition tDOT CLOAD =

10pF

VOVDD = 1.5V to 2.35V 4 16.5 ns

VOVDD = 2.35V to 3.6V 4 15

16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns

14th SCLK Fall to DOUT Disable CLOAD = 10pF, channel ID off 16 ns

SCLK Fall to DOUT Enable tDOE CLOAD = 10pF 14 ns

DIN to SCLK Rise Setup tDS 4 ns

SCLK Rise to DIN Hold tDH 1 ns

5Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CS Fall to SCLK Fall Setup tCSS 4 ns

SCLK Fall to CS Fall Hold tCSH 1 ns

CNVST Pulse Width tCSW See Figure 6 5 ns

CS or CNVST Rise to EOC Low

(Note 6) tCNV_INT See Figure 7, fSAMPLE = 1Msps 5.3 6.2 Fs

CS Pulse Width tCSBW 5 ns

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Notes 3 and 4)

Resolution RES 10 bit 10 Bits

Integral Nonlinearity INL ±0.4 LSB

Differential Nonlinearity DNL No missing codes ±0.4 LSB

Offset Error 0.7 ±1.2 LSB

Gain Error (Note 5) 0 ±1.5 LSB

Offset Error Temperature

Coefficient OETC ±2 ppm/NC

Gain Temperature Coefficient GETC ±0.8 ppm/NC

Channel-to-Channel Offset

Matching ±0.5 LSB

Line Rejection PSR (Note 6) 0.2 ±1.0 LSB/V

DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)

Signal-to-Noise Plus Distortion SINAD 61 61.5 dB

Signal-to-Noise Ratio SNR 61 61.5 dB

Total Harmonic Distortion

(Up to the 5th Harmonic) THD -82.5 -75 dB

Spurious-Free Dynamic Range SFDR 76 83.4 dB

Intermodulation Distortion IMD f1 = 99.2432kHz, f2 = 69.2139kHz -83 dB

Full-Power Bandwidth -3dB 30 MHz

-0.1dB 5 MHz

Full-Linear Bandwidth SINAD ≥ 61dB 0.5 MHz

6Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Crosstalk

-0.5dB below full-scale of 99.2432kHz

sine-wave input to the channel being

sampled; apply full-scale 69.2139kHz sine

wave signal to all 15 nonselected

input channels

-88 dB

CONVERSION RATE

Power-Up Time tPU Conversion cycle, external clock 2 Cycles

Acquisition Time tACQ 156 ns

Conversion Time tCONV

Internally clocked, fSAMPLE = 1Msps,

(Note 8) 5.9 µs

Externally clocked, fSCLK = 16MHz,

16 cycles (Note 8) 1000 ns

External Clock Frequency fSCLK 0.16 16 MHz

Aperture Delay 8 ns

Aperture Jitter RMS 30 ps

ANALOG INPUT

Input Voltage Range VINA

Unipolar (single-ended and pseudo

differential) 0 VREF+

Bipolar (Note 9) RANGE bit set to 0 -VREF+

+VREF+

RANGE bit set to 1 -VREF+ +VREF+

Absolute Input Voltage Range AIN+, AIN- relative to GND -0.1 VREF+

+ 0.1 V

Static Input Leakage Current IILA VAIN_ = VDD, GND -0.1 ±1.5 FA

Input Capacitance CAIN

During acquisition time,

RANGE bit = 0 (Note 10) 15

During acquisition time,

RANGE bit = 1 (Note 10) 7.5

EXTERNAL REFERENCE INPUT

REF- Input Voltage Range VREF- -0.3 +1 V

REF+ Input Voltage Range VREF+ 1VDD

+50mV V

REF+ Input Current IREF+

VREF+ = 2.5V, fSAMPLE = 1Msps 36.7 FA

VREF+ = 2.5V, fSAMPLE = 0Msps 0.1 FA

DIGITAL INPUTS (SCLK, DIN, CS, CNVST)

Input Voltage Low VIL VOVDD

O 0.25 V

7Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Voltage High VIH VOVDD

O 0.75 V

Input Hysteresis VHYST VOVDD

O 0.15 mV

Input Leakage Current IIN VAIN_ = 0V or VDD ±0.09 ±1.0 FA

Input Capacitance CIN 3 pF

DIGITAL OUTPUTS (DOUT, EOC)

Output Voltage Low VOL ISINK = 200FAVOVDD

O 0.15 V

Output Voltage High VOH ISOURCE = 200FAVOVDD

O 0.85 V

Three-State Leakage Current ILCS = VDD -0.3 ±1.5 FA

Three-State Output Capacitance COUT CS = VDD 4 pF

POWER REQUIREMENTS

Positive Supply Voltage VDD 2.35 3.0 3.6 V

Digital I/O Supply Voltage VOVDD 1.5 3.0 3.6 V

Positive Supply Current IDD

fSAMPLE = 1Msps 1.8 2.5

mAfSAMPLE = 0Msps (1Msps devices) 1

Full shutdown 0.0015 0.006

Power Dissipation

Normal mode

(external

reference)

VDD = 3V,

fSAMPLE = 1Msps 5.4

VDD = 2.35V,

fSAMPLE = 1Msps 3.8

AutoStandby

VDD = 3V,

fSAMPLE = 1Msps 2.6

VDD = 2.35V,

fSAMPLE = 1Msps 1.6

Full/

AutoShutdown

VDD = 3V 4.5 FW

VDD = 2.35V 2.1

TIMING CHARACTERISTICS (Figure 1) (Note 11)

SCLK Clock Period tCP Externally clocked conversion 62.4 ns

SCLK Duty Cycle tCH 40 60 %

SCLK Fall to DOUT Transition tDOT CLOAD =

10pF

VOVDD = 1.5V to 2.35V 4 16.5 ns

VOVDD = 2.35V to 3.6V 4 15

16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns

14th SCLK Fall to DOUT Disable CLOAD = 10pF, channel ID off 16 ns

SCLK Fall to DOUT Enable tDOE CLOAD = 10pF 14 ns

8Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11321/MAX11324/MAX11327) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design.

Parts are tested with MUX externally connected to the ADC input.

Note 3: Channel ID disabled.

Note 4: Tested in single-ended mode.

Note 5: Offset nulled.

Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V.

Note 7: Tested and guaranteed with fully differential input.

Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.

Maximum conversion time: 4.73Fs + N x 16 x tOSC_MAX

tOSC_MAX = 88.2ns, tOSC_TYP = 75ns.

Note 9: The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The

operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+.

Note 10: See Figure 3 (Equivalent Input Circuit).

Note 11: Guaranteed by characterization.

Figure 1. Detailed Serial-Interface Timing Diagram

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIN to SCLK Rise Setup tDS 4 ns

SCLK Rise to DIN Hold tDH 1 ns

CS Fall to SCLK Fall Setup tCSS 4 ns

SCLK Fall to CS Fall Hold tCSH 1 ns

CNVST Pulse Width tCSW See Figure 6 5 ns

CS or CNVST Rise to EOC Low

(Note 7) tCNV_INT See Figure 7, fSAMPLE = 1Msps 5.3 6.2 Fs

CS Pulse Width tCSBW 5 ns

tCSS tCH tCP tCSH

tDOT

tDS

tDH

tDOD

tDOE

SCLK

DIN

DOUT

16TH

CLOCK

1ST

CLOCK

tCSBW

9Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Typical Operating Characteristics

(MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, TA = +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX11321 toc01

DIGITAL OUTPUT CODE (DECIMAL)

INL (LSB)

307220481024

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 4096

fSAMPLE = 1Msps

GAIN ERROR

vs. TEMPERATURE

MAX11321 toc04

TEMPERATURE (°C)

GAIN ERROR (LSB)

1109580655035205-10-25

-2

-1

-3

-40 125

THD vs. ANALOG INPUT FREQUENCY

MAX11321 toc07

fIN (kHz)

THD (dB)

60 804020

-90

-85

-80

-95

0 100

fSAMPLE = 1Msps

SFDR vs. ANALOG INPUT FREQUENCY

MAX11321 toc08

fIN (kHz)

SFDR (dB)

806020 40

0 100

fSAMPLE = 1Msps

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX11321 toc02

DIGITAL OUTPUT CODE (DECIMAL)

DNL (LSB)

-0.5

0.5

1.0

-1.0

3072204810240 4096

fSAMPLE = 1Msps

HISTOGRAM FOR 30,000

CONVERSIONS

MAX11321 toc05

OUTPUT CODE (DECIMAL)

NUMBER OF OCCURENCES

20502049204820472046

5,000

10,000

15,000

20,000

25,000

30,000

35,000

fSAMPLE = 1Msps

30,000 CODE HITS

OFFSET ERROR

vs. TEMPERATURE

MAX11321 toc03

TEMPERATURE (°C)

OFFSET ERROR (LSB)

1109580655035205-10-25

-2

-1

-3

-40 125

fIN (kHz)

SNR AND SINAD (dB)

80604020

71.5

72.0

72.5

73.0

73.5

74.0

71.0

0 100

SNR AND SINAD

vs. ANALOG INPUT FREQUENCY

MAX11321 toc06

fSAMPLE = 1Msps

SNR

SINAD

10Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Typical Operating Characteristics (continued)

(MAX11322ATJ+/MAX11325ATJ+/MAX11328ATJ+, TA = +25°C, unless otherwise noted.)

SNR vs. INPUT RESISTANCE

MAX11321 toc09

RIN (I)

SNR (dB)

4500

4000

3500

3000

2500

2000

1500

1000

500

71.5

72.0

72.5

fSAMPLE = 1Msps

fIN = 100kHz

BUFFER BETWEEN AOP AND AIP

BUFFER BETWEEN AON AND AIN

AOP SHORTED TO AIP

AON SHORTED TO AIN

73.0

71.0

0 5000

SFDR vs. INPUT RESISTANCE

MAX11321 toc12

SFDR (dB)

RIN (I)

4500

4000

3500

3000

2500

2000

1500

1000

500

0 5000

fSAMPLE = 1Msps

fIN = 100kHz

BUFFER BETWEEN AOP AND AIP

BUFFER BETWEEN AON AND AIN

AOP SHORTED TO AIP

AON SHORTED TO AIN

SUPPLY CURRENT vs. TEMPERATURE

MAX11321 toc15

TEMPERATURE (°C)

IVDD (mA)

1109580655035205-10-25

1.5

2.0

2.5

fSAMPLE = 1Msps

VDD = 3.0V

3.0

1.0

-40 125

SNR vs. REFERENCE VOLTAGE

MAX11321 toc16

VREFP (V)

SNR (dB)

3.43.02.62.21.81.4

1.0

fSAMPLE = 1Msps

fIN = 100kHz

SINAD vs. INPUT RESISTANCE

MAX11321 toc10

SINAD (dB)

RIN (I)

4500

4000

3500

3000

2500

2000

1500

1000

500

0 5000

fSAMPLE = 1Msps

fIN = 100kHz

BUFFER BETWEEN AOP AND AIP

BUFFER BETWEEN AON AND AIN

AOP SHORTED TO AIP

AON SHORTED TO AIN

100kHz SINE-WAVE INPUT

(8192 POINT FFT PLOT)

MAX11321 toc13

FREQUENCY (kHz)

AMPLITUDE (dB)

45040035030025020015010050

-100

-80

-60

-40

-20

-120

0 500

AHD2 = -102.99dB

f = 200kHz

AHD3 = -86.69dB

f = 300kHz

fSAMPLE = 1Msps

fIN = 100kHz

THD vs. INPUT RESISTANCE

MAX11321 toc11

RIN (I)

THD (dB)

4500

4000

3500

3000

2500

2000

1500

1000

500

-85

-80

-75

fSAMPLE = 1Msps

fIN = 100kHz

BUFFER BETWEEN AOP AND AIP

BUFFER BETWEEN AON AND AIN

-70

-90

0 5000

AOP SHORTED TO AIP

AON SHORTED TO AIN

REFERENCE CURRENT

vs. SAMPLING RATE

MAX11321 toc14

fSAMPLE (ksps)

IREF (µA)

500

0 1000

11Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Pin Configurations

MAX11321

MAX11322

TQFN

4 CHANNEL

TOP VIEW

GND

VDD

DIN

GND

REF+

EOC

4567

2324 22 20 19 18

AIN0

AIN1

AIN

AIP

AON

AOP

GND SCLK

31 10

AIN2 GND

32 9

AIN3 GND

DOUT

26 15 CNVST

OVDD

25 16 REF-

GND GND

DGND

MAX11324

MAX11325

TQFN

8 CHANNEL

AIN5

AIN7

GND

AIN4

VDD

DIN

GND

REF+

EOC

4567

2324 22 20 19 18

AIN0

AIN1

AIN

AIP

AON

AOP

AIN6 SCLK

31 10

AIN2 GND

32 9

AIN3 GND

DOUT

26 15 CNVST

OVDD

25 16 REF-

GND GND

DGND

MAX11327

MAX11328

TQFN

16 CHANNEL

TOP VIEW

AIN5

AIN7

AIN8

AIN9

AIN10

AIN4

VDD

DIN

GND

REF+

EOC

4567

2324 22 20 19 18

AIN0

AIN1

AIN

AIP

AON

AOP

AIN6 SCLK

31 10

AIN2 AIN13

32 9

AIN3 AIN12

DOUT

26 15 CNVST/AIN14

OVDD

25 16 REF-/AIN15

AIN11 GND

DGND

12Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Pin Description

MAX11321

MAX11322

(4 CHANNEL)

MAX11324

MAX11325

(8 CHANNEL)

MAX11327

MAX11328

(16 CHANNEL)

NAME FUNCTION

1–10, 17, 19 5–10, 17, 19 17, 19 GND Ground

11 11 11 AOP Positive Output from the Multiplexer

12 12 12 AON Negative Output from the Multiplexer

13 13 13 AIP Positive Input to the ADC

14 14 14 AIN Negative Input to the ADC

15 15 — CNVST Active-Low Conversion Start Input

16 16 — REF- External Differential Reference Negative Input

18 18 18 REF+ External Positive Reference Input. Apply a reference voltage at

REF+. Bypass to GND with a 0.47FF capacitor.

20, 21 20, 21 20, 21 VDD Power-Supply Input. Bypass to GND with a 10FF in parallel with

a 0.1FF capacitors.

22 22 22 SCLK Serial Clock Input. Clocks data in and out of the serial interface.

23 23 23 CS

Active-Low Chip Select Input. When CS is low, the serial

interface is enabled. When CS is high, DOUT is high impedance

or three-state.

24 24 24 DIN Serial Data Input. DIN data is latched into the serial interface on

the rising edge of SCLK.

25 25 25 DGND Digital I/O Ground

26 26 26 OVDD Digital Power-Supply Input. Bypass to GND with a 10FF in

parallel with a 0.1FF capacitors.

27 27 27 DOUT

Serial Data Output. Data is clocked out on the falling edge of

SCLK. When CS is high, DOUT is high impedance or three-

state.

28 28 28 EOC End of Conversion Output. Data is valid after EOC is driven low

(internal clock mode only).

29–32 — — AIN0–AIN3 Analog Inputs

— — 29–32 , 1–10 AIN0–AIN13 Analog Inputs

— 29–32, 1–4 — AIN0–AIN7 Analog Inputs

— — 15 CNVST/

AIN14 Active-Low Conversion Start Input/Analog Input 14

— — 16 REF-/AIN15 External Differential Reference Negative Input /Analog Input 15

— — — EP Exposed Pad. Connect EP directly to GND plane for guaranteed

performance.

13Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Functional Diagrams

OSCILLATOR

SINGLE-

ENDED/

DIFFERENTIAL

BUS

ADC

SCLK

DIN

DOUT

CNVST

EOC

SCLK

REF+

AIN0

AOP AINAON AIP

AIN1

AIN2

AIN3

AIN(N-1)

AIN(N)

REF-

I/P

MUX

CONTROL LOGIC

AND

SEQUENCER

MAX11321–MAX11328

HIGH-INPUT IMPEDANCE

PGA/FILTER/BUFFER

14Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Detailed Description

The MAX11321–MAX11328 are 12-/10-bit with external

reference and industry-leading 500kHz, full linear band-

width, high-speed, low-power, serial output successive

approximation register (SAR) analog-to-digital converters

(ADC). These devices feature scan mode, internal aver-

aging to increase SNR, and AutoShutdown.

The external clock mode features the SampleSet technol-

ogy, a user-programmable analog input channel sequenc-

er. The user may define and load a unique sequencing

pattern into the ADC allowing both high- and low-frequen-

cy inputs to be converted without interface activity. This

feature frees the controlling unit for other tasks while lower-

ing overall system noise and power consumption.

The MAX11321–MAX11328 include internal clock. The

internal clock mode features an integrated FIFO, allowing

data to be sampled at high speed and then held for read-

out at any time or at a lower clock rate. Internal averaging

is also supported in this mode improving SNR for noisy

input signals. All input channels are configurable for sin-

gle-ended, fully differential or pseudo-differential inputs

in unipolar or bipolar mode. The MAX11321–MAX11328

operate from a 2.35V to 3.6V supply and consume only

5.4mW at 1Msps.

The MAX11321–MAX11328 include AutoShutdown, fast

wake-up, and a high-speed 3-wire serial interface. The

devices feature full power-down mode for optimal power

management.

Data is converted from analog voltage sources in a

variety of channel and data-acquisition configurations.

Microprocessor (FP) control is made easy through a 3-wire

SPI-/QSPI-/MICROWIRE-compatible serial interface.

AOP and AON are the output pins of the internal multi-

plexer while AIP and AIN are the ADC inputs which are all

accessible externally through pins. This allows flexibility

to the system designer to process all signals through one

PGA (programmable gain amplifier), filter or gain stage

Functional Diagrams (continued)

OSCILLATOR

SINGLE-

ENDED/

DIFFERENTIAL

BUS

MAX11321–MAX11328

ADC

SCLK

DIN

DOUT

CNVST

EOC

SCLK

REF+

AIN0

AOP AINAON AIP

AIN1

AIN2

AIN3

AIN(N-1)

AIN(N)

REF-

I/P

MUX

CONTROL LOGIC

AND

SEQUENCER

15Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1

Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance

in single-ended or differential configuration. The external

buffering stage should be designed to properly drive the

input sampling network of the ADC.

The external buffer should also have very high input

impedance (low-leakage current) to ensure best linearity.

If additional signal processing is not required, connect

AOP to AIP and AON to AIN. It is recommended to limit

the source impedance to not affect the sampling accu-

racy of the ADC causing degradation in linearity and total

harmonic distortion. See the SINAD vs. Input Resistance

graph in the Typical Operating Characteristics.

Input Bandwidth

The ADC’s input-tracking circuitry features a 500MHz

small-signal full-linear bandwidth to digitize high-speed

transient events and measure periodic signals with

bandwidths exceeding the ADC’s sampling rate by using

undersampling techniques. Anti-alias filtering of the input

signals is necessary to avoid high-frequency signals

aliasing into the frequency band of interest.

3-Wire Serial Interface

The MAX11321–MAX11328 feature a serial interface

compatible with SPI/QSPI and MICROWIRE devices. For

SPI/QSPI, ensure the CPU serial interface runs in master

mode to generate the serial clock signal. Select the SCLK

frequency of 48MHz or less, and set clock polarity (CPOL)

and phase (CPHA) in the control registers to the same

value. The MAX11321–MAX11328 operate with SCLK

idling high, and thus operate with CPOL = CPHA = 1.

Set CS low to latch input data at DIN on the rising edge

of SCLK. Output data at DOUT is updated on the falling

edge of SCLK. A high-to-low transition on CS samples

the analog inputs and initiates a new frame. A frame is

defined as the time between two falling edges of CS.

There is a minimum of 16 bits per frame. The serial data

input, DIN, carries data into the control registers clocked

in by the rising edge of SCLK. The serial data output,

DOUT, delivers the conversion results and is clocked out

by the falling edge of SCLK. DOUT is a 16-bit data word

containing a 4-bit channel address, followed by a 12-bit

conversion result led by the MSB when CHAN_ID is set

to 1 in the ADC Mode Control register (Figure 2a). When

CHAN_ID is set to 1 keep the SCLK high for at least 25ns

before the CS falling edge (Figure 2b). When CHAN_ID is

set to 0 (external clock mode only), the 16-bit data word

includes a leading zero and the 12-bit conversion result

is followed by 3 trailing zeros (Figure 2c). In the 10-bit

conversion result is followed by 5 trailing zeros.

23456781101112131415169

SCLK

DIN

DOUT MSB MSB-1 LSBLSB+1Ch[2] Ch[1] Ch[0]

DI[15] DI[1]

Ch[3]

DI[0]DI[14]

23456781101112131415169

SCLK

DIN

DOUT MSB MSB-1 LSBLSB+1Ch[2] Ch[1] Ch[0]

DI[15] DI[1]

Ch[3]

DI[0]

tQUIET > tSCLK

16Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 3. Equivalent Input Circuit

Single-Ended, Differential,

and Pseudo-Differential Input

The MAX11321–MAX11328 include up to 16 analog input

channels that can be configured on a pin-by-pin basis

to 16 single-ended inputs, 8 fully differential pairs, or 15

pseudo-differential inputs with respect to one common

input (REF-/AIN15 is the common input).

The analog input range is 0V to VREF+ in single-ended

and pseudo-differential mode (unipolar) and QVREF+/2 or

QVREF+ in fully differential mode (bipolar) depending on

the RANGE register settings. See Table 7 for the RANGE

Unipolar mode sets the differential input range from 0

to VREF+. If the positive analog input swings below the

negative analog input in unipolar mode, the digital output

code is zero. Selecting bipolar mode sets the differential

input range to QVREF+/2 or QVREF+ depending on the

RANGE register settings (Table 7).

In single-ended mode, the ADC always operates in uni-

polar mode. The analog inputs are internally referenced

to GND with a full-scale input range from 0V to VREF+.

Single-ended conversions are internally referenced to

GND (Figure 3).

The MAX11321–MAX11328 feature up to 15 pseudo

differential inputs by setting the PDIFF_COM bits in the

Unipolar register to 1 (Table 10). The 15 analog input sig-

nals inputs are referenced to a DC signal applied to the

REF-/AIN15.

Fully Differential Reference (REF+, REF-)

When the reference is used in fully differential mode

(REFSEL = 1), the full-scale range is set by the difference

between REF+ and REF-. The output code reaches its

maximum value if the input signal exceeds this reference

range.

ADC Transfer Function

The output format of the MAX11321–MAX11328 is straight

binary in unipolar mode and two’s complement in bipolar

mode. The code transitions midway between successive

integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure

4 and Figure 5 show the unipolar and bipolar transfer

function, respectively. Output coding is binary, with for

example, 1 LSB = VREF+/4096 in the 12-bit devices such

as the MAX11322/MAX11325/MAX11328.

Internal FIFO

The MAX11321–MAX11328 contain a FIFO buffer that can

hold up to 16 ADC results. This allows the ADC to handle

multiple internally clocked conversions without tying up

the serial bus. If the FIFO is filled and further conversions

are requested without reading from the FIFO, the oldest

ADC results are overwritten by the new ADC results. Each

Figure 2c. External Clock Mode Timing Diagram with CHAN_ID=0

DAC

COMPARATOR

DAC

AIP

AIN

(GND)

HOLD

23456781101112131415169

SCLK

DIN

DOUT 0LSBMSB] MSB-1 MSB-2

DI[15] DI[1]

DI[0]DI[14]

17Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 4. Unipolar Transfer Function for 12-Bit Resolution Figure 5. Bipolar Transfer Function for 12-Bit Resolution

result contains 2 bytes, with the MSB preceded by four

leading channel address bits. After each falling edge of

CS, the oldest available byte of data is available at DOUT.

When the FIFO is empty, DOUT is zero.

External Clock

Apply a soft reset when changing from internal to external

clock mode: RESET [1:0] = 10. The detailed operation

of external clock mode is dependent on the mode of

operation selected for the device using SCAN[3:0] bit

settings (see Table 3). In external clock mode the analog

inputs are sampled at the falling edge of CS. Serial clock

(SCLK) is used to perform the conversion.

Depending on the mode selected, the sequencer reads

in the channel to be converted from the serial data input

(DIN) at each frame (e.g. manual mode). The conversion

results are sent to the serial output (DOUT) at the next

frame.

In other external clocked modes the sequence of channel

to be converted is determined by the mode (SCAN[3:0])

selected in Table 3. See the Applications Information for

more detail on programming modes.

Internal Clock

Apply a soft reset when changing from internal to exter-

nal clock mode: RESET [1:0] = 10. The MAX11321–

MAX11328 operate from an internal oscillator, which is

accurate within Q15% of the 13.33MHz nominal clock

rate. Request internally timed conversions by writing the

appropriate sequence to the ADC Mode Control register

(Table 2).

The wake-up, acquisition, conversion, and shutdown

sequences are initiated through CNVST and are per-

formed automatically using the internal oscillator. Results

are added to the internal FIFO.

With CS high, initiate a scan by setting CNVST low for

at least 5ns before pulling it high (Figure 6). Then, the

MAX11321–MAX11328 wake up, scan all requested

channels, store the results in the FIFO, and shut down.

After the scan is complete, EOC is pulled low and the

results are available in the FIFO. Wait until EOC goes

low before pulling CS low to communicate with the serial

interface. EOC stays low until CS or CNVST is pulled low

again. Do not initiate a second CNVST before EOC goes

low; otherwise, the FIFO may become corrupted.

01234 FS

FFF

FFE

FFD

FFC

FFB

000

001

002

003

004

OUTPUT CODE (hex)

INPUT VOLTAGE (LSB)

FS = VREF+

ZS = 0

1 LSB = 4096

VREF+

FS -1.5 LSB -FS +FS

7FF

7FE

001

000

800

801

FFE

OUTPUT CODE (hex)

INPUT VOLTAGE (LSB)

ZS = 0

+FS = 2

VREF+

FFF

-FS = 2

-VREF+

1 LSB = 4096

VREF+

+FS -1.5 LSB-FS +0.5 LSB

18Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 7. Internal Conversions with SWCNV

Figure 6. Internal Conversions with CNVST

EOC

SCLK

DIN

DOUT

INTERNAL OSCILLATOR ONMODE CONTROL

SET MODE REG

READ DATA FROM FIFO

SET MODE REG

UP TO N INTERNALLY

CLOCKED ACQUISITIONS

AND CONVERSIONS

SWCNV = 1

tCNV_INT

(N = 1)

1 117 16

SCAN OPERATION AND

RESULTS STORED IN FIFO

INTERNAL

OSCILLATOR ON READ DATA FROM FIFO

SET MODE REG

READ DATA FROM FIFO

SET MODE REG

CNVST

1 1

EOC

SCLK

DIN

DOUT

UP TO N INTERNALLY

CLOCKED ACQUISITIONS

AND CONVERSIONS

tCSW

16 16

SCAN OPERATION AND

RESULTS STORED IN FIFO

tCNV_INT

19Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 8. Echo Back the Configuration Data

Alternatively, set SWCNV to 1 in the ADC Mode Control

edge instead of cycling CNVST (Table 2). For proper

operation, CS must be held low for 17 clock cycles to

guarantee that the device interprets the SWCNV setting.

Wait until EOC goes low before pulling CS low to com-

municate with the serial interface. Upon completing the

conversion, SWCNV is reset to 0 (Figure 7).

Analog Input

The MAX11321–MAX11328 produce a digital output that

corresponds to the analog input voltage as long as the

analog inputs are within the specified operating range.

Internal protection diodes confine the analog input volt-

age within the region of the analog power input rails

(VDD, GND) and allow the analog input voltage to swing

from GND - 0.3V to VDD + 0.3V without damaging the

device. Input voltages beyond GND - 0.3V and VDD +

0.3V forward bias the internal protection diodes. Limit the

forward diode current to less than 50mA to avoid dam-

age to the MAX11321–MAX11328.

ECHO

When writing to the ADC Configuration register, set

ECHO to 1 in ADC Configuration register to echo back

the configuration data onto DOUT at time n+1 (Figure 8,

Table 6).

Scan Modes

The MAX11321–MAX11328 feature nine scan modes

(Table 3).

Manual Mode

The next channel to be selected is identified in each SPI

frame. The conversion results are sent out in the next

frame. The manual mode works with the external clock

only. The FIFO is unused.

Repeat Mode

Repeat scanning channel N for number of times and

store all the conversion results in the FIFO. The number of

scans is programmed in the ADC Configuration register.

The repeat mode works with the internal clock only.

Custom_Int and Custom_Ext

In Custom_Int and Custom_Ext modes, the device scans

preprogrammed channels in ascending order. The chan-

nels to be scanned in sequence are programmed in the

Custom Scan0 or Custom Scan1 registers (see Table 12

and Table 13). A new I/P MUX is selected every frame

on the thirteenth falling edge of SCLK. Custom_Int works

with the internal clock. Custom_Ext works with the exter-

nal clock.

Standard_Int and Standard_Ext

In Standard_Int and Standard_Ext modes, the device

scans channels 0 through N in ascending order where

N is the last channel specified in the ADC Mode Control

thirteenth falling edge of SCLK. Standard_Int works with

the internal clock. Standard_Ext works with the external

clock.

Upper_Int and Upper_Ext

In Upper_Int and Upper_Ext modes, the device scans

channels N through 15/11/7/3 in ascending order where

N is the first channel specified in the ADC Mode Control

thirteenth falling edge of SCLK. Upper_Int works with the

internal clock. Upper_Ext works with the external clock.

SampleSet

The SampleSet mode of operation allows the definition

of a unique channel sequence combination with maxi-

mum length of 256. SampleSet is supported only in the

external clock mode. SampleSet is ideally suited for mul-

tichannel measurement applications where some analog

inputs must be converted more often than others.

DIN

t = n-1

DOUT

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

TURN ON ECHO

t = nt = n+1 t = n+2

20Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 9. SampleSet Use-Model Example

The SampleSet approach provides greater sequencing

flexibility for multichannel applications while alleviat-

ing significant microcontroller communication overhead.

SampleSet technology allows the user to exploit available

ADC input bandwidth without need for constant commu-

nication between the ADC and controlling unit. The user

may define and load a unique sequencing pattern into

the ADC allowing both high- and low-frequency inputs

to be converted appropriately without interface activity.

With the unique sequence loaded into ADC memory, the

pattern may be repeated indefinitely or changed at any

time.

For example, the maximum throughput of MAX11321–

MAX11328 is 1Msps. Traditional ADC scan modes allow

SAMPLE SET

(DEPTH = 256)

1ST CYCLE2

ND CYCLE3

RD CYCLE4

TH CYCLE5

TH CYCLE6

TH CYCLE7

TH CYCLE8

TH CYCLE9

TH CYCLE

POTENTIAL SampleSet PATTERN

CHANNEL:

ENTRY NO.:

AIN2/

AIN3

AIN2/

AIN3

AIN2/

AIN3 AIN2/

AIN3

AIN0 AIN1 AIN0 AIN0 AIN0 AIN0

25413713613513413313213113012912812712612512412312212112054321 255 256

AIN1 AIN1 AIN1 AIN1AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15

120 CONVERSIONS:

AIN0 AND AIN1

135

1122

123

124

125

256

120 CONVERSIONS:

AIN0 AND AIN1

SampleSet REPEATS: LENGTH = 256

100kHz

100 CYCLES

10kHz

10 CYCLES

1kHz

1 CYCLES

AIN0

AIN1

7911

23 25 27

810 12

tS = 1/fS = 1/3Msps = 333.33ns

fin = 100kHz

22 24 26

5µs

10µs

FULLY

DIFFERENTIAL

AIN0

ANALOG

INPUTS

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN11

AIN12

AIN13

AIN9

AIN10

21Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 1. Register Access and Control

Table 2. ADC Mode Control Register

up to 16-channel conversions in ascending order. In this

case, the effective throughput per channel is 1Msps/16

channel or 62.5ksps. The maximum input frequency that

the ADC can resolve (Nyquist Theorem) is 31.25kHz.

If all 16 channels must be measured, with some chan-

nels having greater than 31.25kHz input frequency, the

user must revert back to manual mode requiring con-

stant communication on the serial interface. SampleSet

technology solves this problem. Figure 9 provides a

SampleSet use-model example.

Averaging Mode

In averaging mode, the device performs the specified

number of conversions and returns the average for each

requested result in the FIFO. The averaging mode works

with internal clock only.

Scan Modes and Unipolar/Bipolar Setting

When the Unipolar or Bipolar registers are configured

as pseudo-differential or fully differential, the analog

input pairs are repeated in this automated mode. For

example, if N is set to 15 to scan all 16 channels and

all analog input pairs are configured for fully-differential

conversion, the ADC converts the channels twice. In this

case, the user may avoid dual conversions on input pairs

by implementing Manual mode or using Custom_Int or

Custom_Ext scan modes and only scan even (or odd)

channels (e.g. 0, 2, 4).

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT [10:0]

ADC Mode Control 0 DIN DIN DIN DIN DIN

ADC Configuration 1 0 0 0 0 DIN

Unipolar 1 0 0 0 1 DIN

Bipolar 1 0 0 1 0 DIN

RANGE 1 0 0 1 1 DIN

Custom Scan0 1 0 1 0 0 DIN

Custom Scan1 1 0 1 0 1 DIN

SampleSet 1 0 1 1 0 DIN

Reserved. Do not use. 1 1 1 1 1 DIN

BIT NAME BIT DEFAULT

STATE FUNCTION

REG_CNTL 15 0 Set to 0 to select the ADC Mode Control register

SCAN[3:0] 14:11 0001 ADC Scan Control register (Table 3)

CHSEL[3:0] 10:7 0000

Analog Input Channel Select register (Table 4).

See Table 3 to determine which modes use CHSEL[3:0] for the channel scan

instruction.

RESET[1:0] 6:5 00

RESET1 RESET0 FUNCTION

0 0 No reset

0 1 Reset the FIFO only (resets to zero)

1 0 Reset all registers to default settings (includes FIFO)

1 1 Unused

22Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 2. ADC Mode Control Register (continued)

Table 3. ADC Scan Control

BIT NAME BIT DEFAULT

STATE FUNCTION

PM[1:0] 4:3 00 Power Management Modes (Table 5). In external clock mode, PM[1:0] selects

between normal mode and various power-down modes of operation.

CHAN_ID 2 0

External Clock Mode. Channel address is always present in internal clock mode.

Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by

a 12-bit conversion result led by the MSB.

SWCNV 1 0

Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST

(internal clock mode only).

This bit is used for the internal clock mode only and must be reasserted in the ADC

mode control, if another conversion is desired.

— 0 0 Unused

SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION

0 0 0 0 Null

Continue to operate in the previously selected mode. Ignore data

on bits [10:0]. This feature is provided so that DIN can be held low

when no changes are required in the ADC Mode Control register.

Bits [6:3, 1] can be still written without changing the scan mode

properties.

0 0 0 1 Manual

The next channel to be selected is identified in each SPI frame. The

conversion results are sent out in the next frame.

Clock mode: External clock only

Channel scan/sequence: Single channel per frame

Channel selection: See Table 4, CHSEL[3:0]

Averaging: No

0 0 1 0 Repeat

Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16

conversion results for channel N.

Clock mode: Internal clock only

Channel scan/sequence: Single channel per frame

Channel selection: See Table 4, CHSEL[3:0]

Averaging: Can be enabled

0 0 1 1 Standard_Int

Scans channels 0 through N. The FIFO stores N conversion results.

Clock mode: Internal clock

Channel scan/sequence: N channels in ascending order

Channel selection: See Table 4, CHSEL[3:0] determines channel N

Averaging: Can be enabled

23Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 3. ADC Scan Control (continued)

SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION

0 1 0 0 Standard_Ext

Scans channels 0 through N

Clock mode: External clock only

Channel scan/sequence: N channels in ascending order

Channel selection: See Table 4, CHSEL[3:0] determines channel N

Averaging: No

0 1 0 1 Upper_Int

Scans channel N through the highest numbered channel. The FIFO

stores X conversion results where:

X = Channel 16–N 16-channel devices

X = Channel 8–N 8-channel devices

Clock mode: Internal clock only

Channel scan/sequence: Channel N through the highest numbered

channel in ascending order

Channel selection: See Table 4, CHSEL[3:0] determines channel N

Averaging: Can be enabled

0 1 1 0 Upper_Ext

Scans channel N through the highest numbered channel

Clock mode: External clock only

Channel scan/sequence: Channel N through the highest numbered

channel in ascending order

Channel selection: See Table 4, CHSEL[3:0] determines channel N

Averaging: No

0 1 1 1 Custom_Int

Scans preprogrammed channels in ascending order. The FIFO

stores conversion results for this unique channel sequence.

Clock mode: Internal clock only

Channel scan/sequence: Unique ascending channel sequence

Maximum depth: 16 conversions

Channel selection: See Table 12, Custom Scan0 register and Table

13, Custom Scan1 register

Averaging: Can be enabled

1 0 0 0 Custom_Ext

Scans preprogrammed channels in ascending order

Clock mode: External clock only

Channel scan/sequence: Unique ascending channel sequence

Maximum depth: 16 conversions

Channel selection: See Table 12, Custom Scan0 register and Table

13, Custom Scan1 register

Averaging: No

24Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 3. ADC Scan Control (continued)

Table 4. Analog Input Channel Select

SCAN3 SCAN2 SCAN1 SCAN0 MODE NAME FUNCTION

1 0 0 1 SampleSet

Scans preprogrammed channel sequence with maximum length of

256. There is no restriction on the channel pattern.

Clock mode: External clock only

Channel scan/sequence: Unique channel sequence

Maximum depth: 256 conversions

Channel Selection: See Table 4

Averaging: No

1 0 1 0 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

1 0 1 1 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

1 1 0 0 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

1 1 0 1 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

1 1 1 0 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

1 1 1 1 Null Continue to operate in the previously selected mode. Ignore data on

bits [10:0].

CHSEL3 CHSEL2 CHSEL1 CHSEL0 SELECTED CHANNEL (N)

0 0 0 0 AIN0

0 0 0 1 AIN1

0 0 1 0 AIN2

0 0 1 1 AIN3

0 1 0 0 AIN4

0 1 0 1 AIN5

0 1 1 0 AIN6

0 1 1 1 AIN7

1 0 0 0 AIN8

1 0 0 1 AIN9

1 0 1 0 AIN10

1 0 1 1 AIN11

1 1 0 0 AIN12

1 1 0 1 AIN13

1 1 1 0 AIN14

1 1 1 1 AIN15

25Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 6. ADC Configuration Register

Table 5. Power Management Modes

The MAX11321–MAX11328 communicate between the

internal registers and the external circuitry through the

SPI-/QSPI-compatible serial interface. Table 1 details the

detail the various functions and configurations.

For ADC mode control, set bit 15 of the register code

identification to zero. The ADC Mode Control register

determines when and under what scan condition the

ADC operates.

To set the ADC data configuration, set the bit 15 of the

Power-Down Mode

The MAX11321–MAX11328 feature three power-down

modes.

Static Shutdown

The devices shut down when the SPM bits in the ADC

Configuration register are asserted (Table 6). There are

two shutdown options:

U Full shutdown where all circuitry is shutdown.

U Partial shutdown where all circuitry is powered down

except for the internal bias generator.

AutoShutdown with External Clock Mode

When the PM_ bits in the ADC Mode Control register are

asserted (Table 5), the device shuts down at the rising

edge of CS in the next frame. The device powers up

again at the following falling edge of CS. There are two

available options:

U AutoShutdown where all circuitry is shutdown.

U AutoStandby where all circuitry are powered down

except for the internal bias generator.

AutoShutdown with Internal Clock Mode

The device shuts down after all conversions are complet-

ed. The device powers up again at the next falling edge

of CNVST or at the rising edge of CS after the SWCNV

bit is asserted.

PM1 PM0 MODE FUNCTION

0 0 Normal All circuitry is fully powered up at all times.

0 1 AutoShutdown

The device enters full shutdown mode at the end of each conversion. All circuitry

is powered down. The device powers up following the falling edge of CS. It takes 2

cycles before valid conversions take place. The information in the registers is retained.

1 0 AutoStandby

The device powers down all circuitry except for the internal bias generator. The part

powers up following the falling edge of CS. It takes 2 cycles before valid conversions

take place. The information in the registers is retained.

1 1 — Unused.

BIT NAME BIT DEFAULT

STATE FUNCTION

CONFIG_SETUP 15:11 N/A Set to 10000 to select the ADC Configuration register.

REFSEL 10 0

REFSEL VOLTAGE REFERENCE REF- CONFIGURATION

0 External single-ended AIN15 (for the 16-channel devices)

1 External differential REF-

AVGON 9 0 Set to 1 to turn averaging on. Valid for internal clock mode only.

Set to 0 to turn averaging off.

26Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 6. ADC Configuration Register (continued)

BIT NAME BIT DEFAULT

STATE FUNCTION

NAVG[1:0] 8:7 00

Valid for internal clock mode only.

AVGON NAVG1 NAVG0 FUNCTION

0 X X Performs 1 conversion for each requested

result.

1 0 0 Performs 4 conversions and returns the

average for each requested result.

1 0 1 Performs 8 conversions and returns the

average for each requested result.

1 1 0 Performs 16 conversions and returns the

average for each requested result.

1 1 1 Performs 32 conversions and returns the

average for each requested result.

NSCAN[1:0] 6:5 00

Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only.

NSCAN1 NSCAN0 FUNCTION

0 0 Scans channel N and returns 4 results.

0 1 Scans channel N and returns 8 results.

1 0 Scans channel N and returns 12 results.

1 1 Scans channel N and returns 16 results.

SPM[1:0] 4:3 00

Static power-down modes

SPM1 SPM0 MODE FUNCTION

0 0 Normal All circuitry is fully powered up at all times.

0 1 Full

Shutdown

All circuitry is powered down. The information

in the registers is retained.

1 0 Partial

Shutdown

All circuitry is powered down except for

the reference and reference buffer. The

information in the registers is retained.

1 1 — Reserved

ECHO 2 0

Set to 0 to disable the instruction echo on DOUT.

Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at

time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8).

— 1:0 0 Unused

27Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 7. RANGE Register (RANGE Settings Only Applies to Bipolar Fully Differential

Analog Input Configurations)

ADC Output as a Function

of Unipolar and Bipolar Modes

The ADC Scan Control register (Table 3) determines the

ADC mode of operation. The Unipolar and Bipolar regis-

ters in Table 10 and Table 11 determine output coding

and whether input configuration is single-ended or fully

differential.

Table 9 details the conversion output for analog inputs,

AIN0 and AIN1. The truth table is consistent for any other

valid input pairs (AINn/AINn+1). Table 8 shows the appli-

cable input signal format with respect to analog input

configurations.

CHSEL[3:0] is used for MANUAL, REPEAT,

STANDARD_EXT, STANDARD_INT, UPPER_EXT,

UPPER_INT modes of operation. CHSCAN[15:0] is used

for

CUSTOM_EXT and CUSTOM_INT

modes of operation.

SampleSet Mode of Operation

The SampleSet register stores the unique channel

sequence length. The sequence pattern is comprised of

up to 256 unique single-ended and/or differential conver-

sions with any order or pattern.

Patterns are assembled in 4-bit channel identifier nib-

bles as described in Table 4. Figure 10 presents the

SampleSet timing diagram. Note that two CS frames are

required to configure the SampleSet functionality. The

first frame indicates the sequence length. The second

frame is used to encode the channel sequence pattern.

After the SampleSet register has been coded (Table 14),

by the next falling edge of CS, the new SampleSet pattern

is activated (Figure 10). If the pattern length is less than

SEQ_LENGTH, the remaining channels default to AIN0. If

the select pattern length is greater than SEQ_LENGTH,

the additional data is ignored as the ADC waits for the ris-

ing edge of CS. If CS is asserted in the middle of a nibble,

the full nibble defaults to AIN0.

Upon receiving the SampleSet pattern, the user can

set the ADC Mode Control register to begin the conver-

sion process where data readout begins with the first

SampleSet entry. While the last conversion result is read,

the ADC can be instructed to enter AutoShutdown, if

desired. If the user wishes to change the SampleSet

length, a new pattern must be loaded into the ADC as

described in Figure 10.

BIT NAME BIT DEFAULT

STATE FUNCTION

RANGE_SETUP 15:11 N/A Set to 10011 to select the RANGE register

RANGE0/1 10 0 Set to 0 for AIN0/1: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN0/1: +VREF+, fS = 2(VREF+ - VREF-)

RANGE2/3 9 0 Set to 0 for AIN2/3: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN2/3: +VREF+, fS = 2(VREF+ - VREF-)

RANGE4/5 8 0 Set to 0 for AIN4/5: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN4/5: +VREF+, fS = 2(VREF+ - VREF-)

RANGE6/7 7 0 Set to 0 for AIN6/7: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN6/7: +VREF+, fS = 2(VREF+ - VREF-)

RANGE8/9 6 0 Set to 0 for AIN8/9: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN8/9: +VREF+, fS = 2(VREF+ - VREF-)

RANGE10/11 5 0 Set to 0 for AIN10/11: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN10/11: +VREF+, fS = 2(VREF+ - VREF-)

RANGE12/13 4 0 Set to 0 for AIN12/13: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN12/13: +VREF+, fS = 2(VREF+ - VREF-)

RANGE14/15 3 0 Set to 0 for AIN14/15: +VREF+/2, fS = VREF+ - VREF-

Set to 1 for AIN14/15: +VREF+, fS = 2(VREF+ - VREF-)

— 2:0 000 Unused

28Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 8. Analog Input Configuration and Unipolar/Bipolar Waveforms

Table 9. ADC Output as a Function of Unipolar/Bipolar Register Settings

CHANNEL SELECTION UNIPOLAR REGISTER BIPOLAR REGISTER FUNCTION

BIT NAME UCH0/1 PDIFF_COM BCH0/1

AIN0 Selection:

CHSEL[3:0] = 0000

CHSCAN0 = 1

0 0 0 AIN0 (binary, unipolar)

0 0 1 AIN0/1 pair (two’s complement, bipolar)

1 0 0 AIN0/1 pair (binary, unipolar)

1 0 1 AIN0/1 pair (binary, unipolar); Unipolar register

takes precedence

X 1 X AIN0 referred to REF-/AIN15 (binary, unipolar)

AIN1 Selection:

CHSEL[3:0] = 0001

CHSCAN1 = 1

0 0 0 AIN1 (binary, unipolar)

0 0 1 AIN0/1 pair (two’s complement, bipolar)

1 0 0 AIN0/1 pair (binary, unipolar)

1 0 1 AIN0/1 pair (binary, unipolar), Unipolar register

takes precedence

X 1 X AIN1 referred to REF-/AIN15 (binary, unipolar)

ANALOG INPUT

CONFIGURATION

SUPPORTED WAVEFORMS UNIPOLAR/BIPOLAR

REFSEL = 0 REFSEL = 1

Single-

Ended

Unipolar

(Binary

Coding)

Table 10. Unipolar Register:

Set desired channel(s) to 0

or PDIFF_COM to 1.

Counterpart Register

Table 11. Bipolar Register:

Set desired channel(s) to 0.

Fully

Differential

Unipolar

(Binary

Coding)

Table 10. Unipolar Register:

Set desired channel(s) to 1.

Counterpart Register

Table 11. Bipolar Register:

Set desired channel(s) to 0.

Fully

Differential

Bipolar

(2’s

Complement)

Table 11. Bipolar Register:

Set desired channel(s) to 1.

Counterpart Register

Table 10. Unipolar Register:

Set desired channel(s) to 0.

REF+

REF-

VIN+

VIN-VIN-

GND

REF+

RANGE: 1V TO V

REF+

RANGE: 1V TO V

-0.3V

REF+

IN+

VFS = REF+

RANGE = 0

VFS = 2REF+

RANGE = 1

VFS = REF+

RANGE = 0

VFS = 2REF+

RANGE = 1

REF+

REF-

IN+

GND, AIN15

PDIFF_COM = 1

REF+

RANGE: 1V TO V

REF+

RANGE: 1V TO V

-0.3V

REF+

IN+

REF+

REF-

VIN+

VIN-

GND

REF+

RANGE: 1V TO V

REF+

RANGE: 1V TO V

-0.3V

REF+

IN+

VIN-

(DC OFFSET

SINUSOID)

VIN-

(DC OFFSET

SINUSOID)

29Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 10. Unipolar Register

Table 11. Bipolar Register

BIT NAME BIT DEFAULT

STATE FUNCTION

UNI_SETUP 15:11 — Set to 10001 to select the Unipolar register.

UCH0/1 10 0 Set to 1 to configure AIN0 and AIN1 for pseudo-differential conversion.

Set to 0 to configure AIN0 and AIN1 for single-ended conversion.

UCH2/3 9 0 Set to 1 to configure AIN2 and AIN3 for pseudo-differential conversion.

Set to 0 to configure AIN2 and AIN3 for single-ended conversion.

UCH4/5 8 0 Set to 1 to configure AIN4 and AIN5 for pseudo-differential conversion.

Set to 0 to configure AIN4 and AIN5 for single-ended conversion.

UCH6/7 7 0 Set to 1 to configure AIN6 and AIN7 for pseudo-differential conversion.

Set to 0 to configure AIN6 and AIN7 for single-ended conversion.

UCH8/9 6 0 Set to 1 to configure AIN8 and AIN9 for pseudo-differential conversion.

Set to 0 to configure AIN8 and AIN9 for single-ended conversion.

UCH10/11 5 0 Set to 1 to configure AIN10 and AIN11 for pseudo-differential conversion.

Set to 0 to configure AIN10 and AIN11 for single-ended conversion.

UCH12/13 4 0 Set to 1 to configure AIN12 and AIN13 for pseudo-differential conversion.

Set to 0 to configure AIN12 and AIN13 for single-ended conversion.

UCH14/15 3 0 Set to 1 to configure AIN14 and AIN15 for pseudo-differential conversion.

Set to 0 to configure AIN14 and AIN15 for single-ended conversion.

PDIFF_COM 2 0 Set to 1 to configure AIN0–AIN14 to be referenced to one common DC voltage on

the REF-/AIN15. Set to 0 to disable the 15:1 pseudo differential mode.

— 1:0 000 Unused.

BIT NAME BIT DEFAULT

STATE FUNCTION

BIP_SETUP 15:11 — Set to 10010 to select the Bipolar register.

BCH0/1 10 0 Set to 1 to configure AIN0 and AIN1 for bipolar fully differential conversion.

Set to 0 to configure AIN0 and AIN1 for unipolar conversion mode.

BCH2/3 9 0 Set to 1 to configure AIN2 and AIN3 for bipolar fully differential conversion.

Set to 0 to configure AIN2 and AIN3 for unipolar conversion mode.

BCH4/5 8 0 Set to 1 to configure AIN4 and AIN5 for bipolar fully differential conversion.

Set to 0 to configure AIN4 and AIN5 for unipolar conversion mode.

BCH6/7 7 0 Set to 1 to configure AIN6 and AIN7 for bipolar fully differential conversion.

Set to 0 to configure AIN6 and AIN7 for unipolar conversion mode.

BCH8/9 6 0 Set to 1 to configure AIN8 and AIN9 for bipolar fully differential conversion.

Set to 0 to configure AIN8 and AIN9 for unipolar conversion mode.

BCH10/11 5 0 Set to 1 to configure AIN10 and AIN11 for bipolar fully differential conversion.

Set to 0 to configure AIN10 and AIN11 for unipolar conversion mode.

BCH12/13 4 0 Set to 1 to configure AIN12 and AIN13 for bipolar fully differential conversion.

Set to 0 to configure AIN12 and AIN13 for unipolar conversion mode.

BCH14/15 3 0 Set to 1 to configure AIN14 and AIN15 for bipolar fully differential conversion.

Set to 0 to configure AIN14 and AIN15 for unipolar conversion mode.

— 2:0 000 Unused.

30Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Table 12. Custom Scan0 Register

Table 13. Custom Scan1 Register

Table 14. SampleSet Register

BIT NAME BIT DEFAULT

STATE FUNCTION

CUST_SCAN0 15:11 — Set to 10100 to select the Custom Scan0 register.

CHSCAN15 10 0 Set to 1 to scan AIN15. Set to 0 to omit AIN15.

CHSCAN14 9 0 Set to 1 to scan AIN14. Set to 0 to omit AIN14.

CHSCAN13 8 0 Set to 1 to scan AIN13. Set to 0 to omit AIN13.

CHSCAN12 7 0 Set to 1 to scan AIN12. Set to 0 to omit AIN12.

CHSCAN11 6 0 Set to 1 to scan AIN11. Set to 0 to omit AIN11.

CHSCAN10 5 0 Set to 1 to scan AIN10. Set to 0 to omit AIN10.

CHSCAN9 4 0 Set to 1 to scan AIN9. Set to 0 to omit AIN9.

CHSCAN8 3 0 Set to 1 to scan AIN8. Set to 0 to omit AIN8.

— 2:0 000 Unused.

BIT NAME BIT DEFAULT

STATE FUNCTION

CUST_SCAN1 15:11 — Set to 10101 to select the Custom Scan1 register.

CHSCAN7 10 0 Set to 1 to scan AIN7. Set to 0 to omit AIN7.

CHSCAN6 9 0 Set to 1 to scan AIN6. Set to 0 to omit AIN6.

CHSCAN5 8 0 Set to 1 to scan AIN5. Set to 0 to omit AIN5.

CHSCAN4 7 0 Set to 1 to scan AIN4. Set to 0 to omit AIN4.

CHSCAN3 6 0 Set to 1 to scan AIN3. Set to 0 to omit AIN3.

CHSCAN2 5 0 Set to 1 to scan AIN2. Set to 0 to omit AIN2.

CHSCAN1 4 0 Set to 1 to scan AIN1. Set to 0 to omit AIN1.

CHSCAN0 3 0 Set to 1 to scan AIN0. Set to 0 to omit AIN0.

— 2:0 000 Unused.

BIT NAME BIT DEFAULT STATE FUNCTION

SMPL_SET 15:11 — Set to 10110 to select the SampleSet register.

SEQ_LENGTH 10:3 00000000

8-bit binary word indicating desired sequence length. The equation is:

Sequence length = SEQ_LENGTH + 1

00000000 = Sequence length = 1

11111111 = Sequence length = 256

Coding: Straight binary

Maximum length: 256 ADC conversions

— 2:0 — Unused.

31Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 10. SampleSet Timing Diagram

Applications Information

How to Program Modes

1) Configure the ADC (set the MSB on DIN to 1).

2) Program ADC mode control (set the MSB on DIN to 0)

to begin the conversion process or to control power

management features.

• IfADCmodecontroliswrittenduringaconversion

sequence, the ADC finishes the present conver-

sion and at the next falling edge of CS initiates its

new instruction.

• Ifconfigurationdata(MSBonDINisa1)iswritten

during a conversion sequence, the ADC finishes

the present conversion in the existing scan mode.

However, data on DOUT is not valid in following

frames until a new ADC mode control instruction

is coded.

Programming Sequence Flow Chart

See Figure 11 for programming sequence.

Layout, Grounding, and Bypassing

For best performance, use PCBs with a solid ground

plane. Ensure that digital and analog signal lines are

separated from each other. Do not run analog and digital

(especially clock) lines parallel to one another or digital

lines underneath the ADC package. Noise in the VDD,

OVDD, and REF affects the ADC’s perfor mance. Bypass

the VDD, OVDD, and REF to ground with 0.1FF and 10FF

bypass capacitors. Minimize capacitor lead and trace

lengths for best supply-noise rejection.

Choosing an Input Amplifier

It is important to match the settling time of the input

amplifier to the acquisition time of the ADC. The conver-

sion results are accurate when the ADC samples the

input signal for an interval longer than the input signal’s

worst-case settling time. By definition, settling time is the

interval between the application of an input voltage step

and the point at which the output signal reaches and

stays within a given error band centered on the result-

ing steady-state amplifier output level. The ADC input

sampling capacitor charges during the sampling cycle,

referred to as the acquisition period. During this acquisi-

tion period, the settling time is affected by the input resis-

tance and the input sampling capacitance. This error

can be estimated by looking at the settling of an RC time

constant using the input capacitance and the source

impedance over the acquisition time period. Figure 13

shows a typical application circuit. The MAX4430, offer-

ing a settling time of 37ns at 16-bit resolution, is an excel-

lent choice for this application.

Table 15 lists serveral recommended operational ampli-

fiers for MAX11321–MAX11328.

SCLK

DIN

ENTRY 1

WRITE SampleSet REGISTER

DEFINE SEQ_LENGTH

WRITE ADC MODE CONTROL

OR CONTINUE WITH ADDITIONAL

CONFIGURATION SETTINGS

ENTRY 2 ENTRY N = (SEQ_LENGTH)

DOUT

1 1 116

LOAD SampleSet PATTERN

TIME BETWEEN CS FALLING AND

RISING EDGE DEPENDS IN SEQ_LENGTH

32Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 11. ADC Programming Sequence

SELECT REFERENCE

UNIPOLAR

RANGE SELECT

EXTERNAL SINGLE-ENDED EXTERNAL DIFFERENTIAL

SINGLE-ENDED

OR DIFFERENTIAL

SELECT ADC

CONFIGURATION REGISTER

SET REFSEL BIT TO 0

SELECT ADC

CONFIGURATION REGISTER

SET REFSEL BIT TO 1

FIGURE OUT NUMBER

OF CHANNELS TO USE (N)

FOR EACH ADC CHANNEL

SINGLE-ENDED

PSEUDO-

DIFFERENTIAL

FULLY-

DIFFERENTIAL

SINGLE-ENDED

PSEUDO-

DIFFERENTIAL

UNIPOLAR OR

BIPOLAR

PSEUDO-DIFFERENTIAL SINGLE-ENDED BIPOLAR

SE, PsD/FD

SELECT UNIPOLAR AND

TO 1 FOR PSEUDO-

DIFFERENTIAL SELECTION

SELECT UNIPOLAR AND

BIPOLAR REGISTER SET PER

CHANNEL UCH{X}/{X+1}

AND BCH{X}/{X+1} TO 0 FOR

SINGLE-ENDED SELECTION

SELECT BIPOLAR REGISTER

SET PER CHANNEL

BCH{X}/{X+1} TO 1

FOR BIPOLAR FULLY

DIFFERENTIAL

SELECT UNIPOLAR

CHANNEL UCH{X}/{X+1}

TO 1 FOR UNIPOLAR

SELECT RANGE REGISTER SET PER CHANNEL

PAIR RANGE{X}/{X+1} TO 1 QVREF+

SELECT RANGE REGISTER SET PER CHANNEL

PAIR RANGE{X}/{X+1} TO 0 QVREF+/2

NEXT CHANNEL

SEE FIGURE 12

FOR EACH ADC CHANNEL

33Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 12. ADC Mode Select Programming Sequence

REPEAT

INTERNAL/EXTERNAL

CLOCK

STANDARD-INT

UPPER-INT

CUSTOM-INT

MANUAL

ADC CONFIGURATION REGISTER

SET AVG ON BIT TO 1

SET NAVG[1:0] TO N

ADC CONFIGURATION REGISTER

SET AVG ON BIT TO 1

SET NAVG[1:0] TO N

AVERAGE

ADC CONFIGURATION REGISTER

SET AVG ON BIT TO 1

SET NAVG[1:0] TO N

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0101

SET CHSEL[3:0] TO CHANNEL NUMBER

SELECT THE RIGHT SWCNV BIT

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0011

SET CHSEL[3:0] TO CHANNEL NUMBER

SELECT THE RIGHT SWCNV BIT

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0010

SET CHSEL[3:0] TO CHANNEL NUMBER

SELECT THE RIGHT SWCNV BIT

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0001

SET CHSEL[3:0] TO CHANNEL NUMBER

SELECT THE PM[1:0] BITS

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0100

SET CHSEL[3:0] TO CHANNEL NUMBER

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0110

SET CHSEL[3:0] TO CHANNEL NUMBER

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 1001

SET CHSEL[3:0] TO CHANNEL NUMBER

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 1000

SET CHSEL[3:0] TO CHANNEL NUMBER

SampleSet REGISTER

SET SEQ_DEPTH[7:0] TO SET

CHANNEL CAPTURE DEPTH

FOLLOW SampleSet REGISTER WITH

CHANNEL PATTERN OF THE SAME SIZE

AS SEQUENCE DEPTH

AVERAGE

ADC CONFIGURATION REGISTER

SET AVGON BIT TO 1

SET NAVG[1:0] TO N

SET CUSTOM Scan0 REGISTER

SET CUSTOM Scan1 REGISTER

SET CUSTOM Scan0 REGISTER

SET CUSTOM Scan1 REGISTER

ADC CONFIGURATION REGISTER

SET NSCAN[1:0] FOR SCAN COUNT

ADC MODE CONTROL REGISTER

SET SCAN[3:0] TO 0111

SET CHSEL[3:0] TO CHANNEL NUMBER

SELECT THE RIGHT SWCNV BIT

INTERNAL EXTERNAL

YES

NO NO

YES

STANDARD-EXT

UPPER-EXT

CUSTOM-EXT

SampleSet

34Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 13. Typical Application Circuit

Choosing a Reference

For devices using an external reference, the choice of the

reference determines the output accuracy of the ADC.

An ideal voltage reference provides a perfect initial accu-

racy and maintains the reference voltage indepen dent

of changes in load current, temperature, and time. The

following parameters need to be considered in selecting

a reference:

U Initial voltage accuracy

U Temperature drift

U Current source capability

U Current sink capability

U Quiescent current

U Noise. See Table 16.

MAX4430

MAX11321–MAX11328

MAX6126

MAX4430

+5V

CPU

SCLK

MISO

MOSI

INPUT 1 4

VDC

100pF

500I

-5V

500I

10I

0.1µF 10µF

0.1µF

470pF

10µF

INPUT 2

COG

CAPACITOR

COG

CAPACITOR

0.1µF 10µF

1µF 0.1µF

+5V

0.1µF

VDD

AGND

AIN0

AIN1

AIN15

REF

OUTF

OUTS

GNDS 1

3GND

DIN

DOUT

SCLK

OVDD

AON

AOP

AIP

AIN

GND

VOVDD

0.1µF 10µF

+5V

INPUT 2 4

VDC

100pF

500I

-5V

500I

10I

0.1µF 10µF

35Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nulled. The static

linearity parameters for the MAX11321–MAX11328 are

measured using the end-points method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1 LSB. A DNL

error specification of 1 LSB or less guarantees no miss-

ing codes and a monotonic transfer function.

Signal-to-Noise Ratio

Signal-to-noise ratio is the ratio of the amplitude of the

desired signal to the amplitude of noise signals at a

given point in time. The larger the number, the better. The

theoretical minimum analog-to-digital noise is caused by

quantization error and results directly from the ADC’s

resolution (N bits):

SNR = (6.02 x N + 1.76) dB

In reality, there are other noise sources besides quantiza-

tion noise, including thermal noise, reference noise, clock

jitter, etc. Therefore, SNR is computed by taking the ratio

of the RMS signal to the RMS noise, which includes all

spectral components minus the fundamental, the first five

harmonics, and the DC offset.

Total Harmonic Distortion

Total harmonic distortion (THD) is expressed as:

2222

2345

VVVV

THD 20 log V



+++



= ×





where V1 is the fundamental amplitude, and V2 through V5

are the amplitudes of the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the

RMS amplitude of the fundamental (maximum signal

component) to the RMS value of the next largest distor-

tion component.

Full-Power Bandwidth

Full-power bandwidth is the frequency at which the input

signal amplitude attenuates by 3dB for a full-scale input.

Table 15. Recommended Input Amplifiers

Table 16. Recommended References

REFERENCE CHANNELS TYPICAL APPLICATION

MAX4430 1 Dual supply, low noise, low distortion, high bandwidth

MAX4432 2 Dual supply, low noise, low distortion, high bandwidth

MAX4454 4 Low power, single, supply, low cost

MAX4418 4 Low noise, low power, high bandwidth

MAX44263 2 Low power, precision, CMOS input, rail-to-rail I/O

REFERENCE TYPICAL APPLICATION

MAX6126 Ultra-high precision, ultra-low noise, wide temperature range

MAX6033 Ultra-high precision, low noise, low power, wide temperature range

MAX6043 High precision, wide temperature range

MAX6129B Low cost, ultra-low power

MAX6003 Low cost, low power

36Maxim Integrated

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Full-Linear Bandwidth

Full-linear bandwidth is the frequency at which the

signal-to-noise plus distortion (SINAD) is more than 70dB

(MAX11322/MAX11325/MAX11328).

Intermodulation Distortion

Any device with nonlinearities creates distortion products

when two sine waves at two different frequencies (f1 and

f2) are input into the device. Intermodulation distortion

(IMD) is the total power of the IM2 to IM5 intermodulation

products to the Nyquist frequency relative to the total

input power of the two input tones, f1 and f2. The indi-

vidual input tone levels are at -6dBFS.

Note: All devices are specified over the -40°C to +125°C temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Ordering Information

Package Information

For the latest package outline information and land patterns (foot-

prints), go to www.maximintegrated.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

PART PIN-PACKAGE BITS SPEED (Msps) NO. OF CHANNELS

MAX11321ATJ+ 32 TQFN-EP* 10 1 4

MAX11322ATJ+ 32 TQFN-EP* 12 1 4

MAX11324ATJ+ 32 TQFN-EP* 10 1 8

MAX11325ATJ+ 32 TQFN-EP* 12 1 8

MAX11327ATJ+ 32 TQFN-EP* 10 1 16

MAX11328ATJ+ 32 TQFN-EP* 12 1 16

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

32 TQFN-EP T3255+5 21-0140 90-0013

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 37

MAX11321–MAX11328

1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 9/12 Initial release —