Philips Components APY 252 SENSOR blue binder, tab 11 2.1 GENERAL INFORMATION This introduction describes a novel two channel passive infrared (PIR} movement sensing system comprising a RPY 222 interdigitated sensor and pattern recognition signal processing circuitry. The characteristics of the overall system provide reliable detection with excellent false trigger immunity. The effects of potential false trigger sources including changing ambient temperature, thermal! disturbances, random noise spikes and interference are shown to be greatly reduced. Currently the vast majority of passive infrared movement sensing units are single-channel systems employing compensated dual element sensors such as the RPW100/KRX10. The false trigger performance of these systems is essentially determined by the level of incidence of internaily and externally generated random noise spike phenomena. These unwanted events can be effectively eliminated by using two identical channels in paraliel to provide more information. Since the probability of random events occurring simultaneously in both channels is extremely low, the overall performance can be substantially improved. A suitable sensor is our RPY222 which comprises two separate series-connected dual element sensors (Fig.1) in a single 4 lead TO-39 encapsulation. The interdigitated electrode construction (Patent No. GB 2170952A) has been designed so as to provide almost coincident signals from each channel to give further options in the design of the associated signal processing (Patent No. GB 217424A). PIR INTRUDER ALARM SYSTEMS A block diagram of a simple passive infrared intruder alarm system is shown in Fig.2. \t basically consists of: A Fresnel lens array. A PIR sensor Two gain stages using bandpass amplifiers. A window comparator determined by positive and negative thresholds. A logic circuit to perform simpie signal processing techniques, as discussed below. An alarm relay and output. moaogrmn FRONT END CIRCUIT DESIGN A circuit suitable for use with our Fresnel lens array and a single-channel sensor is shown in Fig.3. The amplifier frequency response requirements are defined by the range and speed of the intruder, the frequency characteristics of the sensor and the zone dimensions of the associated Fresnel optics. These factors have been taken into account in the design to give optimum performance. The sensor is operated in a source follower configuration and followed by two operational amplifer gain stages which provide 66 dB of gain and defined 3 dB bandwidth of 0.5 Hz to 5 Hz. Table 1 lists the cornponent values that give the above frequency response and gain characteristics. The window comparator threshold levels of +0.5 V and 0.5 V are established by the potential divider chain formed by the resistor network R8, RQ and R10. When the input signal exceeds these preset levels the appropriate comparator switches from a LOW to a HIGH state. Di PH I Li PS February 1989 1INTRODUCTION RPY222 SENSOR Resistor Value Capacitor Value (2) R1 1M2 C1 22 pF R2 820k C2 100 nF R3 4k7 C3 10 uF R4 120k c4 10 pF R5 120k C5 2.2 nF R6 120 k C6 10 wF R7 3 M3 C7 1 pF R8 - 56k c8 10 nF RQ 27 k - R10 56k R11 56 k R12 100 k Table 1 In a two channel unit this circuitry has to be duplicated to provide two completely independent signal paths with the four outputs corresponding to +A, A, +B and B. 2.2 SIGNAL PROCESSING TECHNIQUES FOR SINGLE CHANNEL SYSTEMS Three principal techniques are currently used for processing output signals from the front end comparators: a. Single-shot signal processing. b. Dual-polarity signal processing. c. Pulse-count signal processing. a. Single-shot signal processing This option can be easily implemented by logically combining the comparator outputs to give an alarm condition when either the positive OR the negative threshold level comparator switches from a LOW to HIGH state. The technique can be prone to false triggers due to electrical noise in the front end circuitry, thermal effects and external factors such as radio frequency interference. b. Dual-polarity signal processing This technique relies on the fact that an intruder traversing a zone will generate a dual polarity signal with a characteristic time between peaks. Following a comparator transition the corresponding output is held high for a set time period. Both outputs are connected to the inputs of an AND gate and an alarm condition initiated when both inputs are simultaneously HIGH. To some extent this method reduces the problems associated with single-shot signal processing, but electrical, thermal and external disturbances often give rise to dual-polarity signals. c. Pulse-count signal processing This system will count N comparator output pulses within a predetermined time period before raising an alarm condition. The number of pulses, N, to give optimum performance is a function of the zone coverage and the associated optics. False triggers due to non-intruder type disturbances are now greatly improved but an intruder with knowledge of the detector unit employed could defeat the system. 2 February 1989 PH i Li PSINTRODUCTION RPY222 SENSOR 3.1 3.2 TWO-CHANNEL SIGNAL PROCESSING Present two-channel detection systems generate an alarm condition in response to the occurrence of an electrical output on both channels within a predetermined period of time. For increased false trigger immunity, systems can incorporate additional circuitry to ignore substantially simultaneous signals from both of the sensor channels. In general these systems do not make full use of the additional data which is available from two channel sensors. PATTERN RECOGNITION SIGNAL PROCESSING The additional information provided by a two-channel sensor can effectively be used by employing simple pattern recognition techniques. A block diagram of the intruder alarm unit is shown in Fig.4. The system consists of three main sections: a. Front end circuit. Two stages of amplification and filtering which are duplicated to provide independent signal paths for each channel of the sensor. b. Signal processing. Output signals from the comparators are processed by a method known as Pattern Recognition. c. Alarm unit. An alarm condition raised by the signal processing section is used to drive a warning light and a relay. Our patented signal processing, by the method of Pattern Recognition relies on the generation of unique pulse sequences at the comparator outputs. The sequence information occurring within a predetermined period of time is used to distinguish between intruder and non-intruder type signatures. Movement within the unit's field of view will generate a pulse train containing unique patterns. To allow sufficient time for all of the data to be gathered and processed a delay has been incorporated which is triggered on the leading edge of the first pulse and has a duration of 5 seconds. INTRUDER PATTERNS With this system eight intruder patterns have been defined, each of which comprises three sections. During an intruder disturbance at least one of these patterns occurs. The number of complete patterns depends on the intruders speed and the units optical system. Patterns corresponding to movement of an intruder are tabulated in Table 2. If the two channels are labelled A and B respectively the positive peaks are denoted by +A and +B and negative peaks are denoted by A and B. Examples of timing diagrams corresponding to typical intruder events are shown in Figs.5a and 5b. Pattern First in Second in Third in number sequence sequence sequence 1 +A +A and +B +A 2 +A +A and +B +B 3 +B +B and +A +A 4 +B +B and +A +B 5 -A A and B A 6 -A A and B B 7 B B and -A A 8 B B and A B Table 2 Di PH i LI PS February 1989 3INTRODUCTION RPY222 SENSOR 3.3. FALSE TRIGGER PATTERNS a. Thermal patterns Changes in ambient temperature result in either random or no pattern being generated. Usually thermal patterns are not capable of generating more than one section of an intruder type signature and are therefore incompiete. Exarnples of timing diagrams corresponding to air turbulence and ambient temperature change situations are shown in Figs.5c and 5d respectively. b. Radio Frequency interference (Rfi) When subjected to 900 MHz radiated interference (6 mW into 50 2 at a distance of 15 cm) random signal outputs are produced. Again these comparator transitions are only capable of triggering the first in sequence of the intruder signature and do not therefore initiate an alarm condition. An example of this behaviour is shown in the timing diagrams shown in Fig.5e. 4. CIRCUIT REALISATION A block diagram of our Pattern Recognition signal processing circuit is shown in Fig.6. The biocks describe the major sections of the circuit in relation to the following functions: a. THE DETECTION OF INTRUDER PATTERNS FOR BOTH CHANNELS When the first in sequence of an intruder pattern is detected: (i) aSET-RESET (S-R) type flip-flop remembers that event (ii) the next block to look for the second in sequence is enabled When the second in sequence of an intruder pattern is detected: (i) an S-R type flip-flop remembers that event (ii) the next block to look for the third in sequence is enabled When the third in sequence of an intruder pattern is detected: an intruder sequence memory is SET. b. END OF SEQUENCE DETECTION When all of the comparator outputs go LOW: (i) an end of sequence has been detected (ii) the first and second in sequence flip-flops are RESET. c. TIMING PERIOD When the first comparator in response to a disturbance goes HIGH: the transition is detected and the timer is triggered. Following the detection of such a disturbance, the flip-flops will be RESET when all four comparator outputs are LOW. During the 5 second time delay: (i) the timers trigger is disabled to prevent retriggering (ii) the alarm contro! unit output is disabled When the 5 second time delay has expired: (i) the alarm control unit output is enabled (ii) the intruder sequence memory is RESET 4 February 1989 PH I Li PSINTRODUCTION RPY222 SENSOR d. ALARM CONTROL UNIT (ACU) This monitors the outputs of both the intruder memory and system timer (i) if an intruder sequence has been observed AND the time delay has expired then an alarm condition is raised (ii) otherwise no alarm condition is raised The numbers in Fig.6 refer to the waveforms at these points in the timing diagrams (see Figs.5a, 5b, 5c, 5d and 5e). Each diagram has a duration of 5 seconds. 4.1. CIRCUIT SCHEMATIC Our Pattern Recognition signal processing circuit schematic is shown in Fig.7. This circuit consists of: a. 48 logic gates b. a 555 timer with associated timing components c. analarm RESET switch At power up all of the flip-flop outputs are automatically set LOW, and the front end circuit and detector time constants require the system to be RESET after an initial stabilisation period. The descriptions of the logic gate functions are as follows: a. Detection of the first in sequence of intruder type patterns as listed from 1 to 4 in Table 2 is achieved by using gates: 6a, 5a, la and tb Gates 1a and 1b make up the S-R type flip-flop (#/f1) b. Detection of the second in sequence of intruder patterns 1 to 4: 7a, 9a, 1c and 1d Gate 9a enables the second in sequence to be looked for following a f/f1 HIGH state transition, i.e. only after the detection of the first in sequence. Gates 1c and 1d make up the S-R type flip-flop (f/f2) c. Detection of the third in sequence of intruder patterns 1 to 4: 4d, 6a and 12a Gate 12a enables the third in sequence to be looked for when the output of 9a switches to a LOW state. d. Detection of the first in sequence of intruder type patterns as listed from 5 to 8 in Table 2 is achieved by gates: 6b, 5b, 2a and 2b Gates 2a and 2b make up the S-R type flip-flop (f/f3) e. Detection of the second in sequence of intruder patterns 5 to 8: 7b, 9b, 2c and 2d Gate 9b enables the second in sequence to be looked for following a f/f3 HIGH state transition, ie only after the detection of the first in sequence. ~ Gates 2c and 2d make up the S-R type flip-flop (#/f4) PH i LI DBS February 1989 5INTRODUCTION RPY222 SENSOR f. Detection of the third in sequence of intruder patterns 5 to 8: 4c, 6b and 12b -- Gate 12b enables the third in sequence to be looked for when the output of 9b switches to a LOW state g. The intruder sequence memory, gates 3c and 3d is SET when any of the patterns 1 to 8 are seen as determined by gates 6d and 9c. h. Timer triggering is achieved by use of gates: 11a, lib, 11c, 13a and 1014 (555 timer) ~ Gates 11a, 11b, and 11c look for the first leading edge. Gate 13a is the trigger enable whereby the timer output, pin 3 is inverted via gate 8c and fed into the control input of 13a disabling the trigger (pin 2) when the timer is on and enabling the trigger again when the time delay has expired. i. End of sequence detection is determined via gates: 11a, 11b, 11, 8d, 12c, 12d, 11d, and 5d Gates 11a, 11b, and 11c are employed here to look for no activity on the comparator output lines. Gates 8d, 12c, 12d, 11d, and 5d look at the outputs of the S-R type flip-flops used to record the first in sequence of intruder patterns of both channels to see if they need to be RESET. j. Alarm control unit: 10a, 10b, 10c, 10d, 13b, 13, 8c, 9d, 8a, 8b Gates 8c and 9d gives an output from the ACU when the time delay has expired and the logical condition of an intruder exists. Gates 8a and 8b holds an alarm condition if it appears at the outputs of the ACU. This can be RESET by a manually controlled push to break switch. SUMMARY The system described has been practically walk-tested for a wide range of intruder speeds at distances of up to 12 metres. Detection performance comparable with that of simple single-channel systems has been demonstrated. A prototype unit has been subjected to a number of potential false trigger sources including thermal disturbances and RF interference. The system provides considerably enhanced immunity to these phenomena which will result in a lower incidence of false triggers. The logic circuit, which comprises a timer and a number of logic gates, may be implemented at a low cost with a single chip semi-custom integrated circuit. 6 February 1989 PH i Li PSINTRODUCTION RPY222 SENSOR | JOSUaS JBUUEYD-OM] ZTZZAdY {O UOITeINBIyUOd JUaWAa!y | Bly PHILIPS February 1989 7 oLzew HNDID Juajeainby uoneunbiyuos yUuaWa/y ~--7F 7 zZ ( TT I 1 ; [ : | L 1 J. & } vd & +L Zz S =L * g jeuueyd Ly +7 LS r+ z x A M x V |auueyd S > WY _M ft 4 4) co 4 ao- LO Lo 4 ods LC) 1DWaISAS We|e paseujul aaisseg 7614 LLZEW Q1OHS324HL JAILVOANT | |_| SHaHdIdWV SSVdONV8 YOSNS3S inn |_} sinowto HOLVUVdW0d | wuviv 91907 MOGNIM | | YAQGNYLN! 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