TJA1081TS,112 - NXP Semiconductors

1. General description

The TJA1081 is a FlexRay node transceiver that is fully compliant with the FlexRay

electrical physical layer specification V2.1 Rev. A (see Ref. 1). In addition, it incorporates

features and parameters included in V3.0.1 (see Ref. 2 and Section 14). It is primarily

intended for communication systems from 1 Mbit/s to 10 Mbit/s, and provides an

advanced interf ace between the pr oto co l con tr olle r an d th e ph ysic al bu s in a FlexRa y

network.

The TJA1081 features enhan ced low-power modes, optimized for ECUs that are

permanen tly co nn ec te d to the ba tt er y.

The TJA1081 provides differential transmit capability to the network and differential

receive capability to the FlexRay controller. It offers excellent EMC performance as well as

high ESD protection.

The TJA1081 actively monitors system per formance using dedicated error and status

information (that can be read by any microcontroller), along with internal voltage and

temperature monitoring.

The TJA1081 supports mode control as used in the TJA1080A (s ee Ref. 3).

2. Features and benefits

2.1 Optimized for time triggered communication systems

Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1)

Automotive product qualification in accordance with AEC-Q100

Data transfer up to 10 Mbit/s

Support of 60 n s min im um bit tim e

Very low ElectroM ag n et ic Emission (EME) to su pp or t unsh ield ed cab l e

Diffe rential receiver with wide common-mode range for high ElectroMagnetic Immunity

(EMI)

Auto I/O level adaptation to host controller supply voltage VIO

Can be used in 14 V and 42 V powe re d sys te ms

Instant shut-down interface (via BGE pin)

Independent power supply ramp-up for VBAT, VCC and VIO

2.2 Low power management

Low power manag em e nt including inhibit switch

Very low current in Sleep and Standby modes

TJA1081

FlexRay node transceiver

Rev. 4 — 24 February 2011 Product data sheet

Product data sheet Rev. 4 — 24 February 2011 2 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

Local and remote wake-up

Supports remote wake-up via dedicated data frames

Wake-up source recognition

2.3 Diagnosis (detection and signalling)

Overtemperature de tection

Short-circuit on bus lines

VBAT power-on flag (first battery connection and cold start)

Pin TXEN and pin BGE clamping

Undervoltage detectio n on pin s VBAT, VCC and VIO

Wake source indication

2.4 Protection

Bus pins protected against ±8 kV HBM ESD pulses

Bus pins protected against transients in automotive environment (according to

ISO 7637 class C)

Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground

Fail-silent behavior in the event of an und ervoltage on pins VBAT, VCC or VIO

Passive behavior of bus lines while the transceiver is not powered

2.5 Functional classes according to FlexRay electrical physical layer

specification (see Ref. 1)

Bus driver voltage regulator control

Bus driver - bus guardian control interface

Bus driver logic level adaptation

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

TJA1081TS SSOP16 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

Product data sheet Rev. 4 — 24 February 2011 3 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

4. Block diagram

Fig 1. Block diagram

VIO

VBAT

INH

SIGNAL

ROUTER

TRANS-

MITTER

BUS

FAILURE

DETECTION

NORMAL

RECEIVER

INPUT

VOLTAGE

ADAPTATION

OUTPUT

VOLTAGE

ADAPTATION STATE

MACHINE

015aaa066

TJA1081

VCC

VIO

TXD

RXD RXDINT

RXDINT

VBAT

ERRN

RXEN

WAKE-UP

DETECTION

OSCILLATOR

UNDERVOLTAGE

DETECTION

WAKE

OVER-

TEMPERATURE

DETECTION

LOW-

POWER

RECEIVER

TXEN

BGE

STBN

316 11

GND

Product data sheet Rev. 4 — 24 February 2011 4 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 2. Pin configuration

TJA1081

INH VCC

EN BP

VIO BM

TXD GND

TXEN WAKE

RXD VBAT

BGE ERRN

STBN RXEN

015aaa067

Table 2. Pin description

Symbol Pin Type Description

INH 1 O inhibit output for switching external voltage regulator

EN 2 I enable input; enabled when HIGH; internal pull-down

VIO 3 P supply voltage for VIO voltage level adap tation

TXD 4 I transmit data input; internal pull-down

TXEN 5 I transmitter enable input; when HIGH transmitter disabled; internal

pull-up

RXD 6 O receive data output

BGE 7 I bus guardian enable input; when LOW transmitter disabled; internal

pull-down

STBN 8 I standby input; low-power mode when LOW; internal pull-down

RXEN 9 O receive data enable output; when LOW bus activity detected

ERRN 10 O error diagnoses output; when LOW error detected

VBAT 11 P battery supply voltage

WAKE 12 I local wake-up input; inte rnal pull-up or pull-down (d epends on

voltage at pin WAKE)

GND 13 P ground

BM 14 I/O bus line minus

BP 15 I/O bus line plus

VCC 16 P supply voltage (+5 V)

Product data sheet Rev. 4 — 24 February 2011 5 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

6. Functional description

The block diagram of the transceiver is shown in Figure 1.

6.1 Operating modes

The TJA1081 supports the following operating modes:

•Normal (normal-power mode)

•Receive-only (normal-power mode)

•Standby (low-power mode)

•Go-to-sleep (low-power mode)

•Sleep (low-power mode)

6.1.1 Bus activity and idle detection

The following mechanisms for activity and idle detection are valid in normal-powe r modes:

•If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for

tdet(act)(bus), activity is detected on the bus lines and pin RXEN is switched LOW which

results in pin RXD being released:

–If, after bus activity detection, the dif ferential voltage on the bus lines is higher than

VIH(dif), pin RXD will go HIGH

–If, after bus activity detection, the differential voltage on the bus lines is lower than

VIL(dif), pin RXD will go LOW

•If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for

tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH.

This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)

6.2 Mode control pins: STBN and EN

Control inputs STBN and EN are used to select the operating mode. See Table 3 for a

detailed description of pin signalling and Figure 3 for the timing diagram.

All mode transitions are controlled via the STBN and EN pins, unless an unde rvoltage

condition is detected. If VIO and (VCC or VBAT) ar e with in th eir spe cifie d op er a ting ra ng es ,

pin ERRN will indicate the status of the error flag.

[1] Pin ERRN provides a serial interface for retrieving diagnostic information.

[2] Valid if VIO and (VCC or VBAT) are present.

Table 3. Pin signalling

Mode STBN EN ERRN[1] RXEN RXD Transmitter INH

LOW HIGH LOW HIGH LOW HIGH

Normal HIGH HIGH error flag

set error flag

reset bus

activity bus

idle bus DATA_0 bus DATA_1

or idle enabled HIGH

Receive-only HIGH LOW disabled

Go-to-sleep LOW HIGH error flag

set[2] error flag

reset wake flag

set[2] wake

flag

reset

wake flag

set[2] wake flag

reset

Standby LOW LOW

Sleep LOW X float

Product data sheet Rev. 4 — 24 February 2011 6 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

The state diagram is shown in Figure 5.

Fig 3. Timing diagram in Normal mode

001aae43

TXD

BGE

RXD

RXEN

TXEN

Fig 4. Timing diagram of control pins EN and STBN

015aaa06

tdet(EN)

td(STBN-stb)

td(STBN-RXD)

normal

receive

onlystandby

receive

onlynormal

STBN

ERRN

0.7VIO

0.3VIO

0.7VIO

0.3VIO

Product data sheet Rev. 4 — 24 February 2011 7 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

The state transitions are represented with numbers, which correspond with the numbers

in column 3 of Table 4 to Table 7.

(1) At the first battery connection the transceiver will enter the Standby mode.

Fig 5. State diagra m

001aae43

NORMAL

STBN = HIGH

EN = HIGH

STANDBY(1)

STBN = LOW

EN = LOW

SLEEP

STBN = LOW

EN = X

GO-TO-SLEEP

STBN = LOW

EN = HIGH

RECEIVE ONLY

STBN = HIGH

EN = LOW

12, 22

9, 18

11, 2131, 32 7, 16, 38

3, 30

6, 33 10, 20 28, 17, 3915, 25, 42, 43

19 23

26, 44 27, 45

36, 37 13, 34, 35

14, 24, 40, 41

28, 29

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Product data sheet Rev. 4 — 24 February 2011 8 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] STBN must be set to LOW at least tdet(EN) after the falling edge on EN.

[2] Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared.

[3] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags.

[4] Hold time of go-to-sleep is less than th(gotosleep).

[5] Hold time of go-to-sleep becomes greater than th(gotosleep).

Table 4. State transitions forced by EN and STBN

→

indicates the action that initiates a transact ion; 1

→

and 2

→

indicated the consequences of a transaction.

Transition

from mode Direction to

mode Transition

number Pin Flag Note

STBN EN UVVIO UVVBAT UVVCC PWON Wake

Normal Receive-only 1 H → L cleared cleared cleared cleared cleared

Go-to-sleep 2 → L H cleared cleared cleared cleared cleared

Standby 3 → L → L cleared cleared cleared cleared cleared [1]

Receive-only Normal 4 H → H cleared cleared cleared X X

Go-to-sleep 5 → L → H cleared cleared cleared X X

Standby 6 → L L cleared cleared cleared X X

Standby Normal 7 → H → H cleared cleared 2 → cleared X 1 → cleared [2][3]

Receive-only 8 → H L cleared cleared 2 → cleared X 1 → set [2][3]

Go-to-sleep 9 L → H cleared cleared X X X

Go-to-sleep Normal 10 → H H cleared cleared cleared X 1 → cleared [2][4]

Receive-only 11 → H → L cleared cleared cleared X 1 → set [2][4]

Standby 12 L → L cleared cleared X X X [4]

Sleep 13 L H cleared cleared X X cleared [5]

Sleep Normal 14 → HH 2 → cleared 2 → cleared 2 → cleared X 1 → cleared [2][3]

Receive-only 15 → HL 2 → cleared 2 → cleared 2 → cleared X 1 → set [2][3]

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Product data sheet Rev. 4 — 24 February 2011 9 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags.

[2] Transition via Standby mode.

Table 5. State transitions forced by a wake-up

→

indicates the action that initiates a transact ion; 1

→

and 2

→

indicated the consequences of a transaction.

Transition

from mode Direction to

mode Transition

number Pin Flag Note

STBN EN UVVIO UVVBAT UVVCC PWON Wake

Standby Normal 16 H H cleared cleared 1 → cleared X → set [1]

Receive-only 17 H L cleared cleared 1 → cleared X → set [1]

Go-to-sleep 18 L H cleared cleared 1 → cleared X → set [1]

St andby 19 L L cleared cleared 1 → cleared X → set [1]

Go-to-sleep Normal 20 H H cleared cleared 1 → cleared X → set [1]

Receive-only 21 H L cleared cleared 1 → cleared X → set [1]

St andby 22 L L cleared cleared 1 → cleared X → set [1]

Go-to-sleep 23 L H cleared cleared 1 → cleared X → set [1]

Sleep Normal 24 H H 1 → cleared 1 → cleared 1 → cleared X → set [1][2]

Receive-only 25 H L 1 → cleared 1 → cleared 1 → cleared X → set [1][2]

St andby 26 L L 1 → cleared 1 → cleared 1 → cleared X → set [1]

Go-to-sleep 27 L H 1 → cleared 1 → cleared 1 → cleared X → set [1][2]

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Product data sheet Rev. 4 — 24 February 2011 10 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] UVVIO, UVVBAT or UVVCC detected clears the wake flag.

[2] UVVIO overrules UVVCC.

[3] UVVBAT overrules UVVCC.

Table 6. State transitions forced by an undervoltage condition

→

indicates the action that initiates a transact ion; 1

→

and 2

→

indicated the consequences of a transaction.

Transition from

mode Direction to

mode Transition

number Flag Note

UVVIO UVVBAT UVVCC PWON Wake

Normal Sleep 28 → set cleared cleared cleared cleared [1]

Sleep 29 cleared → set cleared cleared cleared [1]

Standby 30 cleared cleared → set cleared cleared [1]

Receive-only Sleep 31 → set cleared cleared X 1 → cleared [1]

Sleep 32 cleared → set cleared X 1 → cleared [1]

Standby 33 cleared cleared → set X 1 → cleared [1]

Go-to-sleep Sleep 34 → set cleared cleared X 1 → cleared [1]

Sleep 35 cleared → set cleared X 1 → cleared [1]

Standby Sleep 36 → set cleared X X 1 → cleared [1][2]

Sleep 37 cleared → set X X 1 → cleared [1][3]

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Product data sheet Rev. 4 — 24 February 2011 11 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] Recovery of UVVCC flag.

[2] Recovery of UVVBAT flag.

[3] Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared.

[4] Recovery of UVVIO flag.

Table 7. State transitions forced by an undervoltage recovery

→

indicates the action that initiates a transaction;

→

1 and

→

2 are the consequences of a transaction.

Transition

from mode Direction to

mode Transition

number Pin Flag Note

STBN EN UVVIO UVVBAT UVVCC PWON Wake

Standby Normal 38 H H cleared cleared → cleared X X [1]

Receive-only 39 H L cleared cleared → cleared X X [1]

Sleep Normal 40 H H cleared → cleared cleared X 1 → cleared [2][3]

Normal 41 H H → cleared cleared cleared X X [4]

Receive-only 42 H L cleared → cleared cleared X 1 → set [2][3]

Receive-only 43 H L → cleared cleared cleared X X [4]

Standby 44 L L cleared → cleared cleared X 1 → set [2][3]

Sleep 45 L X → cleared cleared clea red X cleared [4]

Go-to-sleep 46 L H cleared → cleared cleared X 1 → set [2][3]

Sleep 47 L X → cleared cleared clea red X cleared [4]

Product data sheet Rev. 4 — 24 February 2011 12 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

6.2.1 Normal mode

In Normal mode the transceiver is able to transmit and receive data via the bus lines BP

and BM. The output of the normal receiver is directly connected to pin RXD.

Transmitter behavior in Normal mode, with no time-out present on pins TXEN and BGE

and the temperature flag not set (TEMP HIGH = 0; see Table 9), is detailed in Table 8.

In this mode, pin INH is set HIGH.

6.2.2 Receive-only mode

In Receive-only mode the transceiver can only receive data. The transmitter is disabled,

regardless of the voltage levels on pins BGE and TXEN.

In this mode, pin INH is set HIGH.

6.2.3 Standby mode

St andb y mode is a low-power mode featurin g very low current consumption. In this mode,

the transceiver ca nn ot tran sm it or receive da ta. The low-power receiver is activated to

monitor the bus for wake-up patterns.

A transition to Standby mode can be triggered by applying the appropriate levels on pins

EN and STBN (see Figure 5 and Table 4) or if an undervoltage is detected on pin VCC

(see Figure 5 and Section 6.2.5).

In this mode, pin INH is set HIGH.

If the wake flag is set, pins RXEN and RXD are driven LOW; otherwise pins RXEN and

RXD are set HIGH (see Section 6.3).

6.2.4 Go-to-sleep mode

In this mode, the transceiver behaves as in Standby mode. If this mode is selected for a

time longer than the go-to-sleep ho ld time (t h(gotosleep)) and the wake flag ha s be en

previously cleared, the transceiver will enter Sleep mode, regardless of the voltage on

pin EN.

6.2.5 Sleep mode

Sleep mode is a low-power mode. Th e only difference be twe en Slee p mod e and Standby

mode is that pin INH is set floating in Sleep mode. A transition to Sleep mode will be

triggered from all other modes if the UVVIO flag or the UVVBAT flag is set (see Table 6).

If an undervolta ge is detected on pin V CC or VBAT while VIO is present, the wake flag is set

by a positive edge on pin STBN, provided that VIO and (VCC or VBAT) are present.

Table 8. Transmitter function table

BGE TXEN TXD Transmitter

L X X transmitter is disabled

X H X tran s mitter is disabled

H L H transmitter is enabled ; th e bus lines are actively driven; BP is driven

HIGH and BM is driven LOW

H L L transmitter is enab led; the bus lines are actively driven; BP is driven

LOW and BM is driven HIGH

Product data sheet Rev. 4 — 24 February 2011 13 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

The undervoltage flags will be reset when the wake flag is set, and the transceiver will

enter the mode ind ica te d by th e lev els on pin s EN and STBN if VIO is present.

6.3 Wake-up mechanism

From Sleep mode (pin INH is switched off), the transceiver will enter Standby or

Go-to-sleep mode (depend ing on the level at pin EN) if the wake flag is set. Consequently,

pin INH is switched on.

If an undervoltage is not detected on pins VIO, VCC and VBAT, the transceiver will switch

immediately to the m od e indi ca te d by the levels on pins EN and STBN.

In Standby, Go-to-s lee p an d Sleep mo de s, pin s RXD an d RXEN are dr ive n LO W if the

wake flag is set.

6.3.1 Remote wake-up

6.3.1.1 Bus wake-up via wake-up pattern

Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated

by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least

tdet(wake)idle are present on the bus lines within tdet(wake)tot.

6.3.1.2 Bus wake-up via dedicated FlexRay data frame

The reception of a dedicated data frame, emulating a valid wake-up p attern, as shown in

Figure 7, sets the wake-up flag of the TJA1081.

Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1

phases for the wake-up symbol are interrupted every 1 μs. For 10 Mbit/s the maximum

interruption time is 130 ns. Such interruptions do not prevent the transceiver from

recognizing the wake-up pa ttern in the payload of a data frame.

The wake-up flag will not be set if an invalid wake-up pattern is received.

Fig 6. Bus wake-up timing

001aae4

0 V

−425 mV

Vdif

tdet(wake)tot

tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle

Product data sheet Rev. 4 — 24 February 2011 14 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

6.3.2 Local wake-up via pin WAKE

If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling

edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time,

the biasing of this pin is switched to pull-down.

If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the

biasing of this pin is switched to pull-up, and no local wake-up will be detected.

Each interruption is 130 ns.

The transition time from DATA_0 to DATA_1 and from DATA_1 to DATA_0 is about 20 ns.

The TJA1081 wake-up flag will be set with the following pattern:

FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h,

FFh, FFh, FFh, FFh, FFh, FFh

Fig 7. Minimum bus pattern for bus wake-up

015aaa043

Vdif

0 V

−1500

wake-up

+1500

870

870 ns 870 ns

770

130 ns

130

5 μs5 μs 5 μs 5 μs

Sleep mode: VIO and (VBAT or VCC) still provided.

Fig 8. Local wake-up timing via pin WAKE

015aaa06

VBAT

RXD and

RXEN

INH

0 V

WAKE

twake(WAKE)

pull-up pull-up

twake(WAKE)

pull-down

Product data sheet Rev. 4 — 24 February 2011 15 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

6.4 Fail-silent behavior

In order to be fail silent, unde rvoltage dete ction and a reset mechanism for the digit al state

machine are implemented.

If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a

low-power mode. This ensures the passive and defined behavior of the transmitter and

receiver when an undervoltage is detected.

In the range between th e minimum operating voltage and the undervoltage detection

threshold, the principle functions o f the tran smitter and receiver a re maint ained . Howeve r,

in this range param eters (e.g. thresholds and delays of the transmitter and receiver) may

deviate from the levels specified for the operating range.

The digital state machine is supplied by VCC, VIO or VBAT, depending on which voltage is

available. Therefore, the digital state machine will be properly supplied as long as the

voltage on pin VCC or pin VIO remains above 4.75 V or the voltage on pin VBAT remains

above 6.5 V.

If the voltage on all pins (i.e. VCC, VIO and VBAT) breaks down, a reset signal will be given

to the digital state machine as soon as the internal supply voltage for the digital state

machine becomes too low fo r the proper oper ation of the state machine. This ensures th e

passive and d efined behavio r of the digital state machine in the event o f an overall supply

voltage breakdown.

6.4.1 VBAT undervoltage

If the UVVBAT flag is set, the transceiver will enter Sleep mode (pin INH is switched off)

regardless of the voltages present on pins EN and STBN. If the undervoltage r ecovers,

the wake flag will be set and the transcei ver will enter the mode determined by the

voltages on pins EN and STBN.

6.4.2 VCC undervoltage

If the UVVCC flag is set, the transceiver will enter Standby mode regardless of the voltages

present on pins EN and STBN. If the undervoltage recovers or the wake flag is set, mode

switching via pins EN and STBN is possible.

6.4.3 VIO undervoltage

If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO flag is reset) pins EN,

STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If

the UVVIO flag is set, the transceiver will enter Sleep mode (pin INH is switched off). If the

undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is

possible.

6.5 Flags

6.5.1 Local wake-up source flag

The local wake-up source flag can only be set in a low-po we r mo d e. When a wake - up

event is detected on pin WAKE (see Section 6.3.2), the local wake-up source flag is set.

The local wake-up source flag is reset by entering a low-power mode.

Product data sheet Rev. 4 — 24 February 2011 16 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

6.5.2 Remote wake-up source flag

The remote wake-up source flag can only be set in a low-power mode if pin VBAT is within

its operating range. When a remote wake-up event is detecte d on the bus lines (see

Section 6.3.1), the remote wake-up source flag is set. The remote wake-up source flag is

reset by entering a low-power mode.

6.5.3 Wake flag

The wake flag is set if one of the following events occurs:

•The local or remote wake-up source flag is set (edge sensitive)

•A positive edge is detected on pin STBN when VIO is present

•Recovery of the UVVBAT flag

The wake flag is reset by entering Normal mode, a low- power mode or by setting one of

the undervoltage flags.

6.5.4 Power-on flag

The PWON power-on flag is set if the internal supply voltage for the digital part becomes

higher than the lowest va lue it needs to operat e. Entering Normal mode r esets the PWON

flag.

6.5.5 Temperature medium flag

The temperature medium fla g is set if the junction temperature exceeds T j(warn)(medium) in a

normal-power mode while pin VBAT is within its operating range. The temper ature medium

flag is reset when the junction tempe rature drops belo w Tj(warn)(medium) in a norm a l -p ow er

mode with pin VBAT within its operating range or after a re ad of the status register in a

low-power mode while pin VBAT is within its operating range. No action will be taken if this

flag is set.

6.5.6 Temperature high flag

The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a

normal-power mode wh ile pin VBAT is within its operating range.

The temperature high flag is reset if a negative edge is applied to pin TXEN while the

junction temperature is lower than T j(dis)(high) in a normal-power mod e with pin V BAT within

its opera ting range.

If the temperature high flag is set, the transmitter will be disabled.

6.5.7 TXEN_BGE clamped flag

The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer

than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin

BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled.

6.5.8 Bus error flag

The bus error flag is se t if pin TXEN is LOW and pin BGE is HIGH and the data received

from the bus lines (pins BP and BM) are different to that received on pin TXD. The

transmission of any valid communication element, includin g a wake-up pattern, does not

lead to bus error indication.

Product data sheet Rev. 4 — 24 February 2011 17 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

The error flag is r eset if the dat a on the b us lines (pins BP and BM) are the same as on pin

TXD or if the transmitter is disabled. No action will be taken if the bus error flag is set.

6.5.9 UVVBAT flag

The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag

is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see

Section 6.4.1.

6.5.10 UVVCC flag

The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than

tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer

than trec(uv)(VCC) or the wake flag is set; see Section 6.4.2.

6.5.11 UVVIO flag

The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than

tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wak e

flag is set; see Section 6.4.3.

6.5.12 Error flag

The error flag is set if one of the status bit s S4 to S1 0 is se t. The err or flag is reset if non e

of the S4 to S10 status bits are set; see Table 9.

6.6 Status register

The status regi ster can be rea d out on pin ERRN by using pin EN a s clock; the st atus bit s

are given in Table 9. The timing diagram is shown in Figure 9.

The status register is accessible if:

•UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V

•UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V

After reading the status registe r, if no edg e is detected on pin EN for longer than tdet(EN),

the status bits (S4 to S12) will be cleared if the corresponding flag has been reset. Pin

ERRN is LOW if the corresponding status bit is set.

Table 9. Status bits

Bit number Status bi t Description

S0 LOCAL WAKEUP local wake-up source flag is redirected to this bit

S1 REMOTE WAKEUP remote wake-up so urce flag is redirected to this bit

S2 - not used; always set

S3 PWON status bit set means PWON flag has been set previously

S4 BUS ERROR status bit set means bus error flag has been set previously

S5 TEMP HIGH status bit set means temperature high flag has been set previously

S6 TEMP MEDIUM status bit set means temperature medium flag has been set previou sly

S7 TXEN_BGE CLAMPED status bit set means TXEN_BGE clamped flag has been set previously

S8 UVVBAT status bit set means UVVBAT flag has been set previously

S9 UVVCC status bit set means UVVCC flag has been set previously

Product data sheet Rev. 4 — 24 February 2011 18 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

S10 UVVIO status bit set means UVVIO flag has been set previously

S11 - not used; always reset

S12 - not used; always reset

Table 9. Status bits …continued

Bit number Status bi t Description

Fig 9. Timing diag ram for status bits

001aag89

S0 S1 S2

TEN

tdet(EN)

td(EN-ERRN)

receive

onlynormal

STBN

ERRN

0.7VIO

0.3VIO

Product data sheet Rev. 4 — 24 February 2011 19 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

7. Limiting values

[1] According to ISO7637, test pulse 1, class C; verified by an external test house.

[2] According to ISO7637, test pulse 2a, class C; verified by an external test house.

[3] According to ISO7637, test pulse 3a, class C; verified by an external test house.

[4] According to ISO7637, test pulse 3b, class C; verified by an external test house.

[5] In accordance with IEC 60747-1. An alternative definition of Tvj is: Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value to be used for the

calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).

[6] HBM: C = 100 pF; R = 1.5 kΩ.

[7] MM: C = 200 pF; L = 0.75 μH; R = 10 Ω.

[8] CDM: R = 1 Ω.

Table 10. L imiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.

Symbol Parameter Conditions Min Max Unit

VBAT battery supply voltage no time limit −0.3 +60 V

operating range 6.5 60 V

VCC supply voltage no time limit −0.3 +5.5 V

operating range 4.75 5.25 V

VIO supply voltage on pin VIO no time limit −0.3 +5.5 V

operating range 2.2 5.25 V

VINH voltage on pin INH −0.3 VBAT + 0.3 V

IO(INH) output current on pin INH no time limit −1- mA

VWAKE voltage on pin WAKE −0.3 VBAT + 0.3 V

Io(WAKE) output current on pin WAKE pin GND not connected −15 - mA

VBGE voltage on pin BGE no time limit −0.3 +5.5 V

VTXEN voltage on pin TXEN no time limit −0.3 +5.5 V

VTXD voltage on pin TXD no time limit −0.3 +5.5 V

VERRN voltage on pin ERRN no time limit −0.3 VIO + 0.3 V

VRXD voltage on pin RXD no time limit −0.3 VIO + 0.3 V

VRXEN voltage on pin RXEN no time limit −0.3 VIO + 0.3 V

VEN voltage on pin EN no time limit −0.3 +5.5 V

VSTBN voltage on pin STBN no time limit −0.3 +5.5 V

VBP voltage on pin BP no time limit −60 +60 V

VBM voltage on pin BM no time limit −60 +60 V

Vtrt transient voltage on pi ns BM and BP [1] −100 - V

[2] -75 V

[3] −150 - V

[4] -100 V

Tstg storage temperature −55 +150 °C

Tvj virtual junction temperature [5] −40 +150 °C

VESD electrostatic discharge voltage HBM on pins BP and BM to ground [6] −8.0 +8.0 kV

HBM at any other pin [6] −4.0 +4.0 kV

MM on all pins [7] −200 +200 V

CDM on all pins [8] −1000 +1000 V

Product data sheet Rev. 4 — 24 February 2011 20 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

8. Thermal characteristics

9. Static characteristics

Table 11. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient in free air 118 K/W

Table 12. Static characteristics

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Pin VBAT

IBAT battery supply current low-power modes;

no load on pin INH --55μA

normal-power modes - - 1 mA

Vuvd(VBAT) undervoltage detection voltage on

pin VBAT

2.75 - 4.5 V

Pin VCC

ICC supply current low-power modes −10 +10μA

Normal mode;

VBGE =0V; V

TXEN = VIO;

Receive-only mode

--15mA

Normal mode;

VBGE =V

IO; VTXEN = 0 V --37mA

Normal mode;

VBGE =V

IO; VTXEN = 0 V;

Rbus = ∞ Ω

--15mA

Vuvd(VCC) undervoltage detection voltage on

pin VCC

(VBAT ≥5.5 V AND

VIO ≥4.75 V) OR

VBAT ≥6.5 V

2.75 3.7 4.5 V

Pin VIO

IIO supply current on pin VIO low-power modes −1+1+10μA

Normal and Receive-only

modes; VTXD = VIO

- - 1000 μA

Vuvd(VIO) undervoltage detection voltage on pin VIO 11.52V

Vuvr(VIO) undervoltage recovery voltage on pin VIO 11.62.2V

Vuvhys(VIO) undervoltage hysteresis voltage on

pin VIO

VBAT > 5.5 V 25 - 200 mV

Pin EN

VIH(EN) HIGH-level input voltage on pin EN 0.7VIO -5.5V

VIL(EN) LOW-level input voltage on pin EN −0.3 - 0.3VIO V

IIH(EN) HIGH-level input current on pin EN VEN = 0.7VIO 3- 11μA

IIL(EN) LOW-level input current on pin EN VEN = 0 V −10 +1μA

Pin STBN

VIH(STBN) HIGH-level input voltage on pin STBN 0.7VIO -5.5V

Product data sheet Rev. 4 — 24 February 2011 21 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

VIL(STBN) LOW-level input voltage on pin STBN −0.3 - 0.3VIO V

IIH(STBN) HIGH-level input current on pin STBN VSTBN = 0.7VIO 3- 11μA

IIL(STBN) LOW-level input current on pin STBN VSTBN = 0 V −10 +1μA

Pin TXEN

VIH(TXEN) HIGH-level input voltage on pin TXEN 0.7VIO -5.5V

VIL(TXEN) LOW-level input voltage on pin TXEN −0.3 - 0.3VIO V

IIH(TXEN) HIGH-level input current on pin TXEN VTXEN = VIO −10 +1μA

IIL(TXEN) LOW-level input current on pin TXEN VTXEN = 0.3VIO −15 - −3μA

IL(TXEN) leakage current on pin TXEN VTXEN = 5.25 V; VIO = 0 V −10 +1μA

Pin BGE

VIH(BGE) HIGH-level input voltage on pin BGE 0.7VIO -5.5V

VIL(BGE) LOW -level input voltage on pin BGE −0.3 - 0.3VIO V

IIH(BGE) HIGH-level input current on pin BGE VBGE = 0.7VIO 3- 11μA

IIL(BGE) LOW-level input current on pin BGE VBGE = 0 V −10 +1μA

Pin TXD

VIH(TXD) HIGH-level input voltage on pin TXD normal-power modes 0.7VIO -V

IO +

0.3 V

VIL(TXD) LOW-level input voltage on pin TXD normal-power modes −0.3 - 0.3VIO V

IIH(TXD) HIGH-level input current on pin TXD VTXD = VIO 70 230 650 μA

IIL(TXD) LOW-level input current on pin TXD normal-power modes;

VTXD =0V −50 +5μA

low-power modes −1 0 +1 μA

ILI(TXD) input leakage current on pin TXD VTXD = 5.25 V; VIO = 0 V −10 +1μA

Ci(TXD) input capacitance on pin TXD not tested; with respect to

all other pins at ground;

VTXD =100 mV; f=5MHz

[1] - 5 10 pF

Pin RXD

IOH(RXD) HIGH-level output current on pin RXD VRXD = VIO − 0.4 V;

VIO =V

−20 - −2mA

IOL(RXD) LO W-level output current on pin RXD VRXD = 0.4 V 2 - 20 mA

Pin ERRN

IOH(ERRN) HIGH-level output current on pin ERRN VERRN =V

IO − 0.4 V;

VIO =V

−1500 −600 −100 μA

IOL(ERRN) LOW-le ve l ou tp ut current on pin ERRN VERRN = 0.4 V 300 700 1500 μA

Pin RXEN

IOH(RXEN) HIGH-level output current on pin RXEN VRXEN = VIO − 0.4 V;

VIO =V

−4−1.7 −0.5 mA

IOL(RXEN) LOW-l e ve l ou tput current on pin RXEN VRXEN = 0.4 V 1 3.2 8 mA

Table 12. Static characteristics …continued

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 24 February 2011 22 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

Pins BP and BM

Vo(idle)(BP) idle output vol tage on pin BP Normal or Receive-only

mode; VTXEN =V

0.4VCC 0.5VCC 0.6VCC V

Standby, Go-to- sleep or

Sleep mode −0.1 0 +0.1 V

Vo(idle)(BM) idle output voltage on pin BM Normal or Receive-only

mode; VTXEN = VIO

0.4VCC 0.5VCC 0.6VCC V

Standby, Go-to- sleep or

Sleep mode −0.1 0 +0.1 V

Io(idle)BP idle output curren t on pin BP −60 V ≤ VBP ≤ +60 V; with

respect to GND and VBAT

−7.5 - +7.5 mA

Io(idle)BM idle output curren t on pin BM −60 V ≤ VBM ≤ +60 V; with

respect to GND and VBAT

−7.5 - +7.5 mA

Vo(idle)(dif) differential idle output voltage −25 0 +25 mV

VOH(dif) differential HIGH-level output voltage 40 Ω ≤ Rbus ≤ 55 Ω;

VCC =5 V; C

bus = 100 pF 600 850 1500 mV

VOL(dif) di fferential LO W-level output vol tage 40 Ω ≤ Rbus ≤ 55 Ω;

VCC =5V; C

bus = 100 pF −1500 −850 −600 mV

VIH(dif) differential HIGH-level input voltage normal-power modes;

−10 V ≤VBP ≤ +15 V;

−10 V ≤VBM ≤ +15 V

150 210 300 mV

VIL(dif) differential LOW-level input voltage normal-power modes;

−10 V ≤VBP ≤ +15 V;

−10 V ≤VBM ≤ +15 V

−300 −210 −150 mV

low-power modes;

−10 V ≤VBP ≤ +15 V;

−10 V ≤VBM ≤ +15 V

−400 −210 −125 mV

|ΔVi(dif)(H-L)|differential input volt. diff. betw. HIGH-

and LOW-levels (abs. value) normal-power modes;

(VBP +V

BM)/2=2.5V --10%

|Vi(dif)det(act)|activity detection differential input voltage

(absolute value) normal-power modes 150 210 300 mV

|IO(sc)|short-circuit output current (absolute

value) on pin BP;

0V≤VBP ≤60 V --35mA

on pin BM;

0V≤VBM ≤60 V --35mA

on pins BP and BM;

VBP =V

BM:

0V≤VBP ≤60 V;

0V≤VBM ≤60 V

--35mA

Ri(BP) input resistance on pin BP idle level; Rbus = ∞ Ω10 18.5 40 kΩ

Ri(BM) input resistance on pin BM idle level; Rbus = ∞ Ω10 18.5 40 kΩ

Ri(dif)(BP-BM) differential input resistance between pin

BP and pin BM idle level; Rbus = ∞ Ω20 37 80 kΩ

ILI(BP) input leakage current on pin BP VBP =5V;

VBAT =V

CC =V

IO =0 V −10 0 +10 μA

Table 12. Static characteristics …continued

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 24 February 2011 23 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] These values are based on measurements taken on several samples (less than 10 pieces). These measurements have taken place in

the laboratory and have been done at Tamb = 25 °C and Tamb = 125 °C. No characterization has been done for these parameters. No

industrial test will be performed on production products.

ILI(BM) input leakage current on pin BM VBM =5V;

VBAT =V

CC =V

IO =0 V −10 0 +10 μA

Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Rbus = 45 Ω0.4VCC 0.5VCC 0.6VCC V

Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Rbus = 45 Ω0.4VCC 0.5VCC 0.6VCC V

ΔVcm(bus) bus common-mode voltage difference Rbus = 45 Ω−25 0 +25 mV

Ci(BP) input capacitance on pin BP not tested; with respect to

all other pins at ground;

VBP = 100 mV; f = 5 MHz

[1] - 8 15 pF

Ci(BM) input capacitance on pin BM not tested; with respect to

all other pins at ground;

VBM = 100 mV; f = 5 MHz

[1] - 8 15 pF

Ci(dif)(BP-BM) dif ferential input capacitance between pin

BP and pin BM not tested; with respect to

all other pins at ground;

V(BM-BP) =100 mV;

f=5MHz

[1] -25pF

Pin INH

VOH(INH) HIGH-level output voltage on pin INH IINH = −0.2 mA VBAT −

0.8 VBAT −

0.3 VBAT −

0.1 V

IL(INH) leakage current on pin INH Sleep mode −50 +5μA

IOL(INH) LOW-le ve l ou tp ut current on pin INH VINH = 0 V −15 −5−1mA

Pin WAKE

Vth(det)(WAKE) d etection threshold voltage on pin WAKE low-power mode 2.5 - 4.5 V

IIL(WAKE) LOW-level input current on pin WAKE VWAKE = 2.4 V for

t>t

wake(WAKE)

3- 11μA

IIH(WAKE) HIGH-level input current on pin WAKE VWAKE = 4.6 V for

t>t

wake(WAKE)

−11 - −3μA

Temperature protection

Tj(warn)(medium) medium warning jun ction temperature VBAT > 5.5 V 155 165 175 °C

Tj(dis)(high) high disable junction temperature VBAT > 5.5 V 180 190 200 °C

Power-on reset

Vth(det)POR power-on reset detection threshold

voltage 3.0 - 3.4 V

Vth(rec)POR power-on reset recovery threshold

voltage 3.1 - 3.5 V

Vhys(POR) power-on reset hysteresis voltage 100 - 200 mV

Table 12. Static characteristics …continued

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 24 February 2011 24 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

10. Dynamic characteristics

Table 13. Dynamic characteristics

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Pins BP and BM

td(TXD-bus) delay time from TXD to bus Normal mode [1]

DATA_0 --50ns

DATA_1 --50ns

Δtd(TXD-bus) delay time difference from TXD to bus Nor mal mode; between

DATA_0 and DATA_1 [1] --4 ns

td(bus-RXD) delay time from bus to RXD Normal mode;

CRXD = 15 pF; see Figure 11

DATA_0 --50ns

DATA_1 --50ns

Δtd(bus-RXD) delay time difference from bus to RXD Normal mode CRXD = 15 pF;

between DATA_0 and

DATA_1; see Figure 11

--5 ns

td(TXEN-busidle) delay time from TXEN to bus idle Normal mode - 46 80 ns

td(TXEN-busact) delay time from TXEN to bus acti ve Normal mode - 39 75 ns

td(BGE-busidle) delay time from BGE to bus idle Normal mode - 47 100 ns

td(BGE-busact) delay ti me fr om BGE to bus active Normal mode - 40 75 ns

td(bus)(idle-act) bus delay time from idle to active Normal mode - 7 30 ns

td(bus)(act-idle) bus delay time from active to idle Normal mode - 7 30 ns

tr(dif)(bus) bus differential rise time 10 % to 90 %; Rbus = 45 Ω;

Cbus = 100 pF 51725ns

tf(dif)(bus) bus differential fall time 90 % to 10 %; Rbus = 45 Ω;

Cbus = 100 pF 51725ns

WAKE symbol detection

tdet(wake)DATA_0 DATA_0 wake-u p detecti on time Standby or Sleep mode;

−10 V ≤VBP ≤+15 V;

−10 V ≤VBM ≤ +15 V

1- 4 μs

tdet(wake)idle idle wake-up detection time 1 - 4 μs

tdet(wake)tot total wake-up detection time 50 - 115 μs

Undervoltage

tdet(uv)(VCC) undervoltage detection time on pin VCC 100 - 670 ms

trec(uv)(VCC) undervoltage recovery time on pin VCC 1- 5.2ms

tdet(uv)(VIO) undervoltage detection time on pin VIO 100 - 670 ms

tdet(uv)(VBAT) undervoltage detection time on pin VBAT --1 ms

Activity detection

tdet(act)(bus) activity detection time on bus pins Vdif: 0 mV → 400 mV 100 - 250 ns

tdet(idle)(bus) idle detection time on bus pins Vdif: 400 mV → 0 mV 100 - 245 ns

Mode control pins

td(STBN-RXD) STBN to RXD delay time STBN HIGH to RXD HIGH;

wake flag set --2 μs

Product data sheet Rev. 4 — 24 February 2011 25 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

[1] Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns ±1 ns.

[2] Same parameter is guaranteed by design for the transition from Normal to Go-to-sleep mode.

td(STBN-stb) delay time from STBN to standby mode STBN LOW to Standby

mode; Receive-only mode[2] --10μs

th(gotosleep) go-to -sl eep hold time 20 35 50 μs

Status register

tdet(EN) detection time on pin EN for mode control 20 - 80 μs

TEN time period on pin EN for reading sta tu s bits 4 - 20 μs

td(EN-ERRN) delay time from EN to ERRN for reading status bits - - 2 μs

WAKE

twake(WAKE) wake-up time on pin WAKE low-power modes; falling

edge on pin WAKE;

6.5 V ≤VBAT ≤ 27 V

528100μs

low-power modes; falling

edge on pin WAKE;

27 V < VBAT ≤ 60 V

25 75 175 μs

Miscellaneous

tdetCL(TXEN_BGE) TXEN_BGE clamp detection time 2600 - 10400 μs

Table 13. Dynamic characteristics …continued

All parameters are guaranteed for VBAT = 6.5 V to 60 V ; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; T vj =

−

C to +150

Rbus = 45

unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 4 — 24 February 2011 26 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

Fig 10. Detailed timin g dia gram

015aaa14

10 %

90 %

td(bus-RXD)

−150 mV

0.7VIO

0.3VIO

0.7VIO

0.3VIO

0.7VIO

0.3VIO

+300 mV

−300 mV

0 VBP and BM

BGE

TXEN

TXD

RXEN

RXD

0.7VIO

0.3VIO

0.7VIO

0.3VIO

−300 mV −150 mV −300 mV

tr(dif)(bus) tf(dif)(bus)

td(TXD-bus)

td(TXEN-busidle) td(BGE-busidle)

td(TXEN-busact) td(BGE-busact)

td(bus-RXD) +

tdet(idle)(bus)

td(bus-RXD) +

tdet(act)(bus)

td(bus-RXD) +

tdet(idle)(bus)

td(bus-RXD) +

tdet(act)(bus)

Product data sheet Rev. 4 — 24 February 2011 27 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

Vdif is the receiver test signal.

Fig 11. Receiver test signal

015aaa0

22.5 ns

400

Vdif

(mV)

RXD

300

−300

−400

td(bus-RXD)

37.5 ns

60 ns

22.5 ns

td(bus-RXD)

22.5 ns

400

Vdif

(mV)

RXD

300

−300

−400

td(bus-RXD)

37.5 ns

60 ns

22.5 ns

td(bus-RXD)

Product data sheet Rev. 4 — 24 February 2011 28 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

11. Test information

Fig 12. Test circuit for dynamic characteristics

The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a and

3b.

Test conditions:

Normal mode: bus idle

Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz

Standby mode

Fig 13. Test circuit for automotive transients

015aaa070

15 pF

TJA1081

10 μF

+12 V

VCC

VIO VBAT

Rbus Cbus

BP 15

316 11

RXD

+5 V

100

015aaa071

12 V or 42 V

1 nF

ISO 7637

TJA1081

10 μF

VCC

VIO VBAT

Rbus Cbus

BP 15

316 11

+5 V

100

ISO 7637

Product data sheet Rev. 4 — 24 February 2011 29 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

12. Package outline

Fig 14. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05

1.80

1.65 0.25 0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2 0.65 1.25

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338

-1

max.

Product data sheet Rev. 4 — 24 February 2011 30 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orie ntation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4 — 24 February 2011 31 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 15) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 14 and 15

Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 15.

Table 14. SnPb eutectic proc ess (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 15. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 25 0 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 24 February 2011 32 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 15. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 4 — 24 February 2011 33 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

14. Appendix

14.1 EPL 3.0.1 requirements implemented in the TJA1081

Table 16. EPL 3.0.1 requirements implemented

EPL 3.0.1 parameter Description

- wake-up via dedicated data frames

RDCLoad transmitter output voltage defined for DC bus load of 40 Ω to 55 Ω/100 pF

dBDTx10, dBDTx01 transmitter delay: ≤ 75 ns

uData0_LP receiver thresholds for detecting DATA_0 in low-power modes: −400 mV (min)/

−100 mV (max)

dBDRxai idle reaction time: 50 ns to 275 ns

dBDActivityDetection activity detection time 100 ns to 250 ns

dBDRxia acti vity re action time: 100 ns to 325 ns

uData1 − |uData0|receiver threshold mismatch: ≤ 30 mV

dBDRx10, dBDRx01 receiver delay: ≤ 75 ns

dBusRx0BD, dBusRx1BD minimum bit time: 70 ns

C_StarTxD, C_BDTxD maximum input capacitance on pin TXD: 10 pF

dBDTxRxai idle loop delay: ≤ 325 ns

- BD_Off mode defined

Short circuit currents:

iBPBMShortMax,iBMBPShortMax BP shorted to BM: < 60 mA; no time limit

iBPGNDShortMax,iBMGNDShortMax BP/BM shorted to ground: < 60 mA; no time limit

iBP-5ShortMax,iBM-5ShortMax BP/BM shorted to −5 V: < 60 mA; no time limit

iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 27 V: < 60 mA; no time limit

iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 48 V: < 72 mA; no time limit

iBPBAT60ShortMax,iBMBAT60ShortMax BP/BM shorted to 60 V: < 90 mA; for 400 ms (max)

dBDRVCC VCC undervoltage recovery time: 10 ms (max)

uINH1Not_Sleep voltage drop from VBAT to INH: ≤ 1 V @ 200 μA and VBAT ≥ 5.5 V

iINH1Leak leakage current, when INH is floating: ≤ 10 μA

- Qualification according to AEC-Q100 temperature classes

uESDExt 6 kV ESD (min) on pins BP and BM according to HBM (100 pF/1500 Ω)

uESDInt 2 kV ESD (min) on all other pins according to HBM (100 pF/1500 Ω)

Product data sheet Rev. 4 — 24 February 2011 34 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

15. Abbreviations

16. References

[1] EPL — FlexRay Communications System Electrical Physical Layer Specification

Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005

[2] EPL — FlexRay Communications System Electrical Physical Layer Specification

Version 3.0.1, FlexRay Consortium

[3] TJA1080A — FlexRay transceiver data sheet, www.nxp.com

17. Revision history

Table 17. Abbreviations

Abbreviation Description

BSS Byte Start Sequence

CDM Charged Device Model

ECU Electronic Control Unit

EMC ElectroMagnetic Compatibility

EME ElectroMagnetic Emission

EMI ElectroMagnetic Immunity

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TSS Transmission Start Seque nce

Table 18. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TJA1081 v.4 20110224 Product data sheet - TJA1081 v.3

Modifications: •Section 1, Section 2, Section 16: text revised

•Table 10, Table 12, Table 13: parameter values/conditions/description/table notes revised

•Figure 10: revised

•Figure 13: figure note revised

•Section 14 “Appendix”: added

•Ref. 2: added

•Section 18 “Legal information”: updated

TJA1081 v.3 20090904 Product data sheet - TJA1081 v.2

TJA1081 v.2 20090728 Product data sheet - TJA1081 v.1

TJA1081 v.1 20090415 Preliminary data sheet - -

Product data sheet Rev. 4 — 24 February 2011 35 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

suitable for use in medica l, military, aircraft, space or life suppo rt equipment,

nor in applications where failure or malf unction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 24 February 2011 36 of 37

NXP Semiconductors TJA1081

FlexRay node transceiver

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

18.4 Licenses

18.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP ICs with FlexRay functionality

This NXP product contains functionality that is compliant with the FlexRay

specifications.

These specifications and th e material cont ained in them, as released by the

FlexRay Consortium, are for the purpose of information only. The FlexRay

Consortium and the companies that have contributed to the specifications

shall not be liable for any use of the specifications.

The material contained in t hese specifications is pro tected by copyright a nd

other types of Intellectual Property Rights. The commercial exploit ation of

the material contained in the specifications requires a license to such

Intellectual Property Rights.

These specifications may be utilized or reproduced without any

modification, in any form or by any means, for information al purposes only.

For any other purpose, no part of the specifications may be utilized or

reproduced, in any form or by any mea ns, without permission in writing from

the publisher.

The FlexRay specifications have been developed for automotive

applications only. They have neither been developed nor tested for

non-automotive applications.

The word FlexRay and the FlexRay logo are registered trademarks.

NXP Semiconductors TJA1081

FlexRay node transceiver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 February 2011

Document identifier: TJA1081

Please be aware that important notices concerning this document and the product(s)

described herein, have been in cluded in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 Optimized for time triggered communication

systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Low power management . . . . . . . . . . . . . . . . . 1

2.3 Diagnosis (dete ction and signalling). . . . . . . . . 2

2.4 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.5 Functional classes according to Fle xRay

electrical physical layer specification

(see Ref. 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5

6.1.1 Bus activity and idle detection . . . . . . . . . . . . . 5

6.2 Mode control pins: STBN and EN. . . . . . . . . . . 5

6.2.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2.2 Receive-only mode. . . . . . . . . . . . . . . . . . . . . 12

6.2.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2.4 Go-to-sleep mode. . . . . . . . . . . . . . . . . . . . . . 12

6.2.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.3 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 13

6.3.1 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 13

6.3.1.1 Bus wake-up via wake-up pattern. . . . . . . . . . 13

6.3.1.2 Bus wake-up via dedicated FlexRay

data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.3.2 Local wake-up via pin WAKE . . . . . . . . . . . . . 14

6.4 Fail-silent behavior . . . . . . . . . . . . . . . . . . . . . 15

6.4.1 VBAT undervoltage . . . . . . . . . . . . . . . . . . . . . 15

6.4.2 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 15

6.4.3 VIO undervoltage. . . . . . . . . . . . . . . . . . . . . . . 15

6.5 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5.1 Local wake-up source flag . . . . . . . . . . . . . . . 15

6.5.2 Remote wake-up source flag . . . . . . . . . . . . . 16

6.5.3 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5.4 Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5.5 Temperature medium flag. . . . . . . . . . . . . . . . 16

6.5.6 Temperature high flag. . . . . . . . . . . . . . . . . . . 16

6.5.7 TXEN_BGE clamped flag. . . . . . . . . . . . . . . . 16

6.5.8 Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5.9 UVVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.10 UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.11 UVVIO flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5.12 Error flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6 Status register . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Thermal characteristics . . . . . . . . . . . . . . . . . 20

9 Static characteristics . . . . . . . . . . . . . . . . . . . 20

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 24

11 Te st information . . . . . . . . . . . . . . . . . . . . . . . 28

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 29

13 Soldering of SMD pa ckages. . . . . . . . . . . . . . 30

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 30

13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 30

13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 30

13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 31

14 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14.1 EPL 3.0.1 requirements implemente d

in the TJA1081. . . . . . . . . . . . . . . . . . . . . . . . 33

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34

16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

18 Legal information . . . . . . . . . . . . . . . . . . . . . . 35

18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 35

18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35

18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36

19 Contact information . . . . . . . . . . . . . . . . . . . . 36

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37