Description
The CXA1391Q/R is a bipolar IC developed for
signal processing in complementary color mosaic
CCD cameras.
Features
•Low power consumption (170mW)
•Number of delay lines used for signal processing
can be selected according to the system
requirements
•The LPF peripheral to 1H delay line is built in
Structure
Bipolar silicon monolithic IC
Applications
Complementary color mosaic CCD cameras
Absolute Maximum Ratings
•Supply voltage Vcc 7 V
•Storage temperature Tstg –55 to +150 °C
•Allowable power dissipation
PD690 mW
(LQFP: Ta = 25°C, without P.C.B)
Recommended Operating Conditions
•Supply voltage Vcc 4.75 to 5.25 V
•Ambient temperature Topr –20 to +75 °C
– 1 –
CXA1391Q/R
E89Z18-ST
Processing IC for Complementary Color Mosaic CCD Camera
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA1391Q
64 pin QFP (Plastic) CXA1391R
64 pin LQFP (Plastic)
CLP C Y H
DLYH IN
CLP C DLYH
DLYH OUT
YH OUT 1
YH OUT 2
TP
DLYH GAIN
CLP4
CLP2
VAP OUT
VAP GAIN
CLP C VAP
VAP SLICE
CLP C CS
CS IN B-r
G-r
R-r
CLP
(CLP2)
&
MPX
B
G
R
-CB
CR
Y
C1
Y0
Y1
CS VAP
CS-Y MAX
CS
V-APCN
Y2
Y1
Y0
Y1
Y2
C0
Y0
Y0
V-APCN
YH1
YH0
YH0
YH1
V-APCN
G ch SLICE
CS-Y
B-Y
R-Y
C0
GC
GC
LPF
LPF
CLP
(CLP4)
LPF
CLP
(CLP4)
3H
APCN 2H
APCN
KNEE
LPF
CLP
(CLP2)
CLP
(CLP4)
LPF
CLP
SLICE
CLP
(CLP4)
r
YL MTX
MTX
Hue & GC
LPF
WB AMP
MATRIX
LPF
LPF
WB CONTROL
GC
GC
16
2345678910 11 12 13 14 15
1
GC
B-Y
R-Y G-WB
R-WB
B-WB
CLP
(CLP2)
LPF
r
B-r
R-r
G-r
C S LICE
WB DC
WB B
WB G
WB R
C-r CONT
GND 1
YL OUT
CS OUT
CS GAIN
R – Y HUE
B – Y HUE
R – Y OUT
B – Y OUT
B – Y GAIN
R – Y GA IN
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KNEE
LPF
ABS
KNEE
S2 IN
S1 IN
CLP C Y O
DLY0 OUT
DLY1 OUT
Y1 GAIN
DLY1 IN
DLY2 IN
Y2 GAIN
GND 2
LPF ADJ 1
LPF ADJ 2
LPF ADJ 3
VCC
Y -r CONT
YH IN
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
DLC1 IN
C1 GAIN
DLCO OUT
R MTX
CLP C MPX1
CLP C MPX2
B MTX
ID
B GAIN
B CONT
R CONT
R GA IN
CLP C B
CLP C G
CLF C R
C LEVEL
40 39 38 37 36 35 34 33
4142
43
44
45
46
47
48
GC
SLICE
CLP
(CLP4)
–––
CLP
(CLP4)
CLP
(CLP4)
Block Diagram and Pin Configuration
(Top View)
For the availability of this product, please contact the sales office.
– 2 –
CXA1391Q/R
Pin Description
PIn
No.
1
2
3
4
Symbol
CLP C YH
Pin voltage
3 to 3.5V
Equivalent circuit Description
Capacitor connecting pin
for YHclamp
(Clamp at CLP2)
DL YHsignal input pin
(Input from 1H delay line)
Sig: Typ. 200mV
(Positive polarity)
Capacitor connecting pin
for DL YHclamp
(Clamp at CLP4)
DL YHsignal output pin
(To 1H delay line)
Sig: Typ. 400mV
Max. 600mV
(Negative polarity)
2.4k 2.4k
180µA 80µA
1k 147
800
80µA
5k
1k
147
2.6k 2.6k
180µA 40µA
1k 147
1k
400µA
200
1
2
3
4
DL YHIN 3.65V
CLP C
DL YH2.6 to 3.8V
DL YH
OUT 2.7 to 3.1V
Note) Pin voltage for input and output pins indicate black level.
– 3 –
CXA1391Q/R
5YHOUT1 1.9 to 2.3V
YH1 signal output pin
Sig: Typ. 1V
Max. 1.5V
(Positive polarity)
160µA
100
400µA
100
80µA
500
1k
30k 147 100k
100k
30k
40µA
5
6
7
854
6YHOUT2 1.9 to 2.3V
YH2 signal output pin
Sig: Typ. 1V
Max. 1.5V
(Positive polarity)
7TP
2.6 to 3.0V
(YH)
2.5 to 2.9V
(G)
TP OUT (adjusting pin)
1H mode: Outputs YH1–YH0
0H mode: Outputs Gch
C-slice OUT
(Mode selection is executed
through Pin 8)
8DL YHGAIN
0V
(0H Mode)
1.8 to 5V
(1H Mode)
DL YHsignal gain control
pin
(For 1H delay line gain
compensation of YH)
TP (Pin 7) mode selection
0H Mode: 0V
1H Mode: 1.8 to 5V
54 Y1 GAIN
0V:
Common
control by
Pin 57
1.8 to 5V
Independent
control
DLY1signal gain control pin
(1H delay line gain
compensation)
0V: DLY1signal gain
control is executed in
common with DLY2
signal gain control.
1.8 to 5V: DLY1signal gain
control is executed
independently from
DLY2signal gain
control.
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 4 –
CXA1391Q/R
9CLP4
CLP4 pulse input pin
(BLK clamp)
(CMOS level input,
VTH = 2.5V)
10 CLP2
CLP2 pulse input pin
(OPB clamp)
(CMOS level input,
VTH = 2.5V)
11 VAP OUT 2.6 to 3.0V V-APCN signal output pin∗
Sig: Max. 1.2Vp-p
V-APCN signal output level
adjustment pin
2.6k 2.6k
180µA 12µA
1k
147
280µA
431
40µA
30k1k
40µA
25k
1k
25k
147
147
9
10
11
12
13
12 VAP GAIN 1.8 to 5V
(Control)
Capacitor connecting pin
for VAP clamp
(Clamp at CLP4)
13 CLP C VAP 3.4 to 3.8V
5V
0
5V
0
∗V-APCN: Vertical Aperture Compensation
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 5 –
CXA1391Q/R
14 VAP SLICE 1.8 to 5V
(Control)
V-APCN signal
dark slice volume
adjustment pin
2.6k 2.6k
180µA 20µA
1k
147
40µA
30k
1k
30k
147
147
2.6k 2.6k 1k
20µA180µA
147
147
14
15
16
15 CLP C CS 3.5 to 3.7V Capacitor connecting pin
for CS clamp
(Clamp at CLP4)
16 CS IN C-Couple
input
2.9 to 3.3V
AGC CS signal input pin
Sig: Max. 1V
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 6 –
CXA1391Q/R
17 R–Y GAIN
0V:
R–G output
1.8 to 5V:
R–Y output
R–Y signal output level
adjustment pin
Pin 20 Mode select
0V: R–G output
1.8 to 5V: R–Y output
18 B–Y GAIN
0V:
B–G output
1.8 to 5V:
B–Y output
B–Y signal output level
adjustment pin
Pin 19 Mode select
0V: B–G output
1.8 to 5V: B–Y output
23 CS GAIN 1.8 to 5V
(Control) V-APCN CS signal
gain control pin
B–Y hue control pin
R–Y hue control pin
19 B–Y OUT
20 R–Y OUT
2.75 to 3.15V
(Hue OFF)
2.35 to 2.75V
(Hue ON)
46 DLC0OUT 1.8 to 2.2V
52 DLY0OUT 1.4 to 1.8V
53 DLY1OUT 2.8 to 3.2V
21 B–Y Hue 0V:
Hue OFF
22 R–Y Hue 0V:
Hue OFF
B–Y signal output pin
Sig: Typ. 590mVp-p
R–Y signal output pin
Sig: Typ. 800mVp-p
DLC0signal output pin
Sig: Typ. 200mVp-p
Max. 600mVp-p
(Positive polarity)
DLY0signal output pin
Sig: Typ. 200mVp-p
Max. 600mVp-p
(Positive polarity)
DLY1signal output pin
Sig: Typ. 200mVp-p
Max. 600mVp-p
(Positive polarity)
1k
30k 100k
100k
30k
40µA
17 18 23
300µA
431
19
20
46
52
53
1k
30k 147 80k
100k
30k
40µA 21 22
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 7 –
CXA1391Q/R
24 CS OUT 1.5 to 1.8V CS signal output pin
Sig: Max. 1V
200µA
431
1k
30k
100k
30k
40µA
80µA
431
147
24
25
27
25 YLOUT 1.9 to 2.3V YLsignal output pin
26 GND1 GND
27 C-γCONT 0V: Typ.
γcurve Chroma (R.G.B)
γcurve adjustment pin
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 8 –
CXA1391Q/R
28 WB R 1.4 to 2V
R signal output pin
WB Mode:
Sig: Typ. 400mV
γMode:
Sig: Typ. 500mV
29 WB G 1.4 to 2V
G signal output pin
WB Mode:
Sig: Typ. 400mV
γMode:
Sig: Typ. 500mV
30 WB B 1.4 to 2V
B signal output pin
WB Mode:
Sig: Typ. 400mV
γMode:
Sig: Typ. 500mV
31 WB DC 1.4 to 2V
When used as output pin,
it is an Auto WB DC output
pin.
Pin 28, 29 and 30 turn
to WB mode.
When connected to Vcc:
Pins 28, 29 and 30 turn to
γmode.
200µA
431
67µA
1k
40µA
30k
1k
30k
18k
18k
100k
200µA
431 1k
100k
300
28
29
30
31
32
33
47
32 C SLICE 0V:
Slice OFF
Chroma (R.G.B) signals
dark slice level adjustment
pin
33 C LEVEL 1.8 to 5V
(Control)
Chroma (R.G.B) gain
control pin
(Chroma modulation factor
control for all 3 channels)
47 C1GAIN 1.8 to 5V
(Control)
DL C1signal gain control
pin
(1H delay line gain
compensation)
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 9 –
CXA1391Q/R
34 CLP C R 3.0 to 3.6V Capacitor connecting pin
for R WB amplifier clamp
(Clamp at CLP2)
35 CLP C G 3.0 to 3.6V Capacitor connecting pin
for G WB amplifier clamp
(Clamp at CLP2)
36 CLP C B 3.0 to 3.6V Capacitor connecting pin
for B WB amplifier clamp
(Clamp at CLP2)
37 R GAIN 1.8 to 5V
(Control)
Rch WB amplifier gain
control pin
(Pre-WB)
40 B GAIN 1.8 to 5V
(Control)
Bch WB amplifier gain
control pin
(Pre-WB)
2.2k 2.2k
125µA 40µA
1k
1k
10µA
1k
80µA
15k
1k
15k
147
147
147
34 35 36
37
40
38
39
38 R CONT 2.5 to 4.6V Rch WB amplifier gain
control pin
39 B CONT 2.5 to 4.6V Bch WB amplifier gain
control pin
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 10 –
CXA1391Q/R
41 ID
ID pulse
(color discrimination pulse)
input pin
(CMOS level VIH = 2.5V)
ID = L C0→CR
C1→CB
ID = H C0→CB
C1→CR
1k
15k 147 100k
15k
80µA
40µA
30k
1k
147
100k
147
6k
1k
6k
40µA
147
41
42
43
44
42 B MTX
1.8 to 5V
(Control)
0V
(Preset)
B signal operations MTX
coefficient adjustment pin
(Coefficient 0.22)
Refer to Note 2.
43 CLP C
MPX2 2.7 to 3.1V
Capacitor connecting pin
for MPX clamp
(Clamp at CLP2)
44 CLP C
MPX1 2.7 to 3.1V
5V
0
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 11 –
CXA1391Q/R
45 R MTX
1.8 to 5V
(Control)
0V
(Preset)
R signal operations MTX
coefficient adjustment pin
(Coefficient 0.617)
Refer to Note 2.
2.6k 2.6k
150µA 11µA
1k 147
1k
1k
300k 147 100k
30k
40µA
100k
147 147
7.5k
40µA 40µA
40µA
40µA
40µA
40µA
40µA
45
48 55 56
49 50
48 DLC1IN C-Couple
input
3.1 to 3.5V
DL C1signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
55 DLY1IN C-Couple
input
3.6 to 4.0V
DL Y1signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
56 DLY2IN C-Couple
input
3.6 to 4.0V
DL Y2signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
49 S2 IN 1.9V
S2 signal input pin
Sig: Typ. 500mV
Max. 1500mV
50 S1 IN 1.9V
S1 signal input pin
Sig: Typ. 500mV
Max. 1500mV
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 12 –
CXA1391Q/R
51 CLP C Y03.3 to 3.7V Capacitor connecting pin
for Y0clamp
(Clamp at CLP4)
20k
10µA
300
80µA
1k
147
15k
5k
147 1k
2.6k1k
40µA 150µA
51
57
59 60
57 Y2GAIN
1.8 to 5V
(3H Mode)
0V
(2H Mode)
DL Y2signal gain control
pin
(1H delay line gain
compensation)
V-APCON mode selection
0V: 2H Mode
1.8 to 5V: 3H Mode
59 LPF Adj. 1 1.8 to 2.2V
Connecting pin of the
external resistor that
determines the
characteristics of the LPF
for 1H DL.
(External resistor in the
range of 15 to 27kΩ)
60 LPF Adj. 2 1.8 to 2.2V
Connecting pin of the
external resistor that
determines the
characteristics of the
chroma LPF
(LPF for R, G, B, CS).
(External resistor in the
range of 15 to 62kΩ)
58 GND2 GND
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 13 –
CXA1391Q/R
61 LPF Adj. 3 1.8 to 2.2V
Connecting pin of the
external resistor that
determines the
characteristics of the LPF
for V-APCN.
(External resistor in the
range of 15 to 62kΩ)
When connected to Vcc,
the LPF for V-APCN turns
OFF.
1k
30k 147
30k
40µA
100k
10µA
300300
1k
120k
10k
61
63
64
63 Y-γCONT
0V
(Typ. γcurve)
1.8 to 5V
(Control)
YHγcurve adjustment
64 YHIN 0.95V
YHsignal input
Sig: Typ. 220mV
Max. 660mV
62 Vcc Power supply 5V (Typ.)
PIn
No. Symbol Pin voltage Equivalent circuit Description
– 14 –
CXA1391Q/R
Electrical Characteristics
Item
Current consumption
S2–S1 Amp Gain
DLC1
gain control
S1+S2 Amp
Chroma matrix
(Gch)
Note 3)
Chroma matrix
(Rch)
Note 3)
Chroma matrix
(Bch)
Note 3)
Max.
Min.
Gch Y
CR/Y
–CB/Y
Rch CR
Y
(Preset)
Y (Max.)
Y (Min.)
Bch–CB
Y
(Preset)
Y (Max.)
Y (Min.)
ID
SSG
DLC1H
DLC1L
SAG
GY
GCR
GCB
RCR
RYP
RYH
RYL
BCB
BYP
BYH
BYL
Input: S1 IN = –62.5mV, S2 IN = 62.5mV
Calculations: DLC0OUT/S1 IN
Input: DLC1IN = 100mV
Conditions: C1Gain = 5V
C-level = 5V
Calculations: (WB-R/DLC1IN) –CG Note2)
Conditions: C1Gain = 0V
(Others same as DLC1H)
Input: S1 IN = 500mV
Calculations: DLY0OUT/S1 IN
Input: S1 IN = S2 IN = 300mV
Conditions: C-level = 5V
Calculations: WB-G (ID = H, L average)
Input: S1 IN = S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-G/GY (ID = L)
ID = H (Others same as GCR)
Input: S1 IN = –62.5mV, S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-R (ID = L)
Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-R/RCR(ID = H)
RMTX = 5V (Others same as RYP)
RMTX = 1.8V (Others same as RYP)
Input: S1 IN = 62.5mV, S2 IN = –62.5mV
Conditions: C-level = 5V
Calculations: WB-B (ID = H)
Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-B/BCB(ID = H)
BMTX = 5V (Others same as BYP)
BMTX =1.8V (Others same as BYP)
25
–3
6
–2
–15
80
0.9
–1.1
70
0.15
0.22
0.11
80
0.2
0.31
0.13
34.5
–1.95
7
–0.85
–14
100
1
–1
85
0.168
0.25
0.125
100
0.22
0.34
0.15
43
–1
9
0
–13
120
1.1
–0.9
100
0.186
0.27
0.14
120
0.24
0.37
0.17
mA
dB
dB
dB
dB
mV
—
—
mV
—
—
—
mV
—
—
—
Symbol Conditions Min. Typ. Max. Unit
– 15 –
CXA1391Q/R
WB
GAIN
RCONT Max.
RCONT Min.
BCONT Max.
BCONT Min.
RGAIN Max.
BGAIN Max.
RCH
RCL
BCH
BCL
RGH
BGH
Input: DLC1IN = –200mV
Conditions: C-level = 5V
RCONT = 4.6V (ID = H)
Calculations: WB-R/WB-RTyp. Note 4)
WB-R Typ. is the tested output of WB-R
when RCONT is set to 4V (Other inputs,
conditions same as RCH)
Test: RCONT = 2.5V
(Others same as RCH)
Input: DLC1IN = 150mV
Conditions: C-level = 5V
BCONT = 4.6V (ID = L)
Calculations: WB-B/WB-BTyp. Note 4)
WB-B Typ. is the tested output of WB-B
when BCONT is set to 4V (Other inputs,
conditions same as BCH)
Test: BCONT = 2.5V
(Others same as BCH)
Input: DLC1IN = –200mV
Conditions: RCONT = 2.5V RGAIN = 5V
C-level = 5V (ID = H)
Calculations: WB-R/WB-RMin.
WB-R Min. is the tested WB-R, when
tested under the same conditions as RCL.
Input: DLC1IN = 150mV
Conditions: BCONT = 2.5V BGAIN = 5V
C-level = 5V (ID = L)
Calculations: WB-B/WB-BMin.
WB-B Min. is the tested WB-B, when
tested under the same conditions as BCL.
7.5
–8.4
7.5
–8.4
8.6
11.4
8.2
–7.9
8.2
–7.9
9.2
12.2
8.5
–7.4
8.5
–7.4
—
—
dB
dB
dB
dB
dB
dB
Item Symbol Conditions Min. Typ. Max. Unit
– 16 –
CXA1391Q/R
Bch
color
difference
matrix
Note 5)
Gch
color
difference
matrix
Note 5)
R–G OUT/
WB-B
R–Y OUT/
WB-B
B–Y GAIN
Max.
B–Y Hue Max.
B–Y Hue Min.
R–Y/R–G
B–Y/B–G
BMBY
BMRY
BMG
BMHH
BMHL
GMR
GMB
Input: S1IN = 200mV S2IN = 160mV
DLC1IN = 220mV
Conditions: C-γCONT = WB DC =
C-Slice = C-level = 5V
RCONT = 2.5V
BCONT = 4.6V (ID = L)
Calculations: B–Y OUT/WB-B
Conditions: R–Y GAIN = 1.8V
Calculations: R–Y OUT/WB-B
(Others same as BMBY)
Conditions: BCONT = 4V
1. B–Y OUT is tested when B–Y
gain = 0V and taken as A. (Other
conditions are the same as BMBY)
2. B–Y OUT is tested when B–Y
gain = 5V and taken as B. (Other
conditions are the same as BMBY)
Calculations: B/A
Conditions: B–Y HUE = 1.8V
(Others same as BMBY)
Calculations: R–Y OUT/B–Y Typ.
B–Y Typ. is the value of the tested B–Y
OUT when B–Y hue=0V (Other conditions
are the same as BMBY). Note 6)
B–Y HUE = 5V
(Others same as BMHH)
Input: S1IN = 830mV S2IN = 660mV
DLC1IN = –230mV
Conditions: WB-DC = C-level = 5V
RCONT = BCONT = 2.5V
1. R–Y OUT is tested when R–Y
gain = 0V and taken as A.
2. R–Y OUT is tested when R–Y
gain = 1.8V and taken as B.
Calculations: B/A
Input: (The same as GMR)
Conditions:
1. B–Y OUT is tested when B–Y
gain = 0V and taken as A.
2. B–Y OUT is tested when R–Y
gain = 1.8V and taken as B.
(Others same as GMR)
Calculations: B/A
0.4
–0.24
3.0
0.58
—
0.81
0.63
0.44
–0.21
3.3
0.68
–0.67
0.85
0.66
0.48
–0.17
—
—
–0.58
0.89
0.7
—
—
—
—
—
—
—
Item Symbol Conditions Min. Typ. Max. Unit
– 17 –
CXA1391Q/R
C-Slice
Gch γ
curve
Typ.–Min.
Typ.–Max.
C-γCONT=0V
Gch-WB=400mV
C-γCONT=0V
Gch-WB=800mV
C-γCONT=0V
Gch-WB=100mV
C-γCONT=1.8V
Gch-WB=400mV
C-γCONT=1.8V
Gch-WB=800mV
C-γCONT=1.8V
Gch-WB=100mV
C-γCONT=5V
Gch-WB=400mV
C-γCONT=5V
Gch-WB=800mV
C-γCONT=5V
Gch-WB=100mV
CSLL
CSLH
γTyp.
γL8
γL1
γM4
γM8
γM1
γH4
γH8
γH1
Input: DLY1IN = –400mV
Conditions: C-level = 5V
Y1GAIN = 1.8V
C-Slice = 1.8V (ID = H)
Calculations: C-Slice Typ. -TP
C-Slice Typ. is the TP output of
C-Slice = 0V.
Conditions: C-Slice =5V
(Others same as CSLL)
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: Y1GAIN = 1.8V
C-level is valied and
adjusted to obtain 400mV at
WB-G.
After that C-level is fixed
during test.
WB-DC is set to OPEN during C-level
adjusted and set to 5V during test.
Calculations: WB-G is tested.
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
Conditions: Same as γTyp.
Calculations: WB-G/γTyp.
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γL8)
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: CγCONT = 1.8V
Calculations: WB-G/γTyp.
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
(Others same as γM4)
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γM4)
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: CγCONT = 1.8V
Calculations: WB-G/γTyp.
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
(Others same as γH4)
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γH4)
0
95
450
1.13
0.36
0.9
1.13
0.45
0.9
1.13
0.26
5
120
500
1.2
0.4
1
1.2
0.5
1
1.2
0.3
15
145
550
1.25
0.44
1.1
1.25
0.55
1.1
1.25
0.35
mV
mV
mV
—
—
—
—
—
—
—
—
Item Symbol Conditions Min. Typ. Max. Unit
– 18 –
CXA1391Q/R
Yγ
TP
YHAMP
Chroma level Max./Min.
WB DC
Yγ1.0 (Typ.)
Yγ2.0/Yγ1.0
Yγ0.5/Yγ1.0
Yγ0.5 (Max.)/
Yγ1.0
Yγ0.5 (Min.)/
Yγ1.0
TP (YH)
TP (DLYH)
TP (GWBS)
Min. Gain
Max. Gain
YγT
Yγ2.0
Yγ0.5
YγH
YγL
TPY
TPDY
TPG
YLG
YHG
GCL
WDDC
Input: YHIN = 220mV
Calculations: DLYHOUT
Input: YHIN = 440mV
Calculations: DLYHOUT/YγT
Input: YHIN = 110mV
Calculations: DLYHOUT/YγT
Input: YHIN = 110mV
Conditions: YγCONT = 1.8V
Calculations: DLYHOUT/YγT
Input: YHIN = 110mV
Conditions: YγCONT = 5V
Calculations: DLYHOUT/YγT
Input: YHIN = 220mV
Conditions: DLYHGAIN = 1.8V
Calculations: TP/DLYHOUT
Input: DLYHIN = YγT ×0.7
Conditions: Same as TPY
Calculations: TP/–DLYHOUT Note 7)
Input: S1IN = S2IN = 500mV
DLY1IN = 200mV
Conditions: Y1GAIN = 1.8V
Calculations: TP/WB-G
Input: YHIN = 220mV
DLYHIN = – [YγT ×–3.5dB]
Conditions: DLYHGAIN = 1.8V
Calculations: TP is tested to check that
the signal level is below
0mV in relation to black
level. Note 8)
Input: YHIN = 220mV
DLYHIN = – [YγT ×–12dB]
Conditions: DLYHGAIN = 5V
Calculations: TPTP is tested to check that
the signal level is over
0mV in relation to black
level. Note 8)
Input: DLC1IN = 200mV
Conditions:
1. WB-G is tested when C-level = 5V
and taken as GC-level Min.
2. WB-G is tested when C-level = 1.8V
and taken as GC-level Max.
(Both 1 and 2 test at ID-H.)
Calculations: GC-level Max. /
GC-level Min.
Test: WB-DC
–440
1.23
0.59
0.64
0.54
–5
–5
–2
—
12
1.55
1.4
–400
1.37
0.66
0.71
0.6
–4
–4
0
—
—
1.65
1.6
–360
1.51
0.73
0.78
0.66
–3
–3
2
3.5
—
1.75
2
mV
—
—
—
—
dB
dB
dB
dB
dB
—
V
Item Symbol Conditions Min. Typ. Max. Unit
– 19 –
CXA1391Q/R
YL
Note 5)
YHOUT1 (OH mode)
YHOUT1 1H/0H
YHOUT2 (0H) /YHOUT1
YHOUT2 (1H) /YHOUT1
VAP Typ.
Note 9)
VAP Slice
Note 9)
YLOUT/
RγOUT
YLOUT/
BγOUT
YLOUT/
GγOUT
YLR
YLB
YLG
YH1Z
YH1O
YH2Z
YH2O
VAPT
VS
Input: S1IN = 150mV S2IN = 450mV
Conditions: C-γCONT = WB
DC = C-Slice =
C-level = 5V
RCONT = 4.6V BCONT = 2.5V
BGAIN = 1.8V (ID = L)
Calculations: YLOUT/WB-R
Input: S1IN = 200mV S2IN = 160mV
DLC1IN = 220mV
Conditions: C-γCONT = WB
DC = C-Slice =
C-level = 5V RCONT = 2.5V
BCONT = 4.6V (ID = L)
Calculations: YLOUT/WB-B
Input: S1IN = 830mV S2IN = 660mV
DLC1IN = –230mV
Conditions: WB-DC = C-level = 5V
RCONT = BCONT = 2.5V
Calculations: YLOUT/WB-G
Input: YHIN = 220mV
Calculations: YHOUT1 is tested.
Input: DLYHIN = – (YγT ×–4dB)
Conditions: DLYHGAIN = 1.8V
Calculations: YHOUT1/YH1Z Note 8)
Input: YHIN = 220mV
Calculations: YHOUT2/YH1Z
Input: YHIN = 220mV
Conditions: DLYHGAIN = 1.8V
Calculations: YHOUT2/YHOUT2Typ.
YHOUT2Typ. is YHOUT2 output tested at
YH2Z.
Input: S1IN = S2IN = 125mV
Conditions: VAP GAIN = 1.8V
VAP Slice = 1.8V
Y2GAIN = 1.8V
Calculations: VAP OUT is tested.
Input: S1IN = S2IN = 1000mV
Conditions: Y2GAIN = 1.8V
1. VAP OUT is tested when VAP
Slice=1.8V and taken as SMin.
2. VAP OUT is tested when VAP
Slice=5V and taken as SMax.
Calculations: SMax.–SMin. Note 10)
0.27
0.08
0.54
900
–1
–1
–6.5
–250
256
0.3
0.1
0.6
1000
0
0
–6
–200
320
0.34
0.12
0.66
1100
1
1
–5.5
–150
384
—
—
—
mV
dB
dB
dB
mV
mV
Item Symbol Conditions Min. Typ. Max. Unit
– 20 –
CXA1391Q/R
DLY1
gain
Note 11)
DLY2
gain
Note 11)
CS
Note 12)
Min.
Max.
Min.
Max.
VCS Typ.
VCS Min.
VCS Max.
VCS Typ.
DY1L
DY1H
DY2L
DY2H
VCST
VCSL
VCSH
CST
Input: S1IN = S2IN = 500mV
DLY1IN = –200mV
Conditions: VAP GAIN = VAP
Slice = Y1GAIN = 1.8V
Calculations: VAP-OUT is tested to check
that the signal level is over
0mV in relation to black
level.
Input: S1IN = S2IN = 500mV
DLY1IN = –110mV
Conditions: VAP GAIN = VAP Slice =
1.8V Y1GAIN = 5V
Calculations: VAP-OUT is tested to check
that the signal level is below
0mV in relation to black
level.
Input: S1IN = S2IN = –167mV
DLY2IN = –66.7mV
Conditions: VAP GAIN = VAP
Slice = Y1GAIN = Y2GAIN = 1.8V
Calculations: VAP-OUT is tested to check
that the signal level is over
0mV in relation to black
level.
Input: S1IN = S2IN = –167mV
DLY2IN = –37.5mV
Conditions: Y2GAIN = 5V
(Others same as DY2L)
Calculations: VAP-OUT is tested to check
that the signal level is below
0mV in relation to black
level.
Input: S1IN = S2IN = 167mV
Conditions: Y1GAIN = Y2GAIN = 1.8V
CS GAIN = 5V
Calculations: CS OUT is tested.
Conditions: CS GAIN = 0V
(Others same as VCST)
Calculations: CS OUT/VCST
Conditions: CS GAIN = 1.8V
(Others same as VCSL)
Input: CS-IN = 500mV
—
5
—
5
90
—
4.4
440
—
—
—
—
120
0
465
0
—
0
—
150
0.05
—
490
dB
dB
dB
dB
mV
—
—
mV
Item Symbol Conditions Min. Typ. Max. Unit
– 21 –
CXA1391Q/R
Note 1) For pins without specific instructions regarding input, feed the DC value shown on the Test Circuit.
Calculations are mentioned utilizing the pin name or the electrical characteristics symbols. Otherwise,
for exceptional notations explanatory notes, are given with every case.
Note 2) In this item, the gain of DLC1amplifier exclusively is calculated. CG is the gain of the system from
DLC1IN to WB-R from which DLC1GC amplifier gain has been excluded.
—CG calculating method—
In the actual calculation, the system on C0side is utilized.
Input: S1IN = –62.5mV S2IN = 62.5mV
Condition: Same as DLC1H
Calculations: CG = 20log (WB-R/DLC0OUT)
Note 3) Chroma matrix operations
R = 2 [CR+ αY] α: Control with RMTX (Preset 0.167)
G = Y – (CR+ CB)
B = 2 [CB+ ß (Y – C)] ß: Control with BMTX (Preset 0.22)
Note 4) With the typical gain taken when R CONT is at 4V, compare with the gain during Max. and Min. The
same for B CONT.
Note 5) Adjustment and testing is performed so that signals are output only for each of R, G, B channels
respectively.
Note 6) Comparison with B–Y OUT when R–Y HUE = 0V (HUE OFF).
The same for B–Y HUE.
Note 7) The compensation of difference in gain of YH0 andYH1 is as follows.
1) At DLYHGAIN = 1.8V, DLYHamplifier gain is 3dB.
2) Test DLYHOUT (tested at YrT) when YHIN = 220mV signal is input.
3) The difference in gain between YH0 and YH1 is compensated by inputting the signal as –3dB to
DLYHIN.
Note 8) The amplifier input is varied and the gain confirmed.
Note 9) VAP (Vertical Aperture Compensation)
Note 10) Dark slice variable volume. (Output level difference between the value slice volume at Max. and slice
volume at Min.)
Note 11) Utilizing V-APCN 2H mode, DLY1amplifier exclusive gain is obtained through operations. However,
as the amplifier gain cannot be tested directly, only the upper and lower limits of the gain control are
checked according to the following method.
(a) Lower limit check
S1 IN = S2 IN = 500mV (At that time KNEE circuit input turns to 200mV)
DLY1IN = –200mV (For others refer to the conditions chart)
In this condition, if we have VAP OUT ≥0, this indicates that DLY1amplifier is below 0dB.
(b) Upper limit check
S1 IN = S2 IN = 500mV
DLY1IN = –110mV (in (a) the –5dB of –200mV)
In this condition, if we have VAP OUT ≤0, this indicates that DLY1amplifier is above 5dB.
Note 12) CS (Chroma Suppress)
– 22 –
CXA1391Q/R
Timing Chart for Testing
30µ 30µ 30µ 30µ
Differs with each test
DLYH IN
CS IN
DLC1 IN
S1
S2
DLY1 IN
DLY2 IN
YH IN
Output signal
2µ2µ
2µ 2µ
5µ 5µ
15µ 15µ
0V
5V
0V
5V
0V
5V
Input waveform
tD
CLP2
CLP4
Output waveform
DLYH OUT
YH OUT1
YH OUT2
TP
VAP_OUT
B – Y OUT
R – Y OUT
CS OUT
YL OUT
WB_R
WB_G
WB_B
DLC0 OUT
DLY0 OUT
DLY1 OUT
– 23 –
CXA1391Q/R
CLP C YH
DLYH IN
CLP C DLYH
DLYH OUT
YH OUT 1
YH OUT 2
TP
DLYH GAIN
CLP4
CLP2
VAP OUT
VAP GAIN
CLP C VAP
VAP SLICE
CLP C CS
CS IN
C SLICE
WB DC
WB B
WB G
WB R
C-r CONT
GND 1
YL OUT
CS OUT
CS GAIN
R-Y HUE
B-Y HUE
R-Y OUT
B-Y OUT
B-Y GAIN
R-Y GAIN
S2 IN
S1 IN
CLP C YO
DLY0 OUT
DLY1 OUT
Y1 GAIN
DLY1 IN
DLY2 IN
Y2 GAIN
GND 2
LPF ADJ 1
LPF ADJ 2
LPF ADJ 3
VCC
Y-r CONT
YH IN
V
V
DLC1 IN
C1 GAIN
DLCO OUT
R MTX
CLP C MPX1
CLP C MPX2
B MTX
ID
B GAIN
B CONT
R CONT
R GAI N
CLP C B
CLP C G
CLF C R
C LEVEL
0.1
0V 0V 0.1
V0V 0V 4V 0V 0.1V 0V0.1V0.1V4VID0.1
V
DC 1.9V
DC 1.9V
0.1
0.1
0.1
0V
0V
27k
62k
62k
5V
5V
0V
DC 0.95V
0.1 0.1
DC
3.65V
0V
CLP4
CLP2 0V 0V0.1 0.1
0.1
0V
5V
0V
0V
0V
0V
0V
0V
10
62k
B-r
G-r
R-r
CLP
(CLP2)
&
MPX
B
G
R
-CB
CR
Y
C1
Y0
Y1
CS VAP
CS-Y
MAX
CS
V-APCN
Y2
Y1
Y0
Y1
Y2
C0
Y0
Y0
V-APCN
YH1
YH0
YH0
YH1
V-APCN
G ch SLICE
CS-Y
B-Y
R-Y
C0
GC
GC
LPF
LPF
CLP
(CLP4)
LPF
CLP
(CLP4)
3H
APCN 2H
APCN
KNEE
LPF
CLP
(CLP2)
CLP
(CLP4)
LPF
CLP
SLICE
CLP
(CLP4)
r
YL MTX
MTX
Hue & GC
LPF
WB AMP
MATRIX
LPF
LPF
WB CONTROL
GC
GC
16
2345678910 11 12 13 14 15
1
GC
B-Y
R-Y G-WB
R-WB
B-WB
CLP
(CLP2)
LPF
r
B-r
R-r
G-r
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KNEE
LPF
ABS
KNEE
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
40 39 38 37 36 35 34 33
41
42
43
44
45
46
47
48
GC
SLICE
CLP
(CLP4)
–––
CLP
(CLP4)
CLP
(CLP4)
Test Circuit (Typ. setting)
Note 1) µF is unit of capacitor
Note 2) indicates testing pin. (AC, DC test)
Note 3) Input pin DC value indicates input signal black level.
Note 4) indicate relay, side, normal close.
– 24 –
CXA1391Q/R
Standard Control Characteristics (Vcc = 5V, Ta = 25°C)
C1 GAIN control characteristics R-MTX coefficient
R GAIN control characteristicsB-MTX coefficient
B GAIN control characteristics R/B CONT control characteristics
GAIN converted into unit
3
2
1
GAIN
C1 GAIN voltage (V)
234 0
0.3
0.2
0.1 2345
R-MTX voltage (V)
Preset
Preset
0.4
B-MTX voltage (V)
0
0.3
0.2
0.1 2453
7
R GAIN voltage (V)
02 3 4 5
6
5
4
3
2
1/GAIN
3
R/B CONT voltage (V)
2345
2
1
GAIN
10
8
6
4
22345
B GAIN voltage (V)
5
GAIN
– 25 –
CXA1391Q/R
3
2
1
2345
R–Y/B–Y GAIN voltage (V)
GAIN
R–Y/B–Y GAIN control characteristics
3
2
1
2345
Y1/Y2 GAIN voltage (V)
GAIN
Y1/Y2 GAIN control characteristics
C-SLICE control characteristics
GAIN
1.5
1
0.5 3
C-LEVEL voltage (V)
245
C-SLICE control characteristics
5
C-SLICE power supply (V)
432
(mV)
150
100
50
0
BLACK DC difference between sliced
signal and during sliced OFF
R–Y/B–Y HUE control characteristics
5
R–Y/B–Y HUE voltage (V)
432
40°
30°
20°
10°
–10°
0°
–20°
–30°
CS GAIN control characteristics
5
CS GAIN voltage (V)
432
400
(mV)
300
200
100
CS output during
S1 = S2 = 125mV input
(3H_Mode)
– 26 –
CXA1391Q/R
DLYH GAIN control characteristics VAP control characteristics
15
5
10
GAIN (dB)
02345
DLYH GAIN voltage (V)
400
100
300
VAP OUT (mV)
0
200
VAP GAIN voltage (V)
2345
VAP_OUT output
during S1 = S2 = 250mV input
(3H_Mode)
VAP SLICE control characteristics
100
300
200
(mV)
2345
VAP SLICE voltage (V)
VAP GAIN = 0V
Diminution of VAP OUT
output level
– 27 –
CXA1391Q/R
Chroma γ curve (standardize)
1.2
1.0
0.8
0.6
0.4
0.2
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
γ input (standardize)
γ output (standardize)
123
YH γ curve (standardize) (mV)
γ output (standardize)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
γ input (standardize)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
123
V-APCN Knee (standardize) (mV)
Knee output (standardize)
1.0
0.2
Knee input (standardize)
Standardize at typical input (S1 = S2 = 500mV)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.8
0.6
0.4
0.2
2.0
Standardize at typical input (220mV)
1: Y – γ CONT=1.6V (Max.)
2: Y – γ CONT=0V (Typ.)
1: Y – γ CONT=5V (Min.)
Standardize at typical input (400mV)
1: C – γ CONT=1.6V (Max.)
2: C – γ CONT=0V (Typ.)
1: C – γ CONT=5V (Min.)
Standard Design Data
– 28 –
CXA1391Q/R
800
600
400
200 20k10k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60PIN) ] (Ω)
τ
D
(nsec)
Chroma Adjust characteristics
<Group Delay> R–Y out
B–Y out
S1, S2 →
fc (MHz)
1.5
1.0
0.5
10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60PIN) ] (Ω)
<Cut Off> (fc: –3dB)
Pre-Filter Adjust characteristics DL Y0 out
DL C0 out
S1, S2 →
<Group Delay> <Cut Off> (fc: –3dB)
300
250
200
150
10010k 15k 20k 25k 30k
τ
D
(nsec)
REXT [LPF ADJ1 (59PIN) ] (Ω)10k 15k 20k 25k 30k
REXT [LPF ADJ1 (59PIN) ] (Ω)
3.0
2.5
2.0
1.5
1.0
fc (MHz)
– 29 –
CXA1391Q/R
<Cut Off> (fc: –3dB)
CS-VAP Adjust characteristics (S1, S2 → CS OUT)
<Group Delay>
800
600
400
τ
D
(nsec)
10k 20k 30k 40k 50k 60k 70k 80k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
10k 20k 40k 50k 60k 70k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
80k30k
1.0
fc (MHz)
1.5
0.5
– 30 –
CXA1391Q/R
600
400
200
10k 20k 30k 40k 50k 60k 70k 80k
10k 20k 40k 50k 60k 70k 80k30k
1.0
1.5
2.0
0.5
<Cut Off> (fc: –3dB)
CS-Y LPF Adjust characteristics (CS IN → CS OUT)
<Group Delay>
τ
D
(nsec)
REXT [LPF ADJ2 (60 PIN) ] (Ω)
REXT [LPF ADJ2 (60 PIN) ] (Ω)
fc (MHz)
VAP LPF Adjust characteristics
– 31 –
CXA1391Q/R
600
400
200
10k 20k 30k 40k 50k 60k 70k 80k
10k 20k 40k 50k 60k 70k 80k30k
1.0
1.5
0.5
<Cut Off> (fc: –3dB)
VAP LPF Adjust characteristics (S1, S2 → VAP OUT)
<Group Delay>
τ
D
(nsec)
REXT [LPF ADJ3 (61 PIN) ] (Ω)
REXT [LPF ADJ3 (61 PIN) ] (Ω)
fc (MHz)
– 32 –
CXA1391Q/R
PG-IN
DATA-IN
VCC1
XSP3
XSP2
XSP1
GND
FSHI
F3-CLP
F2-CLP
F1-CLP
XSH2
CLP4
XSHD
XSHP
AGC-SEL
AGC-MAX
AGC-CONT
OP-OUT
OPIN-N
OPIN-P
AGC-OUT
AGC-CLP
DET-
LEVEL
XSH1
DC-OUT
GY-OUT
F1-OUT
F2-OUT
F3-OUT
CS-CLP
CS-CCD-SL
CS-CCD-GC
CS-OUT
CS-AGC-GC
CS-AGC-
SL
DET-
OUT
VCC2
IRIS-GC
IRIS-LEVEL
DET-CLP
GND
IRIS-CLP
IRIS-OUT
VG-OUT
WND
PBLK
CLP1
CXA1390 Q/R
DLY0-
OUT
DLY1-OUT
Y1-GAIN
DLY1-IN
DLY2-IN
Y2-GAIN
GND
LPF-ADJ1
LPF-ADJ2
LPF-ADJ3
VCC
YGAM-
CONT
YH-IN
YO-
CLP
S1-IN
S2-IN
DLC1-IN
C1-GAIN
DLCO-OUT
R-MIX
MPX2-CLP
MPX1-CLP
B-MTX
ID
B-GAIN
B-CONT
R-CONT
R-GAIN
B-CLP
G-CLP
R-CLP
C
LEVEL
YH-
CLP
DLYH-IN
DLYH-CLP
DLYH-OUT
YH-OUT1
YH-OUT2
TP
DLYH-GAIN
CLP4
CLP2
VAP-OUT
VAP-GAIN
VAP-CLP
VAP-SLICE
CS-CLP
CS-IN
R-Y GAIN
B-Y GAIN
B-Y OUT
C-
SLICE
WB-DC
WB-B
WB-G
WB-R
CGAM-CONT
GND
YL-OUT
CS-OUT
VCS-GAIN
R-Y HUE
B-Y HUE
R-Y
OU T
CXA1391 Q/R
YTBLK
NOISE-SLICE
YH-CLP
YH-IN
Y L-YH CLP
YL-YH IN
AGND
CLP4
CLP2
B-LEVEL
B-Y IN
B-Y
CLP
SHP-
LEVEL
DLE
SHP-CLP1
DLD
SHP-CLP2
SHP-OUT
Y-LEVEL
FADER-MODE
FADER-SIG
SETUP
SYNC-LEVEL
SYNC
R-Y IN
R-Y CLP
DVCC
4FSC
LALT
NC
NC
FSC-OUT
BFG
BF
CBLK
CTBLK
WC
SETUP-
CLP
V-OUT
VIDEO-OUT
CHROMA-OUT
DGND
C-IN
AVCC
C-OUT
CS-Y
CS-AGC
MODE
CXA1392 Q/R
DR-OUT
CT-BLK
DY-OUT
YT-BLK
DY-CLP
DY-IN
VCC
YG-IN
YR-IN
YB-IN
YT-GC
CT-GC
CLP4
DB-OUT
DB-IN
DR-IN
GND
CB-IN
CG-IN
CR-IN
HYS-
CONT
TH-CONT
COMP-IN
COMP-
OUT
2
3
4
5
6
7
8
9
10
11
12 1
13 14 15 16 17 18 19 20 21 23 24
22
DETECTOR
LPF
LPF IHDL DL
IHDLIHDLIHDL
W/B
CONTROLLER
DL
LPF
BPF
LPF
5V 5V
CXA1393AN/AM
5V
5V
CCD
Y
Vid
C
13
14
15
16
17
18
19
20
21
22
23
24
25
2627
28
29
30
36 35 34 31
32
33
40
39
38
37
41
42
43
44
45
46
47
48
2345678910 11 121
20
21
22
23
24
25
26
27
28
29
30
31
32
2345678910 11 12 13 14 15 16 17 18 19
1
40 39 38 37 36 35 34 33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
2627
28
29
30
36 35 34 31
32
33 25
40
39
38
37
41
42
43
44
45
46
47
48
2345678910 11 121
13
14
15
16
17
18
19
20
21
22
23
24
TG
SG CONTROLLER
FOR TI TLER
5V
5V
XSH1
XSP1
XSP2
CLP4
XSHD
XSHP
CLP2
BFG
HD.VD CL
WND
BLK
CR
YR
DL
XSH2 CLP1 ID PBLK
CG
YG
CB
YB
BF SYNC LALT 4fSC
CXA Series System Diagram
– 33 –
CXA1391Q/R
Package Outline Unit: mm
CXA1391Q
CXA1391R
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 ± 0.4
20.0 – 0.1
1.0 0.4 – 0.1
+ 0.15
14.0 – 0.1
119
20
32
33
51
52
64
0.15 – 0.05
+ 0.1
2.75 – 0.15
16.3
0.1 – 0.05
+ 0.2
0.8 ± 0.2
M
± 0.12
0.15
+ 0.4
17.9 ± 0.4
+ 0.4
+ 0.35
64PIN QFP(PLASTIC)
QFP–64P–L01
∗QFP064–P–1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER/PALLADIUM
COPPER /42 ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
12.0 ± 0.2
∗ 10.0 ± 0.1
(0.22)
0.18 – 0.03
+ 0.08
0.5 ± 0.08116
17
32
33
48
49
64
0.5 ± 0.2 (11.0)
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
64PIN LQFP (PLASTIC)
LQFP-64P-L01
∗QFP064-P-1010-A
0.3g
DETAIL A
0.1
NOTE: Dimension “∗” does not include mold protrusion.
