Supertex inc.
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
HT0440
Features
±400V input to output isolation
±700V isolation between outputs
No external voltage supply required
Dual isolated output drivers
Option of internal or external clock
Applications
Telecommunications
Modems
Solid state relays
High side switches
High end audio switches
Avionics
ATE
General Description
The Supertex HT0440 is a dual, high voltage, isolated
MOSFET driver utilizing Supertex’s proprietary HVCMOS®
technology. It is designed to drive discrete MOSFETs
congured as bidirectional or unidirectional switches. It
can drive N-channel MOSFETs as high-side switches up to
400V. The HT0440 generates two independent DC isolated
voltages to the outputs, VOUTA and VOUTB when logic inputs A
and B are at logic high.
The internal clock of the HT0440 can be disabled by
applying an external clock signal to the CLK pin. This allows
the power dissipation and AC characteristics to be tailored
to meet specic needs. The CLK pin should be connected
to ground when not in use. The HT0440 does not require
any external power supplies, the internal supply voltage is
supplied by either of the two logic inputs, A or B, when they
are at logic high.
For detailed circuit application information, please refer
to application note AN-D26.
Block Diagram
Dual, High Voltage,
Isolated MOSFET Driver
+
V
OUT
B
-
4
3
5
6
2
1
8
7
CLK
A
B
GND
Isolation
Barrier
10R
R
R
R
R
10R
R = 158kΩ ± 47%
Driver A
Driver B
Logic &
Internal
Clock
+
V
OUT
A
-
2
HT0440
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Ordering Information
Part Number Package Options Packing
HT0440K6-G 10-Lead (3x4) DFN 3000/Reel
HT0440LG-G 8-Lead SOIC (Narrow Body) 2500/Reel
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
Input to output isolation voltage, VISO ±400V
Logic input voltage, VA, VB-0.5 to +7.0V
Operating temperature -40°C to +85°C
Storage temperature -55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Pin Congurations
Product Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
HT04
LLLL
8-Lead SOIC (Narrow Body) (LG)
(top view)
8-Lead SOIC (Narrow Body) (LG)
Recommended Operating Conditions
Sym Parameter Min Typ Max Units Conditions
CLK External clock frequency 0.5 - 2.0 MHz ---
VIHCLK Clock input high voltage 3.15 - 5.5 V ---
VILCLK Clock input low voltage 0 - 0.5 V ---
VIH Logic input high voltage 3.15 - 5.5 V ---
VIL Logic input low voltage 0 - 0.5 V ---
TAOperating temperature -40 - +85 OC ---
Package may or may not include the following marks: Si or
10-Lead DFN (K6)
10-Lead DFN (K6)
(top view)
0440
YWLL
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
A
CLK
-VOUTA
+VOUTA
1
2
3
4
8
7
6
5
B
GND
-VOUTB
+VOUTB
A
CLK
NC
-VOUTA
+VOUTA
1
2
3
4
5
10
9
8
7
6
GND
B
GND
NC
-VOUTB
+VOUTB
3
HT0440
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Truth Table
A B CLK VOUTA VOUTB Internal Clock
0 0 0 OFF OFF OFF
0 0 OFF ON ON
0 0 ON OFF ON
1 1 0 ON ON ON
0 0 CLK OFF OFF OFF
0 CLK OFF ON OFF
0 CLK ON OFF OFF
1 1 CLK ON ON OFF
Sym Parameter Min Typ Max Units Conditions
IHA + IHB Total logic high input current
- - 300 µA VA = 3.5V, VB = 3.5V, CLK = 0V
- - 500 µA VA = 3.5V, VB = 3.5V, CLK = 500kHz
- - 2.0 mA VA = 3.5V, VB = 3.5V, CLK = 2.0MHz
- - 1.0 mA VA = 5.5V, VB = 5.5V, CLK = 0V
- - 2.0 mA VA = 5.5V, VB = 5.5V, CLK = 500kHz
VOUTA,
VOUTB
Output voltage
6.0 - - V VA = 3.15V, VB = 3.15V,
CLK = 0V, no load
5.0 - - V VA = 3.15V, VB = 3.15V,
CLK = 500kHz, no load
6.0 - - V VA = 3.15V, VB = 3.15V,
CLK = 2.0MHz, no load
10.0 - - V VA = 4.5V, VB = 4.5V,
CLK = 0V, no load
8.0 - - V VA = 4.5V, VB = 4.5V,
CLK = 500KHz, no load
IILA Logic low input A current - - 10 µA VA = 0.5V, VB = high
IILB Logic low input B current - - 10 µA VA = high, VB = 0.5V
IILQ Quiescent current - - 10 µA VA = 0.5V, VB = 0.5V
VISO Input to output isolation voltage ±400 - - V ---
VCISO Output to output isolation voltage ±700 - - V ---
DC Electrical Characteristics (TA = 25°C unless otherwise specied)
Sym Parameter Min Typ Max Units Conditions
td(ON) Turn-ON delay time - - 50 µs
See timing diagram and test circuit
CLK = 0V, CL = 600pF
trRise time - - 650 µs
td(OFF) Turn-OFF delay time - - 150 µs
tfFall time - - 3.0 ms
AC Electrical Characteristics (TA =25°C unless otherwise specied)
4
HT0440
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Test Circuit
VOUTA
CL = 600pF
VOUTB
4.5V
0V
1
8
2
7
4
3
5
6
HT0440
VOUTA
+ A
B
VOUTB
+
CLK
GND
-
- CL = 600pF
90%
10%
50% 50%
90%
10%
4.5V
0V
V
OUT
A, V
OUT
B
t
d(ON)
t
r
t
d(OFF)
t
f
V
A
, V
B
Timing Diagram
5
HT0440
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
10-Lead DFN Package Outline (K6)
3.00x4.00mm body, 1.00mm height (max), 0.50mm pitch
Symbol A A1 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.80 0.00 0.18 2.95 2.20 3.95 2.50
0.50
BSC
0.30 0.00 0O
NOM 0.90 0.02 0.25 3.00 2.35 4.00 2.65 0.40 - -
MAX 1.00 0.05 0.30 3.05 2.45 4.05 2.75 0.50 0.15 14O
Drawings not to scale.
Supertex Doc. #: DSPD-10DFNK63X4P050, Version A072611
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Seating
Plane
θ
Top View
Side View
Bottom View
A
A1
D
E
D2
e
b
E2
L
L1
View B
Note 1
(Index Area
D/2 x E/2)
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
10
1
10
1
Pin #1 ID
R = 0.20
View B
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
6
HT0440
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HT0440
C033012
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Note:
1. This chamfer feature is optional. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier;
an embedded metal marker; or a printed indicator.