DAC2902Y/250 - Texas Instruments

Dual, 12-Bit, 125MSPS

DIGITAL-TO-ANALOG CONVERTER

FEATURES

●125MSPS UPDATE RATE

●

SINGLE SUPPLY: +3.3V or +5V

●HIGH SFDR: 70dB at fOUT = 20MHz

●LOW GLITCH: 2pV-s

●LOW POWER: 310mW

●INTERNAL REFERENCE

●POWER-DOWN MODE: 23mW

APPLICATIONS

●COMMUNICATIONS:

Base Stations, WLL, WLAN

Baseband I/Q Modulation

●MEDICAL/TEST INSTRUMENTATION

●ARBITRARY WAVEFORM GENERATORS (ARB)

●DIRECT DIGITAL SYNTHESIS (DDS)

DESCRIPTION

The DAC2902 is a monolithic, 12-bit, dual-channel,

high-speed Digital-to-Analog Converter (DAC), and is opti-

mized to provide high dynamic performance while dissipat-

ing only 310mW.

Operating with high update rates of up to 125MSPS, the

DAC2902 offers exceptional dynamic performance, and

enables the generation of very high output frequencies

suitable for

Direct IF

applications. The DAC2902 has

been optimized for communications applications in which

separate I and Q data are processed while maintaining

tight gain and offset matching.

Each DAC has a high-impedance differential-current out-

put, suitable for single-ended or differential analog output

configurations.

The DAC2902 combines high dynamic performance with

a high throughput rate to create a cost-effective solution

for a wide variety of waveform-synthesis applications:

• Pin compatibility between family members provides 10-

bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)

resolution.

• Pin compatible to the AD9765 dual DAC.

• Gain matching is typically 0.5% of full-scale, and offset

matching is specified at 0.02% max.

• The DAC2902 utilizes an advanced CMOS process; the

segmented architecture minimizes output glitch energy,

and maximizes the dynamic performance.

• All digital inputs are +3.3V and +5V logic compatible.

The DAC2902 has an internal reference circuit, and

allows use of an external reference.

• The DAC2902 is available in a TQFP-48 package, and

is specified over the extended industrial temperature

range of –40°C to +85°C.

DAC2902

SBAS167C– JUNE 2001 – REVISED SEPTEMBER 2008

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

All trademarks are the property of their respective owners.

www.ti.com

DAC2902

2SBAS167C

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ELECTRICAL CHARACTERISTICS

DAC2902Y

PARAMETER CONDITIONS MIN TYP MAX UNIT

RESOLUTION 12 Bits

Output Update Rate (fCLOCK)125 MSPS

STATIC ACCURACY(1)

Differential Nonlinearity (DNL) TA = +25°C–2.0 ±1 +2.0 LSB

TMIN to TMAX –2.5 +2.5 LSB

Integral Nonlinearity (INL) TA = +25°C–2.0 ±1 +2.0 LSB

TMIN to TMAX –3.0 +3.0 LSB

DYNAMIC PERFORMANCE

Spurious-Free Dynamic Range (SFDR) To Nyquist

fOUT = 1MHz, fCLOCK = 50MSPS 0dBFS Output 72 82 dBc

–6dBFS Output 77 dBc

–12dBFS Output 72 dBc

fOUT = 1MHz, fCLOCK = 26MSPS 81 dBc

fOUT = 2.18MHz, fCLOCK = 52MSPS 81 dBc

fOUT = 5.24MHz, fCLOCK = 52MSPS 81 dBc

fOUT = 10.4MHz, fCLOCK = 78MSPS 77 dBc

fOUT = 15.7MHz, fCLOCK = 78MSPS 71 dBc

fOUT = 5.04MHz, fCLOCK = 100MSPS 80 dBc

fOUT = 20.2MHz, fCLOCK = 100MSPS 70 dBc

fOUT = 20.1MHz, fCLOCK = 125MSPS 72 dBc

fOUT = 40.2MHz, fCLOCK = 125MSPS 64 dBc

Spurious-Free Dynamic Range within a Window

fOUT = 1.0MHz, fCLOCK = 50MSPS 2MHz Span 80 90 dBc

fOUT = 5.02MHz, fCLOCK = 50MSPS 10MHz Span 88 dBc

fOUT = 5.03MHz, fCLOCK = 78MSPS 10MHz Span 88 dBc

fOUT = 5.04MHz, fCLOCK = 125MSPS 10MHz Span 88 dBc

Total Harmonic Distortion (THD)

fOUT = 1MHz, fCLOCK = 50MSPS –79 –70 dBc

fOUT = 5.02MHz, fCLOCK = 50MSPS –77 dBc

fOUT = 5.03MHz, fCLOCK = 78MSPS –76 dBc

fOUT = 5.04MHz, fCLOCK = 125MSPS –75 dBc

Multitone Power Ratio 8 Tone with 110kHz Spacing

fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS 0dBFS Output 80 dBc

At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments

recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation pro-

cedures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

+VA to AGND ........................................................................ –0.3V to +6V

+VD to DGND ........................................................................ –0.3V to +6V

AGND to DGND................................................................. –0.3V to +0.3V

+VA to +VD............................................................................... –6V to +6V

CLK, PD, WRT to DGND ........................................... –0.3V to VD + 0.3V

D0-D11 to DGND ....................................................... –0.3V to VD + 0.3V

IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V

GSET to AGND .......................................................... –0.3V to VA + 0.3V

REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V

Junction Temperature.................................................................... +150°C

Case Temperature......................................................................... +100°C

Storage Temperature .................................................................... +125°C

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

DAC2902Y TQFP-48 PFB –40°C to +85°C DAC2902Y DAC2902Y/250 Tape and Reel, 250

""" ""DAC2902Y/1K Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

PRODUCT EVM ORDERING NUMBER COMMENT

DAC2902 DAC2902-EVM Fully populated evaluation board. See user manual for details.

DAC2902 3

SBAS167C www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.

DYNAMIC PERFORMANCE (Cont.)

Signal-to-Noise Ratio (SNR) 0dBFS Output 68 dBc

fOUT = 5.02MHz, fCLOCK = 50MHz

Signal-to-Noise and Distortion (SINAD) 0dBFS Output 67 dBc

fOUT = 5.02MHz, fCLOCK = 50MHz

Channel Isolation

fOUT = 1MHz, fCLOCK = 52MSPS 85 dBc

fOUT = 20MHz, fCLOCK = 125MSPS 77 dBc

Output Settling Time(2) to 0.1% 30 ns

Output Rise Time(2) 10% to 90% 2 ns

Output Fall Time(2) 10% to 90% 2 ns

Glitch Impulse 2pV-s

DC ACCURACY

Full-Scale Output Range(3)(FSR) All Bits HIGH, IOUT 220mA

Output Compliance Range –1.0 +1.25 V

Gain Error—Full-Scale With Internal Reference –5±1+5%FSR

Gain Error With External Reference –2.5 ±1 +2.5 %FSR

Gain Matching With Internal Reference –2.0 0.5 +2.0 %FSR

Gain Drift With Internal Reference ±50 ppmFSR/°C

Offset Error With Internal Reference –0.02 +0.02 %FSR

Offset Drift With Internal Reference ±0.2 ppmFSR/°C

Power-Supply Rejection, +VA+5V, ±10% –0.2 +0.2 %FSR/V

Power-Supply Rejection, +VD+3.3V, ±10% –0.025 +0.025 %FSR/V

Output Noise IOUT = 20mA, RLOAD = 50Ω50 pA/√Hz

IOUT = 2mA 30 pA/√Hz

Output Resistance 200 kΩ

Output Capacitance IOUT, IOUT to Ground 6 pF

REFERENCE/CONTROL AMP

Reference Voltage +1.18 +1.25 +1.31 V

Reference Voltage Drift ±50 ppmFSR/°C

Reference Output Current 100 nA

Reference Multiplying Bandwidth 0.3 MHz

Input Compliance Range +0.5 +1.25 V

DIGITAL INPUTS

Logic Coding Straight Binary

Logic High Voltage, VIH +VD = +5V 3.5 5 V

Logic Low Voltage, VIL +VD = +5V 0 1.2 V

Logic High Voltage, VIH +VD = 3.3V 2 3 V

Logic Low Voltage, VIL +VD = 3.3V 0 0.8 V

Logic High Current, IIH(4) +VD = 3.3V ±10 µA

Logic Low Current +VD = 3.3V ±10 µA

Input Capacitance 5pF

POWER SUPPLY

Supply Voltages

+VA+3.0 +5 +5.5 V

+VD+3.0 +3.3 +5.5 V

Supply Current

IVA(5) VA = +5V, lOUT = 20mA 58 65 mA

IVA(5) Power-Down Mode 1.7 3 mA

IVD(5) 4.2 7 mA

IVD(6) 17 19.5 mA

Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 20mA 310 350 mW

Power Dissipation(6) VA = +5V, VD = 3.3V, lOUT = 20mA 348 390 mW

Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 2mA 130 mW

Power Dissipation Power-Down Mode 23 38 mW

Thermal Resistance, TQFP-48

JA 60 °C/W

JC 13 °C/W

TEMPERATURE RANGE

Specified Ambient –40 +85 °C

Operating Ambient –40 +85 °C

NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω load. (3) Nominal full-scale output current is 32 × IREF; see Application

section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz. (6) Measured

at fCLOCK = 100MSPS and fOUT = 40MHz.

DAC2902Y

PARAMETER CONDITIONS MIN TYP MAX UNIT

DAC2902

4SBAS167C

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PIN DESIGNATOR DESCRIPTION

1-12 D[11:0]_1 Data Port DAC1, Data Bit 11 (MSB) to Bit 0 (LSB).

13, 14 NC No Connection

15 DGND Digital Ground

16 +VDDigital Supply, +3.0V to +5.5V

17 WRT1 DAC1 Input Latches Write Signal

18 CLK1 Clock Input DAC1

19 CLK2 Clock Input DAC2

20 WRT2 DAC2 Input Latches Write Signal

21 DGND Digital Ground

22 +VDDigital Supply, +3.0V to +5.5V

23-34 D[11:0]_2 Data Port DAC2, Data Bit 11 (MSB) to Bit 0 (LSB).

35, 36 NC No Connection

37 PD

Power-Down Function Control Input;

= DAC in power-down mode;

= DAC in normal operation (Internal pull-down for default “L”).

38 AGND Analog Ground

39 IOUT2 Current Output DAC2. Full-scale with all bits of data port 2 HIGH.

40 IOUT2 Complementary Current Output DAC2. Full-scale with all bits of data port 2 LOW.

41 FSA2 Full-Scale Adjust, DAC2. Connect External RSET Resistor.

42 GSET Gain-Setting Mode (H = 1 Resistor, L = 2 Resistor)

43 REFIN Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference

operation.

44 FSA1 Full-Scale Adjust, DAC1. Connect External RSET Resistor

45 IOUT1 Complementary Current Output DAC1. Full-scale with all bits of data port 1 LOW.

46 IOUT1 Current Output DAC1. Full-scale with all bits of data port 1 HIGH.

47 +VAAnalog Supply, +3.0V to +5.5V

48 NC No Connection

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View TQFP-48

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23

DAC2902

D0_2

D1_2

D2_2

D3_2

D4_2

D5_2

D6_2

D7_2

D8_2

D9_2

OUT

FSA

REF

GSET

FSA2

OUT

AGND

DGND

WRT1

CLK1

CLK2

WRT2

DGND

D11_2 (MSB)

D10_2

D11_1 (MSB)

D10_1

D9_1

D8_1

D7_1

D6_1

D5_1

D4_1

D3_1

D2_1

D1_1

D0_1

DAC2902 5

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SYMBOL DESCRIPTION MIN TYP MAX UNITS

tSInput Setup Time 2 ns

tHInput Hold Time 1.5 ns

tLPW, tCPW Latch/Clock Pulsewidth 3.5 4 ns

tCW Delay Rising CLK Edge to 0 tPW – 2ns

Rising WRT Edge

tPD Propagation Delay 1 ns

tSET Settling Time (0.1%) 30 ns

TIMING DIAGRAM

tPD

tLPW

tCPW

tCW tSET

D[11:0](n) D[11:0](n + 1)

IOUT(n) IOUT(n +1)

50%

DATA IN

WRT1

WRT2

CLK1

CLK2

IOUT1

IOUT2

DIGITAL INPUTS AND TIMING

The data input ports of the DAC2902 accept a standard

positive coding with data bit D11 being the most significant

bit (MSB). The converter outputs support a clock rate of up

to 125MSPS. The best performance will typically be achieved

with a symmetrical duty cycle for write and clock; however,

the duty cycle may vary as long as the timing specifications

are met. Also, the setup and hold times may be chosen

within their specified limits.

All digital inputs of the DAC2902 are CMOS-compatible.

The logic thresholds depend on the applied digital supply

voltages, such that they are set to approximately half the

supply voltage: Vth = +VD/2 (±20% tolerance). The DAC2902

is designed to operate with a digital supply (+VD) of +3.0V

to +5.5V.

The two converter channels within the DAC2902 consist of

two independent, 12-bit, parallel data ports. Each DAC

channel is controlled by its own set of write (WRT1, WRT2)

and clock (CLK1, CLK2) inputs. Here, the WRT lines

control the channel input latches and the CLK lines control

the DAC latches. The data is first loaded into the input latch

by a rising edge of the WRT line. This data is presented to

the DAC latch on the following falling edge of the WRT

signal. On the next rising edge of the CLK line, the DAC is

updated with the new data and the analog output signal will

change accordingly. The double latch architecture of the

DAC2902 results in a defined sequence for the WRT and

CLK signals, expressed by parameter tCW. A correct timing

is observed when the rising edge of CLK occurs at the same

time, or before, the rising edge of the WRT signal. This

condition can simply be met by connecting the WRT and

CLK lines together. Note that all specifications were mea-

sured with the WRT and CLK lines connected together.

DAC2902

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TYPICAL CHARACTERISTICS

TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.

SFDR vs fOUT AT 26MSPS

fOUT (MHz)

SFDR (dBc)

60 426810120

0dBFS

–6dBFS

SFDR vs fOUT AT 52MSPS

fOUT (MHz)

SFDR (dBc)

60 1051520250

0dBFS

–6dBFS

SFDR vs fOUT AT 78MSPS

fOUT (MHz)

SFDR (dBc)

55 105 15202530350

0dBFS

–6dBFS

SFDR vs fOUT AT 100MSPS

fOUT (MHz)

SFDR (dBc)

50 105 152025303540450

0dBFS

–6dBFS

TYPICAL DNL

Code

DNL (LSBs)

1.4

1.2

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–11k500 1k5 2k 2k5 3k 3k5 4k0

TYPICAL INL

Code

INL (LSBs)

1.5

0.5

–0.5

–1

–1.5 1k500 1k5 2k 2k5 3k 3k5 4k0

DAC2902 7

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SFDR vs fOUT AT 125MHz

fOUT (MHz)

SFDR (dBc)

50 2010 30 40 50 600

–6dBFS

0dBFS

SFDR AT 125MSPS vs TEMPERATURE

Temperature (°C)

SFDR (dBc)

50 0–20 25 50 70 85–40

2MHz

40MHz

10MHz

20MHz

SINAD vs fCLK AND IOUT AT 5MHz

fCLK (MSPS)

SINAD (dBc)

67.5

62.5

60 40 60 80 100 120 14020

20mA

10mA

5mA

GAIN AND OFFSET DRIFT

Temperature (°C)

Gain Error (% FS)

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

Offset Error (% FS)

0.004

0.003

0.002

0.001

–0.001

–0.002

–0.003

–0.004

0–20 20 40 60 80 85–40

Offset Error

Gain Error

SFDR vs I

OUT

FS AND f

OUT

AT 78MSPS, 0dBFS

OUT

(MHz)

SFDR (dBc)

60 1051520250

OUT

FS = 20mA

OUT

FS = 10mA

OUT

FS = 2mA

OUT

FS = 5mA

vs RATIO AT +V

= +3.3V

Ratio (F

OUT

CLK

)

(mA)

00.100.05 0.15 0.20 0.25 0.30 0.35 0.40 0.450.00

125MSPS

100MSPS

78MSPS

52MSPS

26MSPS

TYPICAL CHARACTERISTICS (continued)

TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.

DAC2902

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.

IVA vs IOUTFS

IOUTFS (mA)

IVA (mA)

10 1051520250

SINGLE-TONE SFDR

Frequency (MHz)

Magnitude (dBm)

–10

–20

–30

–40

–50

–60

–70

–80

–90 4 8 12 16 200

CLOCK

= 52MSPS

OUT

= 5.23MHz

Amplitude = 0dBFS

SINGLE-TONE SFDR

Frequency (MHz)

Magnitude (dBm)

–10

–20

–30

–40

–50

–60

–70

–80

–90 10 20 30 40 500

CLOCK

= 100MSPS

OUT

= 20.2MHz

Amplitude = 0dBFS

DUAL-TONE SFDR

Frequency (MHz)

Magnitude (dBm)

–10

–20

–30

–40

–50

–60

–70

–80

–90 7.8 15.6 23.4 31.2 39.00

CLOCK

= 78MSPS

OUT

1 = 9.44MHz

OUT

2 = 10.44MHz

Amplitude = 0dBFS

FOUR-TONE SFDR

Frequency (MHz)

Magnitude (dBm)

–10

–20

–30

–40

–50

–60

–70

–80

–90 510

15 20 250

CLOCK

= 50MSPS

OUT

1 = 6.25MHz

OUT

2 = 6.75MHz

OUT

3 = 7.25MHz

OUT

4 = 7.75MHz

Amplitude = 0dBFS

DAC2902 9

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FIGURE 1. Block Diagram of the DAC2902.

APPLICATION INFORMATION

THEORY OF OPERATION

The architecture of the DAC2902 uses the current steering

technique to enable fast switching and a high update rate.

The core element within the monolithic DAC is an array of

segmented current sources that are designed to deliver a full-

scale output current of up to 20mA, as shown in Figure 1. An

internal decoder addresses the differential current switches

each time the DAC is updated and a corresponding output

current is formed by steering all currents to either output

summing node, IOUT or IOUT. The complementary outputs

deliver a differential output signal, which improves the

dynamic performance through reduction of even-order har-

monics, common-mode signals (noise), and double the peak-

to-peak output signal swing by a factor of two, compared to

single-ended operation.

The segmented architecture results in a significant reduction

of the glitch energy, improves the dynamic performance

(SFDR), and DNL. The current outputs maintain a very high

output impedance of greater than 200kΩ.

The full-scale output current is determined by the ratio of the

internal reference voltage (approx. +1.25V) and an external

resistor, R

SET

. The resulting I

REF

is internally multiplied by a

factor of 32 to produce an effective DAC output current that

can range from 2mA to 20mA, depending on the value of R

SET

The DAC2902 is split into a digital and an analog portion,

each of which is powered through its own supply pin. The

digital section includes edge-triggered input latches and the

decoder logic, while the analog section consists of the

current source array with its associated switches, and the

reference circuitry.

DAC TRANSFER FUNCTION

Each of the DACs in the DAC2902 has a complementary

current output, IOUT1 and IOUT2. The full-scale output cur-

rent, IOUTFS, is the summation of the two complementary

output currents:

IOUTFS = IOUT + IOUT (1)

The individual output currents depend on the DAC code and

can be expressed as:

IOUT = IOUTFS × (Code/4096) (2)

IOUT = IOUTFS × (4095 - Code) (3)

where Code is the decimal representation of the DAC data

input word. Additionally, IOUTFS is a function of the refer-

ence current IREF, which is determined by the reference

voltage and the external setting resistor, RSET.

IOUTFS = 32 × IREF = 32 × VREF/RSET (4)

In most cases the complementary outputs will drive resistive

loads or a terminated transformer. A signal voltage will

develop at each output according to:

VOUT = IOUT × RLOAD (5)

VOUT = IOUT × RLOAD (6)

DAC

Latch 1

WRT1

CLK1

CLK2

WRT2

Data Input

Port 2

D[11:0]_2

Data Input

Port 1

D[11:0]_1

OUT

Input

Latch 1

Reference

Control Amplifier FSA2

REF

FSA1

GSET

DAC1

Segmented Switches

Current Sources

DAC2902

OUT

DAC

Latch 2

Input

Latch 2 DAC2

Segmented Switches

Current Sources

AGNDDGNDDGND

OUT

DAC2902

10 SBAS167C

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The value of the load resistance is limited by the output

compliance specification of the DAC2902. To maintain

specified linearity performance, the voltage for IOUT and

IOUT should not exceed the maximum allowable compliance

range.

The two single-ended output voltages can be combined to

find the total differential output swing:

VVV Code IR

OUTDIFF OUT OUT OUTFS LOAD

×××–(–)2 4095

4096

(7)

ANALOG OUTPUTS

The DAC2902 provides two complementary current out-

puts, IOUT and IOUT. The simplified circuit of the analog

output stage representing the differential topology is shown

in Figure 2. The output impedance of IOUT and IOUT results

from the parallel combination of the differential switches,

along with the current sources and associated parasitic

capacitances.

be adapted to the output of the DAC2902 by selecting a

suitable transformer while maintaining optimum voltage

levels at IOUT and IOUT. Furthermore, using the differential

output configuration in combination with a transformer will

be instrumental for achieving excellent distortion perfor-

mance. Common-mode errors, such as even-order harmon-

ics or noise, can be substantially reduced. This is particularly

the case with high output frequencies.

For those applications requiring the optimum distortion and

noise performance, it is recommended to select a full-scale

output of 20mA. A lower full-scale range down to 2mA may

be considered for applications that require a low power

consumption, but can tolerate a slightly reduced perfor-

mance level.

OUTPUT CONFIGURATIONS

The current outputs of the DAC2902 allow for a variety of

configurations, some of which are illustrated in Table I. As

mentioned previously, utilizing the converter’s differential

outputs will yield the best dynamic performance. Such a

differential output circuit may consist of an RF transformer

or a differential amplifier configuration. The transformer

configuration is ideal for most applications with ac coupling,

while op amps will be suitable for a DC-coupled configura-

tion.

The signal voltage swing that may develop at the two

outputs, IOUT and IOUT, is limited by a negative and positive

compliance. The negative limit of –1V is given by the

breakdown voltage of the CMOS process, and exceeding it

will compromise the reliability of the DAC2902, or even

cause permanent damage. With the full-scale output set to

20mA, the positive compliance equals 1.25V, operating with

an analog supply of +VA = 5V. Note that the compliance

range decreases to about 1V for a selected output current of

IOUTFS = 2mA. Care should be taken that the configuration

of the DAC2902 does not exceed the compliance range to

avoid degradation of the distortion performance and integral

linearity.

Best distortion performance is typically achieved with the

maximum full-scale output signal limited to approximately

0.5VPP. This is the case for a 50Ω doubly-terminated load

and a 20mA full-scale output current. A variety of loads can

The single-ended configuration may be considered for appli-

cations requiring a unipolar output voltage. Connecting a

resistor from either one of the outputs to ground will convert

the output current into a ground-referenced voltage signal.

To improve on the DC linearity by maintaining a virtual

ground, an I-to-V or op-amp configuration may be consid-

ered.

DIFFERENTIAL WITH TRANSFORMER

Using an RF transformer provides a convenient way of convert-

ing the differential output signal into a single-ended signal

while achieving excellent dynamic performance (see Figure 3).

The appropriate transformer should be carefully selected based

on the output frequency spectrum and impedance requirements.

The differential transformer configuration has the benefit of

significantly reducing common-mode signals, thus improving

the dynamic performance over a wide range of frequencies.

Furthermore, by selecting a suitable impedance ratio (winding

ratio), the transformer can be used to provide optimum imped-

ance matching while controlling the compliance voltage for the

converter outputs. The model shown, ADTT1-1 (by Mini-

Circuits), has a 1:1 ratio and may be used to interface the

DAC2902 to a 50Ω load. This results in a 25Ω load for each of

the outputs, IOUT and IOUT. The output signals are ac coupled

and inherently isolated because of its magnetic coupling.

FIGURE 2. Equivalent Analog Output.

OUT

DAC2902

INPUT CODE (D11 - D0) IOUT IOUT

1111 1111 1111 20mA 0mA

1000 0000 0000 10mA 10mA

0000 0000 0000 0mA 20mA

TABLE I. Input Coding Versus Analog Output Current.

DAC2902 11

SBAS167C www.ti.com

As shown in Figure 3, the transformer center tap is con-

nected to ground. This forces the voltage swing on IOUT and

IOUT to be centered at 0V. In this case the two resistors, RL,

may be replaced with one, RDIFF, or omitted altogether. This

approach should only be used if all components are close to

each other, and if the VSWR is not important. A complete

power transfer from the DAC output to the load can be

realized, but the output compliance range should be ob-

served. Alternatively, if the center tap is not connected, the

signal swing will be centered at RL × IOUTFS/2. However, in

this case, the two resistors (RL) must be used to enable the

necessary DC-current flow for both outputs.

The OPA680 is configured for a gain of two. Therefore,

operating the DAC2902 with a 20mA full-scale output will

produce a voltage output of ±1V. This requires the amplifier

to operate from a dual power supply (±5V). The tolerance of

the resistors typically sets the limit for the achievable com-

mon-mode rejection. An improvement can be obtained by

fine tuning resistor R4.

This configuration typically delivers a lower level of ac

performance than the previously discussed transformer solu-

tion because the amplifier introduces another source of

distortion. Suitable amplifiers should be selected based on

their slew-rate, harmonic distortion, and output swing capa-

bilities. High-speed amplifiers like the OPA680 or OPA687

may be considered. The ac performance of this circuit may

be improved by adding a small capacitor (CDIFF) between the

outputs IOUT and IOUT, as shown in Figure 4). This will

introduce a real pole to create a low-pass filter in order to

slew-limit the DAC fast output signal steps, that otherwise

could drive the amplifier into slew-limitations or into an

overload condition; both would cause excessive distortion.

The difference amplifier can easily be modified to add a

level shift for applications requiring the single-ended output

voltage to be unipolar (that is, swing between 0V and +2V.)

DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION

The circuit example of Figure 5 shows the signal output

currents connected into the summing junctions of the dual

voltage-feedback op amp OPA2680 that is set up as a

transimpedance stage, or I-to-V converter. With this circuit,

the DAC output will be kept at a virtual ground, minimizing

the effects of output impedance variations, which results in

the best DC linearity (INL). As mentioned previously, care

should be taken not to drive the amplifier into slew-rate

limitations, and produce unwanted distortion.

DIFFERENTIAL CONFIGURATION USING AN OP AMP

If the application requires a DC-coupled output, a difference

amplifier may be considered, as shown in Figure 4. Four

external resistors are needed to configure the voltage-feed-

back op amp OPA680 as a difference amplifier performing

the differential to single-ended conversion. Under the shown

configuration, the DAC2902 generates a differential output

signal of 0.5VPP at the load resistors, RL. The resistor values

shown were selected to result in a symmetric 25Ω loading

for each of the current outputs since the input impedance of

the difference amplifier is in parallel to resistors RL, and

should be considered.

FIGURE 4. Difference Amplifier Provides Differential to

Single-Ended Conversion and DC-Coupling. FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680

Forms Differential Transimpedance Amplifier.

FIGURE 3. Differential Output Configuration Using an RF

Transformer.

DAC2902

OUT

1:1

ADTT1-1

(Mini-Circuits)

50Ω

DIFF

100Ω

IOUT

DAC2902

26.1ΩRL

28.7ΩR4

402Ω

200Ω

402Ω

200Ω

OPA680

COPT +5V

VOUT

–5V

1/2

OPA2680

1/2

OPA2680

DAC2902

–VOUT = IOUT • RF1

–VOUT = IOUT • RF2

RF1

RF2

CF1

CF2

CD1

CD2

IOUT

50Ω

50Ω–5V

+5V

DAC2902

12 SBAS167C

www.ti.com

The DC gain for this circuit is equal to feedback resistor RF.

At high frequencies, the DAC output impedance (CD1, CD2)

will produce a 0 in the noise gain for the OPA2680 that may

cause peaking in the closed-loop frequency response. CF is

added across RF to compensate for this noise gain peaking.

To achieve a flat transimpedance frequency response, the

pole in each feedback network should be set to:

24ππRC GBP

FF FD

(8)

with GBP = Gain Bandwidth Product of OPA,

which will give a corner frequency f-3dB of approximately:

fGBP

dB FD

−

2π

(9)

The full-scale output voltage is simply defined by the prod-

uct of IOUTFS × RF, and has a negative unipolar excursion. To

improve on the ac performance of this circuit, adjustment of

RF and/or IOUTFS should be considered. Further extensions of

this application example may include adding a differential

filter at the OPA2680 output followed by a transformer, in

order to convert to a single-ended signal.

SINGLE-ENDED CONFIGURATION

Using a single-load resistor connected to the one of the DAC

outputs, a simple current-to-voltage conversion can be ac-

complished. The circuit in Figure 6 shows a 50Ω resistor

connected to IOUT, providing the termination of the further

connected 50Ω cable. Therefore, with a nominal output

current of 20mA, the DAC produces a total signal swing of

0V to 0.5V into the 25Ω load.

Different load resistor values may be selected as long as the

output compliance range is not exceeded. Additionally, the

output current, IOUTFS, and the load resistor, may be mutu-

ally adjusted to provide the desired output signal swing and

performance.

INTERFACING ANALOG

QUADRATURE MODULATORS

One of the main applications for the dual-channel DAC is

baseband I- and Q-channel transmission for digital commu-

nications. In this application, the DAC is followed by an

analog quadrature modulator, modulating an IF carrier with

the baseband data, as shown in Figure 7. Often, the input

stages of these quadrate modulators consist of npn-type

transistors that require a DC bias (base) voltage of > 0.8V.

The wide output compliance range (–10V to +1.25V) allows

for a direct DC–coupling between the DAC2902 and the

quadrature modulator.

FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly.

FIGURE 7. Generic Interface to a Quadrature Modulator. Signal Conditioning (Level-Shifting) May Be Required to Ensure

Correct DC Common-Mode Levels At the Input of the Quadrature Modulator.

OUT

DAC2902

25Ω

50Ω50Ω

OUTFS

= 20mA V

OUT

= 0V to +0.5V

OUT

DAC2902

Signal

Conditioning

REF

∑

Quadrature Modulator

OUT

~ 0Vp to 1.20Vp V

~ 0.6Vp to 1.8Vp

REF

DAC2902 13

SBAS167C www.ti.com

Figure 8 shows an example of a DC-coupled interface with

DC level-shifting, using a precision resistor network. An ac-

coupled interface, as shown in Figure 9, has the advantage

that the common-mode levels at the input of the modulator

can be set independently of those at the output of the DAC.

Furthermore, no voltage loss is obtained in this setup.

INTERNAL REFERENCE OPERATION

The DAC2902 has an on-chip reference circuit that consists

of a 1.25V bandgap reference and two control amplifiers,

one for each DAC. The full-scale output current, IOUTFS, of

the DAC2902 is determined by the reference voltage, VREF,

and the value of resistor RSET. IOUTFS can be calculated by:

IOUTFS = 32 × IREF = 32 × VREF / RSET (10)

The external resistor RSET connects to the FSA pin (Full-

Scale Adjust), see Figure 10. The reference control amplifier

operates as a V-to-I converter producing a reference current,

IREF, which is determined by the ratio of VREF and RSET (as

shown in Equation 10). The full-scale output current, IOUTFS,

results from multiplying IREF by a fixed factor of 32.

OUT

DAC2902

OUT

FIGURE 8. DC-Coupled Interface to Quadrature Modulator

Applying Level Shifting.

FIGURE 9. AC-Coupled Interface to Quadrature Modulator Applying Level Shifting.

IOUT1

DAC2902

IOUT1

VOUT1

0.01µF

VDC

VOUT1

RLOAD

50Ω50Ω

DAC2902

14 SBAS167C

www.ti.com

Using the internal reference, a 2kΩ resistor value results in

a full-scale output of approximately 20mA. Resistors with a

tolerance of 1% or better should be considered. Selecting

higher values, the output current can be adjusted from 20mA

down to 2mA. Operating the DAC2902 at lower than 20mA

output currents may be desirable for reasons of reducing the

total power consumption, optimizing the distortion perfor-

mance, or observing the output compliance voltage limita-

tions for a given load condition.

It is recommended to bypass the REFIN pin with a ceramic

chip capacitor of 0.1µF or more. The control amplifier is

internally compensated, and its small signal bandwidth is

approximately 0.3MHz.

GAIN SETTING OPTIONS

The full-scale output current on the DAC2902 can be set two

ways: either for each of the two DAC channels independently or

for both channels simultaneously. For the independent gain set

mode, the GSET pin (pin 42) must be LOW (that is, connected

to AGND). In this mode, two external resistors are required—

one RSET connected to the FSA1 pin (pin 44) and the other to the

FSA2 pin (pin 41). In this configuration, the user has the

flexibility to set and adjust the full-scale output current for each

DAC independently, allowing for the compensation of possible

gain mismatches elsewhere within the transmit signal path.

Alternatively, bringing the GSET pin HIGH (that is, con-

nected to +VA), the DAC2902 will switch into the simulta-

neous gain set mode. Now the full-scale output current of both

DAC channels is determined by only one external RSET

resistor connected to the FSA1 pin. The resistor at the FSA2

pin may be removed, however this is not required since this

pin is not functional in this mode and the resistor has no effect

to the gain equation. The formula for deriving the correct RSET

remains unchanged (for example, RSET = 2kΩ will result in a

20mA output for both DACs).

EXTERNAL REFERENCE OPERATION

The internal reference can be disabled by simply applying an

external reference voltage into the REFIN pin, which in this

case functions as an input, as shown in Figure 11. The use

of an external reference may be considered for applications

that require higher accuracy and drift performance, or to add

the ability of dynamic gain control.

While a 0.1µF capacitor is recommended to be used with the

internal reference, it is optional for the external reference

operation. The reference input, REFIN, has a high input

impedance (1MΩ) and can easily be driven by various

sources. Note that the voltage range of the external reference

should stay within the compliance range of the reference

input (0.5V to 1.25V).

POWER-DOWN MODE

The DAC2902 features a power-down function that can be

used to reduce the total supply current to less than 6mA.

Applying a logic HIGH to the PD pin will initiate the power-

down mode, while a logic LOW enables normal operation.

When left unconnected, an internal active pull-down circuit

will enable the normal operation of the converter.

FIGURE 10. Internal Reference Configuration.

FIGURE 11. External Reference Configuration.

DAC2902

+1.25V Ref.

SET

2kΩ0.1µF

FSA

+5V

REF

Current

Sources

REF

= V

REF

SET

Ref

Control

Amp

SET

External

Reference

REF

= V

REF

SET

DAC2902

+1.25V Ref.

FSA

+5V

REF

Current

Sources

Ref

Control

Amp

DAC2902 15

SBAS167C www.ti.com

GROUNDING, DECOUPLING, AND

LAYOUT INFORMATION

Proper grounding and bypassing, short lead length, and the use

of ground planes are particularly important for high-frequency

designs. Multilayer PCBs are recommended for best perfor-

mance since they offer distinct advantages such as minimiza-

tion of ground impedance, separation of signal layers by

ground layers, etc.

The DAC2902 uses separate pins for its analog and digital

supply and ground connections. The placement of the decou-

pling capacitor should be such that the analog supply (+VA)

is bypassed to the analog ground (AGND), and the digital

supply bypassed to the digital ground (DGND). In most

cases 0.1µF ceramic chip capacitors at each supply pin are

adequate to provide a low impedance decoupling path. Keep

in mind that their effectiveness largely depends on the

proximity to the individual supply and ground pins. There-

fore, they should be located as close as physically possible

to those device leads. Whenever possible, the capacitors

should be located immediately under each pair of supply/

ground pins on the reverse side of the pc board. This layout

approach will minimize the parasitic inductance of compo-

nent leads and PCB runs.

Further supply decoupling with surface-mount tantalum ca-

pacitors (1µF to 4.7µF) may be added as needed in proxim-

ity of the converter.

Low noise is required for all supply and ground connections

to the DAC2902. It is recommended to use a multilayer PCB

utilizing separate power and ground planes. Mixed signal

designs require particular attention to the routing of the

different supply currents and signal traces. Generally, analog

supply and ground planes should only extend into analog

signal areas, such as the DAC output signal and the refer-

ence signal. Digital supply and ground planes must be

confined to areas covering digital circuitry, including the

digital input lines connecting to the converter, as well as the

clock signal. The analog and digital ground planes should be

joined together at one point underneath the DAC. This can

be realized with a short track of approximately 1/8" (3mm).

The power to the DAC2902 should be provided through the

use of wide PCB runs or planes. Wide runs will present a

lower trace impedance, further optimizing the supply decou-

pling. The analog and digital supplies for the converter

should only be connected together at the supply connector of

the pc board. In the case of only one supply voltage being

available to power the DAC, ferrite beads along with bypass

capacitors may be used to create an LC filter. This will

generate a low-noise analog supply voltage that can then be

connected to the +VA supply pin of the DAC2902.

While designing the layout, it is important to keep the analog

signal traces separated from any digital line, in order to

prevent noise coupling onto the analog signal path.

DAC2902

16 SBAS167C

www.ti.com

DATE REVISION PAGE SECTION DESCRIPTION

1–Updated front page to standard format.

2 Pkg/Ordering Info Table Updated Package/Ordering Information table.

3 Electrical Characteristics Changed values for Supply Current and Power Dissipation.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

9/08 C

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

DAC2902Y/1K ACTIVE TQFP PFB 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DAC2902Y/1KG4 ACTIVE TQFP PFB 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DAC2902Y/250 ACTIVE TQFP PFB 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DAC2902Y/250G4 ACTIVE TQFP PFB 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DAC2902Y/1K TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

DAC2902Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC2902Y/1K TQFP PFB 48 1000 367.0 367.0 38.0

DAC2902Y/250 TQFP PFB 48 250 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

7,20

6,80

5,50 TYP

8,80

9,20

1,05

0,95

1,20 MAX 0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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