IXDE504PI - IXYS - Pdf.Support

First Release

Features

• Built using the advantages and compatibility

of CMOS and IXYS HDMOSTM processes

• Latch-Up Protected up to 4 Amps

• High 4A Peak Output Current

• Wide Operating Range: 4.5V to 30V

•-55°C to +125°C Extended Operating

Temperature

• Ability to Disable Output under Faults

• High Capacitive Load

Drive Capability: 1800pF in <15ns

• Matched Rise And Fall Times

• Low Propagation Delay Time

• Low Output Impedance

• Low Supply Current

• Two Drivers in a Single Package

Applications

• Limiting di/dt under Short Circuit

• Driving MOSFETs and IGBTs

• Motor Controls

• Line Drivers

• Pulse Generators

• Local Power ON/OFF Switch

• Switch Mode Power Supplies (SMPS)

• DC to DC Converters

• Pulse Transformer Driver

• Class D Switching Amplifiers

• Power Charge Pumps

General Description

The IXDD504 and IXDE504 each consist of two 4-Amp

CMOS high speed MOSFET gate drivers for driving the

latest IXYS MOSFETs & IGBTs. Each of the dual outputs

can source and sink 4 Amps of peak current while produc-

ing voltage rise and fall times of less than 15ns. The input

of each driver is TTL or CMOS compatible and is virtually

immune to latch up. Patented* design innovations eliminate

cross conduction and current "shoot-through". Improved

speed and drive capabilities are further enhanced by fast,

matched rise and fall times.

Additionally, each IXDD504 or IXDE504 driver incorporates a

unique ability to disable the output under fault conditions.

When a logical low is forced into the Enable input of a

driver, both of it's final output stage MOSFETs (NMOS and

PMOS) are turned off. As a result, the respective output of

the IXDD504 enters a tristate mode and, with additional

cicuitry, achieves a soft turn-off of the MOSFET/IGBT when

a short circuit is detected. This helps prevent damage that

could occur to the MOSFET/IGBT if it were to be switched

off abruptly due to a dv/dt over-voltage transient.

The IXDD504 and IXDE504 are each available in the 8-Pin

P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the

8-Lead DFN (D2) package, (which occupies less than 65%

of the board area of the 8-Pin SOIC).

*United States Patent 6,917,227

Ordering Information

Part Num ber Description Package

Type Packing Style Pack

Qty Configuration

IXDD 504PI 4A Low Side Gate Driver I.C. 8-Pin PDIP Tube 50

IXDD 504SIA 4A Low Side Gate Driver I.C. 8-Pin SO IC Tube 94

IXDD 504SIAT/R 4A Low Side Gate Driver I.C. 8-Pin SO IC 13” Tape and Reel 2500

IX DD 5 0 4 D2 4 A L o w Sid e Ga te Driv e r I.C . 8 -L e a d D F N 2 ” x 2 ” W a ffle P a c k 5 6

IXDD 504D2T/R 4A Low Side Gate Driver I.C. 8-Lead DFN 13” Tape and Reel 2500

Dual Non-

In ve rtin g

Drivers with

Enable

IXDE504P I 4A Low Side Gate Driver I.C. 8-Pin PDIP Tube 50

IXDE504S IA 4A Low Side Gate Driver I.C. 8-Pin SO IC Tube 94

IXDE504S IAT/R 4A Low Side Gate Driver I.C. 8-Pin SO IC 13” Tape and Reel 2500

IXDE504D 2 4A Low Side Gate Driver I.C. 8-Lead DFN 2” x 2” W affle Pack 56

IXDE504D 2T/R 4A Low Side Gate Driver I.C. 8-Lead DFN 13” Tape and Reel 2500

D u a l In v er tin g

Drivers

In v ertin g with

Enable

DS99568A(10/07)

NOTE: All parts are lead-free and RoHS Compliant

IXDD504/ IXDE504

4 Ampere Dual Low-Side Ultrafast MOSFET Drivers

with Enable for fast, controlled shutdown

IXDD504 / IXDE504

Figure 2 - IXDE504 Dual Inverting + Enable 4A Gate Driver Functional Block Diagram

Figure 1 - IXDD504 Dual Non-Inverting + Enable 4A Gate Driver Functional Block Diagram

* United States Patent 6,917,227

OUT A

Vcc

OUT B

IN A

IN B

GND

ANTI-CROSS

CONDUCTION

CIRCUIT *

ANTI-CROSS

CONDUCTION

CIRCUIT *

EN A

200 K

EN B

200 K

OUT A

Vcc

OUT B

IN A

IN B

GND

ANTI-CROSS

CONDUCTION

CIRCUIT *

ANTI-CROSS

CONDUCTION

CIRCUIT *

EN A

200 K

EN B

200 K

IXDD504 / IXDE504

Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .

All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.

Electrical Characteristics @ TA = 25 oC (3)

Absolute Maximum Ratings (1) Operating Ratings (2)

Parameter Value

Supply Voltage 35 V

All Other Pins (unless specified -0.3 V to VCC + 0.3V

otherwise)

Junction Temperature 150 °C

Storage Temperature -65 °C to 150 °C

Lead Temperature (10 Sec) 300 °C

Parameter Value

Operating Supply Voltage 4.5V to 30V

Operating Temperature Range -55 °C to 125 °C

(4)

IXYS reserves the right to change limits, test conditions, and dimensions.

Package Thermal Resistance *

8-Pin PDIP (PI) θJ-A (typ) 125 °C/W

8-Pin SOIC (SIA) θJ-A(typ) 200 °C/W

8-Lead DFN (D2) θJ-A(typ) 125-200 °C/W

8-Lead DFN (D2) θJ-C(max) 2.1 °C/W

8-Lead DFN (D2) θJ-S(typ) 6.4 °C/W

Symbol Parameter Test Conditions Min Typ Max Units

VIH, VENH High input & EN vo ltag e 4.5V ≤ VIN ≤ 18V 3 V

VIL, VENL Low input & EN voltage 4.5V ≤ VIN ≤ 18V 0.8 V

VIN Input voltage range -5 VCC + 0.3 V

VEN Enable voltage range - 0.3 VCC + 0.3 V

IIN Input current 0V ≤ VIN ≤ VCC -10 10

µA

VOH High output voltage VCC - 0.025 V

VOL Low output voltage 0.025 V

ROH High state output resistance VCC = 18V

IOUT = 10mA 1.5 2.5

Ω

ROL Low sta te ou tp ut resistance VCC = 18V

IOUT = 10mA 1.2 2.0

Ω

IPEAK Peak output current VCC = 15V 4 A

IDC Continuous output current Limited by package

dissipation 1 A

tR Rise time CLOAD =1000pF

VCC =18V 9 16 ns

tF Fall time CLOAD =1000pF

VCC =18V 8 14 ns

tONDLY On-time propagation delay CLOAD =1000pF

VCC =18V 19 40 ns

tOFFDLY Off-time propagation delay CLOAD =1000pF

VCC =18V 18 35 ns

tENOH Enabl e to output high delay tim e 15 30 ns

tDOLD Disable to high impedance state

delay time 63 100 ns

VCC Power supply voltage 4.5 18 30 V

REN Enable Pull-up Resistor 200 kΩ

ICC Pow er supply current VCC = 18V, VIN = 0V

VIN = 3.5V

VIN = VCC

µA

IXDD504 / IXDE504

Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC

All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.

Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)

Symbol Parameter Test Conditions Min Typ Max Units

VIH High input voltage 4.5V ≤ VCC ≤ 18 V 3 V

VIL Low input vol t age 4.5V ≤ VCC ≤ 18 V 0.8 V

VIN Input voltage range -5 VCC + 0.3 V

IIN Input current 0V ≤ VIN ≤ VCC -10 10

µA

VOH High output voltage VCC - 0.025 V

VOL Low output voltage 0.025 V

ROH High state output

resistance VCC = 18V, IOUT = 10m A 3 Ω

ROL Low state output

resistance VCC = 18V, IOUT = 10mA 2. 5 Ω

IDC Continuous output current 1 A

tR Rise time CLOAD =1000pF VCC =18V 10 ns

tF Fall time CLOAD =1000pF VCC =18V 9 ns

tONDLY On-time propagation delay CLOAD =1000pF VCC =18V 23 ns

tOFFDLY Off-time propagation delay CLOAD =1000pF VCC =18V 32 ns

tENOH Enable to output high

dela y time 60 ns

tDOLD Disable to high impedance

state delay time 120 ns

VCC Power supply voltage 4.5 18 30 V

IHIOL High impedance state

output leakage VCC = 18V, Temp. = 125°C 200 µA

ICC Power supply current VCC = 18V, VIN = 0V

VIN = 3.5V

VIN = VCC

150

µA

Notes:

1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The device is not intended to be operated outside of the Operating Ratings.

3. Electrical Characteristics provided are associated with the stated Test Conditions.

4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily

to highlight any specific performance limits within which the device is guaranteed to function.

* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:

1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the

resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards

and the values would be lower with forced convection. For the 8-Lead DFN package, the θJ-A value supposes the DFN package is soldered

on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance

to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W

easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size,

construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.

2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not

published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to

the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.

3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.

The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the

U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was

given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the

DFN package.

IXDD504 / IXDE504

SYMBOL FUNCTION DESCRIPTION

EN A A Channel Enable Channel A enable pin. When driven low, this pin disables the A channel and

forces a high impedance state to the A channel output.

IN A A Channel Input A channel input signal-TTL or CMOS compatible.

GND Ground

The system ground pin. Internally connected to all circuitry, this pin provides

ground reference for the entire chip. This pin should be connected to a low

noise analog ground plane for optimum performance.

IN B B Channel Input B channel input signal-TTL or CMOS compatible.

OUT B B Channel Output B channel driver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

VCC Supply Voltage

Positive power-supply voltage input. This pin provides power to the entire

chip. The range for this voltage is from 4.5V to 30V.

OUT A A Channel Output A channel driver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

EN B B Channel Enable Channel B enable pin. When driven low, this pin disables the B channel and

forces a high impedance state to the B channel output.

Pin Description

Figure 3 - Characteristics Test Diagram

CAUTION: Follow proper ESD procedures when handling and assembling this component.

IXYS reserves the right to change limits, test conditions, and dimensions.

NOTE: Solder tabs on bottoms of DFN packages are grounded

8 PIN DIP (PI)

8 PIN SOIC (SIA)

EN A

IN A

GND

IN B

EN B

OUT A

OUT B

VCC

8 LEAD DFN (D2)

(Bottom View)

EN A

IN A

IN B

EN B

OUT A

GND

OUT B

VCC

8 PIN DIP (PI)

8 PIN SOIC (SIA)

EN A

IN A

GND

IN B

EN B

OUT A

OUT B

VCC

8 LEAD DFN (D2)

(Bottom View)

EN A

IN A

IN B

EN B

OUT A

GND

OUT B

VCC

Pin Configurations

IXDD504 / IXDE504

Fall Time vs. Capacitive Load

100 1000 10000

Load Capacitance (pF)

Fall Time (ns)

30V

15V

Input Threshold Levels vs. Supply Voltage

0.5

1.5

2.5

0 5 10 15 20 25 30 35

Supply Voltage (V)

Threshold Level (V)

Positive going input

Negative going input

Rise Time vs. Capacitive Load

100 1000 10000

Load Capacitance (pF)

Rise Time (ns)

15V

30V

Typical Performance Characteristics

Fig. 4 Fig. 5

Fig. 6 Fig. 7

Fig. 8 Fig. 9

R ise T ime s v s. S u p ply Vo ltag e

0 5 10 15 20 25 30 35

Supp ly V oltage (V )

Rise Time (ns)

100pF

1000pF

10000pF

5400pF

Fall T im e vs. Supply V o ltage

0 5 10 15 20 25 30 35

S upp ly Vo ltage (V )

Fall Time (ns)

100pF

1000pF

10000pF

5400pF

Ris e / F all Time vs. Te mperature

VSUPPLY = 15V CLOAD = 10 00pF

-50 -30 -10 10 30 50 70 90 110 130 150

T emperature (C)

Rise / Fall Time (ns)

IXDD504 / IXDE504

Fig. 11

Fig. 13

Fig. 15

Fig. 10

Fig. 12

Fig. 14

Input T hreshold Levels vs. Temperature

VSUPPLY = 15V

0.5

1.5

2.5

-50 -30 -10 10 30 50 70 90 110 130 150

Temperature (C)

In put T hres ho ld Lev el (V )

Positive going input

N egative going input

Propagation Delay vs. Supply Voltage

Rising Input, CLOAD = 1000pF

0 5 10 15 20 25 30 35

Supply Voltage (V)

Propagation Delay Time (ns)

Propagation Delay vs. Supply Voltage

Falling Input, CLOAD = 1000pF

0 5 10 15 20 25 30 35

Supply Voltage (V)

Propagation Delay Time (ns)

Propagation Delay vs. Tem perature

VSUPPLY = 15V C LOAD = 1000pF

-50 0 50 100 150

Tem e prature (C)

Propagation Delay Time (ns)

Positve going input

Negative going input

Q uiescent Current vs. Supply V oltage

VIN = 0V

0.01

0.1

0 5 10 15 20 25 30 35

Supply V oltage (V )

Quiesent C urrent (uA)

Q uiescent Current vs. T em perature

VSUPPLY = 15V

0.01

0.1

100

1000

-50 -30 -10 10 30 50 70 90 110 130 150

T emperature (C)

Quies c ent Cu rrent (uA)

N on-inverting, Input= "0"

Inverting Input = "1"

IXDD504 / IXDE504

Fig. 17

Fig. 16

Fig. 18 Fig. 19

Fig. 20 Fig. 21

Supply Current vs. Capacitive Load

VSUPPLY = 5V

0.01

0.1

100

100 1000 10000

Load Capacitance (pF)

Supply C urren t (m A)

100kHz

1MHz

2MHz

10kHz

Sup ply Cu r r ent vs. Frequ enc y

VSUPPLY = 5V

0.01

0.1

100

10 100 1000 10000

Frequency (kH z)

Supply C urrent (m A)

100pF

1000pF

10000pF

5400pF

Supply Current vs. Capacitive Load

VSUPPLY = 15V

0.01

0.1

100

1000

100 1000 10000

Load Capacitance (pF)

Supply C urrent (m A)

100kHz

1MHz

2MHz

10kHz

Su pply Current vs. Frequency

VSUPPLY = 15V

0.01

0.1

100

1000

10 100 1000 10000

Frequency (kH z)

Supply Current (mA)

100pF

1000pF

10000pF

5400pF

Supply Current vs. Capacitive Load

VSUPPLY = 30V

0.1

100

1000

100 1000 10000

Load Capacitance (pF)

Supply C urrent (m A)

2MHz

1MHz

100kHz

10kHz

Su pply Current v s. Frequency

VSUPPLY = 30V

0.1

100

1000

10 100 1000 10000

Frequency (kH z)

Supply C urrent (m A)

100pF

1000pF

5400pF

10000pF

IXDD504 / IXDE504

Fig. 24 Fig. 25

Fig. 22 Fig. 23

Fig. 26 Fig. 27

O utput S ource Current vs. Supply V oltage

0 5 10 15 20 25 30 35

Supp ly V oltage (V )

Sourc e C urrent (A)

Output Sink Current vs. Supply Voltage

-14

-12

-10

-8

-6

-4

-2

0 5 10 15 20 25 30 35

Supply Voltage (V )

Sink Current (A)

Output Source Current vs. Tem perature

VSUPPLY = 15V

-50 0 50 100 150

Temperature (C)

Output Source Current (A)

Output Sink Current vs. Temperature

VSUPPLY = 15V

-6

-5

-4

-3

-2

-1

-50 0 50 100 150

Temperature (C)

Output Sink Current (A)

H igh State Output Resistance vs. Supply Voltage

0.5

1.5

2.5

0 5 10 15 20 25 30 35

Supply Voltage (V)

Output Resistance (ohms)

Low State O utput Resistance vs. Supply Voltage

0.5

1.5

2.5

0 5 10 15 20 25 30 35

Supply Voltage (V)

Output Resistance (ohms)

IXDD504 / IXDE504

ENA BLE Propagation vs. Temperature

VSUPPLY = 15V

100

-50 0 50 100 150

Tem perature (C)

ENABLE Delay Time (ns)

Positive going ENAB LE to output ON

Negative going ENA B LE to high impedance state

Fig. 28

Ref

Figure 32 - Typical Application Short Circuit di/dt Limit

ENABLE Threshold vs. Supply Voltage

0.5

1.5

2.5

0 5 10 15 20 25 30 35

Supply Voltage (V)

Positive Going Level (V)

Positive going input

Negative goi ng input

ENABLE Threshold vs. Temperature

VSUPPLY = 15V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 0 50 100 150

Temperature (C)

Enable Threshold (V)

Positive going input

Negative going input

EN A BLE Propagation Tim e vs. Supply Voltage

100

150

200

250

300

350

400

0 5 10 15 20 25 30 35

Supply Voltage (V)

ENABLE Delay Time (ns)

Positve going ENA BLE to output ON

Negative going ENABLE to high impedance state

Fig. 29

Fig. 30 Fig. 31

IXDD504 / IXDE504

APPLICATIONS INFORMATION

Short Circuit di/dt Limit

A short circuit in a high-power MOSFET such as the IXFN100N20,

(20A, 1000V), as shown in Figure 32, can cause the current

through the module to flow in excess of 60A for 10µs or more

prior to self-destruction due to thermal runaway. For this

reason, some protection circuitry is needed to turn off the

MOSFET module. However, if the module is switched off too

fast, there is a danger of voltage transients occuring on the

drain due to Ldi/dt, (where L represents total inductance in

series with drain). If these voltage transients exceed the

MOSFET's voltage rating, this can cause an avalanche break-

down.

The IXDD504 and IXDE504 have the unique capability, with

additional circuitry, to softly switch off the high-power MOSFET

module, significantly reducing these Ldi/dt transients.

Thus, the IXDD504 & IXDE504 help to prevent device destruc-

tion from both dangers; over-current, and avalanche break-

down due to di/dt induced over-voltage transients.

The IXDD504 & IXDE504 are designed to not only provide ±4A

per output under normal conditions, but also to allow their

outputs to go into a high impedance state. This permits the

IXDD504 or IXDE504 outputs to control a separate weak pull-

down circuit during detected overcurrent shutdown conditions

to limit and separately control dVGS/dt gate turnoff. This circuit

is shown in Figure 33.

Referring to Figure 33, the protection circuitry should include

a comparator, whose positive input is connected to the source

of the IXFN100N20. A low pass filter should be added to the

input of the comparator to eliminate any glitches in voltage

caused by the inductance of the wire connecting the source

resistor to ground. (Those glitches might cause false triggering

of the comparator).

The comparator's output should be connected to a SRFF(Set

Reset Flip Flop). The flip-flop controls both the Enable signal,

and the low power MOSFET gate. Please note that CMOS 4000-

series devices operate with a VCC range from 3 to 15 VDC, (with

18 VDC being the maximum allowable limit).

A low power MOSFET, such as the 2N7002, in series with a

resistor, will enable the IXFN100N20 gate voltage to drop

gradually. The resistor should be chosen so that the RC time

constant will be 100us, where "C" is the Miller capacitance of

the IXFN100N20.

For resuming normal operation, a Reset signal is needed at

the SRFF's input to enable the IXDD504 again. This Reset can

be generated by connecting a One Shot circuit between the

IXDD504 Input signal and the SRFF restart input. The One Shot

will create a pulse on the rise of the IXDD504 input, and this

pulse will reset the SRFF outputs to normal operation.

When a short circuit occurs, the voltage drop across the low-

value, current-sensing resistor, (Rs=0.005 Ohm), connected

between the MOSFET Source and ground, increases. This

triggers the comparator at a preset level. The SRFF drives a low

input into the Enable pin disabling the IXDD504 output. The

SRFF also turns on the low power MOSFET, (2N7000).

In this way, the high-power MOSFET module is softly turned off

by the IXDD504, preventing its destruction.

10uH

0.1

20nH

10k

R+

IXFN100N20

Rcomp

100pF

C+

V+

V-

Comp

LM339

1600

Rsh

Ccomp

1pF

VCC

DGND

OUT

IXDD504

VIN

VCC

REF

CD4001A

NOR2

Ros

NOT2

CD4049A

CD4011A

NAND

CD4049A

NOT1

CD4001A

NOR1

CD4049A

NOT3

Low_Power

2N7000

1pF

Cos

One Shot

Circuit

SR Fli p-F l op

Figure 33 - Application Test Diagram

IXDD504 / IXDE504

When designing a circuit to drive a high speed MOSFET

utilizing the IXDD504 or IXDE504, it is very important to keep

certain design criteria in mind, in order to optimize performance

of the driver. Particular attention needs to be paid to Supply

Bypassing, Grounding, and minimizing the Output Lead

Inductance.

Say, for example, we are using the IXDD504 to charge a

2500pF capacitive load from 0 to 25 volts in 25ns.

Using the formula: IC = C (∆V / ∆t), where ∆V=25V C=2500pF

and ∆t=25ns we can determine that to charge 2500pF to 25

volts in 25ns will take a constant current of 2.5A. (In reality, the

charging current won’t be constant, and will peak somewhere

around 4A).

SUPPLY BYPASSING

In order for our design to turn the load on properly, the IXDD504

must be able to draw this 2.5A of current from the power supply

in the 25ns. This means that there must be very low impedance

between the driver and the power supply. The most common

method of achieving this low impedance is to bypass the

power supply at the driver with a capacitance value that is a

magnitude larger than the load capacitance. Usually, this

would be achieved by placing two different types of bypassing

capacitors, with complementary impedance curves, very close

to the driver itself. (These capacitors should be carefully

selected, low inductance, low resistance, high-pulse current-

service capacitors). Lead lengths may radiate at high frequency

due to inductance, so care should be taken to keep the lengths

of the leads between these bypass capacitors and the IXDD504

to an absolute minimum.

GROUNDING

In order for the design to turn the load off properly, the IXDD504

must be able to drain this 2.5A of current into an adequate

grounding system. There are three paths for returning current

that need to be considered: Path #1 is between the IXDD504

and it’s load. Path #2 is between the IXDD504 and it’s power

supply. Path #3 is between the IXDD504 and whatever logic

is driving it. All three of these paths should be as low in

resistance and inductance as possible, and thus as short as

practical. In addition, every effort should be made to keep

these three ground paths distinctly separate. Otherwise, (for

instance), the returning ground current from the load may

develop a voltage that would have a detrimental effect on the

logic line driving the IXDD504.

OUTPUT LEAD INDUCTANCE

Of equal importance to Supply Bypassing and Grounding are

issues related to the Output Lead Inductance. Every effort

should be made to keep the leads between the driver and it’s

load as short and wide as possible. If the driver must be

placed farther than 0.2” from the load, then the output leads

should be treated as transmission lines. In this case, a

twisted-pair should be considered, and the return line of each

twisted pair should be placed as close as possible to the

ground pin of the driver, and connect directly to the ground

terminal of the load.

Supply Bypassing and Grounding Practices, Output Lead inductance

IXDD504 / IXDE504

IXYS Semiconductor GmbH

Edisonstrasse15 ; D-68623; Lampertheim

Tel: +49-6206-503-0; Fax: +49-6206-503627

e-mail: marcom@ixys.de

IXYS Corporation

3540 Bassett St; Santa Clara, CA 95054

Tel: 408-982-0700; Fax: 408-496-0670

e-mail: sales@ixys.net

www.ixys.com

h X 45

0.197 [5.00]

0.158 [4.00]

0.101 [2.56]

0.121 [3.06]

0.048 [1.22] 0.048 [1.22]

0.031 [0.78] 0.031 [0.78]

0.016 [0.40]

0.022 [0.55]

0.035 [0.90]

S0.002^0.000; o S0.05^0.00;o

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