ST24/25C04, ST24C04R
ST24/25W04
SERIAL 4K (512 x 8) EEPROM
July 1996 1/16
AI00851D
2
E1-E2 SDA
VCC
ST24x04
ST25x04
St24C04R
MODE/WC*
SCL
VSS
PRE
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLESwith
40 YEARSDATARETENTION
SINGLESUPPLYVOLTAGE:
– 3V to 5.5V for ST24x04 versions
– 2.5V to 5.5V forST25x04versions
– 1.8V to 5.5V forST24C04Rversion only
HARDWARE WRITE CONTROL VERSIONS:
ST24W04and ST25W04
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIALINTERFACE, FULLY I2C
BUS COMPATIBLE
BYTEand MULTIBYTE WRITE (up to 4
BYTES)
PAGEWRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIALREAD
MODES
SELFTIMED PROGRAMMINGCYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers arange of4K bits I2C bus
EEPROM products, the ST24/25C04, the
ST24C04RandtheST24/25W04.Inthetext,prod-
ucts are referredto as ST24/25x04, where ”x” is:
”C” for Standard version and ”W” for hardware
Write Control version.
PRE Write Protect Enable
E1-E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock
MODE Multibyte/Page Write Mode
(C version)
WC Write Control (W version)
VCC Supply Voltage
VSS Ground
Table 1. Signal Names
8
1
SO8 (M)
150mil Width
8
1
PSDIP8 (B)
0.25mm Frame
Note: WC signalis only available for ST24/25W04 products.
The ST24/25x04 are 4K bit electrically erasable
programmable memories (EEPROM), organized
as 2 blocksof 256x 8 bits. They are manufactured
in SGS-THOMSON’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
ance of one million erase/write cycles with a data
retention of 40 years. The memories operate with
a power supply value as low as 1.8V for the
ST24C04Ronly.
Both Plastic Dual-in-Line andPlastic Small Outline
packagesare available.
The memories are compatible with the I2C stand-
ard, two wire serialinterfacewhich usesa bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus defini-
tion.Thisisused together with2 chipenableinputs
(E2, E1) so that up to 4 x 4K devices may be
attached to the I2C bus and selected individually.
Thememoriesbehave as a slave device in theI2C
protocol with all memoryoperations synchronized
by the serial clock. Read and writeoperations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
streamof7 bits (identificationcode1010),plusone
read/write bit and terminated by an acknowledge
bit.
SDAVSS SCL
MODE/WCE1
PRE VCC
E2
AI00852D
ST24x04
ST25x04
ST24C04R
1
2
3
4
8
7
6
5
Figure2A. DIP Pin Connections
1
AI01107D
2
3
4
8
7
6
5 SDAVSS SCL
MODE/WCE1
PRE VCC
E2
ST24x04
ST25x04
ST24C04R
Figure 2B. SO Pin Connections
DESCRIPTION (cont’d)
Symbol Parameter Value Unit
TAAmbient Operating Temperature –40 to125 °C
TSTG Storage Temperature –65 to150 °C
TLEAD Lead Temperature, Soldering (SO8 package)
(PSDIP8 package) 40 sec
10 sec 215
260 °C
VIO Input or Output Voltages –0.6 to 6.5 V
VCC Supply Voltage –0.3 to 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) (2) 4000 V
Electrostatic Discharge Voltage (Machine model) (3) 500 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Programand other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
2/16
ST24/25C04, ST24C04R, ST24/25W04
Mode RW bit MODE Bytes Initial Sequence
Current Address Read ’1’ X 1 START, Device Select, RW = ’1’
Random Address Read ’0’ X1
START, Device Select, RW =’0’, Address,
’1’ reSTART, Device Select,RW = ’1’
Sequential Read ’1’ X 1 to 512 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, RW = ’0’
Multibyte Write (2) ’0’ VIH 4 START, Device Select, RW = ’0’
Page Write ’0’ VIL 8 START, Device Select, RW = ’0’
Notes: 1. X= VIH or VIL
2. Multibyte Write not available in ST24/25W04 versions.
Table 4. OperatingModes (1)
Device Code Chip Enable Block
Select RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 A8 RW
Note: The MSB b7 is sent first.
Table 3. Device SelectCode
Whenwriting data tothe memory it respondsto the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master,it acknowledgesthe receiptof the data
bytes in the same way. Data transfers are termi-
natedwith a STOPcondition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset(POR) circuit is implemented. Until the VCC
voltage has reached the POR thresholdvalue, the
internal reset is active, all operationsare disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
mustbe appliedbefore applying anylogic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor canbe connectedfrom the SCLline to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
andis usedto transferdatain orout ofthe memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus.AresistormustbeconnectedfromtheSDA
bus line to VCC to actas pull up (see Figure3).
Chip Enable (E1 - E2). These chip enable inputs
are used to set the 2 least significantbits (b2, b3)
of the 7 bit device select code. These inputs may
be driven dynamically or tied to VCC or VSS to
establish the device selectcode.
Protect Enable (PRE). The PRE input pin, in ad-
dition to thestatusof theBlock AddressPointerbit
(b2, location 1FFh as in Figure 7), sets the PRE
write protectionactive.
Mode(MODE). TheMODEinputisavailableonpin
7 (seealsoWC feature)andmaybedrivendynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL forPage
Writemode. When unconnected,the MODE input
is internallyread as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W04 and
ST25W04versions onpin 7. Thisfeature is usefull
to protect the contents of the memory from any
erroneouserase/write cycle. The Write Controlsig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory areais not writeprotected.
3/16
ST24/25C04, ST24C04R, ST24/25W04
AI01100
VCC
CBUS
SDA
RL
MASTER
RL
SCL CBUS
100 200 300 400
0
4
8
12
16
20
CBUS (pF)
RLmax (kΩ)
VCC =5V
Figure3. Maximum RLValueversus Bus Capacitance(CBUS) for an I2C Bus
The devices with this Write Control feature no
longersupport the Multibyte Write mode ofopera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The ST24/25x04 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitterand any device that reads
the data asa receiver. The device that controlsthe
data transfer isknown as the master and the other
as the slave. The master willalways initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x04 are always slave
devicesin all communications.
Start Condition. STARTis identifiedby a high to
low transitionof the SDAline while the clock SCL
is stable in the high state. ASTARTcondition must
precede any command for data transfer. Except
duringa programmingcycle, the ST24/25x04con-
tinuously monitor the SDAand SCL signals for a
START conditionand will not respond unless one
isgiven.
StopCondition. STOPis identifiedbya lowtohigh
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x04
and the bus master.A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledgesignal
is usedto indicate a successfulldatatransfer.The
bus transmitter, either master or slave,will release
theSDAbusaftersending8 bitsof data.During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledgethe receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x04
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tionthe SDAsignalmust bestable duringthe clock
low to high transition and the data must change
ONLY when the SCL line is low.
MemoryAddressing. To startcommunication be-
tween the bus master and the slave ST24/25x04,
themastermustinitiatea STARTcondition.Follow-
ing this, the mastersends onto the SDAbus line 8
bits(MSB first) corresponding to the device select
code(7 bits)and a READ or WRITEbit.
SIGNAL DESCRIPTIONS (cont’d)
4/16
ST24/25C04, ST24C04R, ST24/25W04
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
ZWCL WC Input Impedance (ST24/25W04) VIN ≤0.3 VCC 520kΩ
Z
WCH WC Input Impedance (ST24/25W04) VIN ≥0.7 VCC 500 kΩ
tLP Low-pass filter input time constant
(SDAand SCL) 100 ns
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA=25°C, f = 100kHz )
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤VIN ≤VCC ±2µA
ILO Output LeakageCurrent 0V ≤VOUT ≤VCC
SDAin Hi-Z ±2µA
ICC Supply Current (ST24 series) VCC =5V,f
C= 100kHz
(Rise/Fall time < 10ns) 2mA
Supply Current (ST25 series) VCC = 2.5V,fC= 100kHz 1 mA
ICC1 Supply Current (Standby)
(ST24 series)
VIN =V
SS or VCC,
VCC =5V 100 µA
VIN =V
SS or VCC,
VCC =5V,f
C= 100kHz 300 µA
ICC2 Supply Current (Standby)
(ST25 series)
VIN =V
SS or VCC,
VCC = 2.5V 5µA
VIN =V
SS or VCC,
VCC = 2.5V,fC= 100kHz 50 µA
ICC3 Supply Current (Standby)
(ST24C04R)
VIN =V
SS or VCC,
VCC = 3.6V 20 µA
VIN =V
SS or VCC,
VCC = 3.6V,fC= 100kHz 60 µA
ICC4 Supply Current (Standby)
(ST24C04R)
VIN =V
SS or VCC,
VCC = 1.8V 10 µA
VIN =V
SS or VCC,
VCC = 1.8V,fC= 100kHz 20 µA
VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V
VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC +1 V
V
IL Input Low Voltage
(E1-E2, PRE, MODE, WC) –0.3 0.5 V
VIH Input HighVoltage
(E1-E2, PRE, MODE, WC) VCC – 0.5 VCC +1 V
V
OL
Output Low Voltage(ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage(ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V
Output Low Voltage
(ST24C04R) IOL = 1mA, VCC = 1.8V 0.3 V
Table 6. DC Characteristics
(TA= 0 to70°C, –20to 85°C or –40 to 85°C; VCC = 3V to 5.5V,2.5V to 5.5V or 1.8Vto 5.5V)
5/16
ST24/25C04, ST24C04R, ST24/25W04
The4most significantbitsofthedeviceselectcode
are the device type identifier, correspondingto the
I2C bus definition. For these memories the 4 bits
arefixed as1010b. The following 2 bitsidentify the
specific memoryon the bus. They are matched to
the chip enable signals E2, E1. Thusup to 4 x 4K
memories can be connected on the same bus
giving a memorycapacity total of 16K bits. After a
START condition any memory on thebus will iden-
tify the device code and compare the following 2
bits to its chipenable inputsE2, E1.
The 7th bit sent is the block number (one block =
256 bytes). The 8th bit sent is the reador write bit
(RW), this bit is set to ’1’ for read and ’0’ for write
operations.If a matchis found, the corresponding
memory will acknowledgethe identificationon the
SDAbus during the 9th bit time.
Input Rise and Fall Times ≤50ns
Input Pulse Voltages 0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
AC MEASUREMENT CONDITIONS
AI00825
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Figure4. AC TestingInput Output Waveforms
DEVICEOPERATION (cont’d)
Symbol Alt Parameter Min Max Unit
tCH1CH2 tRClock Rise Time 1 µs
tCL1CL2 tFClock Fall Time 300 ns
tDH1DH2 tRInput Rise Time 1 µs
tDL1DL1 tFInput Fall Time 300 ns
tCHDX (1) tSU:STA Clock High to Input Transition 4.7 µs
tCHCL tHIGH Clock Pulse Width High 4 µs
tDLCL tHD:STA Input Low to Clock Low (START) 4 µs
tCLDX tHD:DAT Clock Low to Input Transition 0 µs
tCLCH tLOW Clock Pulse Width Low 4.7 µs
tDXCX tSU:DAT Input Transition to Clock Transition 250 ns
tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs
tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs
tCLQV (2) tAA Clock Low to Next Data Out Valid 0.3 3.5 µs
tCLQX tDH Data OutHold Time 300 ns
fCfSCL Clock Frequency 100 kHz
tW(3) tWR Write Time 10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDAaway from SCL= 1 in order to avoidunwanted STARTand/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 addressMSB are not constant) the
maximum programming timeis doubledto 20ms.
Table 7. ACCharacteristics
(TA= 0 to70°C, –20to 85°C or –40 to 85°C; VCC = 3V to 5.5V,2.5V to 5.5V or 1.8Vto 5.5V)
6/16
ST24/25C04, ST24C04R, ST24/25W04
SCL
SDA IN
SCL
SDA OUT
SCL
SDA IN
tCHCL
tDLCL
tCHDX
START
CONDITION
tCLCH
tDXCX
tCLDX
SDA
INPUT SDA
CHANGE
tCHDH
tDHDL
STOP &
BUS FREE
DATA VALID
tCLQV tCLQX
DATA OUTPUT
tDHDL
tCHDH
STOP
CONDITION
tCHDX
START
CONDITION
WRITE CYCLE
tW
AI00795
Figure5. ACWaveforms
Write Operations
The Multibyte Write mode (only available on the
ST24/25C04and ST24C04Rversions) isselected
when the MODE pin is at VIH and the Page Write
modewhenMODEpinisatVIL. TheMODE pinmay
be driven dynamicallywith CMOSinput levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac-
cessto oneblockof 256bytesof thememory. After
receipt of the byte address the device again re-
spondswith an acknowledge.
For theST24/25W04versions, anywritecommand
with WC = 1will not modifythe memory content.
Byte Write. In the Byte Write mode the master
sendsonedatabyte,whichisacknowledgedbythe
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independantof the state of theMODE pinwhich
could be left floating if only this mode was to be
used. However it is nota recommendedoperating
mode, asthispinhasto beconnectedto eitherVIH
or VIL, to minimize the stand-by current.
7/16
ST24/25C04, ST24C04R, ST24/25W04
SCL
SDA
SCL
SDA
SDA
START
CONDITION SDA
INPUT SDA
CHANGE
AI00792
STOP
CONDITION
123 789
MSB ACK
START
CONDITION
SCL 123 789
MSB ACK
STOP
CONDITION
Figure6. I2C Bus Protocol
Multibyte Write. For theMultibyteWritemode, the
MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the
memory. The master sends fromone up to 4 bytes
ofdata,whichare eachacknowledgedbythemem-
ory. The transfer is terminated by the master gen-
eratinga STOPcondition.The duration ofthe write
cycle is tW= 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 6 most significant address bits A7-
A2), the programming time is then doubled to a
maximumof20ms.Writing more than4 bytesinthe
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutivebytes as soon as the first address of
these 8 bytes is the first address of the row, the 7
followingbytesbeingwritteninthe7followingbytes
of this same row.
Page Write. For the Page Write mode, the MODE
pin must be at VIL. The Page Write modeallowsup
to 8 bytes to be written in a single write cycle,
providedthat they are all located in the same ’row’
in the memory: thatis the 5 most significantmem-
8/16
ST24/25C04, ST24C04R, ST24/25W04
ory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytesof
data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
mastergeneratingaSTOPcondition.Caremustbe
taken to avoid address counter ’roll-over’ which
couldresultin databeing overwritten.Note that,for
anywritemode, thegenerationbythe masterof the
STOP condition starts the internal memory pro-
gramcycle.Allinputsaredisableduntilthecomple-
tion of this cycle and the memorywill not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internalwrite cycle,the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value ofthe write time (tW) isgiven inthe
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequenceissued by the
master.
WRITE
Cycle
in Progress
AI01099B
Next
Operation
is
Addressing the
Memory
START Condition
DEVICE
SELECT
with RW = 0
ACK
Returned
YES
NO
YESNO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random
Address
READ Operation
Send
Byte Address
First byte of
instruction
with RW = 0
already
decodedby ST24xxx
Figure 8. Write Cycle Polling using ACK
AI00855B
1FFh b7 b3 b2 XX
100h
Block 1
Block 0
Protect
Flag
Enable =
0
Disable = 1
8
byte
boundary
address
Protect Location
Figure 7. Memory Protection
9/16
ST24/25C04, ST24C04R, ST24/25W04
The sequenceis as follows:
– Initialcondition:aWriteisinprogress(seeFigure
8).
– Step 1: the Master issues a START condition
followedbya Device Selectbyte(1stbyte ofthe
newinstruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goesback to Step 1. If thememory has
terminated the internal write cycle, it will re-
spond with an ACK, indicating that the memory
is ready to receive the second part of the next
instruction (the first byte of this instruction was
alreadysent during Step 1).
Write Protection. Data in the upper block of 256
bytes of the memory may be write protected. The
memory is write protected between a boundary
address and the top of memory (address 1FFh)
when thePREinputpinis takenhigh and whenthe
Protect Flag (bit b2 in location 1FFh) is set to ’0’.
The boundary addressis user defined by writing it
in the Block Address Pointer. The Block Address
Pointeris an 8 bitEEPROM registerlocated at the
address1FFh. It is composedby 5 MSBsAddress
Pointer, which defines the bottom boundary ad-
dress,and 3 LSBs which must be programmed at
DEVICE OPERATION (cont’d) ’0’. This Address Pointer can therefore address a
boundaryin steps of 8 bytes.
The sequence to use the Write Protected feature
is:
– write the data to beprotected into the top of the
memory, upto,but not including, location1FFh;
– set the protection by writing the correct bottom
boundary address in the Address Pointer (5
MSBs of location 1FFh) with bit b2 (Protect flag)
set to ’0’.Note that for a correct fonctionalityof
thememory, allthe 3LSBsof theBlockAddress
Pointermust also be programmed at ’0’.
Thearea willnowbeprotectedwhenthe PREinput
pin is taken High. While the PRE input pin is read
at’0’bythe memory, thelocation1FFhcanbeused
asa normalEEPROMbyte.
Caution:
Special attention must be used when
using the protect mode together with the Multibyte
Write mode (MODE input pinHigh).If theMultibyte
Write starts atthe locationright belowthe first byte
oftheWrite Protectedarea,then theinstructionwill
write over the first 3 bytes of the Write Protected
area. The area protected is thereforesmaller than
thecontentdefinedinthelocation1FFh,by3bytes.
This doesnot apply to the Page Write mode as the
address counter ’roll-over’ and thus cannot go
abovethe 8 bytes lower boundaryofthe protected
area.
STOP
START
BYTE WRITE DEV SEL BYTE ADDR DATA IN
START
MULTIBYTE
AND
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
AI00793
STOP
DATA IN N
ACK ACK ACK
R/W
ACK ACK ACK
R/W
ACK ACK
Figure 9. Write Modes Sequence (ST24/25C04 and ST24C04R)
10/16
ST24/25C04, ST24C04R, ST24/25W04
STOP
START
BYTE WRITE DEV SEL BYTE ADDR DATA IN
WC
START
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1
WC
DATA IN 2
AI01101B
PAGE WRITE
(cont’d)
WC (cont’d)
STOP
DATA IN N
ACK ACK ACK
R/W
ACK ACK ACK
R/W
ACK ACK
Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W04)
Read Operations
Readoperationsareindependentofthestateofthe
MODE pin. On delivery, the memory content is set
at all ”1’s” (orFFh).
CurrentAddress Read.Thememoryhasaninter-
nal byte addresscounter.Eachtime a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with theRW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
addresscounter.This counter isthen incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOPcon-
dition.
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 11. This is followedby another
START condition from the master and the byte
addressis repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed.The master haveto NOTacknowledge
the byte output, but terminatesthe transfer with a
STOPcondition.
SequentialRead. This modecan be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledgethe last byte out-
11/16
ST24/25C04, ST24C04R, ST24/25W04
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counterwill’roll-over’andthememorywillcontinue
to output data.
Acknowledge in Read Mode. In all read modes
theST24/25x04waitforanacknowledgeduringthe
9thbit time. If themasterdoes notpulltheSDAline
low during thistime, the ST24/25x04terminate the
data transferand switches to a standbystate.
START
DEV SEL * BYTE ADDR
START
DEV SEL DATA OUT 1
AI00794C
DATA OUT N
STOP
START
CURRENT
ADDRESS
READ DEV SEL DATA OUT
RANDOM
ADDRESS
READ
STOP
START
DEV SEL * DATA OUT
SEQUENTIAL
CURRENT
READ
STOP
DATA OUT N
START
DEV SEL * BYTE ADDR
SEQUENTIAL
RANDOM
READ
START
DEV SEL * DATA OUT 1
STOP
ACK
R/W
NO ACK
ACK
R/W
ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
Figure11. Read Modes Sequence
Note: * The 7 Most Significantbits ofDEV SELbytes of a Random Read (1stbyte and3rd byte) must beidentical.
DEVICE OPERATION (cont’d)
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ST24/25C04, ST24C04R, ST24/25W04
ORDERING INFORMATION SCHEME
Notes: 3 * Temperature range on special request only.
5 * Temperature range for ST24C04R only.
Parts are shipped with the memory content set at all ”1’s” (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortformcatalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearestto you.
Operating Voltage
ST24C04 3V to 5.5V
ST24W04 3V to 5.5V
ST25C04 2.5V to 5.5V
ST25W04 2.5V to 5.5V
ST24C04R 1.8Vto 5.5V
Range
Standard
Hardware Write Control
Standard
Hardware Write Control
Standard
Package
B PSDIP8
0.25mm Frame
M SO8 150milWidth
Temperature Range
1 0 to 70 °C
5 * –20 to 85 °C
6 –40 to 85 °C
3 * –40 to 125 °C
Option
TR Tape & Reel
Packing
Example: ST24C04 M 1 TR
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ST24/25C04, ST24C04R, ST24/25W04
PSDIP-a
A2
A1
A
L
e1
D
E1 E
N
1
C
eA
eB
B1
B
Symb mm inches
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N8 8
PSDIP8
Drawing is not to scale
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
14/16
ST24/25C04, ST24C04R, ST24/25W04
SO-a
E
N
CP
Be
A
D
C
LA1 α
1H
hx45°
Symb mm inches
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0°8°0°8°
N8 8
CP 0.10 0.004
SO8
Drawing is not to scale
SO8 - 8 lead Plastic Small Outline, 150 mils body width
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ST24/25C04, ST24C04R, ST24/25W04
Information furnished is believed to be accurate and reliable. However,SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use ofsuch informationnor for anyinfringement of patents or other rights of third parties which may result from its use. No
license is grantedby implicationor otherwise under any patent orpatent rightsof SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproducts are notauthorized for use as criticalcomponents inlife support devices or systems withoutexpress
written approval ofSGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics - All RightsReserved
Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada -China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta -Morocco - TheNetherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand- United Kingdom -U.S.A.
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ST24/25C04, ST24C04R, ST24/25W04
