MT9M413C36STM - Micron

09005aef806807ca

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

1.3-MEGAPIXEL CMOS

ACTIVE-PIXEL DIGITAL

IMAGE SENSOR

MT9M413

Micron Part Number: MT9M413C36STC

Description

The MI-MV13 is a 1,280H x 1,024V (1.3 megapixel)

CMOS digital image sensor capable of 500 frames-per-

second (fps) operation. Its TrueSNAP™ electronic

shutter allows simultaneous exposure of the entire

pixel array. Available in color or monochrome, the sen-

sor has on-chip 10-bit analog-to-digital converters

(ADCs), which are self-calibrating, and a fully digital

interface. The chip's input clock rate is 66 MHz at

approximately 500 fps, providing compatibility with

many off-the-shelf interface components.

The sensor has ten 10-bit-wide digital output ports.

Its open architecture design provides access to internal

operations. ADC timing and pixel-read control are

integrated on-chip. At 60 fps, the sensor dissipates less

than 150mW, and at 500 fps less than 500mW; it oper-

ates on a 3.3V supply. Pixel size is 12 microns square,

and digital responsivity is 1,600 bits per lux-second.

Features/Top Level Specifications

• Array Format: 1,280H x 1,024 V (1,310,720 pixels)

• Pixel Size and Type: 12.0µm x 12.0µm TrueSNAP

(shuttered-node active pixel)

• Sensor Imaging Area: H: 15.36mm, V: 12.29mm,

Diagonal: 19.67mm

• Frame Rate: 0–500+ fps @ (1,280 x 1,024), >10,000

fps with partial scan, [e.g. 0–4000 fps @ (1,280 x 128)]

• Output Data Rate: 660 Mbs (master clock 66 MHz,

~500 fps)

• Power Consumption: < 500 mW @ 500 fps; <150 mW

@ 60 fps

• Digital Responsivity: Monochrome: 1,600 bits per

lux-second @ 550nm; ADC reference @ 1V

• Internal Intra-Scene Dynamic Range: 59dB

• Supply Voltage: +3.3V

• Operating Temperature: -5°C to +60°C

• Output: 10-bit digital through 10 parallel ports

•Conversion Gain = 13µV/e-

• Color: Monochrome or color RGB

• Shutter: TrueSNAP freeze-frame electronic shutter

• Shutter Efficiency: >99.9%

•Shutter Exposure Time: 2µs to > 33 msec

• ADC: On-chip, 10-bit column-parallel

• Package: 280-pin ceramic PGA

• Programmable Controls: Open architecture

On-chip:

•ADC controls

•Output multiplexing

•ADC calibration

Off-chip:

•Window size and location

•Frame rate and data rate

•Shutter exposure time (integration time)

•ADC reference

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

General

The MI-MV13 is a 1280H x 1024V (1.31 megapixel)

CMOS digital image sensor capable of 500 frames-per-

second (fps) operation. Its TrueSNAP™ electronic

shutter allows simultaneous exposure of the entire

pixel array. Available in color or monochrome, the sen-

sor has on-chip 10-bit analog-to-digital converters

(ADCs), which are self-calibrating, and a fully digital

interface. The chip’s input clock rate is 66 MHz at

approximately 500 fps, providing compatibility with

many off-the-shelf interface components as shown in

Figure 1.

The sensor has ten (10) 10-bit-wide digital output

ports. Its open architecture design provides access to

internal operations. ADC timing and pixel-read control

are integrated on-chip. At 60 fps, the sensor dissipates

less than 150 mW, and at 500 fps less than 500 mW; it

operates on a 3.3V supply. Pixel size is 12 microns

square and digital responsivity is 1600 bits per lux-sec-

ond.

The MI-MV13 CMOS image sensor has an open

architecture to provide access to its internal opera-

tions. A complete camera system can be built by using

the chip in conjunction with the following external

devices:

• An FPGA/CPLD/ASIC controller, to manage the

timing signals needed for sensor operation.

• A 20mm diagonal lens.

• Biasing circuits and bypass capacitors.

Figure 1: A Camera System Using the MI-MV13 CMOS Image Sensor

Controller

(FPGA, CPLD, ASIC, etc.)

System

Clock

System

Interface

Off-Chip

ADC

Pixel Array

(1280H x 1024V)

ADC Bias

+3.3V

System

Clock

Control

Timing

Port 1 D0~D9

Port 2 D10~D19

Port 3 D20~D29

Port 4 D30~D39

Port 5 D40~D49

Port 6 D50~D59

Port 7 D60~D69

Port 8 D70~D79

Port 9 D80~D89

Port 10 D90~D99

Memory

On-Chip Control

On-Chip

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 2: Sensor Architecture (not to scale)

Figure 3: Signal Path Diagram

BOTTOM ADCs

TOP ADCs

PIXEL ARRAY

MEMORY

SENSE AMPS

DIGITAL

CONTROL

Photo

Detector

Pixel

Memory

Sample

& Hold ADC

Per Column Processing

Pixel

DAC

ADC

Calibration

Offset

(VREF3-VCLAMP3)/20

BIAS

VLN2

ADC

registers

Bias

VLN1 Bias

VLP

VREF1 VREF4

VREF2

∑∑

Buffer

VRST_PIX

PG_N

TX_N

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

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Figure 4: Functional Block Diagram

PIXEL ARRAY

Row Driver

Row Decoder

ROW

Row

Timing

Block

LogicRST

RowSTRT

RowDone

1280 x 10 SRAM

ADC Register

Sample

Data Shift /

Read 1280 x 10 SRAM

Output Register

Column Decoder

S/H

ADC

#1280

...

SRAM

Read

Control

10 x 10

Shift

Sense Amps

TX_N

PG_N

Output Ports

Pads

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

External Control Sequence

The MI-MV13 includes on-chip timing and control

circuitry to control most of the pixel, ADC, and output

multiplexing operations. However, the sensor still

requires a controller (FPGA, CPLD, ASIC, etc.) to guide

it through the full sequence of its operation.

With the TrueSNAP freeze-frame electronic shutter

signal charges are integrated in all pixels in parallel.

The charges are then sampled into pixel analog memo-

ries (one memory per pixel) and subsequently, row by

row, are digitized and read out of the sensor. The inte-

gration of photosignal is controlled by two control sig-

nals: PG_N and TX_N. To clear pixels and start new

integration, PG_N is made low. To transfer the data

into pixel memory, TX_N is made low. The time differ-

ence between the two procedures is the exposure time.

It should be noted that neither the PG_N or TX_N

pulses clear the pixel analog memory. Pixel memory

can be cleared during the previous readout (i.e., the

readout process resets the pixel analog memory), or by

applying PG_N and TX_N together (i.e., clearing both

pixel and pixel memory at the same time).

With the TrueSNAP freeze-frame electronic shutter

the sensor can operate in either simultaneous or

sequential mode in which it generates continuous

video output. In simultaneous mode, as a series of

frames are being captured, the PG_N and TX_N signals

are exercised while the previous frame is being read

out of the sensor. In simultaneous mode typically the

end of integration occurs in the last row of the frame

(row #1023) or in the last row of the window of interest.

The position of the start integration is then calculated

from the desired integration time. In sequential mode

the PG_N and TX_N signals are exercised to control the

integration time, and then digitization and readout of

the frame takes place. Alternatively, the sensor can run

in single frame or snapshot mode in which one image

is captured.

The sensor has a column-parallel ADC architecture

that allows the array of 1,280 analog-to-digital convert-

ers on the chip to digitize simultaneously the analog

data from an entire pixel row. The following input sig-

nals are utilized to control the conversion and readout

process:

The 10-bit ROW_ADDR (row address) input bus

selects the pixel row to be read for each readout cycle.

The ROW_STRT_N signal starts the process of reading

the analog data from the pixel row, the analog-to-digi-

tal conversion, and the storage of the digital values in

the ADC registers. When these actions are completed,

the sensor sends a response back to the system con-

troller using the ROW_DONE_N. Row address must be

valid for the first half of the row processing time (the

period between ROW_START_N and ROW_DONE_N).

The MI-MV13 contains a pipeline style memory

array, which is used to store the data after digitization.

This memory also allows the data from the previous

row conversion cycle to be read while a new conver-

sion is taking place.

The digital readout is controlled by lowering the

LD_SHFT_N signal, followed by the

DATA_READ_EN_N signal. LD_SHFT_N transfers the

digitized data from the ADC register to the output reg-

ister. DATA_READ_EN_N is used to enable the data

output from the output register. A new pixel row read-

out and conversion cycle can be started two clock

cycles after DATA_READ_EN_N is pulled low. The out-

put register allows the reading of the digital data from

the previous row to be performed at the same time as a

new conversion (pipeline mode). This means that the

total row time will be only that between when: (a) the

ROW_STRT_N signal is applied and ROW_DONE_N is

returned; and (b) LD_SHFT_N and DATA_READ_EN_N

are applied plus two clock cycles. The pipelined opera-

tion means there will always be 1 row of latency at the

start of sensor operation. The alternative to pipelined

operation is burst data operation in which a new pixel

row conversion is not initiated until after the output

high). The ratio of line active and blanking times can

be adjusted to easily match a variety of display and

collection formats. See “Timing Diagram For One

Row” on page 7.

Table 1: Conversion and Readout

Process

SIGNAL NAME DESCRIPTION

INPUT BUS

WIDTH

ROW_ADDR Row Address 10-bit

ROW_STRT_N Row Start 1-bit

LD_SHFT_N Load shift register 1-bit

DATA_READ_EN_N Data read enable 1-bit

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 5: Example 1 - Row 4 of the MI-MV13 Being Digitized

PG_N and TX_N

To start integration, the PG_N signal simultaneously

resets the photodetectors for the entire pixel array. To

end integration, the TX_N signal simultaneously trans-

fers charge from photodetector to memory inside each

pixel for the entire pixel array. In sequential mode the

PG_N and the TX_N pulses must have a minimum

duration of 64 SYSCLK cycles. In simultaneous mode

the PG_N and TX_N pulses must have a duration of 64

SYSCLK cycles and be applied in the window between

the 66th and 129th SYSCLK cycles. Additionally, in

simultaneous mode between exposures a single

SYSCLK duration pulse must be applied each row dur-

ing the 130th clock cycle.

ROW_ADDR

The address for the pixel row to be read is input

externally via this 10-bit input bus. Must be valid for at

least 66 SYSCLK cycles, must be valid when

ROW_STRT_N is pulled low.

ROW_STRT_N

This signal reads the contents of the pixel row speci-

fied by ROW_ADDR, converts the pixel row signal to

digital value, and stores the digital value in ADC regis-

ter (1280 x 10-bit).

This process is completed in 128-1291 SYSCLK

cycles. Must be valid for a minimum of two clock

cycles and a maximum of 100 clock cycles.

ROW_DONE_N

128-1291 SYSCLK cycles after ROW_STRT_N has

been pulled low the sensor acknowledges the comple-

tion of a row read operation/digitization by sending

out a low going pulse on this pin. Valid for two clock

cycles.

PIXEL ARRAY

Even

Columns

Odd

Columns

SYSCLK

Column Parallel 10 -bit

ADC 640 x 1

Column Parallel 10 -bit

ADC 640 x 1

Control

Logic/

Decoders

ADC

Controls

ADC

Controls

ROW_STRT_N

ROW_ADDR

1. Reads the contents of pixel row specified by ROW_ADDR

2. Converts pixel row signals to digital values

3. Stores digital values in ADC register (1280 x 10 bit)

Controller

ROW 4

PIXEL ARRAY

Even

Columns

Odd

Columns

SYSCLK

Column Parallel 10 -bit

ADC 640 x 1

Column Parallel 10 -bit

ADC 640 x 1

Control

Logic/

Decoders

ADC

Controls

ADC

Controls

ROW_STRT_N

ROW_ADDR

LD_SHFT_N

1. Reads the contents of pixel row specified by ROW_ADDR

2. Converts pixel row signals to digital values

3. Stores digital values in ADC register (1280 x 10 bit)

Controller

ROW 4

1. In order to minimize the sensor power con-

sumption, the row processing circuitry

operates at SYSCLK/2. Therefore, depend-

ing on the user’s implementation, there will

be either 128 or 129 SYSCLK cycles between

the start of ROW_STRT_N and

ROW_DONE_N.

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

LD_SHFT_N

This signal transfers the digitized data from the ADC

the power to the sense amplifiers. The first data (col-

umns 1-10) are available for output at the third rising

edge of SYSCLK after LD_SHFT_N is pulled low. May

be enabled simultaneously with or after the falling

edge of ROW_DONE_N. Must remain low the entire

time the data is being read out.

DATA_READ_EN_N

This signal is used to enable the data output from

the output register (1280 x 10-bit) to the ten, 10-bit

output ports. May be initiated simultaneously with or

after LD_SHFT_N is selected. Minimum width is one

clock cycle. Output Register

The use of an output register allows the processing

of a row to be performed while the digital data from

the previous operation is being read out of the sensor.

A new pixel readout and conversion cycle can be

started two clock cycles after DATA_READ_EN_N is

pulled low.

Figure 6: Timing Diagram For One Row

Table 2: Pixel Array

CLK 1 CLK 2 …CLK128

Port 1 Col. 1 Col. 11 … Col. 1271

Port 2 Col. 2 Col. 12 … Col. 1272

Port 3 Col. 3 Col. 13 … Col. 1273

Port 4 Col. 4 Col. 14 … Col. 1274

Port 5 Col. 5 Col. 15 … Col. 1275

Port 6 Col. 6 Col. 16 … Col. 1276

Port 7 Col. 7 Col. 17 … Col. 1277

Port 8 Col. 8 Col. 18 … Col. 1278

Port 9 Col. 9 Col. 19 … Col. 1279

Port 10 Col. 10 Col. 20 … Col. 1280

ROW_ADDR [0:9]

0 1 129 13167

ROW VA LI D XXXXXX

ROW_STRT_N

SYSCLK

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

DATA [0:99] 0 1 2 3 4 5 127

PG2

PG1

TX_N

1-3 nsec SKEW

66 130

2 0

PG_N

ROW_ADDR [0:9]

0 1 129 13167

ROW VA LI D XXXXXX

ROW_STRT_N

SYSCLK

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

DATA [0:99] 0 1 2 3 4 5 127

PG2

PG1

TX_N

1-3 nsec

66 130

2 0

PG_N

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 7: Frame Timing

The MI-MV13 contains special self-calibrating cir-

cuitry that enables it to reduce its own column-wise

fixed-pattern noise. This calibration process consists

of connecting a calibration signal (VREF2) to each of

the ADC inputs, and estimating and storing these off-

sets (7 bits) to subtract from subsequent samples. The

Typical I/O Signal Timing (Initialization Sequence)

diagram (Figure 8) shows the timing sequence to cali-

brate the sensor. Calibration occurs automatically after

logic reset (LRST_N) but it can also be started by the

user, by pulling CAL_STRT_N low. When calibration is

finished, the sensor generates the active low

CAL_DONE_N. Significant ambient temperature drift

may justify recalibration. See Figure 7 and Figure 8.

ROW_ST RT_N

ROW_DONE_N

LD_SHFT_N

DATA_READ_EN_N

1023

ROW_ADDR [0:9]

DATA [0:99]

1022

ROW1023

ROW1022

ROW1021

ROW0

ROW1

ROW1023

1023

N+1

ROW N-1

ROW N

PG_N=PG1+PG2

PG2

PG1

EXPOSURE TIM E (= 1023 –N rows)

TX_ N

READOUT (one full frame)

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 8: Typical I/O Signal Timing (Initialization Sequence)

CAL_STRT_N

CAL_STRT_N is a two-clock cycle-wide active-low

pulse that initiates the ADC calibration sequence. The

pulse must not be actuated for 1 microsecond after

either power-up or removal of the sensor from a

power-down state. Users may find it easiest to cali-

brate by means of the logic reset.

CAL_DONE_N

CAL_DONE_N is a two-clock cycle-wide active-low

output pulse that is asserted when the ADC calibration

is complete. The device will automatically initiate a

calibration sequence upon a logic reset. Completion of

this sequence, in cases where it is initiated by a reset, is

still with the CAL_DONE_N signal. This process is

complete within 112 SYSCLK cycles of CAL_STRT_N.

This process is complete within 112 SYSCLK cycles of

LRST_N.

LRST_N

LRST_N is a two-clock cycle-wide active-low pulse

that resets the digital logic. It puts all logic into a

known state (all flip-flops are reset). This signal also

initiates an ADC calibration sequence.

CAL_DONE_N

CAL_STRT_N

SYSCLK

CAL_DONE_N

LRST_N

SYSCLK

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Electronic Shutter

The MI-MV13 is intended to be operated primarily

with the TrueSNAP freeze-frame electronic shutter, but

is also capable of operating in Electronic Rolling Shut-

ter (ERS) mode. With TrueSNAP the shutter can be

operated to generate continuous video output (simul-

taneous mode or sequential mode) or capture single

images (single frame mode).

When considering timing for the various shutter

modes it is useful to keep in mind the functionality of

PG_N and TX_N. When PG_N is low, the photodetector

is shorted to a reset voltage source. When high, the

switch is open. When TX_N is low, the photodetector is

shorted to pixel memory. When high, they are discon-

nected. Please refer to the switches shown in the Signal

Path Diagram, Figure 3 on page 3. The memory is also

reset during readout. It occurs for the selected row in

the middle of the 0-66 clock interval after application

of ROW_STRT_N (approximately clocks 20 through

40).

TrueSNAP Simultaneous Mode

In simultaneous mode, as a series of frames are

being captured, the PG_N and TX_N signals are exer-

cised while the previous frame is being read out of the

sensor. In simultaneous mode typically the “end of

integration” occurs in the last row of the frame (row

#1023) or in the last row of the window of interest. The

position of the “start integration” is then calculated

from the desired integration time. Please note that

pixel memory is cleared during readout process

(Figure 9).

Figure 9: Typical Example of TrueSNAP

Simultaneous Mode: Exposure During

Readout

TrueSNAP Sequential Mode

In sequential mode the PG_N and TX_N signals are

exercised to control the integration time, and then dig-

itization and readout of the frame takes place. Please

note that pixel memory is cleared during readout pro-

cess. The photodetector is reset when PG_N is low.

Raising PG_N starts integration and lowering TX_N

while PG_N is still high ends integration by sampling

the signal into memory. There must be at least one

SYSCLK cycle after returning TX_N to the high state

until PG_N is lowered (Figure 10 on page 11).

Read row#0

Read row#1023

Exposure

time

Read row# 0

Read row#1023

Readout Time

ROW_ADDR

1023

PG_N

TX_N

Readout

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 10:

Typical Example of TrueSNAP

Sequential Mode: Exposure Following

Readout

TrueSNAP Single Frame

The MI-MV13 can run in single frame or snap-shot

mode in which one image is captured. In single frame

mode integration must be preceded with a void frame

read (selecting all addresses and applying

ROW_STRT_N) or PG_N and TX_N must be applied

together (for a minimum of 10 SYSCLK cycles) to clear

pixel and pixel memory. Holding PG_N and TX_N low

resets the photodioide (PG_N) and the analog memory

which is shorted to the photodiode by the TX_N

switch. To start integration both TX_N and PG_N are

released. To end integration and sample the signal into

memory TX_N is made low again for 10 clocks mini-

mum, up to 64 clocks (see Figure 6 on page 7). After

TX_N is returned to the high state there must be a

delay of >1 SYSCLK prior to lowering PG_N again to

erase charge in the photodetector.

Figure 11:

Typical Example of TrueSNAP Single

Frame Mode

ERS Mode

This mode is enabled by pulling PG_N high and

TX_N low.

Partial Scan Examples

The MI-MV13 can be partially scanned by sub-sam-

pling rows. The user may select which rows and how

many rows to include in a partial scan. For example,

with a 66-megahertz clock, a row time is approxi-

mately 2 microseconds, resulting in the following pos-

sibilities:

1 row in frame: 500,000 frames per second

2 rows in frame: 250,000 frames per second

10 rows in frame: 50,000 frames per second

100 rows in frame: 5,000 frames per second

256 rows in frame: 2,000 frames per second

512 rows in frame: 1,000 frames per second

1,024 rows in frame: 500 frames per second ...etc

Read row#0

Read row#1023

Readout Time

ROW_ADDR

1023

PG_N

TX_N

Read row#0

Read row#1023

Readout

Exposure

time

Exposure

time

TIME

ROW_ADDR

1023

PG_N

TX_N

READ ROW #0

EAD ROW #1023

EXPOSURE TIME

READOUT

“SLEEP” STATE “SLEEP” STATE

TIME

ROW_ADDR

1023

PG_N

TX_N

READ ROW #0

EAD ROW #1023

EXPOSURE TIME

READOUT

“SLEEP” STATE “SLEEP” STATE

Table 3: Pin Description

PIN NUMBER(S) SIGNAL NAME FUNCTION

DATA [99:0] Pixel data output bus that is ten pixels (100 bits) wide.

Bit 0 is the LSB (least significant bit) of the lowest order

pixel (See Table 2, Pixel Array, on page 7). In the group of ten pixels

being output, bit 9 is the MSB (most significant bit).

T13 DATA0

U14 DATA1

V15 DATA2

T14 DATA3

V16 DATA4

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

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T15 DATA5

U16 DATA6

R14 DATA7

V18 DATA8

P15 DATA9

D14 DATA10

A16 DATA11

C16 DATA12

E13 DATA13

D15 DATA14

A18 DATA15

E14 DATA16

B18 DATA17

D17 DATA18

E16 DATA19

W11 DATA20

U10 DATA21

V11 DATA22

R11 DATA23

V12 DATA24

W13 DATA25

U12 DATA26

V13 DATA27

R12 DATA28

V14 DATA29

B11 DATA30

C12 DATA31

A12 DATA32

B12 DATA33

E11 DATA34

B13 DATA35

C14 DATA36

D13 DATA37

E12 DATA38

C15 DATA39

U6 DATA40

V7 DATA41

T8 DATA42

R9 DATA43

V8 DATA44

U8 DATA45

V9 DATA46

T9 DATA47

V10 DATA48

R10 DATA49

Table 3: Pin Description (Continued)

PIN NUMBER(S) SIGNAL NAME FUNCTION

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

C8 DATA50

A7 DATA51

D9 DATA52

E9 DATA53

A8 DATA54

C10 DATA55

A9 DATA56

D10 DATA57

B10 DATA58

C11 DATA59

T4 DATA60

R6 DATA61

V3 DATA62

W3 DATA63

R7 DATA64

W4 DATA65

T6 DATA66

V5 DATA67

R8 DATA68

V6 DATA69

E6 DATA70

D5 DATA71

C5 DATA72

D6 DATA73

A3 DATA74

C6 DATA75

D7 DATA76

A5 DATA77

E8 DATA78

A6 DATA79

M5 DATA80

P2 DATA81

N3 DATA82

T1 DATA83

P3 DATA84

U1 DATA85

P4 DATA86

T2 DATA87

V1 DATA88

R4 DATA89

H5 DATA90

E3 DATA91

E2 DATA92

D1 DATA93

D3 DATA94

Table 3: Pin Description (Continued)

PIN NUMBER(S) SIGNAL NAME FUNCTION

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

E4 DATA95

C2 DATA96

A1 DATA97

F5 DATA98

B2 DATA99

L3 CAL_DONE_N A two-clock cycle-wide active-low pulse that indicates the ADC has

completed its calibration operation.

L2 CAL_STRT_N Starts the calibration process for the ADC. This is a two- clock cycle-

wide active-low pulse.

F1 DARK_OFF_EN_N A low input enables common mode dark offset to all pixels. The

value of the offset is defined by VREF3 and VCLAMP3. Subtracts a

fixed offset pre-ADC. Signal is pulled up on-chip.

J4, N15, J16 VDD Power supply for core digital circuitry.

H3, H18, T18 DGND Ground for core digital circuitry.

K2 LD_SHFT_N An active-low envelope signal that places the recently converted

row of data into output register for out put, enables the sense amps

and resets the column counter.

J3 DATA_READ_EN_N An active-low envelope signal that enables the column counter and

causes the ten 10-bit output ports to be updated with data on the

rising edge of the system clock. Column counter skips data when

this input is high.

L1 LRST_N Global logic reset function (asynchronous). Active-low pulse.

ROW_ADDR [9:0] 10-bit bus (0 to 1023, bottom to top) that controls which pixel row is

being processed or read out. An asychronous (unclocked) digital

input. Bit 9 is the MSB.

G18 ROW_ADDR0

H16 ROW_ADDR1

H15 ROW_ADDR2

F18 ROW_ADDR3

G17 ROW_ADDR4

F17 ROW_ADDR5

E18 ROW_ADDR6

G15 ROW_ADDR7

F16 ROW_ADDR8

D18 ROW_ADDR9

L5 ROW_DONE_N A two-cycle-wide pulse that indicates that processing of the

currently addressed row has been completed.

K4 ROW_STRT_N Starts ADC conversion of the pixel row (defined by the row address)

content. A two-clock cycle-wide active-low pulse.

H2 STANDBY_N A low input sets the sensor in a low power mode. (Allow 1

microsecond before calibrating, after coming out of this mode).

Signal is pulled up on-chip.

J5 PIXEL_CLK_OUT Data synchronous output. User may prefer to use this pin as data

clock instead of SYSCLK.

G3 SYSCLK Clock input for entire chip. Maximum design frequency is 66 MHz

(50%, ±5%, duty cycle).

Table 3: Pin Description (Continued)

PIN NUMBER(S) SIGNAL NAME FUNCTION

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

G16, E10, C13, B4,

B8, C7, F4, M2,

B14,

F15, R13, T12, B1,

H4, N4, R3, T5, U5,

W7, U9, U11, T16,

B16

VDD_IO Power supply for digital pad ring.

G5, D4, G4, K3,

N5, P5, U4, T7,

T10, U7, U13 K5,

B15, B17, H17,

D12, D11, E17, C9,

D8 M4, T11,U18,

B5,U15

DGND_IO Digital ground for pad ring.

R18, P18, K18,J18 VAA Power supply for analog processing circuitry (column buffers, ADC,

and support).

T17, N16, L17,

K17, J15, R17

AGND Ground for analog signal processing circuitry.

L15 VLN1 Bias setting for pixel source follower operating current. Impedance:

3kΩ, 10pF. Decoupling capacitors recommended.

M18 VLN2 The bias setting for the ADC is generated on-chip. A decoupling

capacitor to ground is recommended. External biasing may be

preferable to optimize performance. Impedance: 3kΩ, 10pF.

N17 VLP Bias setting voltage for the column source follower operating

current. Impedance: 3kΩ, 10pF. Decoupling capacitor recommended.

K16, M15 VREF1 ADC reference input voltage that sets the maximum input signal

level (defines the level where the FF code occurs) and thus sets the

size of the least significant bit (LSB) in the analog to digital

conversion process. A smaller VREF1 produces a smaller LSB, which

means a smaller analog signal level input is required to produce the

same digital code out. Likewise, a larger VREF1 produces a larger

LSB, which means a larger analog signal level input is required to

produce the same digital code out. Thus the reference value can be

used like a global gain adjustment (halving this voltage doubles the

gain). This signal has two pin connections to minimize internal

losses during high-speed operation. User voltage source must supply

a transient current of 100mA at a frequency of 500 kHz with a 2%

duty cycle. Decoupling capacitors to AGND of ~1µF (ceramic) and

100µF (electrolytic) placed as close to the package pins as possible

are usually sufficient to filter out this required current transient.

P17 VREF2 ADC reference used for the calibration operation. User voltage

source must supply a transient current of 20mA at a frequency of

500 kHz with a 2% duty cycle. A ceramic decoupling capacitor to

AGND of ~0.1µF is usually sufficient to filter out this required

current transient.

M16 VREF3 Dark offset cancellation positive input reference, tied to the

pedestal voltage to be added to the signal.

K15 VCLAMP3 Dark offset cancellation negative input reference. User voltage

source must supply a transient current of 40mA at a frequency of

500 kHz with a 2% duty cycle. A ceramic decoupling capacitor to

AGND of ~0.1µF to 1µF is usually sufficient to filter out this required

current transient.

Table 3: Pin Description (Continued)

PIN NUMBER(S) SIGNAL NAME FUNCTION

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

R16 VLP_DRV Should be connected to AGND.

L4 TX_N This is an active low pulse that controls transfer of charge from

photodetector to memory inside each pixel for entire pixel array.

M3 PG_N This is an active low pulse that resets the photodetectors and

thereby starts new integration cycle.

L18, P16, J17 VRST_PIX Power supply for pixel array. There is no noticeable dc power

consumption by this pin (<100µA). User voltage source must supply

a transient current of 10mA at a frequency of 500 kHz, once a

frame. Decoupling capacitors to AGND ~1µF (ceramic) and 100µF

(electrolytic) are usually sufficient to filter out this required current

transient.

L16 VREF4 ADC reference input value should be 1/4 VREF1. User voltage source

must supply a transient current of 100mA at a frequency of 500 kHz

with a 2% duty cycle. A ceramic decoupling capacitor to AGND of

~0.1µF is usually sufficient to filter out this required current

transient.

E5,C3,C1, D2,

E1,F2, F3, G1, H1,

J2, J1, K1, M1, N1,

N2, P1,R1, R2, T3,

U2, R5, U3, V2,

W2, W1, V4, W5,

W6, W8, W9,

W10,W12, W14,

W15, W17, W18,

V17, R15, U17,

V19, W19, U19,

T19, R19, P19,

N18, N19, M19,

M17, L19, K19,

J19, H19, G19,

F19, E19, D19,

C19, B19, C18,

E15, C17, D16,

A19, A17, A15,

A14, A13, A11,

A10, B9, B7, B6,

A4, E7, A2, C4, B3,

W16, G2

No connect.

Table 3: Pin Description (Continued)

PIN NUMBER(S) SIGNAL NAME FUNCTION

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 12: Board Connections

NOTE:

1. It is recommended that 0.01µF and 0.1µF capacitors be placed as physically close as possible to the MI-MV13's package.

2. Alternatively, the analog voltages depicted as being generated from potentiometers could be supplied from DACs.

3. The analog voltages VLN1, VLN2, VLP, and VREF4 are generated on-chip, but user may supply voltages to override the internal biases.

nalog ground

Digital Ground

DATA0 T13

DATA1 U14

DATA2 V15

DATA3 T14

DATA4 V16

DATA5 T15

DATA6 U16

DATA7 R14

DATA8 V18

DATA9 P15

DATA10 D14

DATA11 A16

DATA12 C16

DATA13 E13

DATA14 D15

DATA15 A18

DATA16 E14

DATA17 B18

DATA18 D17

DATA19 E16

DATA20 W11

DATA21 U10

DATA22 V11

DATA23 R11

DATA24 V12

DATA25 W13

DATA26 U12

DATA27 V13

DATA28 R12

DATA29 V14

DATA30 B11

DATA31 C12

DATA32 A12

DATA33 B12

DATA34 E11

DATA35 B13

DATA36 C14

DATA37 D13

DATA38 E12

DATA39 C15

DATA40 U6

DATA41 V7

DATA42 T8

DATA43 R9

DATA44 V8

DATA45 U8

DATA46 V9

DATA47 T9

DATA48 V10

DATA49 R10

DATA50 C8

DATA51 A7

DATA52 D9

DATA53 E9

DATA54 A8

DATA55 C10

DATA56 A9

DATA57 D10

DATA58 B10

DATA59 C11

DATA60 T4

DATA61 R6

DATA62 V3

DATA63 W3

DATA64 R7

DATA65 W4

DATA66 T6

DATA67 V5

DATA68 R8

DATA69 V6

DATA70 E6

DATA71 D5

DATA72 C5

DATA73 D6

DATA74 A3

DATA75 C6

DATA76 D7

DATA77 A5

DATA78 E8

DATA79 A6

DATA80 M5

DATA81 P2

DATA82 N3

DATA83 T1

DATA84 P3

DATA85 U1

DATA86 P4

DATA87 T2

DATA88 V1

DATA89 R4

DATA90 H5

DATA91 E3

DATA92 E2

DATA93 D1

DATA94 D3

DATA95 E4

DATA96 C2

DATA97 A1

DATA98 F5

DATA99 B2

Pixel

Data

Output

G18 ROWADDR0

H16 ROWADDR1

H15 ROWADDR2

F18 ROWADDR3

G17 ROWADDR4

F17 ROWADDR5

E18 ROWADDR6

G15 ROWADDR7

F16 ROWADDR8

D18 ROWADDR9

G3 SYSCLK

J3 DATA_READ_EN_N

K2 LD_SHFT_N

L3 CAL_DONE_N

L5 ROW_DONE_N

L2 CAL_STRT_N

K4 ROW_STRT_N

F1 DARK_OFF_EN_N

H2 STANDBY_N

L1 LRST_N

M3 PG_N

L4 TX

J5 PIXEL_CLK_OUT

VCLAMP3

VLN1

VLP

VREF1

VREF2

VLN2

VLP_DRV

VRST_PIX

VREF4

VREF3

1kΩ

nalog +3.3V

0.1µ

10µ

1kΩ

nalog +3.3V

0.1µ

10µ

1kΩ

nalog +3.3V

1µ

0.01µ

1kΩ

nalog +3.3V

0.1µ

10µ

1kΩ

nalog +3.3V

0.1µ

10µ

0.1µ

F10µ

nalog +3.3V

Digital 3.3V

DGND_IO

T10

DGND_IO

U13

DGND_IO

U15

DGND_IO

B15

DGND_IO

B17

DGND_IO

H17

DGNC_IO

D12

DGND_IO

D11

DGND_IO

T11

DGND_IO

U18

DGND_IO

E17

DGND_IO

DGND

H18

DGND

T18

DGND

T17

AGND

N16

AGND

K17

AGND

R17

AGND

L17

AGND

J15

AGND

nalo

Ground

Digital Ground

____

_______

____

_______

____

_______

____

_______

____

_______

____

_____

____

R18

P18

K18

J18

N15

J16

B14

F15

R13

T12

U11

T16

G16

B16

E10

C13

VAA

VDD

VDD_IO

Controller

Interface

1µ

100µ

nalog +3.3V

0.1µ

10µ

1kΩ

01µ

0.01µ

100µ

0.01µ

10µ

0.1µ

F0.01

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Electrical Specifications

Table 4: AC Electrical Characteristics

(Vsupply = 3.3V ± 0.3V)

SYMBOL CHARACTERISTIC CONDITION MIN. TYP. MAX. UNIT

Tplh Data output propagation

delay for low to high trans.

123ns

Tphl Data output propagation delay

for high to low trans.

123ns

Tsetup Setup time for input to SYSCLK Vin = Vpwr or

Vgnd

34 ns

Thold Hold time for input to SYSCLK Vpwr=Min,VOH

min

34 ns

Table 5: DC Electrical Characteristics

(Vsupply = 3.3V ± 0.3V)

SYMBOL CHARACTERISTIC CONDITION MIN. TYP. MAX. UNIT

VLP Bias for Column Buffers 0.5 1.9 2.7 V

VREF1 Reference for ADC 0.2 1.0 1.5 V

VREF2 Reference for ADC Calibration 0.3 0.8 1.5 V

VREF3 Dark offset 0 0.6 2.5 V

VLN1 Bias for pixel source follower 0.8 1.0 1.1 V

VLN2 Bias for ADC 0.8 1.0 1.1 V

VCLAMP3 Dark offset 0 0 3.0 V

VLP_DRV Row driver control Grounded 0 0 0 V

VRST_PIX Pixel Array Power 2.2 2.7 2.9 V

VREF4 Reference for ADC 0.25 V

VIH Input High Voltage 2.0 Vpwr+0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIN Input Leakage Current, No

Pullup Resistor

Vin = Vpwr or Vgnd -5 5 µA

VOH Output High Voltage Vpwr=Min, IOH=-

100µA

Vpwr-0.2 V

VOL Output Low Voltage Vpwr=Min,

IOL=100µA

0.2 V

Ipwr1Maximum

Supply Current

66 MHz clock,

5pF load on outputs

165 mA

NOTE:

1. Ipwr = I (VDD_IO) + I (VDD) + I (VAA)

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

Vpwr = VDD = VAA = VDD_IO (VDD is supply to digital circuit, VAA to analog circuit). Vgnd = DGND = AGND (DGND is the

ground to the digital circuit, AGND to the analog circuit).

NOTE:

This device contains circuitry to protect the inputs against damage from high static voltages or electric fields, but the

user is advised to take precautions to avoid the application of any voltage higher than the maximum rated.

Table 6: Absolute Maximum Ratings

SYMBOL PARAMETER VALUE UNIT

Vpwr DC Supply Voltage -0.5 to 3.6 V

Vin DC Input Voltage -0.5 to Vpwr + 0.5 V

Vout DC Output Voltage -0.5 to Vpwr + 0.5 V

I DC Current Drain per Pin (Any I/O) ±50 mA

I DC Current Drain, Vpwr and Vgnd ±100 mA

Table 7: Recommended Operating Conditions

SYMBOL PARAMETER MIN. MAX. UNIT

Vpower DC Supply Voltage 3.00 3.6 V

TACommercial Operating Temperature -5 60 °C

Table 8: Power Dissipation

(Vpwr = 3.3V; TA = 25°C @500 fps)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Pavg Average Power 250 350 500 mW

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Analog Voltage Setting Considerations

The values suggested in the Typical Values column

in the “AC Electrical Characteristics” on page 18 should

be the starting point for setting the analog voltages.

Additionally, it is useful to refer to the “Signal Path Dia-

gram” on page 3 that indicates how the analog voltages

affect the image. Other considerations are as follows:

VREF1 This ADC reference voltage can also be utilized

as a gain. A lower value will increase gain, but also

results in amplification of nonuniformities.

VREF4: Should always be set to ¼ of VREF1.

VREF2 Reference used for the ADC calibration to

remove column-wise FPN. If set much lower than the

typical value there is a possibility that some column

nonuniformities will not be corrected. Setting higher

than typical will result in more column-wise FPN.

When debugging analog voltage settings it may be use-

ful to temporarily set VREF2 to zero, effectively stop-

ping the ADC calibration process and adjusting the

VLN/VLP settings.

VLN1 The on-chip generated voltage should be used

as the starting point; increasing above typical will

result in an increase in current, speed, and FPN in the

first buffer.

VLN2 The on-chip generated voltage should be used

as the starting point. Controls the current in the ADC

comparators (there is a safe range where this voltage

has no effect); above or below this range will cause the

comparators to fail. If vertical white stripes appear in

the center of the imaging area or random white spots

appear in contour areas, it is an indication that VLN2

needs to be adjusted.

VLP The on-chip generated voltage should be used as

the starting point.

VRST_PIX Voltage for pixel reset. If this is too close to

VAA the image will be degraded and is not recom-

mended to be above 2.9V, but if it is set too low the

pixel dynamic range may decrease. In the initial pre-

production version of the MI-MV13 the number of

defects increased with reduced VRST_PIX so it was rec-

ommended to keep this as high as possible. If high

VRST_PIX resulted in vertical FPN it was compensated

via adjustments to VLN1 and VLN2.

VREF3 and VCLAMP3 These control the offset as

shown in the “Signal Path Diagram” on page 3. This

must be enabled via DARK_OFF_EN_N; Offset is ~

(VREF3-VCLAMP3)/20.

Figure 13: Set Up and Hold Time

Figure 14: Clock to Data Propagation

Delay

Tsetup Thold

SYSCLK

INPUT

Tplh, Tphl

SYSCLK

DOUT (99:0)

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 15: Pixel Array Layout

Figure 16: Bayer Pattern (Pixel Color Pattern Detail)

Megapixel

(1280H x 1024V)

1280 x 1024 active

ixels

area of

detail below

(0,0)

(

1023

1279

)

no black rows

B G B G

G G R

B G B G

G G R

R R G G G R

(0,0

)

…

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Optical Specification

Table 9: Image Sensor Characteristics

TA = 25°C

SYMBOL PARAMETER TYP UNIT

RIResponsivity (ADC VREF=1V) 1600 LSB/lux-sec.

Nsat Pixel saturation level 63,000 e-

NADC DC noise + DNL ±2 LSB p-p

DSNU, HF1Dark signal non-uniformity, high spatial frequency <0.4 % rms

DSNU, LF2Dark signal non-uniformity, low spatial frequency <1.5 % p-p

Vdrk Output referred dark signal 50 mV/sec

NE Input referred noise 70 e-

Dyn_I Internal dynamic range 59 dB

PRNU, HF1Photo response non-uniformity, high spatial frequency <0.6 % rms

PRNU, LF2Photo response non-uniformity, low spatial frequency <10 % p-p

Kdrk Dark current temperature coefficient 100 %/8°C

NOTE:

1. Calculation method for high frequency PRNU and DSNU:

For PRNU, uniformly adjust illumination so that the average voltage across a sensor partition is Full Scale/2.

For DSNU, block illumination to sensor. Integration time = 2ms.

Calculate spatially-filtered average using 64 pixel square window.

Calculate r.m.s. difference between pixel values and corresponding filtered average values. Calculate average r.m.s. between

windows.

2. Calculation method for low frequency PRNU and DSNU:

For PRNU, uniformly adjust illumination so that the average voltage across a sensor partition is Full Scale/2.

For DSNU, block illumination to sensor. Integration time = 2ms

Calculate spatially-filtered average using 64 pixel square window

Calculate difference between the center pixel value and corresponding filtered average values.

Report peak to peak values between windows.

Table 10: Pixel Array Specifications

SYMBOL PARAMETER TYP. UNIT

Resolution Number of pixels in active image 1280 x 1024 pixels

Pixel size X-Y dimensions 12 x 12 µm

Pixel pitch Center-to-center pixel spacing 12 µm

Pixel fill factor Area of drawn active area 40 %

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 17: Quantum Efficiency

Quantum Effficiency for Color

400 500 600 700 800 900 1000

Wavelength (nm)

Quantum Efficiency (%

Green 1 pixels Green 2 pixels Blue pixels Red pixels

Quantum Effficiency for Monochrome

400 500 600 700 800 900 1000

Wavelength (nm)

Quantum Efficiency (%

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Lens Selection

Much of the specific information in this section is

explained in detail at http://www.micron.com/prod-

ucts/imaging/technology/index.html on our web site.

The following information applies specifically to the

MI-MV13 megapixel image sensor.

Format

The diagonal of the image sensor array, 19.67mm,

fits most closely, but not exactly, within the optical for-

mat corresponding to the 1-inch specification. Some

1-inch optical format lenses have been shown to work

well with this sensor. Typical 1-inch lens examples are

Computer V2513, V5013, and V7514. F-mount lenses

provide another possible lens solution due to their

large image circle.

Mounting

Several lens mounting standards exist that specify

the threading of the lens' barrel as well as the distance

the back flange of the lens should be from the image

sensor for the lens to properly form an image. Typical

lens mounting standards for the MI-MV13 are:

Another option is to use a C-mount together with a

C-to F-mount adapter for greater lens flexibility.

Field of View and Focal Length

The field of view of an imaging system will depend

on both the focal length of the imaging lens and the

width of the image sensor. As most of the image infor-

mation humans pay attention to generally falls within

a 45-degree horizontal field of view, many camera sys-

tems attempt to imitate this field of view. However, in

some cases a telephoto system (with a narrow field of

view, say less than 20 degrees), or a wide angle system

(with a wide field of view, say more than 60 degrees)

may be desired. The approximate field of view that an

imaging system can achieve is shown in the following

equation:

where θ is the field of view, tan-1 is the trigonometric

function arc-tangent, w is the width of the image sen-

sor, and f is the focal length of the imaging lens. For

example, the imaging system's diagonal field of view

can be determined by using the diagonal of the image

sensor (19.67 mm) for w and a particular lens' focal

length for f. Alternatively, the imaging system's hori-

zontal field of view can be determined by using the

horizontal of the image sensor (15.36 mm) for w and a

particular lens' focal length for f. A lens with an

approximately 50 mm focal length will provide an 18-

degree horizontal field of view with a MI-MV13 (keep

in mind that the above equation is a simplified approx-

imation).

F-Number

The f-number, or f-stop, of an imaging lens is the

ratio of the lens' focal length to its open aperture

diameter. Every doubling in f-number reduces the

light to the sensor by a factor of four. For example, a

lens set at f/1.4 lets in four times more light than that

same lens when it is set at f/2.8. Low f-number lenses

capture a lot of light for delivery to the image sensor,

but also require careful focus. Higher f-number lenses

capture less light for delivery to the image sensor, and

do not require as much effort to bring the imaging sys-

tem to focus. Low f-number lenses generally cost more

than high f-number lenses of similar overall perfor-

mance. Typical f-numbers for various imaging systems

are:

MTF

Modulation Transfer Function (MTF) is a technical

term that quantifies how well a particular system prop-

agates information. For cameras, the “system” is the

Table 11: Lens Mounting Standards

MOUNT MOUNTING

NAME THREADS

BACK-FLANGE-TO-IMAGE-

SENSOR

C 1 - 32 17.526 mm

CS 1 - 32 12.5 mm

Table 12: Typical F-Numbers

F-STOP IMAGING APPLICATION

1.4 Low-light level imaging, manual focus systems

2.0 Typical for PC and other small form cameras

2.8 Common in digital still cameras

4.0+ Often used in machine vision applications

θ2-1 w

-----





tan≈

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

lens and the sensor, and the "information" is the pic-

ture they are capturing. MTF ranges from zero (no

information gets through) to 100 (all information gets

through), and is always specified in terms of informa-

tion density. In most imaging systems, the MTF is lim-

ited by the performance of the imaging lens. A lens

must be able to transfer enough information to the

image sensor to be able to resolve details in the image

that are as small as the pixels in the image sensor. The

pixels are set on a 12-micron pitch (the center of one

pixel is 12 microns from the center of its neighboring

pixel). Thus, a lens used should be able to resolve

image features as small as 12 microns. Typically, a lens'

MTF is plotted as a function of the number of line pairs

per millimeter the lens is attempting to resolve (more

line pairs per millimeter mean higher information

densities). For an electronic imaging system, one line

pair will correspond to two image sensor pixels (each

pixel can resolve one line). This is equated as:

where LP/mm means line pairs per millimeter and z is

the image sensor's pixel pitch, in millimeters. For the

MI-MV13, z = 0.012 mm, such that the MI-MV13 has 42

LP/mm. Thus, a lens should provide an acceptable

level of MTF all the way out to 42 LP/mm. For most

lenses, the MTF will be highest in the center of the

images they form, and gradually drop off toward the

edges of the images they form. As well, MTFs at low

values of LP/mm will generally be larger than MTFs at

high values of LP/mm. One of the many trade-offs that

must be decided by the end user is how high the MTF

needs to be for a particular imaging situation. Gener-

ally, near an image sensor's LP/mm good MTFs are

higher than 40, moderate MTFs are from 20 to 40, and

poor MTFs are less than 20.

Infrared Cut-Off Filters

In most visible imaging situations it is necessary to

include a filter in the imaging path that blocks infrared

(IR) light from reaching the image sensor. This filter is

called an IR cut-off filter. Various forms of IR cut-off fil-

ters are available, some absorptive (like Hoya's CM500

or Schott's BG18) and some reflective (i.e., dielectric

stacks). Infrared light poses a problem to visible imag-

ing because its presence blurs and decreases the MTF

in the images formed by a lens. Since human vision

only extends across a narrow range of the electromag-

netic spectrum, camera systems hoping to capture

images that look like the images our eyes capture must

not capture light outside of our vision range. Silicon-

based light detectors (like the ones in the MI-MV13's

pixels) detect light from the very deep blue to the near

infrared. Thus, a filter must exist in the light's path that

keeps the infrared from reaching the image sensor's

pixels. In most cases, it is important that such a filter

begin blocking light around 650 nm (in the deep red)

and continue blocking it until at least 1100 nm (in the

near IR). In most camera systems, the IR cut-off filter is

included in the imaging lens. However, this point must

be verified by a lens vendor when a particular lens is

chosen for use with an image sensor.

---------1

-----

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 18: C-Mount Lens Shroud for MI-MV13 and Socket

NOTE: This shroud is designed to accommodate the

MI-MV13 when it is inserted into a PGA

socket. These dimensions are based on the

MILL MAX #510-93-281-19-081003 socket

(www.mill-max.com).

2.50

”

0.25” 2.50”

1.25”

0.0

0.25”

0.12

0.125”

0.12

2.50”

0.75”

0.015” Recess

2.50”

1-32 Thread

2.50

”

1.25

BASE

Threaded holes for 4-40 screws (4 places)

LID Holes Dia = 0.12” (for 4-40 screws), 4 places

No thread

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 19: 280-Pin Ceramic PGA Package

Top Vi e w

Notes:

1. Sensor is centered on package, pixel array is off-center.

2. Die offset is±10 mils in both the X and Y directions.

3. Die rotation is±2 degrees.

(1023, 1279)

(0, 0) 19mils

1.067±0.012

0.840±0.009

0.840±0.008

INDEX

0.782

0.743

1.900±0.018

1.343±0.016

1.106±0.012

0.003

ROW

COLUMN

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 20: 280-Pin Ceramic PGA Package

Side View

(0.0235 X 2)

0.047± 0.005

0.039±0.005

NITS: INCHES

otes:

. Die thickness 28.5 mils± 1 mil.

. Die epoxy thickness 1 mil.

. D-263 glass lid thickness 31± 2 mils.

. Glass lid epoxy thickness 1 mil.

Glass Lid

0.118±0.012

0.012± 0.002

0.020± 0.002

0.047±0.005

(4X)

0.018±0.002

(281X)

R0.005

BRAZE

(0.008)

0.150±0.008

0.039± 0.004 0.007

(AT CERAMIC)

Die

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 21: 280-Pin Ceramic PGA Package

Bottom View

1.800±0.012

(P = 0.100 X 18)

Alumina Coat

(281X)

0.067 TYP. DIA.

EXTRA

0.100 typ.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

1.3-MEGAPIXEL CMOS ACTIVE-PIXEL

DIGITAL IMAGE SENSOR

09005aef806807ca Micron Technology, Inc., reserves the right to change products or specifications without notice.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, the Micron logo, and TrueSNAP are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Environmental

Document History

Table 13: Absolute Maximum Ratings

SYMBOL PARAMETER VALUE UNIT

Tstorage Storage Temperature Range -40 to 125 °C

Tlead Lead Temperature (10 second soldering) 235 max. °C

Table 14: Document Change History

CHANGE DATE

CHANGED

BY COMMENTS

Ver. 3.0 Initial release

Ver. 3.0 1/7/04 EJakl 1. Page 1, added additional bullet under Features/Top Level Specifications:

•Conversion Gain = 13µV/e-

2. Page 11, added “for 10 clocks minimum, up to 64 clocks (see Figure 6, page 7)”

line 12 in paragraph titled TrueSNAP Single Frame.

3. Page 15, added “(halving this voltage doubles the gain)” under FUNCTION, for

Pin Numbers K16, M15.

4. Page 20, Updated Figure 13.