HEF4094BT - NXP Semiconductors

1. General description

The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with

each stage for strobing data from the serial input to parallel buffered 3-state outputs

QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is

shifted on positive-going clock transitions. The data in each shift register stage is

transferred to the sto ra g e re gis ter whe n the strobe (STR) input is HIGH. Data in the

storage register appears at the outputs whenever the output enable (OE) signa l is HIGH.

Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B

devices. Serial dat a is available a t QS1 on positive-goi ng clock edges to allow high-speed

operation in cascaded systems with a fast clock rise time. The same serial data is

available at QS2 on the next negative going clock edge. This is used for cascading

HEF4094B devices when the clock has a slow rise time.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +85 C and 40 C to +125 C

Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4094B

8-stage shift-and-store register

Rev. 9 — 16 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4094BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4094BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

HEF4094BTS SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

Product data sheet Rev. 9 — 16 November 2011 2 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

4. Functional diagram

Fig 1. Functional di agram Fig 2. Logic symbol

001aaf119

8-STAGE SHIFT

8-BIT STORAGE

3-STATE OUTPUTS

2QS2 10

QS1

QP0

4 5 6 7 14 13 12 11

QP1 QP2 QP3 QP4 QP5 QP6 QP7

STR

CP STR

QP0

QP1

QP2

QP3

QP4

QP5

QP6

QP7

QS1

QS2

001aaf111

Fig 3. Logic diag ram

001aag799

FF 0

LATCH 0

FF 7

LATCH 7

STAGES 1 TO 6STAGE 0 STAGE 7

QP2

QP0

D QS2

QS1

LATCH

QP1 QP4

QP3 QP6

QP5 QP7

STR

Product data sheet Rev. 9 — 16 November 2011 3 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 4. Pin configuratio n

HEF4094B

STR VDD

DOE

CP QP4

QP0 QP5

QP1 QP6

QP2 QP7

QP3 QS2

VSS QS1

001aae662

Table 2. Pin description

Symbol Pin Description

STR 1 strobe input

D 2 data input

CP 3 clock input

QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output

VSS 8 ground supply voltage

QS1 9 serial ou tp u t

QS2 10 serial output

OE 15 output enable input

VDD 16 supply voltage

Product data sheet Rev. 9 — 16 November 2011 4 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

6. Functional description

[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = positive-going transition;  = negative-going transition;

Z = HIGH-impedance OFF-state; NC = no change;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

Table 3. Function table[1]

Inputs Parallel outputs Serial outputs

CP OE STR DQP0 QPn QS1 QS2

LXXZZQ6SNC

LXXZZNCQ7S

H L X NCNCQ6SNC

HHLLQPn 1Q6S NC

HHHHQPn 1Q6S NC

HHHNCNCNCQ7S

Fig 5. Timing diagram

001aaf117

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

INTERNAL Q6S (FF 6)

OUTPUT QP6

SERIAL OUTPUT QS1

SERIAL OUTPUT QS2

Z-state

Product data sheet Rev. 9 — 16 November 2011 5 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

7. Limiting values

[1] For DIP16 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.

[2] For SO16 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.

8. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping current VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +125 C

Ptot total power dissipation DIP16 [1] - 750 mW

SO16 [2] - 500 mW

P power dissipation per output - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +125 C

t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V

VDD = 10 V - - 0.5 s/V

VDD = 15 V - - 0.08 s/V

Product data sheet Rev. 9 — 16 November 2011 6 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

9. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI=V

SS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 CUnit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 - 4.0 V

VOH HIGH-level

output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

IOH HIGH-level

output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

IOL LOW-level

output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

IOZ OFF-state

output current QPn output

is HIGH;

VO=15V

15 V - 0.4 - 0.4 - 12 - 12 A

IIinput leakage

current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

IDD supply current all valid input

combinations;

IO=0A

5 V - 5 - 5 - 150 - 150 A

10 V - 10 - 10 - 300 - 300 A

15 V - 20 - 20 - 600 - 600 A

CIinput

capacitance ---7.5-- - -pF

Product data sheet Rev. 9 — 16 November 2011 7 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

10. Dynamic characteristics

Table 7. Dynam ic characteristics

VSS = 0 V; Tamb = 25



C; for test circuit see Figure 10; unless otherwise specified.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP to QS1;

see Figure 6 5 V [1] 108 ns + (0.55 ns/pF)CL- 135 270 ns

10 V 54 ns + (0.23 ns/pF)CL- 65 130 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns

CP to QS2;

see Figure 6 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

CP to QPn;

see Figure 6 5 V 138 ns + (0.55 ns/pF)CL- 165 330 ns

10 V 64 ns + (0.23 ns/pF)CL- 75 150 ns

15 V 47 ns + (0.16 ns/pF)CL- 55 110 ns

STR to QPn;

see Figure 7 5 V 83 ns + (0.55 ns/pF)CL- 110 220 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

tPLH LOW to HIGH

propagation delay, CP to QS1;

see Figure 6 5 V [1] 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

CP to QS2;

see Figure 6 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

CP to QPn;

see Figure 6 5 V 123 ns + (0.55 ns/pF)CL- 150 300 ns

10 V 59 ns + (0.23 ns/pF)CL- 70 140 ns

15 V 47 ns + (0.16 ns/pF)CL- 55 110 ns

STR to QPn;

see Figure 7 5 V 73 ns + (0.55 ns/pF)CL- 100 200 ns

10 V 34 ns + (0.23 ns/pF)CL-4590ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

tttransition time 5 V [1] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tPZH OFF-state to HIGH

propagation delay OE to QPn;

see Figure 8 5 V - 40 80 ns

10 V - 25 50 ns

15 V - 20 40 ns

tPZL OFF-state to LOW

propagation delay OE to QPn;

see Figure 8 5 V - 40 80 ns

10 V - 25 50 ns

15 V - 20 40 ns

tPHZ HIGH to OFF-state

propagation delay OE to QPn;

see Figure 8 5 V - 75 150 ns

10 V - 40 80 ns

15 V - 30 60 ns

Product data sheet Rev. 9 — 16 November 2011 8 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas show n (CL in pF).

tPLZ LOW to OFF-state

propagation delay OE to QPn;

see Figure 8 5 V - 80 160 ns

10 V - 40 80 ns

15 V - 30 60 ns

tsu set-up time D to CP;

see Figure 9 5 V 60 30 - ns

10 V 20 10 - ns

15 V 15 5 - ns

thhold time D to CP;

see Figure 9 5 V +5 15 - ns

10 V 20 5 - ns

15 V 20 5 - ns

tWpulse width minimum LOW

clock pulse;

see Figure 6

5 V 60 30 - ns

10 V 30 15 - ns

15 V 24 12 - ns

minimum HIGH

strobe pulse;

see Figure 7

5 V 40 20 - ns

10 V 30 15 - ns

15 V 24 12 - ns

fmax maximum frequency see Figure 6 5 V 5 10 - MHz

10 V 11 22 - MHz

15 V 14 28 - MHz

Table 7. Dynam ic characteristics …continued

VSS = 0 V; Tamb = 25



C; for test circuit see Figure 10; unless otherwise specified.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula for PD (W) where:

PDdynamic power

dissipation 5 V PD = 2100  fi + (fo  CL)  VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

(fo  CL) = sum of the outputs.

10 V PD = 9700  fi + (fo  CL)  VDD2

15 V PD = 26000  fi + (fo  CL)  VDD2

Product data sheet Rev. 9 — 16 November 2011 9 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

11. Waveforms

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 6. Clock to outputs propagation delays, and clock pu lse width and maximum frequency

1/f

max

PHL

PLH

GND

QPn, QS1 output

CP input V

001aaf113

PHL

PLH

QS2 output V

Table 9. Measurement points

Supply voltage Input Output

VDD VMVMVXVY

5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7. Strobe to output propagation delays, and strobe pulse width, set up and hold times

PHL

PLH

GND

QPn output

STR input V

001aaj058

Product data sheet Rev. 9 — 16 November 2011 10 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. 3-state output enable and disable times for OE input

001aai545

tPLZ

tPHZ

outputs

disabled outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input VM

VOL

VOH

GND

tPZL

tPZH

VDD

GND

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 9. Data input dat a se t up a nd hold times

001aaf115

GND

tsu th

tsu

VOH

VOL

QPn, QS1, QS2 output

CP input

D input

Product data sheet Rev. 9 — 16 November 2011 11 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

a. Input waveform

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL= load capacitance including jig and probe capacitance.

RL = load resistance.

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 10. Test circuit

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

001aaj915

VEXT

VDD

VIVO

DUT

Table 10. Test data

Supply voltage Input VEXT Load

VDD VItr, tftPHL, tPLH tPHZ, tPZH tPLZ, tPZL CLRL

5 V to 15 V VSS or VDD  20 ns open VSS VDD 50 pF 1 k 

Product data sheet Rev. 9 — 16 November 2011 12 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

12. Application information

Some examples of applications for the HEF4094B are:

•Serial-to-parallel data conversion

•Remote control holding register

Fig 11. Remote control holding register

001aae666

DIGITALLY CONTROLLED

EQUIPMENT

(REQUIRES CONTINUOUS

DIGITAL CONTROL)

CONTROL

AND

SYNC

CIRCUITRY

data clock

from remote

control panel

HEF4094B

QP0

STR

D QS2

QP7

DIGITALLY CONTROLLED

EQUIPMENT

HEF4094B

QP0

STR

D QS2

QP7

DIGITALLY CONTROLLED

EQUIPMENT

HEF4094B

QP0

STR

DCP

QP7

Product data sheet Rev. 9 — 16 November 2011 13 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

13. Package outline

Fig 12. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 9 — 16 November 2011 14 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

Fig 13. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 9 — 16 November 2011 15 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

Fig 14. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 9 — 16 November 2011 16 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4094B v.9 20111116 Product data sheet - HEF4094B v.8

Modifications: •Table 6: IOH minimu m values changed to maximum

HEF4094B v.8 20100402 Product data sheet - HEF4094B v.7

HEF4094B v.7 20091216 Product data sheet - HEF4094B v.6

HEF4094B v.6 20091103 Product data sheet - HEF4094B v.5

HEF4094B v.5 20090728 Product data sheet - HEF4094B v.4

HEF4094B v.4 20081030 Product data sheet - HEF4094B_CNV v.3

HEF4094B_CNV v.3 19950101 Product specification - HEF4094B_CNV v.2

HEF4094B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 9 — 16 November 2011 17 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

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use of such information.

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with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

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data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those descri bed in the

Product data sheet.

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changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

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therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s app lications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 9 — 16 November 2011 18 of 19

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever cust omer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product cl aims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4094B

8-stage shift-and-store regis te r

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 November 2011

Document iden tifier: HEF4094B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Application information. . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16 Contact information. . . . . . . . . . . . . . . . . . . . . 18

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19