HEF40098BP,652 - NXP SEMICONDUCTORS

1. General description

The HEF40098B is a hex inverting buffer with 3-state outputs. The 3-state outputs are

controlled by two active LOW enable inputs (1OE and 2OE). A HIGH on 1OE causes fo ur

of the six active LOW buffer elements (1Y0 to 1Y3) to assume a high-impedance or

OFF-state regar dless of the other input conditions and a HIGH on 2OE causes the outp uts

of the remaining two buffer elements (2Y0 and 2Y1) to assume a high-impedance or

OFF-state regardle ss of th e ot he r inp ut con ditio n s.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to V SS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +85 C

Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF40098B

Hex inverting buffer; 3-state

Rev. 8 — 21 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF40098BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4

HEF40098BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 21 November 2011 2 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Functional di agram Fig 2. Logic diagram

001aae553

1A0 31Y02

1A1 51Y14

1A2 71Y26

1A3 91Y310

1OE1

2A0 132Y014

2A1 112Y112

2OE15

001aae555

1A0 1Y0

1A1 1Y1

1A2 1Y2

1A3 1Y3 2A1

1OE 2OE

2A0 2Y0

2Y1

Fig 3. Pin configuratio n

HEF40098B

1OE V

1A0 2OE

1Y0 2A0

1A1 2Y0

1Y1 2A1

1A2 2Y1

1Y2 1A3

1Y3

001aae554

Product data sheet Rev. 8 — 21 November 2011 3 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Table 2. Pin description

Symbol Pin Description

1OE 1 output enable input (active LOW)

1A0, 1A1, 1A2, 1A3 2, 4, 6, 10 buffer input

1Y0, 1Y1, 1Y2, 1Y3 3, 5, 7, 9 buffer output (active LOW)

VSS 8 supply voltage

2Y0, 2Y1 13, 11 buffer output (ac ti v e L OW)

2A0, 2A1 14, 12 buffer input

2OE 15 output enable input (active LOW)

VDD 16 supply voltage

Table 3. Function table[1]

Inputs Output

nAn nOE nYn

HLL

LLH

XHZ

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping curre nt VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +85 C

Ptot total power dissipation Tamb = 40 to +85 C

DIP16 package [1] -750mW

SO16 package [2] -500mW

P power dissipation - 100 mW

Product data sheet Rev. 8 — 21 November 2011 4 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +85 C

t/V input transition rise and fall rate VDD = 5 V --3.75ns/V

VDD = 10 V - - 0.5 ns/V

VDD = 15 V --0.08ns/V

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage IO<1A 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage IO<1A 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V - 3.8 - 3.2 - 2.5 mA

VO = 4.6 V 5 V - 1.2 - 1.0 - 0.8 mA

VO = 9.5 V 10 V - 3.8 - 3.2 - 2.5 mA

VO = 13.5 V 15 V - 12.0 - 10.0 - 8.0 mA

IOL LOW-level output current VO = 0.4 V; 4.75 V 3.5 - 2.9 - 2.3 - mA

VO = 0.5 V; 10 V 12.0 - 10.0 - 8.0 - mA

VO = 1.5 V; 15 V 24.0 - 20.0 - 16.0 - mA

IIinput leakage current VI = 0 V or 15 V 15 V - 0.3 - 0.3 - 1.0 A

IDD supply current IO = 0A 5V - 4 - 4 - 30 A

10 V - 8 - 8 - 60 A

15 V - 16 - 16 - 120 A

IOZ OFF-state output current 15 V - 1.6 - 1.6 - 12.0 A

CIinput capacitance - - - 7.5 - - pF

Product data sheet Rev. 8 — 21 November 2011 5 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

10. Dynamic characteristics

[1] The typical value of the propagation delay and transition times are calculated from the extrapolation formula as shown (CL in pF).

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25



C; for test circuit see Figure 6; unless otherwise specified.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay nAntonYn;

see Figure 4 5 V 70 ns + (0.20 ns/pF)CL- 80 160 ns

10 V 31 ns + (0.08 ns/pF)CL-3570ns

15 V 22 ns + (0.06 ns/pF)CL-2550ns

tPLH LOW to HIGH

propagation delay nAntonYn;

see Figure 4 5 V 50 ns + (0.30 ns/pF)CL- 65 130 ns

10 V 24 ns + (0.13 ns/pF)CL-3060ns

15 V 23 ns + (0.05 ns/pF)CL-2550ns

tTHL HIGH to LOW output

transition ti me see Figure 4 5 V 15 ns + (0.30 ns/pF)CL-3060ns

10 V 10 ns + (0.11 ns/pF)CL-1530ns

15 V 7 ns + (0.07 ns/pF)CL-1020ns

tTLH LOW to HIGH output

transition ti me see Figure 4 5 V 10 ns + (0.50 ns/pF)CL-3570ns

10 V 8 ns + (0.24 ns/pF)CL-2040ns

15 V 6 ns + (0.18 ns/pF)CL-1530ns

tPHZ HiGH to OFF-state

propagation delay nOE, to nYn;

see Figure 5 5V - 45 85 ns

10 V - 35 65 ns

15 V - 30 60 ns

tPLZ LOW to OFF-state

propagation delay nOE, to nYn;

see Figure 5 5 V - 65 135 ns

10 V - 40 80 ns

15 V - 35 70 ns

tPZH OFF-state to HIGH

propagation delay nOE, to nYn;

see Figure 5 5 V - 70 140 ns

10 V - 35 75 ns

15 V - 30 65 ns

tPZL OFF-stat e to LOW

propagation delay nOE, to nYn;

see Figure 5 5 V - 90 185 ns

10 V - 40 85 ns

15 V - 35 70 ns

Table 8. Dynamic power dissipation PD

PD can be calculated (in



W) from the formulas shown. VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula for PD (W) where:

PDdynamic power

dissipation 5V P

D = 5000  fi + (fo  CL)  VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

(CL  fo) = sum of the outputs.

10 V PD = 228 00  fi + (fo  CL)  VDD2

15 V PD = 810 00 fi + (fo  CL)  VDD2

Product data sheet Rev. 8 — 21 November 2011 6 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

11. AC waveforms

Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. Input (nAn) to output (nYn) prop a ga tio n de lays

Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.

Fig 5. 3-state enable and disable times

001aai615

input

output

tPLH

tPHL

0 V

VOH

VOL tTLH

tTHL

90 %

10 %

mgu782

PLZ

PHZ

outputs

disabled outputs

enabled

outputs

enabled

nYn output

LOW-to-OFF

OFF-to-LOW

nYn output

HIGH-to-OFF

OFF-to-HIGH

nOE input

GND

PZL

PZH

Table 9. Measur emen t points

Supply voltage Input Output

VDD VMVMVXVY

5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD

Product data sheet Rev. 8 — 21 November 2011 7 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test;

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator;

VEXT = External voltage for measuring switching times.

Fig 6. Test circuitry for switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aae331

EXT

DUT

Table 10. Test data

Supply voltage Input Load VEXT

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

5 V to 15 V VDD  20 ns 50 pF 1 kopen 2VDD GND

Product data sheet Rev. 8 — 21 November 2011 8 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

12. Package outline

Fig 7. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 8 — 21 November 2011 9 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

Fig 8. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 21 November 2011 10 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF40098B v.8 20111121 Product data sheet - HEF40098B v.7

Modifications: •Legal pages updated.

•Changes in “General description” and “Features and benefits”.

•Section “Applications” removed.

HEF40098B v.7 20110914 Product data sheet - HEF40098B v.6

HEF40098B v.6 20090624 Product data sheet - HEF40098B v.5

HEF40098B v.5 20081031 Product data sheet - HEF40098B v.4

HEF40098B v.4 20080731 Product data sheet - HEF40098B_CNV v.3

HEF40098B_CNV v.3 19950101 Product specification - HEF40098B_CNV v.2

HEF40098B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 8 — 21 November 2011 11 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full dat a sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

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Limited warr a nty and liability — Information in this document is believed to

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representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

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Notwithstanding any damages that customer might incur for any reason

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malfunction of an NXP Semiconductors product can reasonably be expected

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NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

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products planned, as well as fo r the planned application and use of

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damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the applica tion or use by customer’s

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testing for th e customer’s applications and products using NXP

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the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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products are sold subject to the general terms and conditions of commercial

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applying the customer’s general terms and conditions with regard to the

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Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 8 — 21 November 2011 12 of 13

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

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liability, damages or failed product cl aims resulting f rom customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specificat ions.

14.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF40098B

Hex inverting buffer; 3-state

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 21 November 2011

Document identifier : HEF40098B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11

14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 Contact information. . . . . . . . . . . . . . . . . . . . . 12

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13