74HC4066D,652 - NXP Semiconductors

1. General description

The 74HC4066; 74HCT406 6 is a hig h-sp eed Si-gate CMOS device and is pin co mpatible

with the HEF4066B. The device is specified in compliance with JEDEC standard no. 7A.

The 74HC4066; 74HCT4066 h as four indepe ndent analog switches. Each switch has two

input/output pins (nY, nZ) and an active HIGH enable input (nE). When nE is low the

corresponding analog switch is turned off.

The 74HC4066; 74HCT4066 is pin compatible with the 74HC4016; 74HCT4016 but

exhibit a much lower ON-resistance. In addition, the ON-resistance is relatively constant

over the full input signal range.

2. Features and benefits

Input levels nE inputs:

For 74HC4066: CMOS level

For 74HCT4066: TTL level

Low ON resistance:

50  (typical) at VCC = 4.5 V

45  (typical) at VCC = 6.0 V

35  (typical) at VCC = 9.0 V

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115 -A ex ce eds 20 0 V

Multiple package options

Specified from 40 Cto +85C and 40 Cto +125C

74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Rev. 6 — 18 July 2012 Product data sheet

Product data sheet Rev. 6 — 18 July 2012 2 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temp erature range Name Description Version

74HC4066N 40 C to +125 C DIP14 plastic dual in-l ine package; 14 leads (300 mil) SOT27-1

74HCT4066N

74HC4066D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

74HCT4066D

74HC4066DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm SOT337-1

74HCT4066DB

74HC4066PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm SOT402-1

74HCT4066PW

74HC4066BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 30.85 mm

SOT762-1

74HCT4066BQ

Fig 1. Logic symbol Fig 2. IEC logic symbol

001aad269

1Y 1Z

2Y 2Z

3Y 3Z

4Y 4Z

11 10

001aad270

13 #

11 10

(a)

12 #

13 1

11 10

(b)

12 #

Product data sheet Rev. 6 — 18 July 2012 3 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 3. Schematic diagram (one sw itc h)

001aad271

GND nZ

VCC VCC

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to VCC.

Fig 4. Pin configuration for DIP14, SO14, SSOP14

and TSSOP14 Fig 5. Pin configuration for DHVQFN14

4066

1Y V

1Z 1E

2Z 4E

2Y 4Y

2E 4Z

3E 3Z

GND 3Y

001aad268

7 8

001aac116

4066

Transparent top view

3E 3Z

2E 4Z

2Y 4Y

2Z 4E

1Z 1E

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

VCC(1)

Table 2. Pin de scription

Symbol Pin Description

1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output

1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output

GND 7 ground (0 V)

1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH)

VCC 14 supply voltage

Product data sheet Rev. 6 — 18 July 2012 4 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level.

7. Limiting values

[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional

switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is

no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 3. Function table[1]

Input nE Switch

LOFF

HON

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +11.0 V

IIK input clamping current VI<0.5 V or VI>V

CC +0.5V - 20 mA

ISK switch clamping current VSW <0.5 V or VSW >V

CC +0.5V - 20 mA

ISW switch current VSW =0.5 V to VCC +0.5V [1] -25 mA

ICC supply current - 50 mA

IGND ground current - 50 mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb = 40 C to +125 C[2]

DIP14 package - 750

SO14, (T)SSOP14 and DHVQFN14

packages -500

P power dissipation per switch - 100 mW

Product data sheet Rev. 6 — 18 July 2012 5 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

8. Recommended operating conditions

9. Static characteristics

Table 5. Re commended operating conditions

Symbol Parameter Conditions 74HC4066 74HCT4066 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 V

VIinput voltage GND - VCC GND - VCC V

VSW switch voltage GND - VCC GND - VCC V

Tamb ambient temperature 40 +25 +125 40 +25 +125 C

t/V input transition rise

and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 1 39 ns/V

VCC = 6.0 V - - 83 - - - ns/V

VCC = 10.0 V - - 35 - - - ns/V

Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066

VI = VIH or VIL; for test circuit see Figure 6.

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

For 74HC4066: VCC



GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V.

For 74HCT4066: VCC



GND = 4.5 V.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

RON(peak) ON resistance (peak) Vis = VCC to GND

VCC = 2.0 V; ISW = 100 A[2] --- - -

VCC = 4.5 V; ISW = 1000 A - 54 - 118 142 

VCC = 6.0 V; ISW = 1000 A - 42 - 105 126 

VCC = 9.0 V; ISW = 1000 A - 32 - 88 105 

RON(rail) ON resistance (rail) Vis = GND

VCC = 2.0 V; ISW = 100 A[2] -80- - -

VCC = 4.5 V; ISW = 1000 A-35-95115

VCC = 6.0 V; ISW = 1000 A - 27 - 82 100 

VCC = 9.0 V; ISW = 1000 A-20-7085

Vis = VCC

VCC = 2.0 V; ISW = 100 A[2] -100- - -

VCC = 4.5 V; ISW = 1000 A - 42 - 106 128 

VCC = 6.0 V; ISW = 1000 A-35-94113

VCC = 9.0 V; ISW = 1000 A-20-7895

Product data sheet Rev. 6 — 18 July 2012 6 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

[1] Typical values are measured at Tamb = 25 C.

[2] At supply voltages (VCC  GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is

recommended that these devices be used to transmit digital signals only, when using these supply voltages.

RON ON resistance

mismatch between

channels

Vis = VCC to GND

VCC = 2.0 V [2] --- - -

VCC = 4.5 V - 5 - - - 

VCC = 6.0 V - 4 - - - 

VCC = 9.0 V - 3 - - - 

Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066 …continued

VI = VIH or VIL; for test circuit see Figure 6.

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

For 74HC4066: VCC



GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V.

For 74HCT4066: VCC



GND = 4.5 V.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

Vis = 0 V to VCC Vis = 0 V to VCC

Fig 6. Test circuit for measuring RON Fig 7. Typical RON as a function of input voltage Vis

aaa-003458

Vis ISW

VIH

VCC

GND

nZnY

VSW

Vis (V)

0 9.07.23.6 5.41.8

aaa-003459

RON

(Ω)

VCC = 4.5 V

6 V

9 V

RON VSW

ISW

----------

Product data sheet Rev. 6 — 18 July 2012 7 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Table 7. Static characteristics 74HC4066

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions Min Typ[1] Max Unit

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V

VCC = 4.5 V 3.15 2.4 - V

VCC = 6.0 V 4.2 3.2 - V

VCC = 9.0 V 6.3 4.7 - V

VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V

VCC = 4.5 V - 2.1 1.35 V

VCC = 6.0 V - 2.8 1.80 V

VCC = 9.0 V - 4.3 2.70 V

IIinput leakage current VI = VCC or GND

VCC = 6.0 V - - 1.0 A

VCC = 10.0 V - - 2.0 A

IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 8

per channel - - 1.0 A

IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 9 --1.0 A

ICC supply current VI = VCC or GND; Vis = GND or VCC;

Vos =V

CC or GND

VCC = 6.0 V - - 20.0 A

VCC = 10.0 V - - 40.0 A

CIinput capacitance - 3.5 - pF

Csw switch capacitance - 8 - pF

Tamb = 40 C to +125 C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V

VCC = 4.5 V 3.15 - - V

VCC = 6.0 V 4.2 - - V

VCC = 9.0 V 6.3 - - V

VIL LOW-level input voltage VCC = 2.0 V - - 0.50 V

VCC = 4.5 V - - 1.35 V

VCC = 6.0 V - - 1.80 V

VCC = 9.0 V - - 2.70 V

IIinput leakage current VI = VCC or GND

VCC = 6.0 V - - 1.0 A

VCC = 10.0 V - - 2.0 A

IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 8

per channel - - 1.0 A

IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 9 --1.0 A

Product data sheet Rev. 6 — 18 July 2012 8 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

[1] Typical values are measured at Tamb = 25 C.

ICC supply current VI = VCC or GND; Vis = GND or VCC;

Vos =V

CC or GND

VCC = 6.0 V - - 40 A

VCC = 10.0 V - - 80 A

Table 7. Static characteristics 74HC4066 …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions Min Typ[1] Max Unit

Table 8. Static characteristics 74HCT4066

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions Min Typ[1] Max Unit

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V

VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V

IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A

IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 8

per channel - - 1.0 A

IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 9 --1.0 A

ICC supply current VI = VCC or GND; Vis = GND or VCC;

Vos =V

CC or GND; VCC = 4.5 V to 5.5 V - - 20.0 A

ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs

at VCC or GND; VCC = 4.5 V to 5.5 V - 100 450 A

CIinput capacitance - 3.5 - pF

Csw switch capacitance - 8 - pF

Tamb = 40 C to +125 C

VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V

VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V

IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A

IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 8

per channel - - 1.0 A

IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL;

VSW=V

CC GND; see Figure 9 --1.0 A

ICC supply current VI = VCC or GND; Vis = GND or VCC;

Vos =V

CC or GND; VCC = 4.5 V to 5.5 V --40A

ICC additional supply current per input pin; VI = VCC  2.1 V ; other inputs

at VCC or GND; VCC = 4.5 V to 5.5 V - - 490 A

Product data sheet Rev. 6 — 18 July 2012 9 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

10. Dynamic characteristics

[1] Typical values are measured at Tamb = 25 C.

[2] tpd is the same as tPHL and tPLH.

[3] ton is the same as tPHZ and tPLZ.

Vis = VCC and Vos = GND

Vis = GND and Vos = VCC

Vis = VCC and Vos = open

Vis = GND and Vos = open

Fig 8. Test circuit for measuring OFF-state leakage

current Fig 9. Test circuit for measuring ON-state leakage

current

aaa-003456

Vos

Vis

GND

ISW

aaa-003457

VIH

ZYn

Vos

Vis

GND

VCC

Table 9. Dynamic characteristics 74HC4066

GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12.

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

tpd propagation delay nY to nZ or nZ to nY; RL=  ;

see Figure 10 [2]

VCC = 2.0 V - 8 75 - 90 ns

VCC = 4.5 V - 3 15 - 18 ns

VCC = 6.0 V - 2 13 - 15 ns

VCC = 9.0 V - 2 10 - 12 ns

toff turn-off time nE to nY or nZ; see Figure 11 [4]

VCC = 2.0 V - 44 1 90 - 225 ns

VCC = 4.5 V - 16 38 - 45 ns

VCC = 5.0 V; CL = 15 pF - 13 - - - ns

VCC = 6.0 V - 13 33 - 38 ns

VCC = 9.0 V - 16 26 - 30 ns

ton turn-on time nE to nY or nZ; see Figure 11 [3]

VCC = 2.0 V - 36 1 25 - 150 ns

VCC = 4.5 V - 13 25 - 30 ns

VCC = 5.0 V; CL = 15 pF - 11 - - - ns

VCC = 6.0 V - 10 21 - 26 ns

VCC = 9.0 V - 8 16 - 20 ns

CPD power dissipation

capacitance per switch; VI = GND to VCC [5] 11 - - - pF

Product data sheet Rev. 6 — 18 July 2012 10 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

[4] toff is the same as tPZH and tPZL.

[5] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2fi+{(CL+C

sw) VCC2 fo} where:

fi = input frequency in MHz;

fo = output frequency in MHz;

{(CL+C

sw) VCC2 fo} = sum of outputs;

CL = output load capacitance in pF;

Csw = switch capacitance in pF;

VCC = supply voltage in V.

[1] Typical values are measured at Tamb = 25 C.

[2] tpd is the same as tPHL and tPLH.

[3] ton is the same as tPHZ and tPLZ.

[4] toff is the same as tPZH and tPZL.

[5] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2fi+{(CL+C

sw) VCC2 fo} where:

fi = input frequency in MHz;

fo = output frequency in MHz;

{(CL+C

sw) VCC2 fo} = sum of outputs;

CL = output load capacitance in pF;

Csw = switch capacitance in pF;

VCC = supply voltage in V.

Table 10. Dynamic characteristics 74HCT4066

GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12.

Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

tpd propagation

delay nY to nZ or nZ to nY; RL=  ;

see Figure 10 [2]

VCC = 4.5 V - 3 15 - 18 ns

toff turn-off time nE to nY or nZ; see Figure 11 [4]

VCC = 4.5 V - 20 44 - 53 ns

VCC = 5.0 V; CL = 15 pF - 16 - - - ns

ton turn-on time nE to nY or nZ; see Figure 11 [3]

VCC = 4.5 V - 12 30 - 36 ns

VCC = 5.0 V; CL = 15 pF - 12 - - - ns

CPD power dissipation

capacitance per switch;

VI=GNDto(V

CC 1.5 V) [5] -12- - -pF

Product data sheet Rev. 6 — 18 July 2012 11 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

11. Waveforms

Fig 10. Input (Vis) to output (Vos) propagation delays

001aad555

tPLH tPHL

50 %

Vis input

Vos output

Measurement points are shown in Table 11.

Fig 11. Turn-on and turn-off times

aaa-003460

PLZ

PHZ

switch OFF switch ON

switch ON

output

E input V

0 V

90 %

10 %

PZL

PZH

50 %

Table 11. Measurement points

Type VIVM

74HC4066 VCC 0.5VCC

74HCT4066 3.0 V 1.3 V

Product data sheet Rev. 6 — 18 July 2012 12 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

[1] For 74HCT4066: maximum input voltage VI = 3.0 V.

Test data is given in Table 12.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistor.

S1 = Test selection switch.

Fig 12. Load circuitry for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aag732

open

GND

DUT

RLS1

PULSE

GENERATOR

Table 12 . Test data

Test Input Output S1 position

Control E Switch Yn (Z) tr, tfSwitch Z (Yn)

VI[1] Vis CLRL

tPHL, tPLH GND GND to VCC 6 ns 50 pF - open

tPHZ, tPZH GND to VCC VCC 6ns 50pF, 15pF 1kGND

tPLZ, tPZL GND to VCC GND 6 ns 50 pF, 15 pF 1 kVCC

Product data sheet Rev. 6 — 18 July 2012 13 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

12. Additional dynamic characteristics

[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ).

[2] Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 ). After set-up, fi is increased to obtain a reading of

3dB at V

os.

Table 13. Additional dynamic characteristic s

Recommended conditio ns and typical values; GND = 0 V; Tamb = 25



Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.

Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

Symbol Parameter Conditions Min Typ Max Unit

THD total harmonic distortion fi= 1 kHz; RL= 10 k; CL=50pF;

see Figure 13 %

VCC = 4.5 V; VI= 4 .0 V (p-p) - 0.04 - %

VCC = 9.0 V; VI= 8.0 V (p-p) - 0.02 - %

fi=10kHz; R

L= 10 k; CL=50pF;

see Figure 13

VCC = 4.5 V; VI= 4 .0 V (p-p) - 0.12 - %

VCC = 9.0 V; VI= 8.0 V (p-p) - 0.06 - %

f(3dB) 3 dB frequency response RL= 50 ; CL=10pF; seeFigure 15 [2]

VCC = 4.5 V - 180 - MHz

VCC = 9.0 V - 200 - MHz

iso isolation (OFF-state) RL= 600 ; CL=50pF; f

i= 1 MHz;

see Figure 14 [1]

VCC = 4.5 V - 50 - dB

VCC = 9.0 V - 50 - dB

Vct crosstalk voltage between digital input and switch (peak to

peak value); RL= 600 ; CL=50pF;

fi= 1 MHz; see Figure 16

VCC = 4.5 V - 110 - mV

VCC = 9.0 V - 220 - mV

Xtalk crosstalk between switches; RL= 600 ; CL=50pF;

fi= 1 MHz; see Figure 17 [1]

VCC = 4.5 V - 60 - dB

VCC = 9.0 V - 60 - dB

Fig 13. Test circuit for measuring total harmonic distortion

10 μF

2RL

2RLCL

VIH

VCC VCC

nY/nZ nZ/nY

001aaj468

Product data sheet Rev. 6 — 18 July 2012 14 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

a. Isolation (OFF-state)

b. Test circuit

VCC = 4.5 V; GND = 0 V; RL = 600 ; Rsource = 1 k.

Fig 14. Isolation (OFF -s tate) as a function of frequency

mna082

−60

−40

−80

−20

(dB)

−10010 fi (kHz)

105106

104

102103

0.1 μF

2RL

VIL

VCC VCC

nY/nZ nZ/nY

001aaj470

Product data sheet Rev. 6 — 18 July 2012 15 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

a. Typical 3 dB frequency response

b. Test circuit

VCC = 4.5 V; GND = 0 V; RL = 50 ; Rsource = 1 k.

Fig 15. 3 dB frequency response

mna083

(dB)

−510 fi (kHz)

105106

104

102103

0.1 μF

2RL

2RLCL

VIH

VCC VCC

nY/nZ nZ/nY

001aaj469

Product data sheet Rev. 6 — 18 July 2012 16 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

a. Circuit

b. Crosstalk voltage

Fig 16. Test circuit for measuring crosstalk volt age (between the digital input and the switch)

DUT

mnb011

2RL

2RLnZ/nYnY/nZ

CLoscilloscope

VCC nE VCC

VCC

GND

mnb012

V(p−p)

Fig 17. Test circuit for measuring crosstalk (between the switches)

001aai846

VIH

VCC

1Z or 1Y1Y or 1Z

CHANNEL

2RL

0.1 μF

CLV

VIL

VCC VCC

2Z or 2Y2Y or 2Z

CHANNEL

OFF

2RL

2RL2RL

2RL

CLV

VO1

VO2

Product data sheet Rev. 6 — 18 July 2012 17 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

13. Package outline

Fig 18. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 6 — 18 July 2012 18 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Fig 19. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 6 — 18 July 2012 19 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Fig 20. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 6 — 18 July 2012 20 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Fig 21. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 6 — 18 July 2012 21 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Fig 22. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 6 — 18 July 2012 22 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

14. Abbreviations

15. Revision history

Table 14. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Mo del

Table 15. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT4066 v.6 20120718 Product data sheet - 74HC_HCT4066 v.5

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

74HC_HCT4066 v.5 20041111 Product data sheet - 74HC_HCT4066 v.4

74HC_HCT4066 v.4 20030617 Product data sheet - 74HC_HCT4066_CNV v.3

74HC_HCT4067_CNV v.3 19981110 Product data sheet - 74HC_HCT4066_CNV v.2

74HC_HCT4066_CNV v .2 19981002 Produ ct specification - -

Product data sheet Rev. 6 — 18 July 2012 23 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still unde r

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those descri bed in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semi conductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 18 July 2012 24 of 25

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC4066; 74HCT4066

16-channel analog multiplexer/demultiplexer

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 July 2012

Document identifier: 74HC_HCT4066

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Additional dynamic characteristics . . . . . . . . 13

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17 Contact information. . . . . . . . . . . . . . . . . . . . . 24

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25