1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
VCC and GND are the supply voltage connections for the digital control inputs (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
2. Features
nOptimized for low-voltage applications: 1.0 V to 3.6 V
nAccepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
nLow ON resistance:
u180 Ω (typical) at VCC − VEE = 2.0 V
u100 Ω (typical) at VCC − VEE = 3.0 V
u75 Ω (typical) at VCC − VEE = 4.5 V
nLogic level translation:
uTo enable 3 V logic to communicate with ±3 V analog signals
nTypical ‘break before make’ built in
nESD protection:
uHBM JESD22-A114-C exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nMultiple package options
nSpecified from −40 °Cto+85°C and from −40 °C to +125 °C
74LV4053
Triple single-pole double-throw analog switch
Rev. 04 — 10 August 2009 Product data sheet
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 2 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV4053N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4053D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74LV4053DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74LV4053PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74LV4053BQ −40 °C to +125 °C DHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 ×3.5 × 0.85 mm
SOT763-1
Fig 1. Functional diagram
001aak341
LOGIC
LEVEL
CONVERSION
11
16
VCC
13 1Y1
S1
LOGIC
LEVEL
CONVERSION
DECODER
LOGIC
LEVEL
CONVERSION
12 1Y0
14 1Z
1 2Y1
2 2Y0
15 2Z
3 3Y1
5 3Y0
43Z
10S2
9
87
VEE
GND
S3
6
E
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 3 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aae125
1Y0 12
1Y1
S1
13
11
S210
S39
6E
2Y0 2
2Y1 1
3Y0 5
3Y1 3
3Z 4
2Z 15
1Z 14
001aae126
6EN
11 #
#
#
MUX/DMUX 12
13
× 0
1
0/1
0
1
14
10 2
1
15
9 5
3
4
Fig 4. Schematic diagram (one switch)
001aad544
from
logic
VCC
VEE
VEE
VCC
VCC
VEE
Y
Z
VCC
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 4 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SOT38-4
and SOT109-1 Fig 6. Pin configuration
SOT338-1 and SOT403-1 Fig 7. Pin configuration for
SOT763-1
74LV4053
2Y1 VCC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
GND S3
001aak424
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15 74LV4053
2Y1 VCC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
GND S3
001aak342
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aak343
VEE S2
ES1
3Y0 1Y0
3Z 1Y1
3Y1 1Z
2Y0 2Z
GND
S3
2Y1
VCC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
VCC(1)
74LV4053
Table 2. Pin description
Symbol Pin Description
E 6 enable input (active LOW)
VEE 7 supply voltage
GND 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 common output or input
VCC 16 supply voltage
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 5 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table [1]
Inputs Channel on
E Sn
L L nY0 to nZ
L H nY1 to nZ
H X switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] −0.5 +7.0 V
IIK input clamping current VI<−0.5 V or VI> VCC + 0.5 V [2] -±20 mA
ISK switch clamping current VSW <−0.5 V or VSW > VCC + 0.5 V [2] -±20 mA
ISW switch current VSW >−0.5VorV
SW <V
CC + 0.5 V;
source or sink current [2] -±25 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[3]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
DHVQFN16 package - 500 mW
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 6 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
8. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with
input levels GND or VCC).
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage see Figure 8 1 3.3 6 V
VIinput voltage 0 - VCC V
VSW switch voltage 0 - VCC V
Tamb ambient temperature in free air −40 - +125 °C
∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
Fig 8. Guaranteed operating area as a function of the supply voltages
VCC - VEE (V)
0 8.06.02.0 4.0
001aak344
4.0
2.0
6.0
8.0
VCC - GND
(V)
0
operating area
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 7 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9. Static characteristics
[1] Typical values are measured at Tamb = 25 °C.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V 3.15 - - 3.15 - V
VCC = 6.0 V 4.20 - - 4.20 - V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V - - 1.35 - 1.35 V
VCC = 6.0 V - - 1.80 - 1.80 V
IIinput leakage current VI=V
CC or GND
VCC = 3.6 V - - 1.0 - 1.0 µA
VCC = 6.0 V - - 2.0 - 2.0 µA
IS(OFF) OFF-state leakage current VI = VIH or VIL; see Figure 9
VCC = 3.6 V - - 1.0 - 1.0 µA
VCC = 6.0 V - - 2.0 - 2.0 µA
IS(ON) ON-state leakage current VI = VIH or VIL; see Figure 10
VCC = 3.6 V - - 1.0 - 1.0 µA
VCC = 6.0 V - - 2.0 - 2.0 µA
ICC supply current VI = VCC or GND; IO = 0 A
VCC = 3.6 V - - 20 - 40 µA
VCC = 6.0 V - - 40 - 80 µA
∆ICC additional supply current per input; VI = VCC − 0.6 V;
VCC = 2.7 V to 3.6 V - - 500 - 850 µA
CIinput capacitance - 3.5 - - - pF
Csw switch capacitance independent pins nYn - 5 - - - pF
common pins nZ - 8 - - - pF
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 8 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9.1 Test circuits
9.2 ON resistance
VI = VCC or VEE and VO = VEE or VCC.V
I = VCC or VEE and VO = open circuit.
Fig 9. Test circuit for measuring OFF-state leakage
current Fig 10. Test circuit for measuring ON-state leakage
current
ISIS
001aak345
VCC
VI
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC
nY1
1
2
VO
IS
001aak346
GND
VO
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC
nY1
1
2
VI
Table 7. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI = 0 V to VCC − VEE
VCC = 1.2 V; ISW = 100 µA[2] --- - -Ω
VCC = 2.0 V; ISW = 1000 µA - 180 365 - 435 Ω
VCC = 2.7 V; ISW = 1000 µA - 115 225 - 270 Ω
VCC = 3.0 V to 3.6 V;
ISW = 1000 µA- 100 200 - 245 Ω
VCC = 4.5 V; ISW = 1000 µA - 75 150 - 180 Ω
VCC = 6.0 V; ISW = 1000 µA - 70 140 - 165 Ω
∆RON ONresistancemismatch
between channels VI = 0 V to VCC − VEE
VCC = 1.2 V; ISW = 100 µA[2] --- - -Ω
VCC = 2.0 V; ISW = 1000 µA-5- - -Ω
VCC = 2.7 V; ISW = 1000 µA-4- - -Ω
VCC = 3.0 V to 3.6 V;
ISW = 1000 µA-4- - -Ω
VCC = 4.5 V; ISW = 1000 µA-3- - -Ω
VCC = 6.0 V; ISW = 1000 µA-2- - -Ω
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 9 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
[1] Typical values are measured at Tamb =25°C.
[2] When supply voltages (VCC −VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, it is recommended to use these devices only for transmitting digital signals.
RON(rail) ON resistance (rail) VI = GND
VCC = 1.2 V; ISW = 100 µA[2] - 250 - - - Ω
VCC = 2.0 V; ISW = 1000 µA - 120 280 - 325 Ω
VCC = 2.7 V; ISW = 1000 µA - 75 170 - 195 Ω
VCC = 3.0 V to 3.6 V;
ISW = 1000 µA- 70 155 - 180 Ω
VCC = 4.5 V; ISW = 1000 µA - 50 120 - 135 Ω
VCC = 6.0 V; ISW = 1000 µA - 45 105 - 120 Ω
RON(rail) ON resistance (rail) VI = VCC − VEE
VCC = 1.2 V; ISW = 100 µA[2] - 350 - - - Ω
VCC = 2.0 V; ISW = 1000 µA - 170 340 - 400 Ω
VCC = 2.7 V; ISW = 1000 µA - 105 210 - 250 Ω
VCC = 3.0 V to 3.6 V;
ISW = 1000 µA- 95 190 - 225 Ω
VCC = 4.5 V; ISW = 1000 µA - 70 140 - 165 Ω
VCC = 6.0 V; ISW = 1000 µA - 65 125 - 150 Ω
Table 7. ON resistance
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 10 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
9.3 On resistance waveform and test circuit
RON =V
SW /I
SW.
Fig 11. Test circuit for measuring RON
V
001aak347
GND
VI
VSW
ISW
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC
nY1
1
2
Vi = 0 V to VCC − VEE
Fig 12. Typical RON as a function of input voltage
VI (V)
0 4.81.2 2.4 3.6
001aak348
100
150
50
200
RON
(Ω)
0
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 11 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay nYn, nZ to nZ, nYn; see Figure 13 [2]
VCC = 1.2 V - 25 - - - ns
VCC = 2.0 V - 9 17 - 20 ns
VCC = 2.7 V - 6 13 - 15 ns
VCC = 3.0 V to 3.6 V [3] - 5 10 - 12 ns
VCC = 4.5 V - 4 9 - 10 ns
VCC = 6.0 V - 3 7 - 8 ns
ten enable time E to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 100 - - - ns
VCC = 2.0 V - 34 65 - 77 ns
VCC = 2.7 V - 25 48 - 56 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -16- - -ns
VCC = 3.0 V to 3.6 V [3] - 19 38 - 45 ns
VCC = 4.5 V - 17 32 - 38 ns
VCC = 6.0 V - 13 25 - 29 ns
Sn to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 125 - - - ns
VCC = 2.0 V - 43 82 - 97 ns
VCC = 2.7 V - 31 60 - 71 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -20- - -ns
VCC = 3.0 V to 3.6 V [3] - 24 48 - 57 ns
VCC = 4.5 V - 21 41 - 48 ns
VCC = 6.0 V - 16 31 - 37 ns
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 12 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
[1] All typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ((CL + CSW)× VCC2×fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
CSW = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL×VCC2×fo) = sum of the outputs.
tdis disable time E to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 95 - - - ns
VCC = 2.0 V - 34 61 - 73 ns
VCC = 2.7 V - 26 46 - 54 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -17- - -ns
VCC = 3.0 V to 3.6 V [3] - 20 37 - 44 ns
VCC = 4.5 V - 18 32 - 38 ns
VCC = 6.0 V - 15 25 - 30 ns
Sn to nYn, nZ; see Figure 14 [2]
VCC = 1.2 V - 90 - - - ns
VCC = 2.0 V - 32 59 - 70 ns
VCC = 2.7 V - 24 44 - 52 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -16- - -ns
VCC = 3.0 V to 3.6 V [3] - 19 36 - 42 ns
VCC = 4.5 V - 17 31 - 36 ns
VCC = 6.0 V - 14 24 - 28 ns
CPD power dissipation
capacitance CL= 50 pF; fi = 1 MHz;
VI= GND to VCC
[4] -36- - -pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 13 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.1 Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 13. nYn, nZ to nZ, nYn propagation delays
001aak351
nYn or nZ
input
nZ or nYn
output
tPLH tPHL
VCC
VEE
VM
VM
VO
VEE
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 14. Enable and disable times
001aak352
tPLZ
tPHZ
switch OFF switch ONswitch ON
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
Sn, E input
VO
VO
VEE
VEE
VCC
VSS
VM
tPZL
tPZH
90 %
90 %
10 %
10 %
Table 9. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
< 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
> 3.6 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 14 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aak353
VEXT
VCC
VEE
VIVO
DUT
CL
RT
RL
RL
G
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
< 2.7 V VCC ≤ 6 ns 50 pF 1 kΩopen VEE 2VCC
2.7 V to 3.6 V 2.7 V ≤ 6 ns 15 pF, 50 pF 1 kΩopen VEE 2VCC
> 3.6 V VCC ≤ 6 ns 50 pF 1 kΩopen VEE 2VCC
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 15 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.2 Additional dynamic parameters
[1] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 Ω).
[2] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 Ω).
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V
I
= GND or V
CC
(unless otherwise
specified); t
r
= t
f
≤
6.0 ns; T
amb
= 25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic
distortion fi= 1 kHz; CL= 50 pF; RL=10kΩ; see Figure 20
VCC = 3.0 V; VI= 2.75 V (p-p) - 0.8 - %
VCC = 6.0 V; VI= 5.5 V (p-p) - 0.4 - %
fi= 10 kHz; CL= 50 pF; RL=10kΩ; see Figure 20
VCC = 3.0 V; VI= 2.75 V (p-p) - 2.4 - %
VCC = 6.0 V; VI= 5.5 V (p-p) - 1.2 - %
f(−3dB) −3 dB frequency
response CL= 50 pF; RL=50Ω; see Figure 16 [1]
VCC = 3.0 V - 180 - MHz
VCC = 6.0 V - 200 - MHz
αiso isolation (OFF-state) fi= 1 MHz; CL= 50 pF; RL= 600 Ω; see Figure 18 [2]
VCC = 3.0 V - −50 - dB
VCC = 6.0 V - −50 - dB
Vct crosstalk voltage between digital inputs and switch;
fi= 1 MHz; CL= 50 pF; RL= 600 Ω; see Figure 21 [2]
VCC = 3.0 V - 0.11 - V
VCC = 6.0 V - 0.12 - V
Xtalk crosstalk between switches; fi= 1 MHz; CL= 50 pF;
RL= 600 Ω; see Figure 22
VCC = 3.0 V - −60 - dB
VCC = 6.0 V - −60 - dB
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 16 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
10.2.1 Test circuits
VCC = 3.0 V; GND = 0 V; VEE =−3.0 V; RL=50Ω;
RSOURCE =1kΩ.
Fig 16. Test circuit for measuring frequency response Fig 17. Typical frequency response
dB
001aak355
GND
fi
2RL
2RL
CL
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
nY1
1
2
0.1 µF
001aak361
0
5
(dB)
−5
f (kHz)
10 106
105
102104
103
VCC = 3.0 V; GND = 0 V; VEE =−3.0 V; RL=50Ω;
RSOURCE =1kΩ.
Fig 18. Test circuit for measuring isolation (OFF-state) Fig 19. Typical isolation (OFF-state) as function of
frequency
dB
001aak356
VCC
fi
2RL
2RL
CL
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
nY1
1
2
0.1 µF
001aak360
−50
0
(dB)
−100
f (kHz)
10 106
105
102104
103
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 17 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 20. Test circuit for measuring total harmonic distortion
D
001aak354
GND
fi
2RL
2RL
CL
switch
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
nY1
1
2
10 µF
a. Test circuit
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
001aak357
VIH or VIL
VCC
switch
GND = VEE
S1 to S3
E
nZ
nY0
VCC VCC
nY1
1
2
GV
2RL
2RL
2RL
2RL
CLVO
001aaj908
on
VOVct
off off
logic
input (Sn, E)
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 18 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
a. Switch closed condition
b. Switch open condition
Fig 22. Test circuit for measuring crosstalk between switches
001aak358
GND VO
2RL
2RL
CL
RL
2RL
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
2RL
VCC
nY1
VI
0.1 µF
dB
001aak359
GND VI
2RL
2RL
RL
2RL
GND = VEE
S1 to S3
E
nZ
nY0
VIH or VIL
VCC VCC
2RL
VCC
2RL
VCC
nY1
VOCLdB
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 19 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
11. Package outline
Fig 23. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 20 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 24. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 21 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 25. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 22 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 26. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 23 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
Fig 27. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 24 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
12. Abbreviations
13. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV4053_4 20090810 Product data sheet - 74LV4053_3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Added type number 74LV4053BQ (DHVQFN16 package)
•RON values changed in Section 2.
•Package version SOT38-1 changed to SOT38-4 in Section 3, and Figure 23.
74LV4053_3 19980623 Product specification - 74LV4053_2
74LV4053_2 19970715 Product specification - -
74LV4053_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 10 August 2009 25 of 26
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LV4053
Triple single-pole double-throw analog switch
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 August 2009
Document identifier: 74LV4053_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
9.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.3 On resistance waveform and test circuit. . . . . 10
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.2 Additional dynamic parameters . . . . . . . . . . . 15
10.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15 Contact information. . . . . . . . . . . . . . . . . . . . . 25
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
