HPC 16164/26 164/36 164/46 164/16104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 National | Semiconductor HPC 16164/26164/36164/46164 HPC16104/26104/36104/46104 HPC 16064/26064/36064/46064 HPC16004/26004/36004/46004 PRELIMINARY High-Performance microControllers with A/D General Description The HPC16164, HPC16104, HPC16064 and HPC16004 are members of the HPCT family of High Performance micro- Controllers. Each member of the famity has the same core CPU with a unique memory and I/O configuration to suit specific applications. The HPC16164 and HPC16104 have 16k bytes of on-chip ROM. The HPC16104 and HPC16104 have no on-chip ROM and is intended for use with external memory. Each part is fabricated in National's advanced microCMOS technology. This process combined with an ad- vanced architecture provides fast, flexible 1/O control, effi- cient data manipulation, and high speed computation. The HPC devices are complete microcomputers on a single chip. All system timing, internal logic, ROM, RAM, and |/O are provided on the chip to produce a cost effective solution for high performance applications. Cn-chip functions such as UART, up to eight 16-bit timers with 4 input capture regis- ters, vectored interrupts, WATCHDOG logic and MICRO- WIRE/PLUS provide a high level of system integration. The ability to address up to 64k bytes of external memory enables the HPC to be used in powerful applications typical- ly performed by microprocessors and expensive peripheral chips. The term HPC16164 is used throughout this data- sheet to refer to the HPC16164, HPC 16104, HPC16064 and HPC16004 devices unless otherwise specified. The HPC16164 and HPC16104 have, as an on-board pe- ripheral, an 8-channel 8-bit Analog-to-Digital Converter. This A/D converter can operate in single-ended mode where the analog input voltage is applied across one of the eight input channels (DO-D7) and AGND. The A/D converter can also operate in differential mode where the analog input voltage is applied across two adjacent input channels. The A/D converter will convert up to eight channels in single-ended mode and up to four channel pairs in differential mode, The HPC16064 and HPC16004 do not have onboard A/D. Tne microCMOS process results in very low current drain and enables the user to select the optimum speed/power product for his system. The IDLE and HALT modes provide further current savings. The HPC is available in 68-pin PLCC, LOC, LOCC, PGA and 84-pin TapePak packages. Features w HPC familycore features: 16-bit architecture, both byte and word 16-bit data bus, ALU, and registers 64k bytes of external direct memory addressing FAST200 ns for fastest instruction when using 20.0 MHz clock ~ High code efficlencymost instructions are single byte 16 x 16 multiply and 32 x 16 divide Eight vectored interrupt sources Four 16-bit timer/counters with 4 synchronous out- puts and WATCHDOG logic MICROWIRE/PLUS serial I/O interface CMOSvery low power with two power save modes: IDLE and HALT m A/D8-channet 8-bit analog-to-digital converter with conversion time minimum 6.6 js for single conversion = A/Osupports conversions in quiet mode Block Diagram (HPc16164 with 16k ROM shown) fovrA ES) staus exe WH Cal Cxecee 1 itt 4 ae FE os SJE) Se Eales i i = LL oT a - als] =[~[-]> TL/DD/9682-1 4-48Features (Continued) m UARTfull duplex, programmable baud rate w Four additional 16-bit timer/counters with pulse width modulated outputs m@ Four input capture registers w@ 52 general purpose I/O lines (memory mapped} Absolute Maximum Ratings if Milltary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Total Allowable Source or Sink Current 100 mA Storage Temperature Range 65C to + 150C Lead Temperature (Soldering, 10 sec.) 300C m@ 16k bytes of ROM, 512 bytes of RAM on-chip @ ROMiess version available (HPC16104) w Commercial (OC to +70C), industrial (40C to +85C), automotive (40C to + 105C) and military (55C to + 125C) temperature ranges Voc with Respect to GND 0.5V to 7.0V Alt Other Pins (Voc + 9.5)V to (GND 0.5)V ESD Rating 2000V Note: Absolute maximum ratings indicate limits beyond which damage to the davice may occur. DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. 20 MHz DC Electrical Characteristics voc = 5.0v +10% unless otherwise specified, Ta = 0C to +70C for HPC46164/HPC46104, HPC46064/HPC46004, 40C to + 85C for HPC36164/HPC36104, HPC36064/HPC36004, 40C to +105C for HPC26164/HPC26104, HPC26064/HPC26004, -55C to +125C for HPC16164/HPC16104, HPS16064/HPC16004 Symbol Parameter Test Conditions Min Max Units ioc, Supply Current Voc = 5.5V, fin = 20.0 MHz (Note 1) 40 mA Voc = 5.5V, fin = 2.0 MHz (Note 1) 15 mA, Isca IDLE Mode Current Voc = 5.5V, fin = 20.0 MHz, (Note 1) 3.5 mA Voc = 5.5V. fin = 2.0 MHz, (Note 1) 1 mA lec HALT Mode Current Voc = 5.5), fin = 0 kHz, (Note 1) 300 pA Veco = 2.5), fin = 0 kHz, (Note 1) 100 pA INPUT VOLTAGE LEVELS RESET, NMI, CKI AND WO (SCHMITT TRIGGERED) VIHy Logic High 0.9 Voc Vv Ving Logic Low 0.1 Ver V ALL OTHER INPUTS Vip Logic High 0.7 Voc Vv Vite Logic Low 0.2 Voc v lu Input Leakage Current +1 pA i RDY/HLD,EXUY 3 -50 | HA IL3 Input Leakage Current B12 0.5 7 pA Cy Input Capacitance (Note 2) 10 pF Cio 1/O Capacitance (Note 2) 20 pF OUTPUT VOLTAGE LEVELS Vou, Logie High (CMOS) lou = 10 pA (Note 2) Voc - 0.1 Vv Vou, Logic Low (CMOS) lon = 10 pA (Note 2) 0.1 Vv VoHo Port A/B Drive, CK2 lon = 7MA 2.4 v Vole (Ao-A1s, B10, B11, Bra, Bis) lo. = 3mMA 0.4 Vv VoHg Other Port Pin Drive, WO (open lon = 1.6 mA 2.4 V Vou3 drain) (Bo-8g, 843, By4, Po-Pa) lo, = 0.5mA 0.4 V Vous $T1 and ST2 Drive lon = 6mA 2.4 Vv VoLy lo. = 1.6mA 0.4 Vv VRAM RAM Keep-Alive Voltage (Note 3) 2.5 Veco Vv loz TRI-STATE Leakage Current +5 pA Note 1: Ioc,, logy: loca measured with no external drive (ion and lo, = 9, hand I, = 0}. log, is measured with RESET = GND. icc, is measured with NMI = Voc and A/D inactive. CKI driven to Vi, and Vi.1 with rise and fall times jess than 10 ns. Vage = AGND = GND. Note 2: This is guaranteed by design and not tested. Note 3: Test duration is 100 ms. 7O0SP / FOOSE /7009Z /009 1 /7909% /7909E/79092/P9091 /P01 9P/POL9E/POL9Z/POL9L/P9L9b/P9198/P91 92/7991 OdHHPC 16164/26 164/36 164/46164/ 16 104/26 104/36 104/46104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 20 MHz AC Electrical Characteristics voc = 5.0v +10% uniess otherwise specified, Ta = 0C to +70C for HPC46164/HPC46104, HPC46064/HPC46004, 40C to +85C for HPC36164/HPC36104, HPC36064/HPC36004, 40C to +105C for HPC26164/HPC26104, HPC26064/HPC26004, 55C to +125C for HPC16164/HPC16104, HPC16064/HPC16004 Symbol Parameter Min Max Units. fo = CKI freq. Operating Frequency 2 20 MHz toy = 1/fo Clock Period 50 500 ns toxin (Note 3) CKI Rise Time 7 ns toxig (Note 3) CK] Fall Time 7 ns [toniH/(tcKiHn + tox] 100 Duty Cycle 45 55 % tc = 2/fc Timing Cycle 100 ns ti = tc - o ALE Pulse Width 41 ns tocicer Delay from CKI Falling 0 55 ns. (Notes 1, 2) Edge to CK2 Rising Edge toc1ceF Delay from CKI Falling 0 55 ns (Notes 1, 2) Edge to CK2 Falling Edge tpc1ALER Delay from CKI Rising 0 35 ns (Notes 1, 2) Edge to ALE Rising Edge tpc1ALEF Delay from CKI Rising 0 95 ns (Notes 1, 2) Edge to ALE Falling Edge tocoaLenR = YVatc + 20 Delay from CK2 Rising 45 ns (Note 2) Edge to ALE Rising Edge toceaLeF = Mate + 20 Delay from CK2 Falling 45 ns (Note 2) Edge to ALE Falling Edge tst = Vato 7 Address Valid to ALE Falling Edge 18 ns typ = Vato 5 Address Hold from ALE Falling Edge 20 ns twait = tc Wait State Period 100 ns fyin = fo /19 External Timer Input Frequency 1.052 MHz tyin = tc Pulse Width for Timer inputs 100 ns fyout = fco/16 Timer Output Frequency 1.25 MHz fuw = fco/19 Clock inpet Froauoncy PLUS 1.052 MHz fy = fc/8 External UART Clock Input Frequency 2.5 MHz CKI Input Signal Characteristics Rise/Fall Time Duty Cycle 90% Ck 50% Ckl 10% ter tour toxin TLIOD 9682-34 TL/DD/9682-35 4-5020 MHz Read Cycle Timing Symbol Parameter Min Max Units tanR = tc-5 ALE Falling Edge to AD Falling Edge 20 ns trw = %to + WS 10 RD Pulse Width 140 ns ton = %tc 15 Data Hold after Rising Edge of AD 0 60 ns tacc = tc + WS 55 Address Valid to Input Data Valid (Note 2) 145 ns tap = Yate + WS 65 RD Falling Edge to Input Data Valid 85 ns tapa = te 5 RD Rising Edge to Address Valid 95 ns Write Cycle Timing Symbol Parameter Min Max Units tanw = Vetc 5 ALE Falling Edge to WR Falling Edge 45 ns tww = %te + WS 15 WA Pulse Width 160 ns thw = Vato 5 Data Hold after Rising Edge of WR 20 ns ty= %te+WwWS-5 Data Valid before Rising Edge of WR 145 ns Note: Bus Output (Port A) C_ = 100 pF, CK2 Output C_ = 50 pF, other Outputs C, = 80 pF. AC parameters are tested using DC Characteristics Inputs and non CMOS Outputs. Measurement of AC Specifications is done with external clock driving CKt with 50% duty cycle. The capacitive load on CKO must be kept below 15 pF or AC measurement will be skewed. Note: WS = twat * number of pre-programmed wait states. Minimum and maxirnum values are calculated from maximum operating frequency with one (1) wait State pre-programmed. Note 1: Do not design with this parameter unless Cil is driven with an active signal. When using a passive crystal circuit, CK| or CKO show/d not be connected to any external logic sinca any load (besides the passive components in the crystal circuit} will affect the stability of the crystal unpredictably. Note 2: These are not directly tested parameters. Therefore the given min/max value cannot be guaranteed. It is, however, derived from measured parameters, and may be used for system design with a very high confidence level. Note 3: This is guaranteed by design and not tested. Ready/Hold Timing Symbol Parameter Min Max Units tpan = Yatc + WS 50 Falling Edge of ALE to Falling Edge of RDY 78 ns tawp = tc RDY Pulse Width 100 ns tsaLe = %tc + 40 Falling Edge of HLD 118 ns to Rising Edge of ALE tywe = tc + 10 HLD Pulse Width 110 ns tHap = %tc +85 Rising Edge on HLD to 160 ns Rising Edge on HLDA tHaE = tc + 100 Falling Edge on HLD to 200" ns Falling Edge on HLDA Data Valid after 116T Falling Edge on HLDA =1 the = Vatc + 66 ns Bus Enable from Rising Edge of HLDA =1 tee = atc + 66 1167 ns *Note: tyac may be as long as (Sic + 4ws + 72t + 90) depending on which instruction is being executed, the addressing mode and number of wait states. tHae maximum value is for the optimal case. Note: Que to emulation restrictionsactual limits will be better. 4-51 009P/F009E/F0097/P0091 /P9091/17909E/F9092/P9091 /F01 Sb/POLSE/POL92/POL SL /POLOF/POLSE/P9L9C/P9191LOdHHPC 16164/26 164/36 164/46 164/16104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 20 MHz MICROWIRE/PLUS Timing Symbol Parameter Min Max Units tuws MICROWIRE Setup Master Time 100 ns Slave 20 tuwH MiCROWIRE Hold Master Time 20 ns Siave 50 tuwy MICROWIRE Output Master Valid Time 50 ns Slave 150 UPI Read/Write Timing Symbol Parameter Min Max Units tuas Address Setup Time to 10 ns Failing Edge of URD tUAH Address Hold Time trom 10 ns Rising Edge of URD tapw URD Pulse Width 100 ns toe URD Falling Edge to Output Data Valid 60 ns top Rising Edge of URD to 5 95 ns Output Data Invalid (Note 4) torpy RDRDY Delay from Rising 70 ns Edge of URD twow UWR Pulse Width 40 ns tups Input Data Valid before 10 ns. Rising Edge of UWR tUDH Input Data Hold after 45 ns Rising Edge of UWR ta WRRDY Delay from Rising Edge of UWR 70 ns Note: Bus Output (Port A) CL = 100 pF, CK2 Output GC, = 50 F, other Outputs C_ = 80 pF. Note 4: Guaranteed by design. Input and Output for AC Tests Vin Vou Vou TEST POINTS x Voi VoL Vit TL/DB/968240 "0! Note: AC testing inputs are driven at Vj, for a logic 1 and Vi, for a logic O". Output timing measurements are made at Voy for a logic 1 and Voy, for a logic 4-5220 MHz A/D Converter Specifications vcc = sv +10% unless otherwise specified, Ta = OC to +70C for HPC46164/HPC46104, 40C to +85C for HPC36164/HPC36104, 40C to + 105C for HPC26164/HPC26104, 55C to + 125C for HPC16164/HPC16104 Symbol Parameter Min Max Units Resolution 8 bits fec_k Clock Frequency (Note 4) 0.1 1.6 MHz tcon = 8.5/focLk Conversion Time (Note 3} 5.3 ps VREF Reference Voitage Input (AGND = OV) 3.0 Voc Vv Wane = 5.000) Error (Note 4) +% LSB RyrRer Reference Input Resistance (Note 5) 1.6 4.8 kQ DC Gommon Mode Error tM LSB Vee SOO. Ven 5V +10%) +% LSB Voltage Reference Tolerance (VRer) TBO LSB Port D Input Capacitance (Note 5) 35 pF Analog Input Voltage Range (Note 2) GND 0.05 Voc + 0.05 Vv On Channel Leakage 1 pA Off Channel Leakage 1 pA Note 1: Total unadjusted error includes offset, full-scate, and multiplexer errors. Note 2: 8 single-ended or 4 differential channels. Inherent sample and hold for single-ended inputs (GND = Pin 62). Note 3: Conversion time does not include sample/hold time plus overhead. Sample and hotd time is 2/foci. Overhead is 1/fccik Note 4: Clock supplied to A/D converter is derived from CKI. See A/D description for details. Note 5: This is guaranteed by design and not tested. 4-53 yO09Y /FOCSE /7009Z /P009I. /#909"/F909E /79097/P9091 /P0l9b/F0! 96/701 9%/POLOL /91.9h/09198/P9192/F9191IdH30 MHz Absolute Maximum Ratings If Military/Aerospace specified devices are required, Voc with Respect to GND 0.5V to 7.0V please contact the National Semiconductor Sales All Other Pins (Voc + 0.5)V to (GND 0.5)V Office/Distributors for availability and specifications. ESD Rating 2000V Total Allowable Source or Sink Current 100 mA Note: Absolute maximum ratings indicate limits beyond Storage Temperature Range 65C to + 150C which damage to the device may occur. DC and AC electri- Lead Temperature (Soldering, 10 sec.) 300C cal specifications are not ensured wher operating the de- vice at absolute maximum ratings. 20 MHz DC Electrical Characteristics vco = 5.0v +10% unless otherwise specified, Ta = 0C to +70C for HPC46164/HPC46104, HPC46064/HPC46004, 40C to +85C for HPC36164/HPC36104, HPC36064/HPC36004, 40C HPC 16 164/26 164/36 164/46 164/16104/26 104/36 104/46104/16064/26064/36064/46064/16004/26004/36004/46004 to +105C for HPC26164/HPC26104, HPC26064/HPC26004, -55C to +125C for HPC16164/HPC161 04, HPC16064/HPC16004 Symbol Parameter Test Conditions Min Max Units icc, Supply Current Veco = 5.54, tin = 90.0 MHz (Note 1) TBD mA Voc = 5.5V, fin = 2.0 MHz (Note 1) 15 mA Icce IDLE Mode Current Voc = 5.5V, fin = 30.0 MHz, (Note 1} TBD mA Voc = 5.5V, fin = 2.0 MHz, (Note 1) 2 mA Iocg HALT Mode Current Voc = 5.5V, fig = 0 kHz, (Note 1) 400 pA Voc = 2.5V, fiq = O kHz, (Note 1) 250 BA INPUT VOLTAGE LEVELS RESET, NMI, CKI AND WO (SCHMITT TRIGGERED) Viny Logie High 0.9 Voc Vv Vity Logic Low 0.1 Voc Vv ALL OTHER INPUTS Vip Logic High 0.7 Vec v Vile Logic Low 0.2 Voc V Iu Input Leakage Current +1 pA te | mBaneshoge cuen - | -s | ms ILs Input Leakage Current B12 0.5 7 pA C Input Capacitance (Note 2) 10 pF Clo 1/0 Capacitance {Note 2) 20 pF OUTPUT VOLTAGE LEVELS Vou, Logic High (CMOS) lou = 10 pA (Note 2) Voc 0.1 Vv Vou, Logic Low (CMOS) loH = 10 pA (Note 2) 0.1 V Vora Port A/B Drive, CK2 loq = 7mMA 2.4 v Volz (Ao-A45, Bio, B14, Biz, By5) lol = 3mA 0.4 Vv VoHg Other Port Pin Drive, WO (open low = 1.6mA 2.4 v VoLs drain) (Bo-Bg, B13, B14, Po-Ps) [1 = 0.5 mA 0.4 v VoHa ST1 and ST2 Drive lon = 6 mA 2.4 v VoL4 lo. = 1.6 mA 0.4 v Vram RAM Keep-Alive Voltage (Note 3) 2.5 Voc Vv loz TRI-STATE Leakage Current +5 pA Note 1: icc), Icca Iccg measured with no external drive (Ion and lol = 0, fy and fy, = 0). ioc, is maasurad with RESET = GND. locg is measured with NMI = Voc and A/D inactive. CKI driven to Viyq and VjL; with rise and fall times less than 10 ns. Vagr = AGND = GND. Note 2: This Note 3: Test is guaranteed by design and not tested. duration is 100 ms. 4-5430 MHz AC Electrical Characteristics voc = 5.0v +10% unless otherwise specified, Ta = 0C to +70C for HPC46164/HPC46104, HPG46064/HPC46004, 40C to +85C for HPC36164/HPC36104, HPC36064/HPC36004, 40C to +105C for HPC26164/HPC26104, HPC26064/HPC26004, 55C to +125C for HPC16164/HPC16104, HPC16064/HPC16004 Symbol Parameter Min Max Units fo = CKl freq. Operating Frequency 2 30 MHz te, = 1/fc Clock Period 33 500 ns toxin (Note 3) CK] Rise Time 7 ns toxig (Note 3) CKI Fall Time 7 ns ltckin/{teKiH + toKiL)}100 Duty Cycle 45 55 % to = 2/fc Timing Cycle 66 ns ttl = Yate - 9 ALE Pulse Width 24 ns tociceR Delay from CK| Falling 0 55 ns (Notes 1, 2) Edge to CK2 Rising Edge tocicer Delay from CKI Falling 0 55 ns (Notes 1, 2) Edge to CK2 Falling Edge toc1ALER Delay from CKI Rising 0 35 ns (Notes 1, 2) Edge to ALE Rising Edge tpoC1ALEF Delay from CKI Rising 0 a5 ns (Notes 1, 2) Edge to ALE Falling Edge toceaLen = Vatc + 20 Delay from Ck2 Rising 37 ns (Note 2) Edge to ALE Rising Edge toc2aLer = Vato + 20 Delay from CK2 Falling 37 ns (Note 2) Edge to ALE Falling Edge tsi = Mtco-7 Address Valid to ALE Falling Edge 9 ns typ = Yio & Address Hold from ALE Falling Edge 11 ns twait = tc Wait State Period 66 ns fun = fo/19 External Timer Input Frequency 1.579 MHz txin = tc Pulse Width for Timer Inputs 66 ns fyouT = fco/16 Timer Output Frequency 1.875 MHz fw = fc/19 External MICROWIRE/PLUS 1.579 MHz Clock Input Frequency fy = f/8 External UART Clock Input Frequency 3.75 MHz CKI Input Signal Characteristics Rise/Fail Time Duty Cycle 90% CKi 50% CKI 10% toxin tore torr oxi to TL/DD/9682-34 TL/DD/9662-35 4-55 p009P/PO09E /P009Z/ 0094 /7909b/$909E/1909Z/P9091 /F0L9b/POL9E/P0192/POL 91 /P9LSb/H919E/P9192/P9L 91 9dH30 MHz Read Cycle Timing Symbol Parameter Min Max Units taaR = Vte5 ALE Falling Edge to RD Falling Edge 12 ns taw = Vato + WS - 14 RD Pulse Width 85 ns ton = %tc 15 Data Hold after Rising Edge of RD 0 35 ns tacc = tc + WS 32 Address Valid to Input Data Valid (Note 2) 100 ns tap = Vete + WS 39 RD Falling Edge to Input Data Valid 60 ns tapa = tt 5 RD Rising Edge to Address Valid 61 ns Write Cycle Timing Symbol Parameter Min Max Units taaw = ic -5 ALE Fatling Edge to WR Falling Edge 28 ns ww = ty + WS 15 WR Pulse Width 101 ns tuw = tc 10 Data Hold after Rising Edge of WR 7 ns ty = %te+wS-5 Data Valid before Rising Edge of WR 94 ns Note: Bus Output (Port A) C_ = 100 pF, CK2 Output C, = 50 pF, other Outputs CG. = 60 pF. AC parameters are tested using DC Characteristics Inputs and non CMOS Outputs. Measurement of AC Specifications is done with external clock driving CKI with 50% duty cycle. The capacitive load on CKO must be kept below 15 pF or AC measurement will ba skewed. Note: WS = twait * number of pre-programmed wait states. Minimum and maximum values are calculated from maximum operating frequency with one (1) wait State pre-programmed. Note 1: Do not design with this parameter unless CK| is driven with an active signal. When using a passive crystal circuit, CKI or CKO should not be connected to any external logic since any toad (besides the passive components in the crystal circuit) will affect the stability of tha crystal unpredictably. Note 2: These are not directly tasted parameters. Therefore the given min/max value cannot be guaranteed. It is, howaver, derived from measured parameters, HPC 16164/26164/36164/46164/16104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 and may be used for system dasign with a very high confidence level. Note 3: This is guaranteed by design and not tested. Ready/Hold Timing Symbol Parameter Min Max Units toan = atc + WS 50 Falling Edge of ALE 75 ns to Falling Edge of RDY tawp = tc RDY Pulse Width 100 ns tsate = %tco + 40 Falling Edge of HLD 118 ns to Rising Edge of ALE tuwp = te + 10 HiD Pulse Width 110 ns tap = Yatc +85 Rising Edge on HLD to 160 ns Rising Edge on HLDA tHaE = tc + 85 Falling Edge on HLD to 451 ns Falling Edge on HLDA ter Data Valid after 0 ns Failing Edge on HLDA =1 tge = Yate Bus Enable from 33 ne Rising Edge of HLDA *Note: tyac may be as long as (3i + 4ws + 72tc + 90) depending on which instruction is being executed, the addressing mode and number of wait states. tHac maximum value is for the optimal case. 4-5630 MHz MICROWIRE/PLUS Timing Symbol Parameter Min Max Units tuws MICROWIRE Setup Master Time 100 ns Slave 20 tuWH MICROWIRE Hold Master Time 20 ns Slave 50 tuwy MICROWIRE Output Master Valid Time 50 ns Slave 150 UPI Read/Write Timing Symbol Parameter Min Max Units tuas Address Setup Time to 10 ns Falling Edge of URD tUAH Address Hold Time from 40 ns Rising Edge of URD tRew URD Pulse Width 100 ns toe URD Falling Edge to Output Data Valid 60 ns top Rising Edge of URD to 5 35 ns Output Data Invalid (Note 4} torby RDRDY Delay from Rising 70 ns Edge of URD twow UWR Pulse Width 40 ns tups input Data Valid before 40 ns Rising Edge of UWR tUCH Input Data Hold after 15 ns Rising Edge of UWR ta WRRDY Delay from Rising 70 ns Edge of UWR Note: Bus Output (Port A) CL = 100 pF, CK2 Output CL = 50 F, other Outputs C_ = 80 pF. Note: AC testing inputs are driven at jq for a logic 1 and Vo, for a logic "0". Output timing measurements are made at Vox for a logic "1" and Vo, for a logic 9, Note 4: Guaranteed by design. Input and Output for AC Tests Vin V V vot TEST POINTS y OL OL Vit TL/DO/9682-40 4-57 7009P/P009E/009Z/F0091 /909b/P909E/P7909Z/F9091 /POLSb/POL9E/PO192/PO191 /P919b/P91L9E/P9L9C/F9L9LOdHHPC 16164/26164/36 164/46 164/16104/26 104/36 104/46 104/16064/26064/36064/46064/ 16004/26004/36004/46004 30 MHz A/D Converter Specifications voc = 5v +10% unless otherwise specified, Ta = 0C to +70C for HPC46164/HPC46104, 40C to + 85C for HPC36164/HPC36104, 40C to + 108C for HPC26164/HPC26104, 55C to + 125C for HPC16164/HPC16104 Symbol Parameter Min Max Unite Resolution 8 bits. fock Clock Frequency (Note 4) 0.1 1.6 MHz icon = 8.5/focik Conversion Time (Note 3) 5.3 ps VREF Reference Voltage Input (AGND = 0V) 3.0 Voc Vv Were 2 5 000M) Error (Note 1) % LSB Ryrer Reference Input Resistance (Note 5) 1.6 48 kn. DCG Common Mode Error ty LSB er ay 0% | _us Voltage Reference Tolerance (Vac) TBD LSB Port D Input Capacitance (Note 5) 35 pF Analog Input Voltage Range (Note 2) GND 0.05 Voc + 0.05 V On Channel Leakage 1 pA Off Channel Leakage 1 pA Note 1: Total unadjusted error includes offset, full-scale, and multiplexer errors. Note 2: 8 single-ended or 4 differential channels. Inharent sample and hold for single-ended inputs (GND = Pin 62). Nate 3: Conversion time does not include sample/hold time. Sample and hold time is 2/foc_K. Note 4: Clock supplied to A/D converter is derived from CKI. See A/D description for details. Note 5: This is guaranteed by design and not tasted. Timing Waveforms CKI, CK2, ALE Timing Diagram te f ter 4 cn | ~~ \ Fo toc car! tocoALeR toci car ALE tocaaLer -} *DCLALER *DCtALEF TL/DD/9682-~2Timing Waveforms (Continued) ee me \ PORT A \ ADEA OUT TT DATA GUT WALID \ ABOn OUT _ T fw ww y / wa K ] 7 x X TL/OD/9682-3 FIGURE 1. Write Cycle ALE PORT A i) TL/DD/9682-4 FIGURE 2. Read Cycle ALE ___(_=_)_ "a anon AG ow WA \ \ / 4 | ror | ton ow TL/DD/9682-5 FIGURE 3. Ready Mode Timing ME /} s+ | a |} +} __* __. mm | _. --__# __+ PORT A 7 tor { L tee TL/DO/9682-6 FIGURE 4. Hold Mode Timing 4-59 7009 /P009E/%009Z/#0091 /P909P/7909E/79092/P9091 /POLSb/POL9E/POL9Z/POL 91 /F9L9b/P91L9E/P9192/F9L9LOdHHPC 16164/26 164/36 164/46 164/16 104/26 104/36 104/46 104/16064/26064/36064/46064/16004/26004/36004/46004 Timing Waveforms (continued) P| 5K [LL taws tuwn | a be tay se 30 TL/DD/9682-39 FIGURE 5. MICROWIRE Setup/Hold Timing f ADDR UAO VALIO hows ws {Rew +} oD / PORT A TRESTATE TRI-STATE DATA OUT VALIO j>' + j-too APU We ONT} TL/DD/9682-9 FIGURE 6. UPI Read Timing tone: OW {ups |= typ TRISTATE + DATA IN | PORT A { ao > |~ ty WRRDY HPC RO OT) TL/DD/9662-10 FIGURE 7. UPI Write Timing 4-60Pin Descriptions The HPC16164 is available in 68-pin PLCC, LCC, LDCC, PGA, and TapePak packages. 1/0 PORTS Port A is a 16-bit bidirectional |/O port with a data diraction register to enable each separate pin to be individualiy de- fined as an input or output. When accessing external memo- ry, port A is used as the multiplexed address/data bus. Port B is a 16-bit port with 12 bits of bidirectional I/O similar in structure to Pert A. Pins B10, B11, B12 and B15 are gen- eral purpose outputs only in this mode. Port B may also be configured via a 16-bit function register BFUN to individually allow each pin to have an alternate function. Bo: TDX UART Data Output B1: B2: CKX UART Clock {Input or Output) B38: T2iO Timer2 I/O Pin B4: T310 Timer3 I/O Pin B5: SO MICROWIRE/PLUS Output B: SK MICROWIRE/PLUS Clock (Input or Output) B7: LDA Hold Acknowledge Output B&8: TSO Timer Synchronous Output Bg: TS1 Timer Synchronous Output B10: UAO Address 0 Input for UPI Mode B11: WRRDY Write Ready Output for UPI Mode B12: B13: TS2 Timer Synchronous Output B14: TS3 Timer Synchronous Output B15: ADADY Aead Ready Output for UP] Mode When accessing external memery, four bits of port B are used as follows: B10: ALE Address Latch Enable Output B11: WR Write Output B12: HBE High Byte Enable Output/ Input (sampled at reset) B15: RD Read Output Port | is an 8-bit input port that can be read as general purpese inputs and is also used for the following functions: 10: 11: NMI Nonmaskable Interrupt Input 12: INT2 Maskable Interrupt/Input Capture/URD 13: INTS Maskable Interrupt/Input Capture/OWR 14: INT4 Maskable Interrupt/Input Capture 16: S| MIGROWIRE/PLUS Data Input 16: RDX UART Data Input \7: Port D is an 8-bit input port that can be used as general purpose digital inputs or as analog channel inputs for the A/D converter. These functions of Port D are mutually ex- clusive and under the control of software. Port P is a 4-bit output port that can be used as genera! purpose data, or selected to be controlled by timers 4 through 7 in order to generate frequency, duty cycle and pulse width modulated outputs. POWER SUPPLY PiNS Veco. and Voce Positive Power Supply GND Ground for On-Chip Logic DGND Ground for Output Buffers Note: There are two electrically connected Voc pins on the chip, GND and DGND are electrically isolated. Both Voc pins and both ground pins must be used. CLOCK PINS CKI CKO The Chip System Clock Input The Chip System Clock Output (inversion of CK Pins CKI and CKO are usually connected across an external crystal. CK2 OTHER PINS wo Clock Output (CKI divided by 2) This is an active low open drain output that signals an illegal situation has been detected by the Watch Dog logic. Bus Cycle Status Output: indicates first op- code fetch. Bus Cycle Status Output: indicates machine states (skip, interrupt and first instruction cy- cle). is an active low input that forces the chip to restart and sets the ports in a TRI-STATE mode. has two uses, selected by a software bit. Its either a READY input to extend the bus cycle for slower memcries, or a HOLD request input to put the bus in a high impedance state for DMA purposes. A/D converter reference voltage input. External memory enable (active high) disables internai ROM and maps it to external memory. El External interrupt with vector address FFF1:FFFO. (Rising/falling edge or high/low level sensitive). Alternately can be configured as 4th input capture. has two uses, selected by a software bit. It can be an external active low interrupt which is internally ORed with the UART interrupt with vector address FFF3:FFF2 or it can be the analog ground for the A/D converter. ST1 ST2 RESET RDY/HLD VREF EXM AGND/EX c 4-61 009% /F009E/0092/P0091 /909%/909E/P9097/P909L /POLSb/P0l9E/P0L92/POLOL/P919b/P919E/P9192/791 91 0dHHPC 16164/26 164/36 164/46 164/16104/26 104/36 104/46 104/ 16064/26064/36064/46064/16004/26004/36004/46004 Connection Diagrams Piastic, Leadiess and Leaded Chip Carrlers AGND/ 4 ty EU B, By Is ty) Vorz2 Bp Op Be Bs 07 GND Oe WO cK HPC16164 FRPP OS SPP Pes EXM Rory Bis 813 81; Bo Ars Ans Any Ap Vec1 Pin Grid Array Pinout 77 INDEX MARK & | 'y YogpBy Bo By Bg WO CKI DOOBOOSEG Ig 1g tpA@D/B, By By By GND h@ OOOO BBG @0 Dodd 430; lh @ &h, dy @ @@ Os STI 6} 6g ST2 H@ @o, RESET 63 69 Ay Ds G9 Dg Ay @ GDA, Dy @ @ EXM As @) GDA, PoG@d GD Py 5 @ @A, Poa GPs by @ @ RY VREF 8 G8) G9 G2 G9 SB 68 GD @ @ G@DGND By 4 By 2 Bip Bg Aq Ai2 Ato Ag CK2 2AOSSHaAaO6 Bys, By 3B yy By AysAqs Ayy AgVocy TL/DD/9682- 12 B 8 14 Baz Bye By Ata Ay2 Arg Ag vupoveese-11 Top View Top View (looking ea oleate ue vote PC Board} Order Number HPC16164E, EL or V See NS Package Number UGA See NS Package Number E68B, EL68A or V68A TapePak Package VOMNFMN So WISN =O 7 qeannes'ceaaee tee TL/DD/9482-36 Top View Order Number HPC 16164TP Available in TapePak 4-62Operating Modes To offer the user a variety of I/O and expanded memory options, the HPC16164 and HPC16104 have four operating modes. The ROMless HPC16104 has one mode of opera- tion. The various modes of operation are determined by the state of both the EXM pin and the EA bit in the PSW regis- ter. The state of the EXM pin determines whether on-chip ROM will be accessed or external memory will be accessed within the address range of the on-chip ROM. The on-chip ROM range of the HPC16164 is C000 to FFFF (16k bytes). The HPC16104 has no on-chip ROM and is intended for use with external memory for program storage. A logic 0 state on the EXM pin will cause the HPC device to address on- chip ROM when the Program Counter (PC) contains ad- dresses within the on-chip ROM address range. A lagic 1 state on the EXM pin will cause the HPC device to address memory that is external to the HPC when the PC contains on-chip ROM addresses. The EXM pin should always be pulled high (logic 1") on the HPC16104 because no on- chip ROM is available. The function of the EA bit is to deter- mine the legal addressing range of the HPC device. A logic 9 state in the EA bit of the PSW register does two thingsaddresses are limited to the on-chip ROM range and on-chip RAM and Register range, and the illegal ad- dress detection feature of the Watchdog logic is engaged. A logic 1" in the EA bit enables accesses to be made anywhere within the 64k byte address range and the illegal address detection feature of the Watchdog logic is dis- abled. The EA bit should be set to 1 by software when using the HPC16104 to disable the illegal address detec- tion feature of Watchdog. Ali HPC devices can be used with external memory. Exter- nal memory may be any combination of RAM and ROM. Both 8-bit and 16-bit external data bus modes are available. Upon entering an operating mode in which extemal memory is used, port A becomes the Address/Data bus. Four pins of port B become the control lines ALE, RD, WR and HBE. The High Byte Enable pin (HBE) is used in 16-bit mode to select high order memory bytes. The RD and WR signals are only generated if the selected address is off-chip. The 8-bit mode is selected by pulling HBE high at reset. If HBE is left float- ing or connected to a memory device chip select at reset, the 16-bit mode is entered. The following sections describe the operating modes of the HPC16164 and HPC16104. Note: The HPC devices use 16-bit words for stack memory. Therefore, when using the 8-bit mode, User's Stack must be in internal RAM. HPC 16164/HPC 16064 Operating Modes SINGLE CHIP NORMAL MODE In this mode, the HPC16164/HPC16064 functions as a self- contained microcomputer (see Figure 77) with all memory (RAM and ROM) on-chip. It can address internal memory only, consisting of 16k bytes of ROM (C000 to FFFF) and 512 bytes of on-chip RAM and Registers (0000 to O2FF). The illegal address detection feature of the Watchdog is enabied in the Single-Chip Norma! mode and a Watchdag Output (WO) will occur if an attempt is made to access ad- dresses that are outside of the on-chip ROM and RAM range of the device. Ports A and B are used for {/O func- tions and not for addressing external memory. The EXM pin and the EA bit of the PSW register must both be logic 0 to enter the Single-Chip Normal mode. EXPANDED NORMAL MODE The Expanded Normal mode of operation enables the HPC16164 to address external memory in addition to the on-chip ROM and RAM (see Table II). Watchdog illegal ad- dress detection is disabled and memory accesses may be made anywhere in the 64k byte address range without trig- gering an illegal address condition. The Expanded Normal mode is entered with the EXM pin pulled low (logic 0) and setting the EA bit in the PSW register to 1. SINGLE-CHIP ROMLESS MODE In this mode, the on-chip mask programmed ROM of the HPC16164 is not used. The address space corresponding to the on-chip ROM is mapped into external memory so 16k of external memory may be used with the HPC16164 (see Table Il). The Watchdog circuitry detects illegal addresses (addresses not within the on-chip ROM and RAM range). The Single-Chip ROMless mode is entered when the EXM pin is pulled high (logic 1") and the EA bit is logic 0. EXPANDED ROMLESS MODE This mode of operation is similar to Single-Chip ROMless mode in that no on-chip ROM is used, however, a full 64k bytes of external memory may be used. The illegal address detection feature of Watchdog is disabled. The EXM pin must be pulled high (logic 1") and the EA bit in the PSW register set to 1 to enter this mode. TABLE Il. HPC 16164 Operating Modes Operating EXM j EA Memory Mode Pin | Bit Configuration Single-Chip Normal 0 0 | CO00:FFFF on-chip Expanded Normal 0 1 | CO00:FFFF on-chip 0300:BFFF off-chip Single-Chip ROMiess 1 0 | CO00:FFFF off-chip Expanded ROMiess 1 1 | 0300:FFFF off-chip Note: in all operating modes, the on-chip RAM and Registers (0000:02FF} may be accessed. 4-63 P009b/P009E/P009Z/F0091 /P909b/79096/F909Z/P9091 /P019b/P0L9E/FOL9Z/FOL 9/91 9b/ P919/P9192/P9L9SLOdHHPC 16164/26 164/36 164/46164/ 16104/26104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 PortsA &B The highly flexible A and B ports are similarly structured. The Port A (see Figure 7), consists of a data register and a direction register. Port B (see Figures & 9 and 70) has an alternate function register in addition to the data and direc- tion registers. All the control registers are read/write regis- ters. The associated direction registers allow the port pins to be individually programmed as inputs or outputs. Port pins se- lected as inputs, are placed in a TRI-STATE mode by reset- ting corresponding bits in the direction register. mn) A write operation to a port pin configured as an input causes the value to be written into the data register, a read opera- tion returns the vaiue of the pin. Writing to port pins config- ured as outputs causes the pins to have the same value, reading the pins returns the value of the data register. Primary and secondary functions are multiplexed onto Port B through the alternate function register (BFUN). The sec- ondary functions are enabled by setting the corresponding bits in the BFUN register. TALSTATE Pw PORT A bie (DATA REGISTER} {DIRECTION y paar ER FAP CP EBMAZ i- q i WRITE REGISTER SELECT + i READ PORT A TL/DD/9682-13 FIGURE 7. Port A: 1/0 Structure PORT B BIT (DATA REGISTER) ALTERNATE qn FUNCTION INPUT PIN q WRITE PORT B ~eyFreanas=z ALTERNATE __y FUNCTION OUTPUT SELECT > > f Xl "1 READ DIR B DIR B BIT DIRECTION D EGISTER) A | T WRITE DIR B A 8] SELECT u + $s READ PORT B BFUN BIT (ALTERNATE NCTION) { WRITE BFUN ns READ BFUN TL/DD/9682-14 FIGURE 8. Structure of Port B Pins BO, 81, B2, B5, BG and B7 (Typical Pins) 4-64Ports A & B (Continued) ALTERNATE ~ FUNCTION INPUT PIN PORT B BIT i (DATA REGISTER) L. a LOAD | TOGGLE \ TIMER N UNDERFLOW T PULSE E R N A L D A T READ BFUN A wr B Seuect | u $ READ PORT & | DIR B BIT DIRECTION EGISTER} WRITE DIR 8 READ DIR B TL/DD/9682-15 FIGURE 9. Structure of Port B Pins B3, 84, B8, B9, 813 and B14 (Timer Synchronous Pins) ALTERNATE pp SN READ BFUN FUNCTION INPUT on a cuncn gl ERNATE PORT B BIT INCTION OUTPUT (DATA REGISTER) > SELECT : WRITE PORT B 1 y T ry E READ DIR B R N OR B BT A DIRECTION L GISTER) | a o WRITE DIR 8 > runes A NCTION T AL 4 U B12 (*HBE) ONLY $ READ PORT B pooqeccce eaweaece - BFUN BT (ALTERNATE ' NCTION) ' MODE. 18-BIT Lapa cece ween wee WRITE BFUN "| woDe Lt EXPANDED OR ROMLESS a 4 e ' o TL/DD/9682-16 FIGURE 10. Structure of Port B Pins B10, B11, B12 and B15 (Pins with Bus Control Roles) 4-65 7009P/P009E/#009Z/F0091 /P909b/7909E/F909Z/P9091 /POl 9b/F01 9E/F0192/POLOL /P9L9b/P9L9E/b9192/P91910dHHPC 16164/26 164/36 164/46 164/16 104/26 104/36 104/46 104/ 16064/26064/36064/46064/16004/26004/36004/46004 HPC16164 Operating Modes (continued) [2 nm rats EY mez] mur HPC16164 K=> PORTA FIGURE 11. Single-Chip Mode ROMLESS ROM vq eExm TL/DD/9682-17 y PORT I PORT D PORT B PORT P 4 q BE PORT A He yg s 1508 + HPC16464 ) LATCH , _ MEMORY Ro- Az Aa-Ats Dg-Og FIGURE 12. 3-Bit External Memory TL/DD/ 9682-18 4-66HPC 16164 Operating Modes (continued) ROMLESS ROM oe eExm PORT | co Aeris LATCH LU a a Pont 0 co ALE 9 HPC16164 POAT P < 4 Ag-Ay LATCH Ar-Ais MEMORY WH ie cs i+ aD + 7 Ar-Ats MEMORY WR 7X2 De-0y Ay TL/DD/9682-19 FIGURE 13. 16-Bit External Memory HPC 16104/HPC 16004 Operating Modes EXPANDED ROMLESS MODE (HPC 16104/HPC 16004) Because the HPC16104 has no on-chip ROM, it has only one mode of operation, the Expanded ROMleass Mode. The EXM pin must be pulled high (logic 1) on power up, the EA bit in the PSW register should be set to a 1. The HPC16104/HPC16004 is a ROMless device and is intended for use with external memory. The external memory may be any combination of ROM and RAM. Up to 64k bytes of ex- ternal memory may be accessed. It is necessary to vector on reset to an address between C000 and FFFF, therefore the user should have external memory at these addresses. The EA bit in the PSW register must immediately be set to 4 at the beginning of the user's program to disabie illegal address detection in the Watchdog logic. TABLE III. HPC 16104 Operating Modes Operating EXM | EA Memory Mode Pin | Bit Canfiguration Expanded ROMIiess 1 1 | 0300:FFFF off-chip Note: The on-chip RAM and Registers (0000:02FF) of the HPC16104 may be accessed at all times. Wait States The internal ROM can be accessed at the maximum operat- ing frequency with one wait state. With 0 wait states, internal ROM accesses are limited to 4 fc max. The HPC16164 provides four software selectable Wait States that allow access to slower memories, The Wait States are selected by the state of two bits in the PSW register. Additionally, the RDY input may be used to extend the instruction cycle, allowing the user to interface with slow memories and peripherals. Power Save Modes Two power saving modes are available on the HPC16164: HALT and IDLE. In the HALT mode, all processor activities are stopped. In the IDLE mode, the on-board oscillator and timer TO are active but all other processor activities are stopped. In either mode, all on-board RAM, registers and 1/0 are unaffected. HALT MODE The HPC16164 is placed in the HALT mode under software control by setting bits in the PSW. All processor activities, including the clock and timers, are stopped. In the HALT mode, power requirements for the HPC16164 are minimal and the applied voltage (Vcc) may be decreased without altering the state of the machine. There are two ways of exiting the HALT mode: via the RESET or the NMi. The RESET input reinitializes the processor. Use of the NMI in- put will generate a vectored interrupt and resume operation from that point with no initialization. The HALT mode can be enabled or disabled by means of a control register HALT enable. To prevent accidental use of the HALT mode the HALT enable register can be modified only once. IDLE MODE The HPC16164 is placed in the IDLE mode through the PSW. In this mode, all processor activity, except the on- board oscillator and Timer TO, is stopped. As with the HALT #0098 /7009E/7009Z/#009! /909/79098/7909Z/F9091 /P01 9b /F01 96/F01.92/P0L91 /P91L9P/P919E/F9192/P9L9LIdHHPC 16 164/26 164/36 164/46164/16104/26104/36104/46104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 Power Save Modes (continued) mode, the processor is returned to full operation by the RESET or NMI inputs, but without waiting for osciliator stabi- lization. A timer TO overflow will also cause the HPC16764 to resume normal operation. HPC 16164 Interrupts Compiex interrupt handling is easily accomplished by the HPC16164s vectored interrupt scheme. There are eight possible interrupt sources as shown in Table IV. TABLE IV. Interrupts Vector Interrupt Arbitration Address Source Ranking $FFFF:FFFE | RESET 0 $FFFD:FFFC| Nonmaskable external on 1 rising edge of I1 pin $FFFB:FFFA | External interrupt on [2 pin 2 $FFF9:FFF6 | External interrupt on [3 pin 3 $FFF7:FFF6 | External interrupt on {4 pin 4 $FFF5:FFFA4 | Overtlow on internal timers 5 $FFF3:FFF2 | Internal by on-board peripherals 6 or external on EXUI $FFF1:FFFO | External interrupt on El pin 7 Interrupt Arbitration The HPC16164 contains arbitration logic to determine which interrupt will be serviced first if two or more interrupts occur simultaneously. The arbitration ranking is given in Table IV. The interrupt on Reset has the highest rank and is serviced first. Interrupt Processing Interrupts are serviced after the current instruction is com- pleted except for the RESET, which is serviced immediately. RESET and EXUI are level-LOW-sensitive interrupts and El is programmable for edge-(RISING or FALLING) or level- (HIGH or LOW) sensitivity. Ail other interrupts are edge-sen- sitive. NMI is positive-edge sensitive. The external interrupts on 12, I3 and |4 can be software selected to be rising or falling edge. External interrupt (EXUI) is shared with the on- board peripherals, UART and A/D. The EXUI interrupt is lavel-LOW-sensitive. To select this interrupt, disable the ERI and ET! UART interrupts by resetting these enable bits in the ENUI register and disable the A/D function by resetting the ADEN bit in the A/D control register #3 (CR3). To se- lect the on-board peripherais interrupt, leave this pin floating or tie it high if the A/D function is disabled. If the A/D func- tion is enabled, this pin becomes the analog ground (AGND). interrupt Control Registers The HPC16164 allows the various interrupt scurces and conditions to be programmed. This is done through the vari- ous control registers. A brief description of the differant con- trol registers is given below. INTERRUPT ENABLE REGISTER (ENIR) RESET and the External Interrupt on 11 are non-maskable interrupts. The other interrupts can be individually enabled or disabled. Additionally, a Global interrupt Enable Bit in the ENIR Register allows the Maskable interrupts to be collec- tively enabled or disabled. Thus, in order for a particular interrupt to request service, both the individual enable bit and the Global Interrupt bit (GIE} have to be set. INTERRUPT PENDING REGISTER (IRPD) The IRPD register contains a bit allocated for each interrupt vector. The occurrence of specified interrupt trigger condi- tions causes the appropriate bit to be set. There is no indi- cation of the order in which the interrupts have been re- ceived. The bits are set independently of the fact that the interrupts may be disabled. IRPD is a Read/Write register. The bits corresponding to the maskable, external interrupts are normally cleared by the HPC16164 after servicing the interrupts. For the interrupts from the on-board peripherals, the user has the responsibility of resetting the interrupt pending flags through software. The NMI bit is read only and 12, 13, and |4 are designed as to only allow a zero to be written to the pending bit (writing a one has no affect). A LOAD IMMEDIATE instruction is to be the only instruction used to clear a bit or bits in the IRPG register. This allows a mask to be used, thus ensuring that the other pending bits are not affected. INTERRUPT CONDITION REGISTER (IRCD) Three bits of the register select the input polarity of the external interrupt on 12, 13, and 14. Servicing the Interrupts The Interrupt, once acknowledged, pushes the program counter (PC) onto the stack thus incrementing the stack painter (SP) twice. The Global Interrupt Enable bit (GIE) is copied into the CGIE bit of the PSW register; it is then reset, thus disabling further interrupts. The program counter is loaded with the contents of the memory at the vector ad- dress and the processor resumes operation at this point. At the end of the interrupt service routine, the user does a RETI instruction to pop the stack and re-enable interrupts if the CGIE bit is set, or RET to just pop the stack if the CGIE bit is clear, and then returns to the main program. The GIE bit can be set in the interrupt service routine to nest inter- rupts if desired. Figure 14 shows the interrupt Enable Logic. Reset The RESET input initializes the processor and sets ports A and B in the TRI-STATE condition and Port P in the LOW state. RESET is an active-low Schmitt trigger input. The processor vectors to FFFF:FFFE and resumes operation at the address contained at that memory location (which must correspond to an on board location). The Reset vector ad- dress must be between C000 and FFFF when using the HPG16104. 4-68HPC 16164/26 164/36 164/46 164/16 104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 02-2896/00/1L <C id Nduaini 21607] }dnwiaqu] Jo Weabeig 4oo!g "yt SUNDA Servicing the Interrupts (Continued) oe <p . oo <tHa} 4F a- me a [ | a : CF ott va G - - | | Ct a CH CH . C# CF aN ANI | | Le) = INO] | | Le] = [ |}a 3 iM IN IN GAL Hdldd a | Lom) asi 7a on <p] 4-69HPC 16 164/26 164/36 164/46 164/ 16104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 Timer Overview The HPC16164 contains a powerful set of flexible timers enabling the HPC16164 to perform extensive timer func- tions; not usually associated with microcontrollers. The HPC16164 contains nine 16-bit timers. Timer TO is a free-running timer, counting up at a fixed CKI/16 (Clock In- put/16) rate. It is used for Watchdog logic, high speed event capture, and to exit from the IDLE mode. Consequently, it cannot be stopped or written to under software control. Tim- er TO permits precise measurements by means of the cap- ture registers I2CR, ICR, and I4CR. A control bit in the ragister TMMODE configures timer T1 and its associated register R1 as capture registers ISCR and !2CR. The cap- ture registers I2CR, I3CR, and |4CR respectively, record the value of timer TO when specific events occur on the inter- rupt pins 12, 13, and 14. The control register IRCD programs the capture registers to trigger on either a rising edge or a falling edge of its respective input. The specified edge can also be programmed to generate an interrupt (see Figure 15). The HPC16164 provides an additional 16-dit free running timer, T8, with associated input capture register EICR (Ex- ternal Interrupt Capture Register) and Configuration Regis- ter, EICON. EICON is used to select the mode and edge of the Ei pin. EICR is a 16-bit capture register which records the value of T8 (which is identical to TO) when a specific event occurs on the El pin. The timers T2 and T3 have selectable clock rates. The clock input to these two timers may be selected from the following two sources: an external pin, or derived internally by dividing the clock input. Timer T2 has additional capabili- ty of being clocked by the timer T3 underflow. This allows the user to cascade timers T3 and T2 into a 32-bit timer/ counter. The control register DIVBY programs the clock in- put to timers T2 and T3 (see Figure 76). The timers T1 through T7 in conjunction with their registers form Timer-Register pairs. The registers hold the pulse du- ration values. All the Timer-Register pairs can be read from or written to. Each timer can be started or stopped under software control. Once enabled, the timers count down, and upon underflow, the contents of its associated register are automatically loaded into the timer. TO WATCHDOG CKI/ 16 ft CKI/ 16 ae at) tr > T0 OWL Se tt 12 re tamara 5 8 ICR ttles D A 1 ' T ! <>) wr fet + feis t ' B greens ' ' Koy RI tess s deenes SOFTWARE at CONFIGURED ! owswon | SOFTWARE Wen eccene Tt 8 CONFIGURED =?> 71 UNFL wm eae, me CKI/I6 TU/DD/9682-21 FIGURE 15. Timers TO, T1 and T8 with Four Input Capture Registers SYNCHRONOUS OUTPUTS The flexible timer structure of the HPC16164 simplifies puise generation and measurement. There are four syn- chronous timer outputs (TSO through TS3) that work in con- junction with the timer T2. The synchronous timer outputs can be used either as regular outputs or individually pro- grammed to toggle on timer T2 underflows (see Figure 76). Lncsonlp 155 > 13, > TE: re TEs - 120 1 a eaew eee amaze TL/DD/9682-22 FIGURE 16. Timers T2-T3 Block 4-70Timer Overview (continuec) Timer/register pairs 4-7 form four identical units which can generate synchronous outputs on port P (see Figure 77). Maximum output frequency for any timer output can be ob- tained by setting timer/register pair to zero. This then will produce an output frequency equal to 14 the frequency of the source used for clocking the timer. Nive a T4-37 UNFL - 14-17 ol FF > id Le ate Pw MODE Ud Timer-Register pairs 4 through 7 are identical TL/OD/9682-23 FIGURE 17. Timers T4-T7 Block Timer Registers There are four control registers that program the timers. The divide by (DIVBY) register programs the clock input to tim- ers T2 and T3. The timer mode ragister (TMMODE) contains control bits to start and stop timers 714 through T3. It also contains bits to latch, acknowledge and enable interrupts from timers TO through T3. The control register PWMODE similarly programs the pulse width timers T4 through T7 by allowing them to be started, stopped, and to latch and en- able interrupts on underflows. The PORTP register contains bits to preset the outputs and enable the synchronous timer output functions. Timer Applications The use of Pulse Width Timers for the generation of various waveforms is easily accomplished by the HPC16164. Frequencies can be generated by using the timer/register pairs. A square wave is generated when the register value is a constant. The duty cycle can be controlled simply by changing the register value. T20UT [Te -f<-Tr-v4 TL/DD/9882-24 FIGURE 18. Square Wave Frequency Generation Synchronous outputs based on Timer T2 can be generated on the 4 outputs TSO-TS3. Each output can be individually programmed to toggle on T2 underflow. Register R2 con- tains the time delay between events. Figure 79 is an exam- ple of synchronous pulse train generation. Watchdog Logic The Watchdog Logic monitors the operations taking place and signals upon the occurrence of any illegal activity. The illegal conditions that trigger the Watchdog logic are poten- a -{<Th | m= | fn Ts1 | jaTco[+Ta->| | { 182 | je Te>l<-th| | L 1s3 tge] >t -Th TL/DD/9682-25 FIGURE 19. Synchronous Pulse Generation tially infinite loops and illegal addresses. Should the Watch- dog register not be written to before Timer TO overflows twice, or more often than once avery 4096 counts, an infi- nite loop condition is assumed to have occurred. An illegal condition also occurs when the processor generates an ille- ga! address when in the Single-Chip modes. Any illegal condition forces the Watchdog Output (WO) pin low. The W6 pin is an open drain output and can be connected to the RESET or NMi inputs or to the users external logic. Note: See Operating Modes for dotails. MICROWIRE/PLUS MICROWIRE/PLUS is used for synchronous serial data communications (see Figure 20}. MICROWIRE/PLUS has an 8-bit paraliel-loaded, serial shift register using SI as the input and SO as the output. SK is the clock for the serial shift register (SIO). The SK clock signal can be provided by an internat or external source. The internal clock rate is pro- grammable by the DIVBY register. A DONE flag indicates when the data shift is completed. ~ > so esi 0 | $1 REGISTER SHIFT CLOCK CLOCK SELECT +3n ie ovey ft L_. x TS UNBEAFLOW CKI/16 =p voce F487 -rEzEwAaz TL/DD/9682-26 FIGURE 20. MICROWIRE/PLUS The MICROWIRE/PLUS capability enables it to interface with any of National Semiconductors MICROWIRE periph- erals (i.e., A/D converters, display drivers, EEPROMs). 4-71 009%/P009E/F0097/P009I./F909/P909E/79092/ P9091 /POL9b/POL9E/O1 97/0191 /POLOb/FSL9E/P9197/POLSLOdHHPC 16164/26 164/36 164/46 164/16 104/26104/36 104/46 104/16064/26064/36064/46064/16004/26004/36004/46004 MICROWIRE/PLUS Operation The HPC16164 can enter the MICROWIRE/PLUS mode as the master or a slave. A control bit in the IRCD register determines whether the HPC16164 is the master or slave. The shift clock is generated when the HPC16164 is config- ured as a master. An externally generated shift clock on the SK pin is used when the HPC16164 is configured as a slave. When the HPC16164 is a master, the DIVBY register pro- grams the frequency of the SK clock. The DIVBY ragister allows the SK clock frequency to be programmed in 15 se- lectable steps from 64 Hz to 1 MHz with CKI at 16.0 MHz. The contents of the SIO register may be accessed through any of the memory access instructions. Data waiting to be transmitted in the SIO register is clocked out on the falling edge of the SK clock. Serial data on the SI pin is clocked in on the rising edge of the SK clock. MICROWIRE/PLUS Application Figure 21 illustrates a MICROWIRE/PLUS arrangement for an automotive application. The microcontroller-based sys- HPC16164 MASTER SYSTEM vo tem could be used to interface to an instrument cluster and various parts of the automobile. The diagram shows two HPC16164 microcontrollers interconnected to other MI- CROWIRE peripherals. HPC16164 #1 is set up as the mas- ter and initiates all data transfers. HPC16164 #2 is set up as a slave answering to the master. The master microcontroller interfaces the operator with the system and could also manage the instrument cluster in an automotive application. information is visually presented to the operator by means of an LCD display controlled by the COP472 display driver. The data to be displayed is sent serially to the COP472 over the MICROWIRE/PLUS fink. Data such as accumulated mileage could be stored and re- trieved from the EEPROM COP494. The slave HPC16164 could be used as a fuel injection processor and generate timing signals required to operate the fuel valves. The mas- ter processor could be used to periodicatly send updated values to the slave via the MICROWIRE/PLUS link. To speed up the response, chip select logic is implemented by connecting an output from the master to the external inter- rupt input on the slave. HPC16164 SLAVE SYSTEM wo SK ot STATUS DISPLAY cs DISPLAY ORIVER SK oO DO Copasa cs e? ROM TL/OD/9682-27 FIGURE 21. MICROWIRE/PLUS ApplicationHPC16164 UART The HPC16164 contains a software programmable UART. The UART (see Figure 22) consists of a transmit shift regis- ter, a receiver shift register and five addressable registers, as follows: a transmit buffer register (TBUF}, a receiver buff- er register (RBUF), a UART control and status register (ENU), a UART receive contro! and status register (ENUR) and a UART interrupt and clock source register (ENUI). The ENU register contains flags for transmit and receive func- tions; this register also determines the length of the data frame (8 or 9 bits) and the value of the ninth bit in transmis- sion. The ENUR register flags framing and data overrun er- rors while tha UART is receiving. Other functions of the ENUR register include saving the ninth bit received in the data frame and enabling or disabling the UARTs Wake-up Mode of operation. The determination of an internal or ex- ternal clock source is done by the ENUI register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. The baud rate clock for the Receiver and Transmitter can be selected for either an internal or external source using two bits in the ENUI register. The internal baud rate is pro- grammed by the DIVBY register. The baud rate may be se- lected from a range of 8 Hz to 128 kHz in binary steps or T3 underflow. By selecting a 9.83 MHz crystal, all standard baud rates from 75 baud to 38.4 kBaud can be generated. The external baud clock source comes from the CKX pin. The Transmitter and Receiver can be run at different rates by selecting one to operate from the internal clock and the other from an external source. The HPC16164 UART supports two data formats. The first format for data transmission consists of one start bit, eight data bits and one or two stop bits. The second data format for transmission consists of one start bit, nine data bits, and one or two stop bits. Receiving formats differ from transmis- sion only in that the Receiver always requires only one stop bit in a data frame. UART Wake-up Mode The HPC16164 UART features a Wake-up Mcde of opera- tion. This mode of operation enables the HPC16164 to be networked with other processors. Typically in such environ- ments, the messages consist of addresses and actual data. Addresses are specified by having the ninth bit in the data frame set to 1. Data in the message is specified by having the ninth bit in the data frame reset to 0. The UART monitors the communication stream looking for addresses. When the data word with the ninth bit set is received, the UART signals the HPC 16164 with an interrupt. The precessor then examines the content of the receiver buffer to decide wheather it has been addressed and whether to accept subsequent data. aparo rePpEAnmo4isz RDX v RECEIVE SHIFT REGISTER +6 4 ub RBUF TRANSMIT SHIFT REGISTER > TDX +16 co TBUF CLOCK SELECT CKI/16 t_, CKX 73 UNFL = DIVBY > ENUI FIGURE 22. UART Block Diagram TL/DD/S682-28 4-73 #009P/P009E/P0097/P0091 /P909/P909E/P9097/P9091 /POL 9b/POL9E/POL9Z/POLSI /919b/P919E/P9L92/P91919dHLa0d A/D Converter Operation 62-2996/00/NL STANNVHO sdvd =<) Ni IndNi 2 a/v 19 anov NONKOD 0/ 2m_| (QNO)SSA d0A we6eid 401g C/V ez FHNDI4 SNS VIVO TWNUSLNI JdH EdTHD" LAD SZLSISIY TOULNOD SN6 TOULNOD a/ (@ x a) SU3ISIOIY inod Lins33 + 1901 LAMAN 0/ 1d Maan w199 wavosaud SMG TOULNOD G/ (9*u9) Nagy xnn NOISUBANGD LYVLS el ne /| MOTIHIONN ZL 009%/P009E/P0092/P009! /P909h/P909E/F9092/F9091 /P0L9b/POLSE/POL92/POl SL /POL9b/P91 96/79192/791 91 DdH 4-74A/D Converter Operation (continued) The HPC16164 has an on-board eight-channel 8-bit Analog to Digital converter. Conversion is performed using a suc- cessive approximation technique. The A/D converter cell can operate in single-ended mode where the input voltage is applied across one of the eight input channels (DO-D7) and AGND or in differential mode where the input voltage is applied across two adjacent input channels. The A/D con- verter will convert up to eight channels in single-ended mode and up to four channel-pairs in differential mode. OPERATING MODES The operating modes of the converter are selected by 4 bits called ADMODE (CR2.4-7). Associated with the eight input channels in single-ended mode are eight result registers, one for each channel. The A/D converter can be pro- grammed by software to convert on any specific channel storing the result in the result register associated with that channel. It can also be programmed to stop after one con- version or to convert continuously. If a brief history of the signal on any specific input channel is required, the convert- er can be programmed to convert on that channel and store the consecutive results in each of the result registers before stopping. As a final configuration in single-ended mode, the converter can be programmed to convert the signal on each input channel and store the result in its associated result ragister continuously. Associated with each even-odd pair of input channels in differential mode of operation are four result register-pairs. The A/D converter performs two conversions on the select- ed pair of input channels. One conversion is performed as- suming the positive connection is made to the even channel and the negative connection is made to the following odd channel. This result is stored in the result register associat- ed with the even channel. Another conversion is performed assuming the positive connection is made to the odd chan- nel and the negative connection is made to the preceding even channel. This result is stored in the result register as- sociated with the odd channel. This technique dogs not re- quire that the programmer know the polarity of the input signal. If the even channel result register is non-zero (mean- ing the odd channel result register is zero}, then the input signal is positive with respect to the odd channel. If the odd channel result register is non-zero (meaning the even chan- nel result register is zero), then the input signal is positive with respect to the even channel. The same operating modes for single-ended operation also apply when the inputs are taken from channel-pairs in difter- ential mode. The programmer can configure the A/D to con- vert on any selected channel-pair and store the result in its associated result register-pair then stop. The A/D can also be programmed to do this continuously. Conversion can also be done any channel-pair storing the result into four result register-pairs for a history of the differential input. Fi- nally, all input channel-pairs can be converted continuously. The final mode of operation suppresses the external ad- dress/data bus activity during the single conversion modes. These quiet modes of operation utilize the RDY function of the HPC Core to insert wait states in the instruction being executed in order to limit digital noise in the environment due to external bus activity when addressing external mem- ory. The overall effect is to increase the accuracy of the A/D. CONTROL The conversion clock supplied to the A/D converter can be selected by three bits in CR1 used as a prescaler on CKI. These bits can be used to ensure that the A/D is clocked as fast as possible when different external crystal frequencies are used. Controlling the starting of conversion cycles in each of the operating modes can be done by four different methods. The method is selected by two bits called SC (CR3.0-1). Conversion cycles can be initiated through soft- ware by resetting a bit in a control register, through hard- ware by an underflow of Timer T2, or externally by a rising or falling edge of a signal input on I7. INTERRUPTS The A/D converter can interrupt the HPC when it completes a conversion cycle if one of the non-continuous modes has been selected. If one of the cycle modes was selected, then the converter will request an interrupt after eight conver- sions. If one of the one-shot modes was selected, then the converter will request an interrupt after every conversion. When this interrupt is generated, the HPC vectors to the on- board peripheral interrupt vector location at address FFF2. The service routine must then determine if the A/D convert- er requested the interrupt by checking the A/D done flag which doubles as the A/D interrupt pending flag. REGISTER MAP The A/D converter status and control registers and the re- sult registers are detailed as follows: Control Register #1 (CR1) | | Prescaler(3) | Result Reg pnitr(4) | msb Isb byte at location 0100 Result Register pointerThese four bits are read/only by the software. In all the operating modes that are single channel or single channel-pair, this pointer gets the value of the Channel Select bits (CR2.03) and remains constant. In the operating modes that work on multiple channels or mul- tiple channel-pairs, this pointer gets initialized to zero and will change to reflect the current channel that is being con- verted (default value on power-up is 0000). PrescalerThese three bits are used to select the clock (CCLK) supplied to the SAR in the A/D converter cell. The maximum clock that can be supplied is 1.67 MHz and the minimum is 100 kHz. Therefore, these bits can be used to ensure that the A/D is clocked as fast as posible at different external crystal! frequencies. 000 = stop the clock (CCLK) to the A/D ceil (default vaiue On power-up) 011 = use CKI/4 to allow max CKI of 6.66 MHz 010 = use CKI/8 to allow max CKI of 13.33 MHz 111 = use CKI/12 to allow max CKI of 20 MHz 101 = use CKI/16 to allow max CKI of 26.66 MHz 001 = use CKI/20 to allow max CKI of 33.33 MHz 110 = use CKI/24 to allow max CKI of 40 MHz 100 = use CKI/32 to allow max CKI of 53.4 MHz Note: All remaining unused bits in this control register are UNDEFINED and not available for use by the program. 4-75 vOOSP/POOSE/F0097/70091 /P909b/P909E/F9097/F9091./POLOb/POL9E/PO!.9Z/POL 91/791 9b/P9LSE/P9L9Z/POLOLOdHHPC 16164/26 164/36 164/46 164/16 104/26 104/36 104/46 104/ 16064/26064/36064/46064/16004/26004/36004/46004 A/D Converter Operation (continued) Control Register #2 (CR2) | ADMODE(4) | Channel Select(4) | msb , isb byte at location 0102 ADMODE--These four bits are used to select the mode of operation for the A/D converter as described in OPERAT- ING MODES. 0000 = single-ended, single channel, single result register, one-shot (default value on power-up) 0001 = single-ended, single channel, single result register, continuous 0010 = single-ended, single channel, multipie result regis- ters, stop after 8 single-ended, multiple channel, multiple result reg- isters, continuous 0100 = differential, single channel-pair, single result regis- ter-pair, one-shot 0101 = differential, single channel-pair, single result regis- ter-pair, continuous 0110 = differential, singla channel-pair, multiple result reg- ister-pairs, stop after 4 pairs 0111 = differential, multipie channel-pair, multiple result register-pairs, continuous Channel SelectThese four bits ara used to select the channel on which to initiate conversions. Single-ended x000 = Convert on Channel 0 (Input Port D.0) x001 = Convert on Channel 1 (Input Port D.1) x010 = Convert on Channel 2 (Input Port D.2) x011 = Convert on Channel 3 (Input Port D.3) x100 = Convert on Channel 4 (input Port D.4) x101 = Convert on Channel 5 (Input Port D.5) x110 = Convert on Channel 6 (Input Port D.6) x111 = Convert on Channel 7 (Input Port D.7) Differential x000 = Convert on Channel-Pair 0,1 x010 = Convert on Channel-Pair 2,3 x100 = Convert on Channel-Pair 4,5 x110 = Convert on Channel-Pair 6,7 0011 Control Register #3 (CR3) | Japon| | |ADIE] ADEN| Sc Mode (2) Isb msb byte at location 0106 SC mode-These two bits are used to select the mode for starting a conversion cycle. 00 = A conversion cycle is initiated by resetting the A/D done flag (ADDN) (default value on power-up). 01 = Aconversion cycle is initiated by an underflow of Tim- er T2. 10 = A conversion cycle is initiated by the falling edge of the signal on input {7. 11 = Aconversion cycle is initiated by the rising edge of the signal on input I7. ADENSetting this bit enables pin 4 to be the analeg ground, AGND. Resetting this bit returns pin 4 as EXUI (re- set on power-up). ADIEThis is the A/D interrupt enable bit. (reset on power- up). ADDNThis bit is the A/D done flag and doubles as the A/D interrupt pending flag. If one of the one-shot modes was selected using ADMODE(=xx00) and control was se- lected as SC = 00, then this bit must be reset by software to initiate the conversion and is set by the hardware at the end of one conversion. If one of the cycle modes was se- lected using ADMODE(= xx10) and control was selected as SC = 00, then this bit must be reset by software to initiate the conversion cycle and is not set by the hardware until the end of one conversion cycle. If any of the continuous modes were selected and control was selected as SC = 00, then this bit must be reset by software to initiate the conversions and is not set by the hardware until the clock to the A/D cell is stopped by selecting the value 000 for the prescaler. In all other control selections, this bit has no effect on the initia- tion of conversions but is still necessary for proper interrupt operation. The ADDN flag must also be reset for the quiet modes to work properly (set on power-up). Note: All ramaining unused bits in this control register are UNDEFINED and not available for use by the program. Also, all result ragister contents are UNDEFINED on power-up. Universal Peripheral Interface The Universal Peripheral Interface (UPI) allows the HPC16164 to be used as an intelligent peripheral to another processor. The UP! could thus be used to tightly link two HPC16164s and set up systems with very high data ex- change rates. Another area of application could be where a HPC16164 is programmed as an intelligent peripheral to a host system such as the Series 32000 microprocessor. Figure 24 illustrates how a HPC16164 could be used as an intelligent peripherial for a Series 32000-based application. The interface consists of a Data Bus (port A), a Read Strobe (URD), a Write Strobe (UWA), a Read Ready Line (RDRDY), a Write Ready Line (WRRDY) and one Address Input (UA0). The data bus can be either eight or sixteen bits wide. The URD and UWR inputs may be used to interrupt the HPC16164. The RDRDY and WRADY outputs may be used to interrupt the host processor. The UPI contains an Input Buffer (IBUF), an Output Buffer (CBUF) and a Control Register (UPIC). In the UPI made, port A on the HPG16164 is the data bus. UPI can only be used if the HPC16164 is in the Single-Chip mode. 4-76Shared Memory Support Shared memory access provides a rapid technique to ex- change data. It is effective when data is moved from a pe- ripheral to memory or when data is moved between blocks of memory. A related area where shared memory access proves effective is in multiprocessing applications where two GPUs share a common memory block. The HPC16164 supports shared memory access with two pins. The pins are the RDY/HLD input pin and the HLDA output pin. The user can software select aither the Hold or Ready function by the state of a control bit. The HLDA output is multiplexed onto port B. The host uses DMA to interface with the HPC16164. The host initiates a data transfer by activating the HLD input of SERIES 32800 SYSTEM Wa CPU * Tcu icu * MEMORY SYSTEM MASTER ADDRESS BUS the HPC16164. In response, the HPC16164 places its sys- tem bus in a TRI-STATE Mode, freeing it for use by the host. The host waits for the acknowledge signal (HLDA) from the HPC16164 indicating that the sytem bus is free. On receiv- ing the acknowledge, the host can rapidly transfer data into, or out of, the shared memory by using a conventional DMA controller. Upon completion of the message transfer, the host removes the HOLD request and the HPC16164 re- sumes normal operations, To insure proper operation, the interface logic shown is rec- ommended as the means for enabling and disabling the us- er's bus. Figure 26 illustrates an application of the shared memory interface between the HPC16164 and a Series 32000 system. SYSTEM wo HPC16164 DATA BUS TFL/DD/9682-30 FIGURE 24. HPC 16164 as a Peripheral: (UPI Interface to Series 32000 Application} bh CPU2 REMOTE HPC16164 BUS GRANT CPUt SERIES 32000 HOST SYSTEM oCPl eTcu y- __ADORESS/DATA BUS DP73048 DMA CONTROLLER | | o. = R, ALE, HBE SHARED WEMORY TL/OD/9682-31 FIGURE 25. Shared Memory Application: HPC 16164 Interface to Series 32000 System 4-77 7009b/P009E/0092/P0091./F909F/P909E/P909Z/P9091 /POL9F/POL9E/FOL9Z/FOLSL /P9LSb/F919E/P9192/P919LOdHHPC 16 164/26 164/36 164/46 164/16104/26 104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/ 46004 Memory The HPC16164 has been designed to offer flexibility in memory usage. A total address space of 64 kbytes can be addressed with 16 kbytes cf ROM and 512 bytes of RAM available on the chip itself. The ROM may contain program instructions, constants or data. The ROM and RAM share the same address space allowing instructions to be execut- ed out of RAM. Program memory addressing is accomplished by the 16-bit program counter on a byte basis. Memory can be addressed TABLE V. HPC 16164 Memory Map directly by instructions or indirectly through the B, X and SP registers. Memory can be addressed as words or bytes. Words are always addressed on even-byte boundaries. The HPC16164 uses memory-mapped organization to suppert registers, |/O and on-chip peripheral functions. The HPC16164 memory address space extends to 64 kbytes and registers and |/O are mapped as shown in Table V. FFFF:FFFO | tnterrupt Vectors O11F:011E | A/D Result Register 7 FFEF:FFDO | JSRP Vectors 011D:011C | A/D Result Register 6 FFCF:FFCE 011B:011A | A/D Result Register 5 : : On-Chip ROM* 0119:0118 | A/D Result Register 4 E001:C000 USER MEMORY 0117:0116 | A/D Result Register 3 AtoD 0115:0114 | A/D Result Register 2 Reaisters+ BFFF-BFFE 0113:0112 | A/D Result Register 1 9 : : External Expansion 0111:0110 A/D Result Register 0 0301:0300 Memory 0106 A/D Control Register #3 O2FF-02FE 0104 Port D Input Register : : On-Chip RAM USER RAM 0102 A/D Control Register #2 | AtoD 01C01:0100 0100 A/D Control Register #1 | Registerst 0195:0194 Watchdog Address { Watchdog Logic OOF5:00F4 | BFUN Register PORTS A&B 0192 TOCON Register Soe ore OI noaister sur | CONTROL 0191:0190 | TMMODE Register : egister 018F:018E DIVBY Register OOE6 UPIC Register UPI CONTROL 018D:018C | T3 Timer 00E3:002 | PortB 018B:018A | R3 Register 00E1:00E0 | Port A / OBUF PORTS A&B 0189:0188 | T2 Timer Timer Block T0:T3 : : OODE Microcode ROM Dump 0187:0186 | R2 Register O00DD:00DC | HALT Enable Register 0185:0184 I2GR Register/ R1 00D8 Port I Inout Reaister PORT CONTROL 0183:0182 | I3GR Register/ 71 00D6 SIOR ouist er & INTERRUPT 0181:0180 |4GR Register 00D4 IRCD Reaister CONTROL , 9) REGISTERS 015E:015F | EICR 00D2 IRPD Register 015 EICON ooDO ENIR Register 0153:0152 Port P Register OOCF:00CE | X Register 0151:0150 PWMODE Register 00CD:00CC | B Register O14F:014E | A7 Register 00CB:00CA | K Register 014D:014C | T? Timer 00C9:00C8 | A Register HPC CORE 014B:014A R6 Register Timer Block T4:T7 00C7:00C6 | PC Register REGISTERS 0149:0148 | T6 Timer 00C5:00C4 | SP Register 0147:0146 R5 Register 00C3:00C2 | (reserved) 4 toot 4 an noe 00Cco PSW Register : egister , 0141:0140 T4 Timer OOBF:00BE On-Chip USER RAM - 4 nn RAM 0128 ENUR Register 0001:0000 Of a BUF Penleter UART Note: The HPC16184 and HPC16064 On-Chip ROM is on addresses COOO:FFFF and the External Expansion Memory is 0300:BFFF. The 0122 ENU! Register HPC16104 and HPC16004 have no On-Chip ROM, External Memory is 0120 ENU Register 0300:FFFF. tNote: Only ane HPC16164 and HPC16104 have on-board A/D. 4-78Design Considerations Designs using the HPC family of 16-bit high speed CMOS micrecontroliers need to follow some general guidelines on usage and board layout. Floating inputs are a frequently overlooked problam. CMOS inputs have extremely high impedance and, if left open, can float to any voltage. You should thus tie unused inputs to Voc or ground, either through a resistor or directly. Unlike the inputs, unused output should be left floating to allow the output to switch without drawing any DC current. To reduce voltage transients, keep the supply lines parasit- ic inductances as low as possible by reducing trace lengths, using wide traces, ground planes, and by decoupling the supply with bypass capacitors. In order to prevent additional voltage spiking, this local bypass capacitor must exhibit low inductive reactance. You should therefore use high frequen- cy ceramic capacitors and place them very near the IC to minimize wiring inductance. e Keep Voc bus routing short. When using double sided or multilayer circuit boards, use ground plane techniques. Keep ground lines short, and on PC boards make them as wide as possible, even if trace width varies. Use sepa- rate ground traces to supply high current devices such as relay and transmission line drivers. * In systems mixing linear and logic functions and where supply noise is critical to the analog components per- formance, provide separate supply buses or even sepa- rate supplies. if you use local regulators, bypass their inputs with a tan- talum capacitor of at least 1 wF and bypass their outputs with a 10 pF to 50 F tantalum or aluminum electrolytic capacitor. If the system uses a centralized regulated power supply, use a 10 pF to 20 pF tantalum electrolytic capacitor or a 50 pF to 100 F aluminum electrolytic capacitor to de- couple the Voc bus connected to the circuit board. Provide localized decoupling. For random logic, a rule of thumb dictates approximately 10 nF (spaced within 12 cm) per every two to five packages, and 100 nF for every 10 packages. You can group these capacitances, but its more effective to distribute them among the ICs. If the design has a fair amount of synchronous logic with out- puts that tend to switch simultaneously, additional decou- pling might be advisable. Octal flip-flop and buffers in bus-oriented circuits might also require more decoupling. Note that wire-wrapped circuits can require more decou- pling than ground plane or multilayer PC boards. Ree cKO xTAL 200k nrcicoed -l CKt TL/DD/9682-41 A recommended crystal oscillator circuit to be used with the HPC is shown below. See table for recommended compo- nent values. The recommended values given in the table below have yielded consistent results and are made to match a crystal with a 20 pF load capacitance, with some small allowance for layout capacitance. A recommended layout for the oscillator network should be as close to the processor as physically possible, entirely within 1" distance. This is to reduce lead inductance frorn long PC traces, as well as interference from other compo- nents, and reduce trace capacitance. The layout contains a large ground plane either on the top or bottom surface of the board to provide signal shielding, and a convenient loca- tion to ground both tha HPC, and the case of the crystal. Itis very critical to have an extremely clean power supply for the HPC crystal oscillator. Ideally one would like a Voc and ground plane that provide low inductance power lines to the chip. The power planes in the PCG board should be decou- pled with three decoupling capacitors as close to the chip as possible. A 1.0 pF, a0.1 pF, anda 0.001 uF dipped mica or ceramic cap mounted as close to the HPC as is physically possible on the board, using the shortest leads, or surface mount components. This should provide a stable power supply, and noiseless ground plane which will vastly im- prove the performance of the crystal oscillator network. HPC Oscillator Table fo(MHz) | Rec(9) | Ct(pF) | C2 pF) 2 50 82 100 4 50 62 75 6 50 50 56 8 50 47 50 10 50 ag 50 12 0 3s 39 14 0 33 39 16 0 33 39 18 0 33 3d 20 0 33 33 22 0 27 39 24 0 27 a9 26 0 27 a3 28 0 27 33 30 0 27 27 Crystal Specifications: AT cut, parallel resonant crystals tuned to the desired frequency with the following specifications are racommended: Series resistance < 652 Loading capacitance: C_ = 20 pF p009%/P009E/7009Z/F0091. /F909/P909E/79092/F9091 /POL9P/POL9E/POL9Z/POL SL /P919b/PSL9E/P9192/P91 91 9dHHPC 16164/26 164/36 164/46164/16104/26104/36 104/46 104/ 16064/26064/36064/46064/16004/26004/36004/46004 HPC16164 CPU The HPC16164 CPU has a 16-bit ALU and six 16-bit regis- ters Arithmetic Logic Unit (ALU) The ALU is 16 bits wide and can do 16-bit add, subtract and shift or logic AND, OR and exclusive OR in one timing cycle. The ALU can also output the carry bit to a 1-bit C register. Accumulator (A) Register The 16-bit A register is the source and destination register for most I/O, arithmetic, logic and data memory access op- erations. Address (B and X) Registers The 16-bit B and X registers can be used for indirect ad- dressing. They can automatically count up or down to se- quence through data memory. Boundary (K) Register The 16-bit K register is used to set limits in repetitive loops of code as register B sequences through data memory. Stack Pointer (SP) Register The 16-bit SP register is the pointer that addresses the stack. The SP register is incremented by two for each push or call and decremented by two for each pop or raturn. The stack can be placed anywhere in user memory and be as deep as the available memory permits. Program (PC) Register The 16-bit PC register addresses program memory. Addressing Modes ADDRESSING MODESACCUMULATOR AS DESTINATION Register Indirect This is the normal mode of addressing for tha HPC16164 (instructions are single-byte). The operand is the memory addressed by the B register (or X register for some instruc- tions). Direct The instruction contains an 8-bit or 16-bit address field that directly points to the memory for the operand. HPC Instruction Set Description Indirect The instruction contains an 8-bit address field. The contents of the WORD addressed points to the memory for the oper- and. Indexed The instruction contains an 8-bit address field and an 8- or 16-bit displacement field. The contents of the WORD ad- dressed is added to the displacement to get the address of the operand. immediate The instruction contains an 8-bit or 16-bit immediate fiald that is used as the operand. Register Indirect (Auto Increment and Decrement) The operand is the memory addressed by the X register. This mode automatically increments or decrements the X register (by 1 for bytes and by 2 for words). Register Indirect (Auto Increment and Decrement) with Conditional Skip The operand is the memory addressed by the B register. This mode automaticaly increments or decrements the B register (by 1 for bytes and by 2 for words). The B register is then compared with the K register. A skip condition is gener- ated if B goes past K. ADDRESSING MODESDIRECT MEMORY AS DESTINATION Direct Memory to Direct Memory The instruction contains two 8- or 16-bit address fields. One field directly points to the source operand and the other field directly points to the dastination operand. Immediate to Direct Memory The instruction contains an 8- or 16-bit address field and an 8- or 16-bit immediate field. The immediate field is the oper- and and the direct field is the destination. Double RegIster Indirect Using the B and X Registers Used only with Reset, Set and IF bit instructions; a specific bit within the 64 kbyte address range is addressed using the B and X registers. The address of a byte of memory is formed by adding the contents of the B register to the most significant 13 bits of the X register. The specific bit to be modified or tested within the byte of memory is selected using the least significant 3 bits of register X. Mnemonic | Description Action ARITHMETIC INSTRUCTIONS ADD Add MA+Meml MA carry C ADC Add with carry MA+Meml+C MA carry > C ADDS Add short imm8 A+timm8 > A carry > DADC Decimal add with carry MA+ Memli+C MA (Decimal) carry CG SUBC Subtract with carry MA-MemI+C>MA ~~ caryC DSUBC Decimal subtract w/ carry MAMaml+C MA (Decimal) carry > C MULT Multiply (unsigned) MA*Meml MA &X,0-->K,0C DIV Divide (unsigned) MA/Meml > MA, rem. > X,0 K,O C DIVD Divide Double Word (unsigned) X & MA/Memi MA, rem X, 0 K, Carry -> C IFEQ If equal Compare MA & Meml, Do next if equal IFGT If greater than Compare MA & Mem, Do next if MA > Meml AND Logical and MA and Meml > MA OR Logical or MA or Meml MA XOR Logical exclusive-or MA xor Mem! > MA MEMORY MODIFY INSTRUCTIONS INC Increment Mem + 1 Mem DECSZ Decrement, skip if 0 Mem 1 --> Mem, Skip next if Mem = 0 4-80HPC Instruction Set Description (continued) Mnemonic | Description Action BIT INSTRUCTIONS SBIT Set bit 1 Mem.bit RBIT Reset bit Q Mem.bit IFBIT If bit If Mem.bit is true, do next instr. MEMORY TRANSFER INSTRUCTIONS LD Load Memi MA Load, incr/decr X Mem(X) > A, X 1 (or 2) > X ST Store to Memory A Mem x Exchange A< Mem Exchange, incr/decr X A <> Mom(X), X +1 (or 2) > X PUSH Push Memory to Stack W W(SP), SP +2 > SP POP Pop Stack ta Memory SP2 SP, W(SP) > W LDS Load A, iner/deer B, Mem(B) A, B +1 (or 2} > B, Skip on condition Skip next if B greater/less than K XS Exchange, incr/decr B, Mem(B) <> A,B+1 (or 2) B, Skip on condition Skip next if B greater/less than K REGISTER LOAD IMMEDIATE INSTRUCTIONS LDB Load B immediate imm B LDK Load K immediate imm > K LD xX Load X immediate imm > X LDBK Load B and K immediate imm > B,imm > K ACCUMULATOR AND C INSTRUCTIONS CLAA Clear A oA INCA Increment A At1i-mA DECA Decrement A A-1A COMP A Complement A 1s complement of A> A SWAP A Swap nibbies of A A15:12 < A11:8 < A7:4 <> A3:0 RRGA Rotate A right thru C CAI5 ... 7 AO>C RLCA Rotate A left thru C C<AI5 ... AD<-C SHR A Shift A right O AI5S ... AD? C SHLA Shift A left C<A15< ... A0+-0 sc Seat C 1-c RG Reset C oc IFC IFC Do next ifC = 1 IFNC IF notC Do next ifC = 0 TRANSFER OF CONTROL INSTRUCTIONS JSRP Jump subroutine from table PC W(SP),SP+ 2 > SP Witable#) > PC JSR Jump subroutine relative PC W(SP),SP+ 2 > SP,PC + # > PC (#is + 1025 to 1023) JSRL Jump subroutine long PC W(SP),SP + 2 > SP,PC+ # > PC JP Jump relative short PO+ # PC(# is +32 to 31) JMP Jump relative PC+ # PC(#is + 257 to 255) JMPL Jump relative long PC+ # > PC JID Jump indirect at PC + A PC+A+1 PC JIDW then Mem(PC) + PC > PC NOP No Operation PO +1 >PC RET Return SP2 > SP,w(SP) PC RETSK Return then skip next SP2 SP,W(SP) PC, & skip RETI Return from interrupt SP2 SP,W(SP) PC, interrupt re-enabled Note: W is 16-bit word of memory MA is Accumulator A or direct memory (8 or 16-bit) Mem is 8-bit byte or 16-bit word of memory Mem is 8- or 16-bit memory or 6 or 16-bit immediate data imm is $-bit or 16-bit immediate data imms is 8-bit immediate data only 4-81 9009%/009E/#0092/P0091 /F909F/909E/F9092/P9091 /POL 9F/POL9E/01 97 /POL OL /P9L9b/F919E/P91 92/91 91 dHHPC 16164/26 164/36 164/46 164/ 16 104/26 104/36 104/46 104/16064/26064/36064/46064/ 16004/26004/36004/46004 Memory Usage Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field) Using Accumulator A To Direct Memory Reg Indir. Direct Indir Index immed. Direct immed. {B) (%) * ss * ae LD 1 1 2(4) 3 4(5) 2{3) 3(5) 5(6) 3(4) 5(6) X 1 1 2(4) 3 4(5) _ ST 1 1 2(4) 3 4(5) ADC 1 2 3(4) 3 4(5) 4(5) 4(5) 5(6) 4(5) 5(6) ADDS _ _ _ _ _ 2 ~ _ - _ SBC 1 2 3(4) 3 4(5) 4(5) 465) 5(8) 4(5) 5(6) DADC. 1 2 3(4) 3 4(5) 4(5) A() 5(6) 4(5) 5(6) DSBC 1 2 3(4) 3 4(5) 4(5) 4(5) 5(6) 4(5) 5(6) ADD 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6) MULT 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6) DIV 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6) DIVD 1 2 3(4) 3 4(5) 4(5) 5(6) 4(5) 5(6) IFEQ 1 2 3(4) 3 4(5) 2(3) 4(5) 5(8) 4(5) 5(6) IFGT 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6) AND 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6) OR 1 2 3(4) 3 4(5) 2(3) 4(5) 5(6) 4(5) 5(6} XOR 1 2 3(4) 3 4{5) 2(3) 4(5) 5(6) 4(5) 5(6) *a.bit direct address **16-bit direct address Instructions that modify memory directly Immediate Load Instructions {B) (xX) Direct indir Index B&x immed. SBIT 1 2 3(4) 3 4(5) 1 LD B,* 2(3) RBIT 1 2 3(4} 3 4(5) 1 LD X,* 2(3) IFBIT 1 2 3(4) 3 4(5) 1 LD K,* 2(3) DECSZ 3 2 2(4) 3 4(5) LD BK,*,* 3(5) INC 3 2 2(4) 3 4(5) Register indirect instructions with Auto increment and Decrement instructions Using A and C Transfer of Control instructions Register B With Skip CLR A 1 |- JSRP 1 (8+) {B-) INC A 1 JSR 2 DEC A 1 JSRL 3 LDS A," 1 1 COMP A 1 UP 1 XS A," 1 1 SWAP A 1 JMP 2 RRC A 1 JMPL 3 Register X RLC A 1 JID 1 SHR A 1 JIDW 1 (X+) (x7) SHL Al 4 NOP 1 LDA," 1 1 sc 1 RET 1 XA,* 1 1 RG 1 RETSK 1 IFC 1 REFI 1 IFNC 1 Stack Reference Instructions Direct PUSH 2 POP 2 4-82Code Efficiency One of the most important criteria of a single chip microcon- troller is code efficiency. The more efficient the code, the more features that can be put on a chip. The memory size on a chip is fixed so if code is not efficient, features may have to be sacrificed or the programmer may have to buy a. larger, more expensive version of the chip. The HPC16164 has been designed to be extremely code- efficient. The HPC16164 looks very good in all the standard coding benchmarks; however, it is not realistic to rely only on benchmarks. Many large jobs have been programmed onto the HPC 16164, and the code savings over other popu- lar microcontrollers has been considerable. Reasons for this saving of cede include the following: SINGLE BYTE INSTRUCTIONS The majority of instructions on the HPC16164 are single- byte. There are two especially code-saving instructions: JP is a 1-byte jump. True, it can only jump within a range of plus or minus 32, but many loops and decisions are often within a small range of program memory. Most other micros need 2-byte instructions for any short jumps. JSAP is a 1-byte call subroutine. The user makes a tabie of his 16 most frequently called subroutines and these calls will only take one byte. Most other micros require two and even three bytes to call a subroutine. The user does not have to decide which subroutine addresses to put into his table; the assembler can give him this information. EFFICIENT SUBROUTINE CALLS The 2-byte JSR instructions can call any subroutine within plus or minus 1k of program memory. MULTIFUNCTION INSTRUCTIONS FOR DATA MOVE- MENT AND PROGRAM LOOPING The HPC16164 has single-byte instructions that perform multiple tasks. For example, the XS instruction will do the following: 1. Exchange A and memory pointed to by the B register 2. Increment or decrement the B register 3. Compare the B register to the K register 4. Generate a conditional skip if B has passed K The value of this multipurpose instruction becomes evident when looping through sequential areas of memory and exit- ing when the loop is finished. BIT MANIPULATION INSTRUCTIONS Any bit of memory, I/O or registers can be set, reset or tested by the single byte bit instructions. The bits can be addressed direcily or indirectly. Since all registers and I/O are mapped into the memory, it is very easy to manipulate spacific bits to do efficient control. DECIMAL ADD AND SUBTRACT This instruction is needed to interface with the decimal user world. It can handle both 16-bit words and 8-bit bytes. The 16-bit capability saves code since many variables can be stored as one piece of data and the programmer does not have to break his data into two bytes. Many applications store most data in 4-digit variables. The HPC16164 supplies 8-bit byte capability for 2-digit variables and literal variables. MULTIPLY AND DIVIDE INSTRUCTIONS The HPC16164 has 16-bit multiply, 16-bit by 16-bit divide, and 32-bit by 16-bit divide instructions. This saves both code and time. Multiply and divide can use immediate data or data from memory. The ability to multiply and divide by immediate data saves code since this function is often needed for scaling, base conversion, computing indexes of arrays, etc. Development Support DEVELOPMENT SYSTEM The Microcomputer On Line Emulator (MOLE) is a low cost development system and emulator for all microcontroller products. These include COPS microcontrollers and the HPC family of products. The development system consists of a BRAIN Board, Personality Board and-optional host soft- ware. The purpose of the development system is to provide the user with a tool to write and assamble code, emulate code for the target microcontroller and assist in both software and hardware debugging of the system. It is a self contained computer with its own firmware which provides for ail system operation, emulation control, com- munication, PROM programming and diagnostic operations. \t contains three serial ports to optionally connect to a termi- nal, a host system, a printer or a modem, or to connect to other development systems in a multi-development system environment. The development system can be used in either a stand alone mode or in conjunction with a selected host system using PC-DOS communicating via a RS-232 port. How to Order To order a complete development package, select the sec- tion for the microcontroller to be developed and order the parts listed. DIAL-A-HELPER Dial-A-Helper is a service provided by the Microcontroller Applications group. Dial-A-Helper is an Electronic Builetin Board Information system and additionally, provides the ca- pability of remotely accessing the MOLE development sys- tem at a customer site. INFORMATION SYSTEM The Dial-A-Helper system provides access to an automated information storage and retrieval system that may be ac- cessed over standard dial-up telephone jines 24 hours a day. The system capabilities include a MESSAGE SECTION (electronic mail) for communications to and from the Micro- controller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities can be found. Tha minimum require- ment for accessing Dial-A-Helper is a Hayes compatible mo- dem. If the user has a PC with a communications package then files from the FILE SECTION can be down loaded to disk for later use. Order P/N: MOLE-DIAL-A-HLP information System Package Contains: Dial-A-Helper Users Manual Public Domain Communications Software vO0SP/PO09E/F0097/P0091 /P909b/P909E/F9092/F9091 /POLSP/POLSE/POL9Z/POLOL/P9LOb/PSLSE/P919Z/P91910dHHPC 16164/26164/36 164/46 164/ 16104/26 104/36 104/46 104/16064/26064/36064/46064/16004/26004/36004/46004 Development Support (Continued) Development Tools Selection Table Order Manual Microcontroller Part Number Description includes Number MOLE-BRAIN Brain Board Brain Board Users Manual 420408188-001 MOLE-HPC-PB1 Personality Board HPC Personality Board 420410477-001 Users Manual MOLE-HPC-IBM-R Relocatable Assembler | HPC Software Users Manual 424410836-001 Software for IBM and Software Disk HPC PC-DOS Communications 420040416-001 Software Users Manual MOLE-HPC-IBM-CR C Compiler for IBM HPC C Compiler Users Manual 424410883-001 and Software Disk Assembler Software for IBM MOLE-HPC-IBM MOLE-HPC-VMS Assembler, Loader, HPC Software Users Manual and 424410836-001 Librarian for VAX/VMS 9 Track Tape MOLE-HPC-VMS-C C Compiler for HPC Software Users Manual and 424410883-001 VAX/VMS 9 Track Tape (Includes Assembler) 424410897-001 Users Manual 424410897-001 4-84Development Support (Continued) FACTORY APPLICATIONS SUPPORT can leave messages on our electronic bulletin board, which Dial-A-Helper also provides immediate factory applications we will respond to, or under extraordinary circumstances, he support. If a user is having difficulty in operating a MOLE, he can arrange for us to actually take control of his system via modem for debugging purposes. Voice: (408) 721-5582 Modem: (408) 739-1162 Baud: 300 or 1200 baud Set-Up: Length: 8-Bit Parity: None Stop Bit: 1 Operation: 24 Hrs. 7 Days . DIAL-A-HELPER peewee nase encecceeaneceeees . posecee eeeseeseenese wowene 4 ' USER'S. ' ' iy ; TARGET : : ' ' SYSTEM 1 e ' , ' ' ' MODEM 1 tt 4 ODEN HOST Py ' + Lal ' M COMPUTER ' ' ' ' 8 ' ' a HOST a ' 4 WOLE ' ' ' COMPUTER 1 a ' 1 a ' ' 7 a e TL/DD/9682-37 4-85 $009b/P009E/7009Z/F0091 /P909t/P9096/#909Z/F9091. /FOl9h/F0L9E/0192/F0191 /POLOb/P9LSE/P9L9Z/P9LSLOdHHPC 16 164/26 164/36 164/46164/16104/26104/36 104/46 104/ 16064/26064/36064/46064/ 16004/26004/36004/46004 Part Selection The HPC family includes devices with many differant options and configurations to meet various application needs. The number HPC16164 has been generically used throughout this datasheet to represent the whole family of parts. The following chart explains how to order various options available when ordering HPC family members. Note: All options may not currently be available. Speed In MHz 20 = 20 MHz 30=30 MHz PACKAGE TYPE E=Leadless Chip Carrier (LCC) U=Pin Grid Array (PGA) V=Plasic Chip Carrier (PLCC) L=Leaded Ceramic Chip Cerrler (LOCC) T=Tape Pak (TP) ROM Information XXX/ = custom masked ROM pattern no designator = ROMless ROM Size B=8k byte ROM 6=16k byte ROM O=romLESs DEVICE A/O 1=A/0 O=No A/D TEMPERATURE 4= Commercial (0C TO +70C) 3 = Industrial (40C TO #85C) 2 = Automotive (-40C TO 105C) 1 =Milltary (=55C TO +125C) FIGURE 8. HPC Family Part Numbering Scheme Examples HPC46104E20 ROMless, Commercial temp. (0C to 70C), LCC HPC16164XXX/U20 16k masked ROM, Military temp. (55C to + 125C), PGA HPC26104XXX/V20 ROMless, Automotive tamp. ( 40C to + 105C), PLCC TL/OD/9682-33 4-86