QB-8 3.3-Volt, 0.44-Micron Gate Arrays NEC Electronics Inc. Preliminary Description April 1996 Figure 1. 672-pin BGA NEC's 3.3-volt QB-8 family consists of ultra-highperformance, submicron gate arrays targeted for applications requiring high speeds and low power dissipation. The QB-8 family offers not only high speed but also low power dissipation and high density at a reasonable price. This combination of features is made possible through the use of a unique epi-less process that delivers the low cost and short manufacturing time of CMOS with the high speed of bipolar technology. QB-8 is targeted for designs in advanced networks and data communications, industrial applications, telecommunications, and computing applications such as engineering workstations, high-end personal computers, mainframes, and high-speed peripherals. The device processing includes a 0.44-micron silicongate technology and three-layer metalization. This technology features channeless (sea-of-gate) architecture with an internal gate delay of 107 ps (F/O = 1, L = 0) and power dissipation of 1.0 W/MHz/gate. The high-performance I/O macros include LVTTL, GTL, HSTL, and pECL. PCI signaling standards are also supported, including those for a 3.3-volt, 66 MHz PCI. This technology is enhanced by a set of advanced features that include phase-locked loops, clock tree synthesis, and high-speed memories. The QB-8 family consists of 11 masters offered in densities of 33K to 382K raw gates. The gate array family is supported by NEC's OpenCAD(R) design system, a mixture of popular third-party CAE tools, and proprietary NEC tools. NEC's proprietary tools include the GALET floorplanner, which helps reduce design cycle time and improve design performance, clock tree synthesis for clock skew minimization, and a table lookup delay calculator for accurate delay calculation. Table 1. QB-8 Series Features and Benefits QB-8 Series Features QB-8 Series Benefits * 0.44-micron (drawn), 3-level metal process * Delivers Bipolar speed at CMOS turn-time and cost * BiCMOS process does not use epitaxial layer * Shortens turnaround time and reduces cost of production * 11 base arrays with raw gates from 33K to 382K gates * Satisfies user requirements with many base arrays * Optimized pad pitch * Reduces assembly cost for BGA and QFP wirebond * Optimized I/O cell size * Enables high-speed I/O buffers in only one I/O slot * "PUZZLE" cell architecture with mixed transistor sizes * Achieves high speed; keeps driveability and low power * PCI, GTL, HSTL, pECL interface blocks * Delivers I/O for up to 250-MHz data transfer * 90- to 160-MHz PLL and clock tree synthesis * Eliminates clock insertion delay; reduces clock skew * Clock tree synthesis tool * Automatic insertion of low-skew clock tree * Low power dissipation of 1.0 W/MHz/gate * Delivers support for ultra-high-speed communications * Asynchronous 1- and 2-port RAM blocks * Allows high-speed, low-power BiCMOS operation * BGA, PQFP, PGA packaging * Provides support for high-speed RAM * 622-MHz I/O and 622MHz PLL in QB-8E (release FY/96) * Supports popular packaging solutions A11111EU1V0DS00 OpenCAD is a registered trademark of NEC Electronics Inc. QB-8 Figure 2. Chip Layout and Internal Cell Configuration Array Architecture The QB-8 family is built with NEC's 0.44-micron channeless array architecture. The array is divided into I/O and core regions (see Figure 2). The I/O regions contain input and output buffers. The core region contains the sea-of-gates array. The QB-8 gate arrays architecture provides extra flexibility for high-performance system designs. The arrays contain several power rails, a 3.3-volt rail, and power rails for special I/O types such as 5-volt PCI, HSTL, GTL, and pECL. 3.3V Core Architecture QB-8 uses a proprietary architecture called PUZZLE. It combines three transistors of different sizes into a single, highly dense architecture tightly interlocked as in a puzzle. The result is an ASIC that uses small CMOS transistors for low input capacitance and signaling within a macro, and bipolar transistors for high drive-ability and signaling between macros. Universal power lines The core region consists of an array of gates. Each cell contains four n-channel and two p-channel transistors and one bipolar transistor. One cell is equivalent to one 2-input NAND gate (L302). The logic transistors are sized to offer a superior ratio of speed to silicon area. Gate Array Sizes Test Available Gates Usable Gates I/O Pads Metal Layers PD67821 32832 22982 156 3 PD67822 44352 31046 180 3 PD67823 56800 39760 204 3 PD67824 69520 48664 224 3 PD67825 93184 65229 260 3 PD67826 123808 86666 300 3 PD67827 136752 95726 316 3 PD67828 167280 117096 348 3 PD67829 234320 164024 412 3 PD67830 292896 205027 460 3 PD67831 381840 267288 524 3 Device Actual gate utilitization varies depending on circuit implementation. Utilization is 70% for three-layer metal. Depending on package and circuit specifications, some pads are used for VDD and GND and are not available as signal pads. 2 The QB-8 family supports automatic test generation through a scan-test methodology, which allows higher fault coverage, easier testing, and quicker development time. NEC also offers optional BIST test architecture for RAM testing. Packaging NEC offers an extensive variety of more than 60 package types. The QB-8 family can be packaged in NEC's most popular surface-mount and through-hole packages. These include plastic quad-flat packs (PQFPs). Pin grid arrays (PGAs) and BGA packages are also supported. The 672-pin BGA package is shown in Figure 1. Publications This data sheet contains specifications, package information, and operational data for the QB-8 gate array families. Additional design information is available in NEC's QB-8 Block Library and QB-8 Design Manual. Call your local NEC design center or call the NEC toll-free literature line for additional ASIC design information; see the back of this data sheet for locations and telephone numbers. QB-8 Input/Output Capacitance Absolute Maximum Ratings Power supply voltage, VDD -0.5 to 4.6 V Input voltage, VI 3 V input buffer (at VI < VDD+ 0.5 V) -0.5 to 4.6 V 3 V fail-safe input buffer (at VI < VDD+ 0.5 V) -0.5 to 4.6 V 5 V-tolerant buffer (at VI < VDD+ 3.0 V) -0.5 to 6.6 V Output voltage, VO 3 V buffer (at VO < VDD+ 0.5 V) -0.5 to 4.6 V 5 V-tolerant buffer (at VO < VDD+ 3.0 V) -0.5 to 6.6 V Latch-up current, ILATCH >1 A (typ) Operating temperature, TOPT -40 to +85C Storage temperature, TSTG -65 to +150C VDD = VI = 0 V; f = 1 MHz Terminal Symbol Typ Max Unit Input Output CIN 10 20 pF COUT 10 20 pF I/O CI/ O 10 20 pF Note: (1) Values do not include package pin capacitance. Power Consumption Description Limits Unit Internal cell 1.09 W/MHz Input block (FI01) 6.92 W/MHz Output block (F002 @ 15 pF) 260 W/MHz Recommended Operating Conditions 3 V Buffer Parameter 5 V-Tolerant 3.3 V PCI 5 V PCI Symbol Min Max Min Max Min Max Min Max Unit Power supply voltage VDD 3.0 3.6 3.0 3.6 3.0 3.6 3.0 3.6 V Junction temperature TJ -40 +125 -40 +125 -40 +125 -40 +125 C Low-level input voltage VIL 0 0.8 0 0.8 -0.5 0.3 VDD -0.5 0.8 V High-level input voltage VIH 2.0 VDD 2.0 VDD 0.5 VDD VDD+0.5 2.0 VDD+0.5 V Input rise or fall time tR, tF 0 200 0 200 0 200 0 200 ns Input rise or fall time, Schmitt t R, tF 0 10 0 10 0 200 ns -- -- ms AC Characteristics VDD = 3.3 V 0.3 V; Tj = -40 to +125C Parameter Toggle frequency Symbol Min fTOG 670 Typ Max Unit Conditions MHz D-F/F; F/O = 1 Delay time 2-input NAND (F322) tPD tPD 90 106 ps ps F/O = 1; L = 0 mm F/O = 2; L = typ Flip-flop (F611) tPD tPD 463 492 ps ps ps ps F/O = 1; L = 0 mm F/O = 2; L = typ -- -- 211 220 ps ps F/O = 1; L = 0 mm F/O = 2; L = typ tSETUP tHOLD 540 10 Input buffer (FI01) tPD tPD Output buffer (12 mA) 3.3 V tPD 925 ps CL = 0 pF Output buffer (12 mA) 3.3 V tPD 2136 ps CL = 50 pF Output buffer (12 mA) 5 V-tolerant tPD TBD ps CL = 0 pF, 50 pF Output buffer (6 mA) 5 V-tolerant tPD 1004 ps CL = 0 pF Output buffer (6 mA) 5 V-tolerant tPD 2158 ps CL = 50 pF Output rise time (9 mA) tR 920 ps CL = 15 pF Output fall time (9 mA) tF 680 ps CL = 15 pF 3 QB-8 DC Characteristics VDD = 3.3 V 0.3 V; TJ = -40 to +125C Parameter Symbol Min Typ Max Unit Conditions Quiescent current PD67831, 67830 IDDS 15 4800 A VI = VDD or GND PD67829, 67828, 67827 I DDS 9 3000 A VI = VDD or GND PD67826, 67825, 67824 I DDS 5 1500 A VI = VDD or GND PD67823, 67822, 67821 I DDS 2 700 A VI = VDD or GND Off-state output leakage current 3 V output IOZ 10 A VO = VDD or GND 5 V-tolerant output IOZ 14 A VO = VDD or GND Output sink current with pull-up (VO = 3 V) IR 14 A VPU = 5.5 V, RPU = 2k Output sink short circuit current IOS -250 mA II 10 A VO = GND Input leakage current Regular VI = VDD or GND 50 k pull-up II -30 -66 -144 A VI = GND 5 k pull-up II -300 -660 -1440 mA VI = GND 50 k pull-down II 30 66 144 A VI = VDD Pull-up resistor 50 k pull-up RPU 25.0 50.0 100.0 ky 5 k pull-up RPU 2.5 5.0 10.0 ky 50 k pull-down RPD 25.0 50.0 100.0 ky 3 mA (F009) IOL 3 mA VOL = 0.4 V 6 mA (F004) IOL 6 mA VOL = 0.4 V 9 mA (F001) IOL 9 mA VOL = 0.4 V 12 mA (F002) IOL 12 mA VOL = 0.4 V 18 mA (F003) IOL 18 mA VOL =0.4 V 24 mA (F006) IOL 24 mA VOL = 0.4 V 1 mA (FV0A) IOL 1 mA VOL = 0.4 V 2 mA (FV0B) IOL 2 mA VOL = 0.4 V 3 mA (FV09) IOL 3 mA VOL = 0.4 V 6 mA (F002) IOL 6 mA VOL = 0.4 V Low-level output current 3 V buffers 5 V-tolerant buffers Low-level output voltage 3 V buffers VOL 0.1 V IOL = 0 mA 5 V-tolerant buffers VOL 0.1 V IOL = 0 mA High-level output voltage 4 3 V buffers VOH VDD-0.1 V IOH = 0 mA 5 V-tolerant buffers VOH VDD-0.2 V IOH = 0 mA QB-8 5 QB-8 NEC ASIC DESIGN CENTERS WEST SOUTH CENTRAL/SOUTHEAST NORTH CENTRAL/NORTHEAST * 3033 Scott Boulevard Santa Clara, CA 95054 * 16475 Dallas Parkway, Suite 380 Dallas, TX 75248 * The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701 TEL 408-588-5008 FAX 408-588-5017 TEL 972-735-7444 FAX 972-931-8680 * One Embassy Centre 9020 S.W. Washington Square Road, Suite 400 Tigard, OR 97223 * Research Triangle Park 2000 Regency Parkway, Suite 455 Cary, NC 27511 TEL 919-460-1890 FAX 919-469-5926 TEL 503-671-0177 FAX 503-643-5911 TEL 508-935-2200 FAX 508-935-2234 * Greenspoint Tower 2800 W. Higgins Road, Suite 765 Hoffman Estates, IL 60195 TEL 708-519-3945 FAX 708-882-7564 * Two Chasewood Park 20405 SH 249, Suite 580 Houston, TX 77070 TEL 713-320-0524 FAX 713-320-0574 THIRD-PARTY DESIGN CENTERS SOUTH CENTRAL/SOUTHEAST * Koos Technical Services, Inc. 385 Commerce Way, Suite 101 Longwood, FL 32750 TEL 407-260-8727 FAX 407-260-6227 * Integrated Silicon Systems Inc. 2222 Chapel Hill Nelson Highway Durham, NC 27713 TEL 919-361-5814 FAX 919-361-2019 * Applied Systems, Inc. 1761 W. Hillsboro Blvd., Suite 328 Deerfield Beach, FL 33442 TEL 305-428-0534 FAX 305-428-5906 For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782 or FAX your request to: 1-800-729-9288 NEC Electronics Inc. CORPORATE HEADQUARTERS 2880 Scott Boulevard P.O. Box 58062 Santa Clara, CA 95052 TEL 408-588-6000 6(c)1996 NEC Electronics Inc./Printed in U.S.A. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY, WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. "Standard" quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, antidisaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given application. Document No. A11111EU1V0DS00