LMH1983SQ/NOPB - NATIONAL SEMICONDUCTOR

LOOP

FILTER 27 MHz

VCXO

LMH1983

FPGA

A/V Frame Sync with

Downconverter,

Audio Embedder and

De-embedder

1080p/59.94 SDI out

+ embedded audio

LMH1981

Sync

Separator

H sync

V sync

525i

Analog

ref. in F sync

27 MHz (PLL1)

148.5 MHz (PLL2)

148.35 MHz (PLL3)

24.576 MHz (PLL4)

1080p/59.94 SDI in

+ embedded audio

Genlocked to video ref. in

525i/29.97 SDI out

+ embedded audio

CLKout1

CLKout4

CLKout2

CLKout3

Hin

Vin

Fin

29.97 Hz (TOF1)

29.97 Hz (TOF2)

59.94 Hz (TOF3)

5.994 Hz

Product

Folder

Sample &

Buy

Technical

Documents

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Software

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LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

LMH1983 3G/HD/SD Video Clock Generator with Audio Clock

1 Features 3 Description

The LMH1983 is a highly-integrated programmable

1• Four PLLs for Simultaneous A/V Clock Generation audio/video (A/V) clock generator intended for

– PLL1: 27 or 13.5 MHz broadcast and professional applications. It can

– PLL2: 148.5 or 74.25 MHz replace multiple PLLs and VCXOs used in

applications supporting SMPTE serial digital video

– PLL3: 148.5/1.001 or 74.25/1.001 MHz (SDI) and digital audio AES3/EBU standards. It offers

– PLL4: 98.304 MHz / 2X(X = 0 to 15) low-jitter reference clocks for any SDI transmitter to

• 3 x 2 Video Clock Crosspoint meet stringent output jitter specifications without

additional clock cleaning circuits.

• Flexible PLL Bandwidth to Optimize Jitter

Performance and Lock Time The LMH1983 features automatic input format

• Soft Resynchronization to New Reference detection, simple programming of multiple A/V output

formats, genlock or digital free-run modes, and

• Digital Holdover or Free-run on Loss of Reference override programmability of various automatic

• Status Flags for Loss of Reference and Loss of functions. The recognized input formats include HVF

PLL Lock syncs for the major video standards, 27 MHz, 10

• 3.3 V Single Supply Operation MHz, and 32/44.1/48/96 kHz audio word clocks.

• I2C Interface with Address Select Pin (3 States) The dual-stage PLL architecture integrates four PLLs

with three on-chip VCOs. The first stage (PLL1) uses

2 Applications an external low-noise 27 MHz VCXO with narrow

loop bandwidth to provide a clean reference clock for

• Triple Rate (3G/HD/SD) SDI SerDes the next stage. The second stage (PLL2, 3, 4)

• FPGA Reference Clock Generation/Cleaning consists of three parallel VCO PLLs for simultaneous

• Audio Embed or De-embed generation of the major digital A/V clock fundamental

rates, including 148.5 MHz, 148.5/1.001 MHz, and

• Video Cameras 98.304 MHz (4 × 24.576 MHz). Each PLL can

• Frame Synchronizers (Genlock, DARS) generate a clock and a timing pulse to indicate top of

• A-D or D-A Conversion, Editing, Processing Cards frame (TOF).

• Keyers and Logo Inserters Device Information(1)

• Format or Standards Converters PART NUMBER PACKAGE BODY SIZE (NOM)

• Video Displays and Projectors LMH1983 WQFN (40) 6.00 mm × 6.00 mm

• A/V Test and Measurement Equipment (1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

Table of Contents

8.3 Feature Description................................................. 12

1 Features.................................................................. 18.4 Device Functional Modes........................................ 20

2 Applications ........................................................... 18.5 Programming........................................................... 24

3 Description............................................................. 18.6 Register Map........................................................... 26

4 Revision History..................................................... 29 Applications and Implementation ...................... 35

5 Description (continued)......................................... 39.1 Application Information............................................ 35

6 Pin Configurations and Functions....................... 39.2 Typical Applications ................................................ 35

7 Specifications......................................................... 510 Power Supply Recommendations ..................... 43

7.1 Absolute Maximum Ratings ...................................... 511 Layout................................................................... 43

7.2 ESD Ratings.............................................................. 511.1 Layout Guidelines ................................................. 43

7.3 Recommended Operating Conditions....................... 511.2 Layout Example .................................................... 44

7.4 Thermal Information.................................................. 512 Device and Documentation Support................. 47

7.5 Electrical Characteristics........................................... 612.1 Documentation Support ........................................ 47

7.6 Frame Timing Outputs Timing Requirements........... 812.2 Trademarks........................................................... 47

7.7 Frame Timing Outputs Switching Characteristics..... 812.3 Electrostatic Discharge Caution............................ 47

7.8 Typical Characteristics.............................................. 912.4 Glossary................................................................ 47

8 Detailed Description............................................ 11 13 Mechanical, Packaging, and Orderable

8.1 Overview................................................................. 11 Information........................................................... 47

8.2 Functional Block Diagram....................................... 12

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (October 2014) to Revision I Page

• Updated ESD Ratings table.................................................................................................................................................... 5

• Updated formatting for Typical Characteristics graphs ......................................................................................................... 9

Changes from Revision G (Nov 2012) to Revision H Page

• Added Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and

Functions,Application and Implementation;Power Supply Recommendations;Layout;Device and Documentation

Support;Mechanical, Packaging, and Ordering Information ................................................................................................. 1

• Changed typical value of low output sink current to match simulation value of 1.25 mA. .................................................... 6

• Added clarification about PLL4 behavior. ............................................................................................................................ 15

• Added clarification section for LOR Determination .............................................................................................................. 17

• Changed appearance of Reg 0x11 mode description for clarity.......................................................................................... 18

• Changed register initialization procedure to prevent device from exhibiting poor duty cycle performance on CLKout3 .... 19

• Added clarification note about 480i/29.97, 480p/59.94, 576i/25 and 576p/50 resolutions................................................... 23

• Changed default value for Reg 0x11[3:2] bits. .................................................................................................................... 28

• Changed Reg 0x11[3:2] description for clarification of TOF1_Sync behavior dependent on LOA window......................... 28

Product Folder Links: LMH1983

VDD

Vin

Fin

VC_LPF

CLKout3+

CLKout4-

XOin-

Cbyp2

VDD

Hin

NO_LOCK

INIT

Fout1

GND

NO_ALIGN

GND

Fout2

CLKout2+

SDA

CLKout3-

CLKout4+

SCL

Fout3

VDD

Fout4

(OSC in)

VDD

Cbyp3

CLKout2-

VDD

CLKout1-

CLKout1+

Die Attach Pad (DAP)

Connect to GND on PCB

ADDR

GND

Cbyp4

VDD

XOin+

VDD

NO_REF

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

5 Description (continued)

When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of

reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output

accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize

to a previous reference with glitch-less operation.

6 Pin Configurations and Functions

RTA40A Package

40-Pin WQFN Package with Exposed Thermal Pad

Top View

Pin Functions

PIN SIGNAL

I/O DESCRIPTION

LEVEL

NO. NAME

1 VDD – Power 3.3-V supply for PLL1

2 VDD – Power 3.3-V supply for logic I/O

Horizontal sync reference signal

3 Hin I LVCMOS Auto polarity correction for HVF will be based off Hin polarity.

Recognized clock inputs can be applied to Hin.

4 Vin I LVCMOS Vertical sync reference signal

5 Fin I LVCMOS Field sync (odd/even) reference signal

6 INIT I LVCMOS Reset signal for audio-video phase alignment (rising edge triggered)

I2C address select

Pin settings:

7 ADDR I LVCMOS – Tie low: 0x65 (7-bit slave address in hex)

– Float: 0x66

– Tie high: 0x67

8 SDA(1) I/O I2C I2C Data signal

9 SCL(1) I I2C I2C Clock signal

10 VDD – Power 3.3-V supply for logic I/O

11 NO_LOCK(2) O LVCMOS Loss of lock status flag for PLLs 1-4 (active high)

12 NO_ALIGN O LVCMOS Loss of alignment status flag for OUTs 1–4 (active high)

(1) SDA and SCL pins each require a pull-up resistor of 4.7 kΩto the VDD supply.

(2) The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked

from the NO_LOCK flag by setting their respective mask bits.

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Pin Functions (continued)

PIN SIGNAL

I/O DESCRIPTION

LEVEL

NO. NAME

13 NO_REF O LVCMOS Loss of reference status flag (active high)

14 CLKout4– Audio clock from PLL4 (fundamental rate is 98.304 MHz).

O LVDS

15 CLKout4+ The output is 24.576 MHz by default and is selectable via the host.

16 VDD – Power 3.3 V supply for CLKout4

Audio frame timing signal for OUT4 (active low.) Timing Generator

fixed to PLL4 clock. The output is the audio-video-frame (AVF) pulse

by default and is programmable via the host. Optional OSCin function

17 Fout4 (OSCin) I/O LVCMOS can be used to apply a 27 MHz external clock for PLL4 to generate an

audio clock independent of the video input reference; this function

must be enabled via the host.

18 GND – GND Ground

19 VDD – Power 3.3 V supply for PLL3 and PLL4

20 VDD – Power 3.3 V supply for CLKout3

21 GND – GND Ground

Video frame timing signal for OUT3 (active low). Timing generator

22 Fout3 O LVCMOS assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable via the

host.

Video clock from PLL1, PLL2, or PLL3 depending on output

23 CLKout3+ O LVDS crosspoint mode. The output is 148.35 MHz by default and is

24 CLKout3– selectable via the host.

Bias bypass for on-chip LDO for PLL3

25 Cbyp3 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors.

Bias bypass for on-chip LDO for PLL4

26 Cbyp4 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors.

Bias bypass for on-chip LDO for PLL2

27 Cbyp2 – Analog Connect to 1.0 µF and 0.1 µF bypass capacitors.

Video clock from PLL1, PLL2, or PLL3 depending on output

28 CLKout2+ O LVDS crosspoint mode. The output is 148.5 MHz by default and is selectable

29 CLKout2– via the host.

Video frame timing signal for OUT2 (active low). Timing generator

30 Fout2 O LVCMOS assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable via the

host.

31 VDD – Power 3.3-V supply for CLKout2

32 VDD – Power 3.3-V supply for PLL2

27 MHz VCXO clock signal for PLL1.

33 XOin–(3) – LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to

I LVCMOS/LVDS

34 XOin+ mid-supply with 0.1µF bypass capacitor.

– LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.(4)

35 CLKout1– Video clock from PLL1.

O LVDS

36 CLKout1+ The output is 27 MHz by default and is selectable via the host.

Reference frame timing signal for OUT1 (active Low). Timing

37 Fout1 O LVCMOS generator fixed to PLL1 OUT1 Format follows the reference input

format.

38 VDD – Power 3.3 V supply for CLKout1

39 GND – GND Ground

Loop filter for PLL1 charge pump output with VCXO Voltage Control

(VC) sensing.

40 VC_LPF O Analog If free-run and holdover mode, PLL1 is disabled and an internal DAC

outputs a control voltage to the VCXO.

– DAP – GND Die Attach Pad (Connect to ground on PCB)

(3) XOin must be driven by a 27 MHz clock in order to read or write registers via I2C.

(4) A TCXO or other clean 27 MHz oscillator can be applied for standalone clock generation using PLLs 2-4 (bypass PLL1).

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3)

MIN MAX UNIT

VDD Supply voltage 3.6 V

VIInput voltage (any input) -0.3 VDD + 0.3 V

VOOutput voltage (any output) -0.3 VDD + 0.3 V

TJMAX Junction temperature 150 °C

Tstg Storage temperature range -65 150 °C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering information, see SNOA549.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

7.2 ESD Ratings VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2500

Machine model (MM)(2) 250

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22- 750

C101(3)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2500 V may actually have higher performance.

(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC).

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Input Voltage 0 VDD V

Temperature Range, TA-40 85 °C

7.4 Thermal Information RTA

THERMAL METRIC(1) UNIT

40 PINS

TJMAX Junction Temperature, VDD 3.3 ± 5% °C/W

RθJA Thermal Resistance(2) 33 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is

PD = (TJ(MAX) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PC Board.

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7.5 Electrical Characteristics(1)

Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 3.3 V, RL_CLK = 100 Ω(CLKout differential load).

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

Default register settings, no load on logic outputs.

IDD Total supply current 170 212 mA

VDD = 3.465 V

PLL2, PLL3 and PLL4 disabled, no load on logic

IDD Total supply current 60 100 mA

outputs. VDD = 3.465 V

REFERENCE INPUTS (Hin, Vin, Fin)

VIL Low input voltage IIN = ±10 μA 0 0.3 VDD V

VIH High input voltage IIN = ±10 µA 0.7 VDD VDD V

Time from when reference input first presented to

when detected as indicated by NO_REF going low. Input

TAFD Auto-format detection time 2 4

Reference timing must be stable and accurate (no Frames

missing pulses).

OSCin LOGIC INPUTS

VIL Low input voltage IIN = ±10 µA 0 0.3 VDD V

VIH High input voltage IIN = ±10 µA 0.7 VDD VDD V

I2C INTERFACE (SDA, SCL)

VIL Low input voltage 0 0.3 VDD V

VIH High input voltage 0.7 VDD VDD V

IIN Input current VIN between 0.1 VDD and 0.9 VDD −10 +10 μA

IOL Low output sink current VOL = 0V or 0.4V 1.25 mA

STATUS FLAG OUTPUTS (NO_REF, NO_ALIGN,NO_LOCK)

VOL Low output voltage IOUT = +10 mA 0.4 V

VOH High output voltage IOUT =−10 mA VDD-0.4V V

FRAME TIMING OUTPUTS

IOUT = +10 mA

VOL Low output voltage 0.4

Fout1, Fout2, Fout3(4)

IOUT = -10mA

VOH High output voltage VDD-0.4 V

Fout1, Fout2, Fout3(4)

Output shutdown leakage Output buffer shutdown, pin connected to VDD or

IOZ 0.4 10 |μA|

current GND VDD = 3.465V

VIDEO and AUDIO CLOCK OUTPUTS (CLKout1, CLKout2 and CLKout3)

Measured at CLKout1 all other CLKouts shutdown 250 fs

27 MHz TIE deterministic Measured at CLKout1, other CLKouts output default

Jitter 250 fs

PLL

Measured at CLKout2 all other CLKouts shutdown 8 ps

148.5 MHz TIE Measured at CLKout2, other CLKouts output default

deterministic Jitter 8 ps

PLL

tDJ Measured at CLKout3 all other CLKouts shutdown 4 ps

148.35 MHz TIE Measured at CLKout3, other CLKouts output default

deterministic Jitter 4 ps

PLL

Measured at CLKout4 all other CLKouts shutdown 15 ps

24.576 MHz TIE Measured at CLKout4, other CLKouts output default

deterministic Jitter 15 ps

PLL

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance

is indicated in the electrical tables under conditions different than those tested.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

statistical analysis methods.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(4) tDfor FoutX is measured from the positive clock edge of CLKout to the negative edge of FoutX at the 50% levels.

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

Electrical Characteristics(1) (continued)

Unless otherwise specified, all limits are specified for TA= 25°C, VDD = 3.3 V, RL_CLK = 100 Ω(CLKout differential load).

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

Measured at CLKout1, other CLKouts shutdown 2.7 ps

27 MHz TIE random Output Measured at CLKout1, other CLKouts output default

Jitter(5) 2.7 ps

PLL

Measured at CLKout2, other CLKouts shutdown 3.0 ps

148.5 MHz TIE Random Measured at CLKout2, other CLKouts output default

Output Jitter(5) 3.0 ps

PLL

tRJ Measured at CLKout3, other CLKouts shutdown 3.5 ps

148.35 MHz TIE Random Measured at CLKout3, other CLKouts output default

Output Jitter (5) 3.5 ps

PLL

Measured at CLKout4, other CLKouts shutdown 3.4 ps

24.576 MHz TIE Random Measured at CLKout4, other CLKouts output default

Output Jitter(5) 3.4 ps

PLL

Measured at 50% level of clock amplitude, any

TDDuty cycle 50%

output clock

Rise time

tR15 pF load 400 ps

20% to 80%

Fall time

tF15 pF load 400 ps

80% to 20%

Differential signal output 100 Ωdifferential load, CLKout1, CLKout2 or

VOD 247 350 454 mV

voltage CLKout3(6)

Common signal output 100 Ωdifferential load, CLKout1, CLKout2 or

VOS 1.125 1.25 1.375 V

voltage CLKout3(6)

|Change to VOD| for 100 Ωdifferential load, CLKout1, CLKout2 or

|VOD| complementary output 50 |mV|

CLKout3(6)

states

|Change to VOS| for 100 Ωdifferential load, CLKout1, CLKout2 or

|VOS| complementary output 50 |mV|

CLKout3(6)

states Differential clock output pins connected to GND for

IOS Output short circuit current 24 |mA|

CLKout1, CLKout2, or CLKout3

Output shutdown leakage Output buffer in shutdown mode, differential clock

IOZ 1 10 |µA|

current output pins connected to VDD or GND

VCXO INPUT (XOin)

Maximum relative frequency

fOFF offset between VCXO input Assumes H input jitter of ±15 ns ±150 ppm

and H input

Single-ended signal input

VXOin_SE Single-ended input buffer mode 0 VDD V

voltage range

Differential signal input

VXOin_DIFF Differential input buffer mode, VCM = 1.2 V 247 350 454 mV

voltage range

DIGITAL HOLDOVER and FREE-RUN SPECIFICATIONS

VDD -

VVCout_RNG DAC output voltage range Digital Free-run Mode 0.5 V

0.5V

(5) The SD and HD clock output jitter is based on XO input clock with 20 ps peak-to-peak using a time interval error (TIE) jitter

measurement. The typical TIE peak-to-peak jitter was measured on the LMH1983 evaluation bench board using TDSJIT3 jitter analysis

software on a Tektronix DSA71604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10-12 bit

error rate (BER), >100K samples recorded using multiple acquisitions. Oscilloscope Setup: 20 mV/div vertical scale, 10 µs/div horizontal

scale, and 25 GS/s sampling rate

(6) The differential output swing and common mode voltage may be adjusted via the I2C interface. Testing is done with a value of 0x3E

loaded into Register 0x3A.

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7.6 Frame Timing Outputs Timing Requirements MIN NOM MAX UNIT

tRRise time 20% to 80% 15 pF load 1 ns

tFFall time 20% to 80% 15 pF load 1 ns

7.7 Frame Timing Outputs Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TOF1 delay measured from the CLKout1 clock reset ns

edge. Delay spec applies for all output clock and format

tD1(1) Timing output delay time 22

supported by the output pair following output initialization.

15 pF load.

TOF2 delay measured from the CLKout2 clock reset ns

edge. Delay spec applies for all output clock and format

tD2 Timing output delay time 2

supported by the output pair following output initialization.

15 pF load.

TOF3 delay measured from the CLKout3 clock reset ns

edge. Delay spec applies for all output clock and format

tD3 Timing output delay time 2

supported by the output pair following output initialization.

15 pF load.

TOF4 delay measured from the CLKout4 clock reset ns

edge. Delay spec applies for all output clock and format

tD4 Timing output delay time 22

supported by the output pair following output initialization.

15 pF load.

(1) tDfor CLKoutX is measured from the positive clock edge of XOin to the positive clock edge of CLKoutX using 50% levels. The

measurement is taken at the clock cycle where the input and output clocks are phase aligned.

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

7.8 Typical Characteristics

Horizontal Scale: 2.6ps / Division

Figure 1. CLKout1 Jitter Histogram Figure 2. CLKout1 Phase Noise

Horizontal Scale: 4.4ps / Division

Figure 3. CLKout2 Jitter Histogram Figure 4. CLKout2 Phase Noise

Horizontal Scale: 4.4ps / Div

Figure 5. CLKout3 Jitter Histogram Figure 6. CLKout3 Phase Noise

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Typical Characteristics (continued)

Horizontal Scale: 7 ps / Div

Figure 7. CLKout4 Jitter Histogram Figure 8. CLKout4 Phase Noise

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

8 Detailed Description

8.1 Overview

The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a

variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The

LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with

programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-

stage PLL architecture. The first stage is a VCXO-based PLL (PLL1) that requires an external 27 MHz VCXO

and loop filter. In Genlock mode, PLL1 can phase lock a low loop bandwidth VCXO clock to the input reference.

The VCXO provides a low phase noise clock source to attenuate input timing jitter for minimum jitter transfer.

The combination of the external VCXO, external loop filter, and programmable PLL parameters provide flexibility

for the system designer to optimize the loop bandwidth and loop response for the application.

The second stage consists of three PLLs (PLL2, PLL3, PLL4) with integrated VCOs and loop filters. These PLLs

continually track the reference VCXO clock phase from PLL1 regardless of the device mode. The PLL2 and PLL3

have pre-configured divider ratios to provide frequency multiplication or translation from the VCXO clock

frequency to generate the two common HD clock rates (148.5 MHz and 148.35 MHz). PLL4 is pre-configured to

generate an audio clock that defaults to a 24.576 MHz output, although PLL4 has several registers that allow it to

be re-configured for a variety of applications.

The VCO PLLs use a high loop bandwidth to assure PLL stability, so the VCXO of PLL1 must provide a stable

low-jitter clock reference to ensure optimal output jitter performance. Any unused clock or TOF output can be

placed in Hi-Z mode. This may be useful for reducing power dissipation as well as reducing jitter or phase noise

on the active clock output. The TOF pulse can be programmed to indicate the start (top) of frame and even

provide format cross-locking. The output format registers should be programmed to specify the output timing

(output clocks and TOF pulse), the output timing offset relative to the reference, and the output initialization

(alignment) to the reference frame.

When a loss of reference occurs during genlock, PLL1 can default to either Free-run or Holdover operation.

When Free-run is selected, the output frequency accuracy will be determined by the external bias on the free-run

control voltage input pin, VC_LPF. When Holdover is selected, the loop filter can hold the control voltage to

maintain short-term output phase accuracy for a brief period in order to allow the application to select the

secondary input reference and re-lock the outputs. These options in combination with a proper PLL1 loop

response design can provide flexibility to manage output clock behavior during loss and re-acquisition of the

reference. The reference status and PLL lock status flags can provide real-time status indication to the

application system. The loss of reference and lock detection thresholds can also be configured.

Product Folder Links: LMH1983

3x2

Video Clock

Crosspoint

External Loop Filter and VCXO

VC_LPF XOin-

CLKout2-

NO_LOCK

Fin

Hin

Vin

SDA

SCL

CLKout2+

CLKout1+

CLKout3-

CLKout3+

CLKout4-

CLKout4+

CLKout1-

Device

Control and

Registers

ADDR

XOin+

= Device pins

NO_REF

27.0

(13.5)

MHz

VDD/2

PLL3

3G(HD)/1.001

Video Clock

PLL2

3G(HD)

Video Clock

I2C Interface

PLL1

Genlock PLL

27 MHz

VCXO

148.5

(74.25)

MHz

PLL4

Audio Clock

148.35,

(74.176)

MHz

98.304 MHz,

others*

In1

In2

In3

Out2

Out3

Vc(Genlock)

Vc(Freerun)

10-Bit SAR

ADC

Input Format

and Polarity

Detection

DAC

Ref

Fbk

* Audio Clock PLL supports 98.304/2X MHz, where X=0-15

I2C Address Options: 0x65h-67h

NO_ALIGN

TOF1

Fout1

Fout2

Fout3

Fout4

(Osc In)

MUX

27 MHz_Osc

AFS/Word

LMH1983

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8.2 Functional Block Diagram

8.3 Feature Description

The following subsections provide information about the various control mechanisms and features that are

fundamental to the LMH1983 clock generator.

8.3.1 Control of PLL1

PLL1 generates a 27 MHz reference that is used as the primary frequency reference for all of the other PLLs in

the device. PLL1 has a dual loop architecture with the primary loop locking the external 27 MHz VCXO to a

harmonic of the HIN signal. In addition to this loop, there is a secondary loop that may be used in genlock

operations. This second loop compares the phase of the TOF1 output signal from the LMH1983 to the FIN signal.

In order to bring the frame alignment of the output signals into sync with the input reference, the second loop

may override the primary loop. Detailed information about controlling this functionality is described in TOF1

Alignment.

To illustrate the dual loop architecture of PLL1, refer to the PLL1 block diagram in Figure 9. The primary loop

takes the reference applied to the HIN input and divides that by R (stored in Registers 0x29 and 0x2A). The

dividend is then compared in phase and frequency to the output of the external 27 MHz VCXO divided by N

(stored in Registers 0x2B and 0x2C). The PFD (phase frequency detector) then generates output pulses that are

integrated via an external loop filter that drives the control voltage of the external VCXO.

Product Folder Links: LMH1983

÷ R PFD CP

Current

Source

÷ N VCXO

(ext)

DAC

H in

SAR

MUX

÷ 1 or ÷ 2 CLK1 Out

PFD

V in

TOF1

Loop Filter

(ext)

LMH1983

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Feature Description (continued)

Figure 9. PLL1 Block Diagram

Since PLL2, PLL3, and PLL4 all use PLL1 as their input reference, the performance of PLL1 affects the

performance of all four clock outputs. The loop filters for the other three PLLs are internal, and the bandwidths

are set significantly higher than that of PLL1, so the low frequency jitter characteristics of all four clock outputs

are determined by the loop response of PLL1. Accordingly, special attention should be paid to the PLL1's loop

bandwidth and damping factor.

8.3.2 PLL1 Loop Response Design Equations

The loop response is primarily determined by the loop filter components and the loop gain. A passive second

order loop filter consisting of RS, CS, and CPcomponents can provide sufficient input jitter attenuation for most

applications. In some cases, a higher order filter may be used to shape the low frequency response of PLL1

further. Assuming a topology for the loop filter similar to that shown in the Figure 9, the bandwidth of the PLL is

determined by:

BWPLL1= RSx KVCO x ICP1/(2*π*FB_DIV)

where

• RSis the series resistor value in the external loop filter.

• KVCO is the nominal 27 MHz VCXO gain in Hz/V. KVCO= Pull_range*27 MHz/Vin_Range. For the VCXO used in

the typical interface circuit (Mfgr: CTS, P/N 357LB3C027M0000): LVCO=100 ppm*27 MHz / (3.0V-0.3V) = 1000

Hz/V

• ICP1 is the current from the PLL1 charge pump.

• FB_DIV is the divide ratio of the PLL, which is set by the R and N register values, this will be equal to the

number of 27 MHz clock pulses in one HIN period. For NTSC, this value will be 1716. (1)

Under normal operation, several of these parameters are set by the device automatically, for example the charge

pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump

current are updated, N is changed to allow for lock to the new reference, and the charge pump current is

adjusted to maintain constant loop bandwidth.

It should be noted that this bandwidth calculation is an approximation and does not take into account the effects

of the damping factor or the second pole introduced by CP.

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VC_LPF

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Feature Description (continued)

Figure 10. External Loop Filter Schematic Detail

At frequencies far above the –3dB loop bandwidth, the closed-loop frequency response of PLL1 will roll off at

about –40dB/decade, which is useful for attenuating input jitter at frequencies above the loop bandwidth. Near

the –3dB corner frequency, the roll-off characteristic depends on other factors, such as damping factor and filter

order.

To prevent output jitter due to the modulation of the VCXO by the PLL's phase comparison frequency, the

bandwidth needs to meet the following criterion:

BW ≤(27 MHz / FB_DIV ) / 20 (2)

PLL1's damping factor can be approximated by:

DF = (RS/2)√(ICP1 x CSx KVCO/FB_DIV)

where

• CSis the value of the series capacitor (in Farads) (3)

Typically, DF is targeted to be between 1/√2 and 1, which will yield a good trade-off between lock time and

reference spur attenuation. DF is related to the phase margin, a measure of the PLL stability.

There is a second parallel capacitor, CP, which is needed to filter the reference spurs introduced by the PLL. The

spurs may modulate the VCXO control voltage, leading to jitter. The following relationship should be used to

determine CP:

CP≈CS/20 (4)

The PLL loop gain, K, can be calculated as:

K = ICP1 x KVCO/FB_DIV (5)

Therefore, Bandwidth and Damping Factor can be expressed in terms of K:

BW = RSx K (6)

DF = (RS/2) x √(CSx K) (7)

Product Folder Links: LMH1983

÷RPhase/

Frequency

Detector

Current

Source Loop Filter

VCO

(~1.3545 GHz)

÷(N x 8)

÷3÷ 4 or 5

(is125M) ÷2PLL4_DIV

÷2TOF4_ACLK

MUX

AFS_div

CLKout4

AFS_mode

Frame_in

TOF4

27MHz In

÷ R PFD CP

Current

Source

÷ N VCO

CLK Out

27 MHz In

LMH1983

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Feature Description (continued)

8.3.3 Control of PLL2 and PLL3

PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed

to run at 148.5 MHz and 148.35 MHz respectively. There is a divide-by-two option available to allow the output to

be 74.25 MHz or 74.18 MHz, should these frequencies be required. These two PLLs can also be disabled –

disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not required. Figure 11

shows a simplified functional block diagram of PLL2 and PLL3.

Figure 11. PLL2 / PLL3 Block Diagram

8.3.4 Control of PLL4

Although originally intended to generate only a clock for audio use, PLL4 features much greater versatility.

Several registers may be used to configure PLL4 to generate a broad selection of frequencies. The default state

for PLL4 is to generate 24.576 MHz (48 kHz x 512) on the output of CLK4 and a 5.996 Hz output from TOF4.

This is done by taking CLK1 (27 MHz), and dividing by 75, resulting in a signal of 360 kHz. This frequency is

compared to the internal PLL4 VCO, nominally 1.2 GHz, divided by 4096. The VCO frequency is adjusted via

generate a 98.304 MHz signal (48 kHz x 2048). Any power of two multiple of 48 kHz can be generated by

changing the contents of the PLL4_DIV component of Register 0x34. Note that the divider here is in powers of 2,

so the default value of 2 results in the 98.304 MHz signal being divided by 22or 4. The final CLKout4 frequency

is therefore 24.576 MHz. PLL4_DIV is a 4-bit value, so values up to 15 may be programmed, resulting in a divide

by 215 or 32,768. If audio clocks based on a 44.1 kHz sampling clock are desired, refer to Application Note

AN–2108, Generating 44.1 kHz Based Clocks with the LMH1983, (SNLA129) for detailed instructions.

TOF4 has two different operation modes. When the AFS_mode bit (Register 0x09) is set to a 0, then TOF4 is

derived by dividing CLKout4 by a value of 2TOF4_ACLK (Register 0x4A). if the AFS_mode bit is set to 1, then TOF4

is derived from TOF1 — divided by AFS_div (Register 0x49). When AutoFormatDetect is true, then the AFS_div

Figure 12. PLL4 Block Diagram

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Feature Description (continued)

8.3.5 Clock Output Jitter

Many circuits that require video clocks, such as the embedded Serializers and Deserializers found in FPGAs, are

sensitive to jitter. In all real world applications, jitter has a random component, so it is best specified in statistical

terms. The SMPTE serial standards (SMPTE 259M, SMPTE 292M and SMPTE 424M) use a frequency domain

method of specifying jitter where they refer to the peak-to-peak jitter of a signal after the jitter has been bandpass

filtered. Jitter at frequencies below 10 Hz is ignored, and the jitter in a band from 10 Hz to an intermediate

frequency (1 kHz for the 270 Mbps standard, 100 kHz for the 1.5 Gbps and 3 Gbps standards) is referred to as

timing jitter. Jitter from the intermediate frequency up to 1/10 of the serial rate is referred to as alignment jitter.

The limits that the SMPTE standards place are peak-to-peak limits, but especially at the higher rates, random

processes have a significant impact, and it is not possible to consider peak-to-peak jitter without a corresponding

confidence level. The methodology used to specify the jitter on the LMH1983 decomposes the jitter into a

deterministic component (tDJ) plus a random component (tRJ). This is the methodology used by the jitter analysis

tools supported on high bandwidth oscilloscopes and timing analysis tools from major instrumentation

manufacturers.

To convert between RMS jitter and peak-to-peak jitter, the Bit Error Rate (BER) must be specified. Since jitter is

a random event, without a known BER, the peak-to-peak jitter will be dependent upon the observation time and

can be arbitrarily large. The equation that links peak-to-peak jitter to RMS jitter is:

tP-P= tDJ+α*tRJ (8)

where αis determined by the BER according to the equation:

1/2erfc(√2*α) = BER (9)

The erfc (error function) can be found in several mathematics references and is also a function in both Excel and

MATLAB. A fairly common BER used for these calculations is 10-12, which yields a value of α= 14.

Another common method for evaluating the jitter of a clock output is to look at the phase noise as a function of

frequency. Plots showing the phase noise for each of the four CLKout outputs can be found in Figure 1 through

Figure 8.

8.3.6 Lock Determination

There are four bits in Register 0x02 that indicate the lock status of the four PLLs. Lock determination for PLL1

can be controlled through two registers: LockStepSize (Register 0x2D) and Loss of Lock Threshold (Register

0x1C). The LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still

considering the device to be locked. If the reference to the LMH1983 has a large amount of jitter, then the device

may be unable to declare lock because the LockStepSize is set too low. The second register, the Loss of Lock

Threshold register, controls the lock state declaration of PLL1. This register sets a number of cycles on the HIN

input that must be seen before loss of lock is declared. For some reference signals, there can be several missing

HIN pulses during vertical refresh. Therefore, it is suggested that this register be loaded with a value greater than

six (Loss of Lock Threshold > 6). Pin 11, NO_LOCK, gives the lock status of the LMH1983. Note that the status

of the NO_LOCK pin can also be read from Register 0x01, and it is a logical OR of the four individual NO_LOCK

status bits of the four PLLs. The NO_LOCK status pin is masked by the bits in the PLL Lock mask (Register

0x1D), and the status is also masked if an individual PLL is powered down.

8.3.7 Lock Time Considerations

The lock time of the LMH1983 is dominated by the lock time of PLL1. The other PLLs have much higher loop

bandwidths, and as a result, they lock more quickly than PLL1 does. Therefore, lock time considerations mainly

rely on PLL1. The lock time for a PLL is dependent upon the loop bandwidth (see Equation 1). A small loop

bandwidth typically increases the time required to achieve lock. To counter this issue, the LMH1983 also allows a

Fastlock mode. In this mode, the bandwidth is increased by increasing the charge pump current when the loop is

unlocked. Then, at a time programmed by the user after lock is declared, ICP1 is throttled back to drop the

bandwidth to the desired set point. The result is both fast lock time and very low residual jitter.

Another factor when considering lock time is whether 'drift lock' has been enabled or not (see TOF1 Alignment).

If drift lock is enabled and there is a significant difference in the phase of TOF1 relative to the FIN signal, the

VCXO is slewed to ramp the clock rate up or down until the two framing signals are brought into alignment. It is

possible that this process may take a long time (tens of seconds).

Product Folder Links: LMH1983

NOLOCK

(output)

NOREF

(output)

reference

(input)

NOLOCK

(output)

NOREF

(output)

reference

(input)

Default SettingsFaster NOLOCK mode

LOCK ~ 4.4s

LOCK ~ 760 ms

LMH1983

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Feature Description (continued)

Aside from the time required for the PLL to lock, there is a circuit that determines how to set the NO_LOCK

output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control pin to lock

the VCXO to a harmonic of the incoming reference. When the device is not locked, the PLL pulls the VCXO

control voltage to one extreme of its range to slew the voltage into lock. Once the phase differences between the

VCXO and the reference are small, the device begins to nudge the control voltage back and forth to maintain the

phase difference. An adjustment might be necessary either due to VCXO drift or due to jitter on the reference. To

determine the status of NO_LOCK, the LMH1983 establishes a window to view the amount of adjustment that is

required over a period of time. Two parameters are set via register control to determine NO_LOCK status.

LockStepSize (Register 0x2D) sets the amount of time in which to observe the signal, and Loss of Lock

Threshold (Register 0x1C) sets the amount of variation in the control voltage that can be seen over this time

frame while still considering the device to be locked.

To minimize the amount of time necessary to assert lock, load LockStepSize (Register 0x2D) with a value of

0x01 and the Loss of Lock Threshold (Register 0x1C) with a value of 0x1F. The effect of this change can be

seen in Figure 13:

Figure 13. Faster NO_LOCK Reaction Mode Timing

8.3.8 LOR Determination

When the PLL is not locked, there is an internal counter that counts the number of 27 MHz clock pulses between

consecutive HSync pulses divide-by-two. This counter saturates at 0x7FFF (or 32767 decimal). Once this

counter saturates, LOR is declared. Given this is a divide-by-two counter, the time to declare LOR is: (2 x 32767)

/ (27E6) = 2.4 ms. On the other hand, when the PLL is locked and there are missing HSync pulses, LOR is set

when the internal counter is greater than the following: (Number of 27 MHz clocks in one Hsync pulse + 3) x

(LOR_THRES + 1).

8.3.9 Output Driver Adjustments

The LVDS output drivers can be adjusted via the I2C interface to change the differential output voltage swing, the

common mode voltage, and the amount of pre-emphasis applied to the LVDS output:

• Register 0x3A, Bit 7 turns on the pre-emphasis, which may be used to extend the reach between the

LMH1983 and the load. It is recommended that the trace length is kept short, as longer traces have more

opportunity to couple with hostile signals and degrade jitter performance.

Product Folder Links: LMH1983

TOF1

HIN

FIN

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Feature Description (continued)

• The differential output swing of the CLKout pins is adjusted through Register 0x3A, Bits [6:4]. A larger value

loaded into Bits [6:4] correspond to an increase in the output swing.

• The common mode output voltage can be adjusted via Register 0x3A, Bits [3:0].

8.3.10 TOF1 Alignment

Each of the four clock outputs has a corresponding Top Of Frame (TOF) output signal. The LMH1983 is

programmed with a video format for each of the three video clocks (CLKout 1-3), and the TOF signal provides a

digital indication when the start of a new frame occurs for that particular format. As an example, if PLL1 is

programmed with a video format corresponding to NTSC, CLK1 is 27 MHz, and TOF1 outputs a pulse once per

frame, or once every 900,900 clock cycles. In its default state, the LMH1983 detects the input reference format

and programs this format as the output format for CLKout1. Therefore, if the input reference is an NTSC

reference, then TOF1 will default to a 29.97 Hz signal.

If the HIN, VIN, and FIN inputs to the LMH1983 are coming from the LMH1981 Sync Separator, then the rising

edge of the FIN input will come in the middle of a line (between HIN pulses). The TOF pulse, if aligned, will be a

pulse with a width of 1 x H period and transitions aligned with the leading edges of the HIN pulses. When set for

zero offset, the TOF pulse will be high during the H period where the FIN input transitions, as seen in Figure 14.

Figure 14. TOF1 Timing

The alignment between the incoming FIN and the TOF1 output may be controlled in a number of ways. There are

three different alignment modes in which TOF1 may operate as selected via Register 0x11:

1. 11'b (default): PLL1 never attempts to align.

2. 10'b: PLL1 always forces alignment to FIN.

3. 00'b: Automatically force alignment to FIN when they are misaligned.

Misalignment can be defined by the user via Register 0x15. In Register 0x15, a time window is defined to specify

the amount of mismatch permitted between FIN and TOF1 while still considering them to be aligned. If the input

reference signal has a significant amount of low frequency jitter or wander, it may be possible for the relative

alignment between TOF1 and FIN to vary over time. Selecting "Always Align" mode may lead to undesirable

timing jumps on the output of CLKout1/TOF1.

Once the device decides that it needs to align TOF1 and FIN, there are two ways that it can be done. Crash lock

involves simply resetting the counter that keeps track of where the TOF1 output transition happens, resulting in

an instantaneous shift of TOF1 to align with FIN. Drift lock involves using the second loop in PLL1 and skewing

the VCXO to make the frequency of CLKout1 either speed up or slow down. The VCXO skewing slowly pulls

TOF1 and FIN into alignment. If a new reference is applied that is not in alignment with TOF1, but the output is

currently in use, it may be better to slew TOF1 into alignment rather than to cause a major disruption in the

timing with a crash lock. The LMH1983 allows the user to select either crash lock or drift lock, controllable via

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Feature Description (continued)

2LOA_window x 27 MHz Clock) and when the difference in phase is large (Output > 2LOA_window x 27 MHz Clock).

Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or

retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock

may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input

HIN.

8.3.11 TOF2 and TOF3 Alignment

Similar to TOF1, CLKout2 and CLKout3 have associated video formats. The format is determined by

programming Register 0x07 and 0x08, respectively. Once the format is programmed and the TOF outputs are

enabled, a TOF pulse is generated at the appropriate rate for each of the outputs. There are four different

alignment modes that may be selected for TOF2 and TOF3:

Table 1. TOF2/TOF3 Alignment Modes

TOF2/TOF3 ALIGNMENT MODE DESCRIPTION

0 Auto Align when Misaligned

1 One Shot Manual Align

2 Always Align

3 Never Align

TOF2 and TOF3 are generally aligned with TOF1. The alignment status bit will only be set if the frame rates are

the same as one another. Another option for alignment is via software, where the TOFX_INIT bit is set. For

example, the LSB of Register 0x12 is the TOF2_INIT bit. Writing a 1 to this bit while also setting TOF2 alignment

mode to anything other than 3 (Never Align) will cause TOF2 to reset its phase immediately. Note that this bit is

a self-clearing bit, so it will always return a zero.

8.3.11.1 TOF3 Initialization Set Up

Under some circumstances, it is possible for an LMH1983 to power up in an anomalous state in which the output

of PLL3 exhibits a large amount of cycle-to-cycle jitter. A simple register write after power up will prevent the

device from remaining in this state. Writing to Register 0x13[5:4] = 10'b to force Always Align Mode ensures that

the device will not exhibit poor duty cycle performance on CLKout3.

8.3.12 TOF4 Alignment

CLKout4 of the LMH1983 is most often used to generate an audio clock. The default base audio clock rate is 48

kHz, and this sample clock is synchronous in phase with the video frame only once every 5 frames for 29.97 and

30 Hz frame rate standards, or once every ten frames for 60 Hz and 59.94 Hz systems. The LMH1983 can

generate a TOF4 pulse that occurs at this rate, allowing audio frames to be synchronized with the video frames.

TOF4 may be aligned either to TOF1 or to the FIN input. Additionally, there is an external INIT input that can be

used to set TOF4 alignment.

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10ns / div 4 ns / div

Top 200mV / div Top 200 mV / div

Bottom 1V / div Bottom 1V / div

Figure 15. TOF1 Timing Figure 16. TOF2 Timing

Top Trace CLKout1, Bottom Trace TOF1 Top Trace CLKout2, Bottom Trace TOF2

4ns / div 10 ns / div

Top 200mV / div Top 200 mV / div

Bottom 1V / div Bottom 1V / div

Figure 17. TOF3 Timing Figure 18. TOF4 Timing

Top Trace CLKout3, Bottom Trace TOF3 Top Trace CLKout4, Bottom Trace TOF4

8.4 Device Functional Modes

8.4.1 Reference Detection

The device uses Auto Format Detect as the default mode, as the device determines the reference format among

those shown in Auto Format Detection Codes, and initiates the internal configurations accordingly. There are 31

pre-defined formats plus one format that the user can define. The device recognizes a format by measuring the

HIN input frequency and looking at the VIN and FIN inputs. The device then determines if the reference input

format is an interlaced or progressive input. For some formats such as a 10 MHz or 27 MHz Hsync reference, if

HIN and VIN create a spurious input, the device will not properly recognize the reference input and will not lock

properly to the reference. Because of this, if HIN has one of these 'special' signals on it, VIN and FIN should be

muted.

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Device Functional Modes (continued)

8.4.2 User Defined Formats

There are several registers in the LMH1983 that are loaded automatically based on the format of the reference

that is detected. The LMH1983 allows the user to define a non-standard format and a corresponding set of

values to load into the appropriate registers if that format is detected. In order to identify the format, the

LMH1983 measures the frequency of the Hsync input, counts the number of lines per frame in the format, and

detects if the particular format is interlaced or progressive. The Hsync frequency is measured by counting the

number of 27 MHz clock edges that occur in a period of time equal to 20 horizontal sync times. To implement a

user defined format, the following registers are configured:

• The minimum and maximum permissible count must be set, thereby establishing a window of frequency for

Hsync. Registers 0x51 and 0x52 define the 16-bit value for the low end of the frequency range, while

Registers 0x53 and 0x54 define the high end of the frequency range.

• Registers 0x5A and 0x5B define the number of lines per frame for the format.

• Register 0x5D, Bit 4 indicates whether the user defined format is interlaced or not.

• Register 0x5D, Bit 7 enables the detection of a user-defined format.

• Once the user-defined format is detected, the contents of Registers 0x55 through 0x59 configure PLL1 to lock

to 27MHz, which is then used as the reference for PLL2, PLL3, and PLL4.

Table 2 lists the supported standard timing formats. Table 2 includes the relevant parameters used to configure

the LMH1983 for the input and output formats. Auto-detection of the input is supported for the formats listed in

Table 2. The input format can also be programmed manually by the host via I2C if it is necessary to override the

auto-detection feature.

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Table 2. Supported Formats Lookup Table (LUT)

INPUT TIMING / PLL1 PARAMETERS OUTPUT TIMING (OUT1–4) PARAMETERS

FORMAT Reference Feedback Phase Detector PD Periods per PLL Clock Total Clocks per Total Lines per Frame Rate

PLL#

Divider Divider (PD) Freq. (kHz) Frame Counter Freq. (MHz) Line Counter Frame Counter (Hz)

1 27.0 1716

NTSC, 525i 1 1716 15.7343 525 525 29.97

2 148.5 9438

1 27.0 1728

PAL, 625i 1 1728 15.625 625 625 25

2 148.5 9504

1 27.0 858

525p 1 858 31.4685 525 525 59.94

2 148.5 4719

1 27.0 864

625p 1 864 31.25 625 625 50

2 148.5 4752

720p/60 1 600 45.0 750 2 148.5 3300 750 60

720p/59.94 5 3003 8.99101 150 3 148.35 3300 750 59.94

720p/50 1 720 37.5 750 2 148.5 3960 750 50

720p/30 1 1200 22.5 750 2 148.5 6600 750 30

720p/29.97 5 6006 4.49550 150 3 148.35 6600 750 29.97

720p/25 1 1440 18.75 750 2 148.5 7920 750 25

720p/24 1 1500 18.0 750 2 148.5 8250 750 24

720p/23.98 2 3003 8.99101 375 3 148.35 8250 750 23.98

1080p/60 1 400 67.5 1125 2 148.5 2200 1125 60

1080p/59.94 5 2002 13.48651 225 3 148.35 2200 1125 59.94

1080p/50 1 480 56.25 1125 2 148.5 2640 1125 50

1080p(psF)/30 1 800 33.75 1125 2 148.5 4400 1125 30

1080p(psF)/29.97 5 4004 6.74326 225 3 148.35 4400 1125 29.97

1080p(psF)/25 1 960 28.125 1125 2 148.5 5280 1125 25

1080p(psF)/24 1 1000 27.0 1125 2 148.5 5500 1125 24

1080p(psF)/23.98 1 1001 26.9730 1125 3 148.35 5500 1125 23.98

1080i/60 1 800 33.75 1125 2 148.5 4400 1125 30

1080i/59.94 5 4004 6.74326 225 3 148.35 4400 1125 29.97

1080i/50 1 960 28.125 1125 2 148.5 5280 1125 25

48 kHz word clock 2 1125 24.0 1 4 98.304 2048 1 48000

96 kHz word clock 4 1125 24.0 1 4 98.304 1024 1 96000

27 MHz osc clk 1000 1000 27.000 1 Input only

10 MHz GPS osc clk 600 1620 16.6666 1 Input only

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8.4.3 Auto Format Detection Codes

The Auto Format Detection Codes apply to Registers 0x07 (Output Mode – PLL2 Format), 0x08 (Output Mode –

PLL3 Format), and 0x20 (Input Format).

FORMAT CODE DESCRIPTION Hsync PERIOD INTERLACED (I) /

(in 27 MHz CLOCKS) PROGRESSIVE (P)

0 525I29.97(1) 1716 I

1 625I25(2) 1728 I

2 525P59.94(1) 858 P

3 625P50(2) 864 P

4 720P60 600 P

5 720P59.94 600.6 P

6 720P50 720 P

7 720P30 1200 P

8 720P29.97 1201.2 P

9 720P25 1440 P

10 720P24 1500 P

11 720P23.98 1501.5 P

12 1080P60 400 P

13 1080P59.94 400.4 P

14 1080P50 480 P

15 1080P30 800 P

16 1080P29.97 800.8 P

17 1080P25 960 P

18 1080P24 1000 P

19 1080P23.98 1001 P

20 1080I30 800 I

21 1080I29.97 800.8 I

22 1080I25 960 I

23 1080I24 1000 I

24 1080I23.98 1001 I

25 48 kHz Audio 562.5 —

26 96 kHz Audio 281.25 —

27 44.1 kHz Audio 612.244898 —

28 32 kHz Audio 843.75 —

29 27 MHz Hsync 1 —

30 10 MHz Hsync 2.7 —

31 User Defined User Defined User Defined

63 Unknown All Others

(1) NTSC, 525i and 525p formats are also commonly known as 480I29.97 and 480P59.94, respectively,

since the visible screen resolution consists of 480 pixels.

(2) PAL, 625i and 625p formats are also commonly known as 576I25 and 576P50, respectively, since the

visible screen resolution consists of 576 pixels.

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SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0

0 00110011 0 0

I2C

Slave

Address

$CD

Address Data Byte n

D7 D6 D5 D4 D3 D2 D1 D0 0

Data Byte 1 A

LMH1983

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8.4.4 Free-Run, Genlock, and Holdover Modes

The LMH1983 primary PLL can operate in three different modes, selected via Register 0x05. These modes are

Free-run, Genlock, and Holdover Mode:

• Free-run mode: HIN, VIN, and FIN are not used, and the VCXO control voltage is set by the contents of

Registers 0x18 and 0x19. By writing to these registers, the VCXO voltage can be trimmed up or down. The

slave PLLs will remain locked to the primary PLL.

• Genlock mode: The VCXO control voltage is actively controlled to maintain lock between HIN and the VCXO

output frequency. In addition, there is a second PLL loop that may take over to assert a lock between TOF1

and FIN. See TOF1 Alignment for more details.

• Holdover mode: In the event that the reference is lost, there is an A/D — D/A pair that is able to take over for

the PLL control loop and hold the VCXO control voltage constant. For this to work properly, the device must

realize that it has lost its reference shortly after the reference is actually lost. Some sync separators, when the

analog input is lost, will output random pulses from the H, V, and F outputs. This can confuse the device.

Therefore if Holdover mode is to be used in conjunction with an analog sync separator, it is best to gate the

H, V, and F signals with a signal that indicates if there is a valid reference input.

8.5 Programming

8.5.1 I2C Interface Protocol

The protocol of the I2C interface begins with the start pulse, followed by a byte which consists of a seven-bit

slave device address and a Read/Write bit as an LSB. The default address of the LMH1983 for write sequences

is 0xCC (11001100'b) and for read sequences is 0xCD (11001101'b). The base address can be changed with the

ADDR pin. When ADDR is left open, the base address is 0x66 (which, when left shifted for a write sequence

becomes 0xCC). When ADDR is connected to GND, the base address is 0x65, and when ADDR is connected to

VDD, the base address is 0x67.

Please note: The I2C interface of the LMH1983 requires the 27 MHz VCXO clock input to be running in order to

read I2C data packets into the 27 MHz clock domain. If the 27 MHz clock is not running, the I2C interface should

still respond (ACK), but Write commands may be ignored and Read commands may return invalid data.

8.5.2 Write Sequence

The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is high.

The slave address is sent next. The slave address is a seven-bit address followed by the Read/Write bit (Read =

1'b and Write = 0'b). For the default base address of 0x66 (1100110'b), the 0 is appended to the end, and the net

address is 0xCC. Each byte sent after the address is followed by an ACK bit. When SCL is high, the master will

release the SDA line, and the slave pulls SDA low to acknowledge. Once the device address has been sent, the

next byte sent is the register address. Following the register address and the ACK, the data byte is sent. When

more than one data byte is sent, the register address is automatically incremented so that the data is written into

the next address location. The Write Sequence Timing Diagram is shown in Figure 19. Note that there is an ACK

bit following each data byte.

Figure 19. Write Sequence Timing Diagram

Product Folder Links: LMH1983

SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0

1 00110011 0 0

I2C

Slave

Address

$CD

Data Byte 1 Data Byte n

SCL

SDA A7 A6 A5 A4 A3 A2 A1 A0

00110011 0

I2C

Slave

Address

$CC

Address A

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

Programming (continued)

8.5.3 Read Sequence

Read sequences consist of two I2C transfers. The first is the address access transfer, which consists of a write

sequence that transfers only the address to be accessed. The second is the data read transfer which starts at

the address indicated in the first transfer and increments to the next address, continuing to read addresses until

a stop condition is encountered. The timing diagram of the address access transfer is shown in Figure 20. A read

sequence begins with a start pulse, the slave device address including the Read/Write bit (Read = 1'b and Write

= 0'b), and then its ACK bit. The next byte is the address to be read, followed by the ACK bit and the stop bit to

indicate the end of the address access transfer. The subsequent read data transfer shown consists of the start

pulse, the slave device address including the Read/Write bit (this time a R/W Bit = 1'b, indicating that the data is

to be read) and the ACK bit. The next byte is the data read from the initial access address. After each data byte

is read, the address is incremented, thereby allowing the next byte of data to be read from the subsequent

address of the device. Each byte is separated from the previous byte by an ACK bit, and the end of the read

sequence is indicated with a STOP bit. The timing diagram for a read data transfer is shown in Figure 21 for

additional timing details.

Figure 20. Read Sequence — Address Access Transfer

Figure 21. Read Sequence — Data Read Transfer

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8.6 Register Map

The following table provides details on the device's configuration registers. Default value for fields that are seven

bits or less are expressed in binary, and default values for fields that are 8 bits (Byte) are expressed in hex. Do

not write to Reserved (RSVD) fields.

Table 3. LMH1983 Register Map

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7 INTERLACED R — Indicates if the input reference format is an interlaced format

This bit is set depending on if the sync detection circuit had

6 ANALOG_REF R — determined if the reference is an analog or digital derived

signal

Returns the value of the input polarity determined by the sync

5 INPUT_POLARITY R — detector for HSYNC — 0 indicates an active low sync

Device Status This bit is set if the Hsync During Vsync detector will set

0x00 4 HSYNC_STATUS R —

— Input Reference NO_H_DURING_V on the next rising edge of VSYNC

3 H_ONLY R — This is set by the Interlaced detector

2 LOR_STATUS R — Returns the inverse of the NO_REF output pin state

Set if HSYNC_MISSING is high wile no_h_during_v is low.

1 LOST_HSYNC R — Remains set until read, then self-clears

0 Reserved R 0 Reserved — always returns '0'

7 Lock_Status R 1 Returns lock status for all unmasked and enabled PLLs

6 Align_Status R 0 Returns the Align Status for all enabled TOFs

0x01 Device Status 5 Wrong_Format R 1 Returns the value of the Wrong_Format bit.

4 Holdover R 0 Returns the value of the PLL Holdover Bit

3:0 RSVD 0000 Reserved

[7] indicates the lock status of PLL4.

[6] indicates the lock status of PLL3.

[5] indicates the lock status of PLL2.

7:4 Lock_Detect R — [4] indicates the lock status of PLL1.

0 = PLL Not Locked

1 = PLL Locked

PLL Lock and Output

0x02 Alignment Status [3] indicates the lock status of TOF4.

[2] indicates the lock status of TOF3.

[1] indicates the lock status of TOF2.

3:0 Align_Detect R — [0] indicates the lock status of TOF1.

0 = TOF Alignment not detected

1 = TOF alignment detected

0x03 Revision ID 7:0 R 0xC0 Returns device revision code

0x04 Reserved 7:0 RSVD 0x00 Reserved

Writing a ‘1’ will reset all registers to their default values. This

7 Soft_Reset R/W 0 bit is self-clearing and always returns ‘0’ when read.

6 Powerdown R/W 0 Controls the power down function.

Enables Auto Format Detection (AFD).

5 EN_AFD R/W 1 0 = Auto Format Detect disabled

1 = Auto Format Detect enabled

Sets PLL1 operating mode:

00 = Force Free-run

4:3 PLL1_Mode R/W 01 01 = Genlock

10 = Force Holdover

11 = Reserved

0x05 Device Control Sets default mode of operation on Loss of Reference (LOR)

condition:

2 LOR Mode R/W 0 0 = Holdover on LOR

1 = Free-run on LOR

When this bit is set, it forces the PLL2 and PLL3 clock rates to

148.xx MHz regardless of chosen output format. Otherwise,

the native clock rate of the chosen output format will be used.

1 Force_148 R/W 1 0 = Uses the native clock rates

1 = Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz clock

rate

Global Output Enable

0 GOE R/W 1 0 = Disables all CLKout and Fout output buffers (Hi-Z)

1 = Enable active outputs

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7:4 RSVD 0000 Reserved

Enables Auto Polarity Detection and Correction. The proper

polarity needs to be set to synchronize the output timing

signals to the leading edges of the H and V inputs.

0 = The polarities of HVF inputs are manually set by their

3 EN_AUTOPOL R/W 1 respective polarity override registers.

1 = The polarity of the H input is auto-detected. The polarity

correction applied to the H input will also be applied to V and

F inputs.

0x06 Input Polarity Used to manually set the H input Polarity.

2 HIN_POL_OVR R/W 0 0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

Used to manually set the V input Polarity.

1 VIN_POL_OVR R/W 0 0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

Used to manually set the F input Polarity.

0 FIN_POL_OVR R/W 0 0 = Active Low (Negative polarity)

1 = Active High (Positive polarity)

7:6 RSVD 00 Reserved

0x07 Output Mode – PLL2 Format 5:0 PLL2_Format R/W 001110 Sets the video format output timing for PLL2.

7:6 RSVD 00 Reserved

0x08 Output Mode – PLL3 Format 5:0 PLL3_Format R/W 001101 Sets the video format output timing for PLL3.

7:5 RSVD 000 Reserved

Sets the TOF4 output timing mode.

4 AFS Mode R/W 0 0 = Secondary Audio Clock Output (derived from PLL4 clock)

0x09 Output Mode – Misc 1 = Audio Frame Sync (derived from TOF1)

Sets the PLL crosspoint mode for Out2 and Out3.

3:0 XPT_Mode R/W 0000 Refer to Table 4.

[3] sets CLKout4 output buffer mode.

[2] sets CLKout3 output buffer mode.

[1] sets CLKout2 output buffer mode.

7:4 CLK_HIZ R/W 0000 [0] sets CLKout1 output buffer mode.

0 = CLKoutx enabled

1 = CLKoutx Hi-Z

0x0A Output Buffer Control [3] sets Fout4 output buffer mode.

[2] sets Fout3 output buffer mode.

[1] sets Fout2 output buffer mode.

3:0 FOUT_HIZ R/W 1111 [0] sets Fout1 output buffer mode.

0 = Foutx enabled

1 = Foutx Hi-Z

7:5 RSVD 000 Reserved

Output Frame Control –

0x0B Offset1_MSB 4:0 TOF1 Offset MSB R/W 00000 TOF1_Offset[12:0] sets number of lines to delay TOF1.

TOF1_Offset_MSB[4:0] sets TOF1_Offset[12:8]

Output Frame Control –

0x0C 7:0 TOF1 Offset LSB R/W 0x00 TOF1_Offset_LSB[7:0] sets TOF1_Offset[7:0]

Offset1_LSB

7:5 RSVD 000 Reserved

Output Frame Control –

0x0D Offset2_MSB 4:0 TOF2 Offset MSB R/W 00000 TOF2_Offset[12:0] sets number of lines to delay TOF2.

TOF2_Offset_MSB[4:0] sets TOF2_Offset[12:8]

Output Frame Control –

0x0E 7:0 TOF2 Offset LSB R/W 0x00 TOF2_Offset_LSB[7:0] sets TOF2_Offset[7:0]

Offset2_LSB

7:5 RSVD 000 Reserved

Output Frame Control –

0x0F Offset3_MSB 4:0 TOF3 Offset MSB R/W 00000 TOF3_Offset[12:0] sets number of lines to delay TOF3.

TOF3_Offset_MSB[4:0] sets TOF3_Offset[12:8]

Output Frame Control –

0x10 7:0 TOF3 Offset LSB R/W 0x00 TOF3_Offset_LSB[7:0] sets TOF3_Offset[7:0]

Offset3_LSB

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7:6 RSVD 00 Reserved

00 = Auto-align when misaligned

01 = Reserved

5:4 TOF1_Align_Mode R/W 11 10 = Always Align

11 = Never Align(1)

This bit sets the PLL1/TOF1 output synchronization behavior

when the same reference is reapplied following a momentary

LOR condition and TOF1 is within 2 lines of the expected

location.

00 = Always Drift Lock – ensures the outputs drift smoothly

back to frame alignment without excessive output phase

3:2 TOF1_Sync R/W 01 disturbances

0x11 Alignment Control – TOF1 01 = Drift Lock if output < (2LOA_window x 27 MHz Clock). Crash

Lock otherwise.

1X = Always Crash Lock – achieves the fastest frame

alignment through PLL/TOF counter resets, which can result in

output phase disturbances

Sets the direction that TOF1 slews to achieve frame alignment

when a new reference is applied and TOF1 is outside of 2

1 TOF1_Sync_Slew R/W 0 lines of the expected location.

0 = TOF1 lags by railing the VCXO input low

1 = TOF1 advances by railing the VCXO input high

0 RSVD 0 Reserved

7:6 RSVD 00 Reserved

00 = auto align when misaligned

01 = one shot manual align when writing TOF2_INIT=1

5:4 TOF2_Align_Mode R/W 11 10 = always align

11 = never align

3:1 RSVD 000 Reserved

0x12 Alignment Control – TOF2 Writing one to this bit while also writing TOF2_Align_Mode =

3, will cause the TOF2_INIT output to go high for at least one

vframe period + one Hsync period and not more than one

vframe period + two Hsync periods. The assertion of

0 TOF2_INIT R/W 0 TOF2_INIT must happen immediately (it cannot wait for

Hsync). If TOF2_Align_Mode is being written to 3, this bit will

have no effect. This bit is self-clearing and will always read

zero.

7:6 RSVD 00 Reserved

00 = auto align when misaligned

01 = one shot manual align when writing TOF3_INIT=1

5:4 TOF3_Align_Mode R/W 11 10 = always align

11= never align

3:1 RSVD 000 Reserved

0x13 Alignment Control – TOF3 Writing one to this bit while also writing TOF3_Align_Mode ≠

3, will cause the TOF3_INIT output to go high for at least one

vframe period + one Hsync period and not more than one

0 TOF3_INIT R/W 0 vframe period + two Hsync periods. The assertion of

TOF3_init must happen immediately (it cannot wait for Hsync).

If TOF3_Align_Mode is being written to 3, this bit will have no

effect. This bit is self-clearing and will always read zero.

(1) NOTE: When H_ONLY is 1, TOF1 align mode is forced to never align.

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7:6 RSVD 00 Reserved

00 = auto align when misaligned

01 = one shot manual align. AFS_Init_Input reg determines if

5:4 AFS_Align_Mode R/W 11 done by pin (INIT) or register (AFS_INIT = 1)

10 = always align

11= never align

0 = Rising edges on INIT (pin 6) trigger AFS one shot manual

align.

3 AFS_Init_Input R/W 0 1 = Writing ‘1’ to AFS_Init register triggers AFS one shot

manual align.

0x14 Alignment Control – AFS 2:1 RSVD 00 Reserved

Writing one to this bit while also writing AFS_Align_Mode = 3

and AFS_Init_Input=1, or providing a rising edge on the init

input when AFS_Align_Mode ≠3 and AFS_Init_Input=0, will

cause the AFS_INIT output to go high for at least one vframe

0 AFS_INIT R/W 0 period + one Hsync period and not more than one vframe

period + two Hsync periods. The assertion of AFS_INIT must

happen immediately (it cannot wait for Hsync). If

AFS_Align_Mode = 3, toggling the init input will have no effect.

This bit is self-clearing and will always read zero.

7:3 RSVD 00000 Reserved

Number of 27 MHz clocks between the TOF1 and Vsync

before Loss of Alignment is reported.

0x15 Loss of Alignment Control If the code loaded in this register is n, then Loss of Alignment

2:0 LOA_Window R/W 010 will be reported if the difference between TOF1 and Vsync

exceeds 2n27 MHz clock cycles

7:2 RSVD 000000 Reserved

The VC_Hold[9:0] input signal changes rather slowly. For

synchronization, it should be sampled on consecutive 27 MHz

clocks until two identical values are found. This value will be

saved as VC_Hold_sampled[9:0].

LOR Control – Holdover

0x16 Whenever the VC_Hold[9:8] register is read,

Sampled Voltage MSB 1:0 VC_Hold_MSB R 10 VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will

memorize the current value of VC_Hold_sampled[7:0] (to be

read at a later time).

This scheme allows a coherent 10-bit value to be read.

Returns a synchronized snapshot of the VC_Hold[9:8] (MSB).

The VC_Hold[9:0] input signal changes rather slowly. For

synchronization, it should be sampled on consecutive 27 MHz

clocks until two identical values are found. This value will be

saved as VC_Hold_sampled[9:0].

LOR Control – Holdover Whenever the VC_Hold[9:8] register is read,

0x17 7:0 VC_Hold_LSB R —

Sampled Voltage LSB VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will

memorize the current value of VC_Hold_sampled[7:0] (to be

read at a later time).

This scheme allows a coherent 10-bit value to be read.

Returns a synchronized snapshot of the VC_Hold[7:0] (LSB)

7:2 RSVD Reserved

LOR Control Free-run Free-run Control Voltage (VC_Free[9:0]) is the voltage

0x18 Control Voltage MSB 1:0 VC_Free_MSB R/W 01 asserted on VC_LPF pin in free-run mode.

Writing will change the MSB (VC_Free[9:8])

Free-run Control Voltage (VC_Free[9:0]) is the voltage

LOR Control – Free-run

0x19 7:0 VC_Free_LSB R/W 0xFF asserted on VC_LPF pin in free-run mode.

Control Voltage LSB Writing will change the LSB (VC_Free[7:0])

7:2 RSVD 000000 Reserved

Directly controls the ADC_Disable output port.

1 ADC_Disable R/W 0 0 = enable holdover ADC

LOR Control – ADC and

0x1A 1 = disable holdover ADC

DAC Disable Directly controls the DAC_Disable output port.

0 DAC_Disable R/W 0 0 = enable Free-run/Holdover DAC

1 = disable Free-run/Holdover DAC

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7 RSVD 0 Reserved

HSYNC_Missing Sets the threshold for number of additional clocks to wait

6:4 R/W 00

Threshold before setting HSYNC_Missing.

Loss of Reference

0x1B 3 RSVD 0 Reserved

Threshold Sets the number of Hsync periods to wait before setting loss

2:0 LOR_Threshold R/W 001 of reference. Since during blanking there can have up to 5

missing Hsync pulses, this value is usually set to 6.

7:5 RSVD 000 Reserved

Sets the number of Hsync periods to wait before setting loss

0x1C Loss of Lock Threshold 4:0 LOCK1_Threshold R/W 10000 of lock. Since during blanking there can have up to 5 missing

Hsync pulses, this value is usually set > 6.

Setting this bit masks the PLL4 lock status in the global

7 MASK_LOCK4 R/W 0 LOCK_STATUS bit.

Setting this bit masks the PLL3 lock status in the global

6 MASK_LOCK3 R/W 0 LOCK_STATUS bit.

Setting this bit masks the PLL2 lock status in the global

5 MASK_LOCK2 R/W 0 LOCK_STATUS bit.

Setting this bit masks the PLL1 lock status in the global

4 MASK_LOCK1 R/W 0 LOCK_STATUS bit.

Mask Control – PLL Lock

0x1D and Output Align Setting this bit masks the TOF4 align status in the global

3 MASK_TOF4_ALIGN R/W 0 ALIGN_STATUS bit.

Setting this bit masks the TOF3 align status in the global

2 MASK_TOF3_ALIGN R/W 0 ALIGN_STATUS bit.

Setting this bit masks the TOF2 align status in the global

1 MASK_TOF2_ALIGN R/W 0 ALIGN_STATUS bit.

Setting this bit masks the TOF1 align status in the global

0 MASK_TOF1_ALIGN R/W 0 ALIGN_STATUS bit.

0x1E Reserved 7:0 RSVD 0x00 Reserved

0x1F Reserved 7:0 RSVD 0x00 Reserved

7:6 RSVD 00 Reserved

When Auto Format Detection is enabled (EN_AFD, address

0x05), this register is read-only and controlled automatically.

When Auto Format Detection is disabled, this register is

writable via I2C.

0x20 Input Format All writes to this register (whether automatic or manual) will

5:0 Input Format 000000 update all the LUT1 (Lookup Table 1), LUT2_2, and LUT2_3

output registers based on the value written here. Writing to

any of the LUT1, LUT2_2, or LUT2_3 output registers will set

this field to 6’d62 (0x3E) indicating that custom changes have

been made.

7:4 RSVD 00 Reserved

Writes to this register update the Vsync code which tells the

device what the Input frame rate is. There is a table which

Output Frame Lookup –

0x21 correlates the Vsync codes to the actual frame rates. When

Input Vsync Code 3:0 Input Vsync Code R/W 0011 Auto Format Detection is enabled (EN_AFD, address 5), this

device.

7:4 RSVD 00 Reserved

Whenever PLL2_FORMAT (address 7) is written, this field is

Output Frame Lookup –

0x22 updated with the appropriate Vsync code. If any custom

PLL2 Vsync Code 3:0 PLL2 Vsync Code R/W 0101 changes are made the device will set this field to 4’d14 (0x0E)

to so indicate.

7:4 RSVD 0000 Reserved

Whenever PLL3_FORMAT (address 8) is written, this field is

Output Frame Lookup –

0x23 updated with the appropriate Vsync code. If any custom

PLL3 Vsync Code 3:0 PLL3 Vsync Code R/W 0110 changes are made the device will set this field to 4’d14 (Ox0E)

to so indicate.

0x24 Reserved 7:0 RSVD 0x00 Reserved

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7:5 RSVD 000 Reserved

0 = Divide by 1 (Output is 27 MHz)

4 PLL1_DIV R/W 0 1 = Divide by 2 (Output is 13.5 MHz)

3 RSVD 0 Reserved

Directly controls the mode of the PLL1 input buffer.

2 PLL1 Input Mode R/W 0 0 = Single Ended

0x25 PLL1 Advanced Control 1 = Differential

1 RSVD 0 Reserved

This bit enables ICP1_FAST (address 0x27) to be used during

locking.

0 FastLock 1 0 = FastLock disabled

1 = FastLock enabled

7:4 RSVD 0000 Reserved

Sets the amount of time that PLL1_Lock must be asserted

before the PLL1 Charge pump current is reduced from the

PLL1 Advanced Control

0x26 ICP1_Fast value to the ICP1 value. The time delay is specified

FastLock Delay 3:0 FastLock Delay R/W 0000 in units of half seconds. Delay = FastlockDelay*0.5 Seconds.

Valid values are from 0 to 10. Values from 11 to 15 are

reserved.

This field specifies the charge pump current to drive when

PLL1 Advanced Control FastLock Charge Pump

0x27 4:0 R/W 11111 FastLock is active. Charge pump current is equal to 34.375 µA

Fastlock CP Current Current * register value

This field defines the charge pump current used when

PLL1 Advanced Control PLL1 Charge Pump

0x28 4:0 R/W 01000 FastLock is not active. Charge pump current is equal to

Charge Pump Current Current 34.375 µA * register value

7:2 RSVD 000000 Reserved

PLL1 Advanced Control

0x29 R Counter MSB 1:0 MSB R/W 00 The two LSBs of Register 0x29 along with the eight bits of

divider for PLL1. This register is internally written based on the

PLL1 Advanced Control

0x2A 7:0 LSB R/W 0x01 input format and when AutoFormatDetect is enabled, these

R Counter LSB registers are read only.

7 RSVD 0 Reserved

PLL1 Advanced Control

0x2B N Counter MSB 6:0 MSB R/W 0000110 The 7 LSBs of Register 0x2B along with the eight bits of

the N divider of PLL1. These registers are internally controlled

PLL1 Advanced Control

0x2C 7:0 LSB R/W 0xB4 based on the input format detected and when

N Counter LSB AutoFormatDetect is enabled, these registers are read only.

7:5 RSVD 000 Reserved

PLL1 Advanced Control

0x2D Lock Step Size 4:0 Lock Step Size R/W 01000 See Application Information section discussion on Lock Detect

7:5 RSVD 000 Reserved

0 = divide by 1

4 PLL2_DIV R/W 0 1 = divide by 2

PLL2 Advanced Control

0x2E 0 = PLL2 disable is determined by XPT_MODE (Address

Main 3 PLL2_DISABLE R/W 0 0x09)

1 = PLL2 is disabled

2:0 RSVD 000 Reserved

7:4 RSVD 0000 Reserved

PLL2 Advanced Control

0x2F Charge Pump Current 3:0 ICP2 R/W 0010 Controls PLL2 Charge Pump Current

PLL2 Advanced Control

0x30 7:0 VCO_RNG2 R/W 0x0C Controls the VCO range

VCO Range

7:5 RSVD 000 Reserved

0 = divide by 1

4 PLL3_DIV R/W 0 1 = divide by 2

PLL3 Advanced Control

0x31 0 = PLL3 disable is determined by XPT_MODE (Address

Main 3 ICP3 R/W 0 0x09)

1 = PLL3 is disabled

2:0 RSVD 000 Reserved

7:4 RSVD 0000 Reserved

PLL3 Advanced Control

0x32 Charge Pump Current 3:0 ICP3 R/W 0011 Controls PLL3 Charge Pump Current

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Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

PLL3 Advanced Control

0x33 7:0 VCO_RNG3 R/W 0x05 Controls the VCO range

VCO Range

Controls the PLL4 output divider — PLL4 is divided by

7:4 PLL4_DIV R/W 0010 2PLL4_DIV

0 = PLL4 is enabled

3 PLL4_Disable R/W 0 1 = PLL4 is disabled

PLL4 Advanced Control

0x34 2 RSVD 0 Reserved

Main 0 = 100 MHz clock

1 IS125M R/W 0 1 = 125 MHz clock

0 = using 27 MHz Clock

0 PLL4_Mode R/W 0 1 = using external clock

7:4 RSVD 0000 Reserved

PLL4 Advanced Control

0x35 Charge Pump Current 3:0 ICP4 R/W 1000 Controls PLL4 Charge Pump Current

7 RSVD 0 Reserved

PLL4 Advanced Control

0x36 R counter 6:0 DIV_R4 R/W 1001011 Sets the R divider in PLL4

7:2 RSVD 000000 Reserved

PLL4 Advanced Control

0x37 N counter MSB 1:0 DIV_N4_MSB R/W 10 Two MSBs of the N divider in PLL4

PLL4 Advanced Control

0x38 7:0 DIV_N4_LSB R/W 0x00 8 LSBs of the N divider in PLL4

N counter LSB

PLL4 Advanced Control The value in the VCO4 Range register is used to adjust the

0x39 7:0 VCO4 Range R/W 0x16

VCO Range center frequency of PLL4.

7 LVDS Boost R/W 0 Applies pre-emphasis to LVDS output

0x3A LVDS Control 6:4 LVDS_DIFF R/W 100 Adjusts LVDS Differential output swing

3:0 LVDS_CM R/W 1001 Adjusts LVDS Common Mode output voltage

7:5 RSVD 000 Reserved

TOF1 Adv Control 5 MSBs of the TOF1 lines per Frame count. This is read-only

0x3B LPF MSB 4:0 TOF1_LPF_MSB R 00010 and loaded automatically when Auto Format Detection is

enabled

8 LSBs of the TOF1 lines per Frame count. This is read-only

and loaded automatically when Auto Format Detection is

TOF1 Advanced Control enabled

0x3C 7:0 TOF1_LPF_LSB R 0x0D

LPF_LSB Together with Register 0x3B this is a 13 bit number which

number of lines per frame. TOF1 will be at a frequency of

Hsync divided by this value.

7 RSVD 0 Reserved

TOF2 Advanced Control

0x3D CPL MSB 6:0 TOF2_CPL_MSB R 0001010 This 15 bit register gives the number of clock cycles per line to

calculate TOF2. It is loaded automatically based on the format

TOF2 Advanced Control

0x3E 7:0 TOF2_CPL_LSB R 0x50 set with Register 0x07.

CPL LSB

7:5 RSVD 000 Reserved

TOF2 Advanced Control

0x3F LPF MSB 4:0 TOF2_LPF_MSB R 00010 This 13 bit register is loaded automatically based on the

format selected via Register 0x07. It sets the number of lines

TOF2 Advanced Control per frame for the selected format to set the TOF2 rate

0x40 7:0 TOF2_LPF_LSB R 0x65

LPF_LSB correctly.

7:5 RSVD 000 Reserved

TOF2 Advanced Control

0x41 Frame Reset MSB 4:0 TOF2_RST_MSB R 00010 Automatically loaded based on formats selected.

TOF2 Advanced Control

0x42 7:0 TOF2_RST_LSB R 0x58

Frame Reset LSB

7 RSVD 0 Reserved

TOF3 Advanced Control

0x43 CPL_MSB 6:0 TOF3_CPL_MSB R 0001000 This 15 bit register gives the number of clock cycles per line to

calculate TOF3. It is loaded automatically based on the format

TOF3 Advanced Control

0x44 7:0 TOF2_CPL_LSB R 0x98 set with Register 0x08.

CPL_LSB

7:5 RSVD 000 Reserved

TOF3 Advanced Control

0x45 LPF_MSB 4:0 TOF3_LPF_MSB R 00100 This 13 bit register is loaded automatically based on the

format selected via Register 0x08. It sets the number of lines

TOF3 Advanced Control per frame for the selected format to set the TOF3 rate

0x46 7:0 TOF3_LPF_LSB R 0x65

LPF_LSB correctly.

Product Folder Links: LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

Table 3. LMH1983 Register Map (continued)

ADD NAME BITS FIELD R/W DEFAULT DESCRIPTION

7:5 RSVD 000 Reserved

TOF3 Advanced Control

0x47 Frame Reset MSB 4:0 TOF3_RST_MSB R 00000 Automatically loaded based on formats selected.

TOF3 Advanced Control

0x48 7:0 TOF3_RST_LSB R 0x01

Frame Reset LSB

TOF4 Advanced Control See Detailed Description section for details. See also PLL4

0x49 7:0 TOF4_AFS R/W 0x05

AFS Block Diagram.

7:4 RSVD 0000 Reserved

TOF4 Advanced Control

0x4A See Detailed Description section for details. See also PLL4

ACLK 3:0 TOF4_ACLK R/W 1011 Block Diagram.

0x4B

to Reserved 7:0 RSVD 0x00 Reserved

0x50

User Auto Format User format detect is determined by looking at the frequency

0x51 7:0 USR_27M_High_MSB R/W 0x00

27M High Value MSB of the Hsync input. This frequency is measured by counting

the number of 27 MHz clock cycles that occur in 20 Hsync

periods. This 16 bit register lists the maximum number of 27

User Auto Format

0x52 7:0 USR_27M_High_LSB R/W 0x00 MHz clock cycles in 20 Hsync periods that could be

27M High Value LSB considered to meet the criteria for the User Format

User Auto Format User format detect is determined by looking at the frequency

0x53 7:0 USR_27M_Low_MSB R/W 0x00

27M Low Value MSB of the Hysnc input. This frequency is measured by counting

the number of 27 MHz clock cycles that occur in 20 Hsync

periods. This 16 bit register lists the minimum number of 27

User Auto Format

0x54 7:0 USR_27M_Low_LSB R/W 0x00 MHz clock cycles in 20 Hsync periods that could be

27M Low Value LSB considered to meet the criteria for the User Format

7:2 RSVD 000000 Reserved

User Auto Format

0x55 R divider MSB 1:0 USR_DIV_R1_MSB R/W 00 See Detailed Description section for details.

User Auto Format

0x56 7:0 USR_DIV_R1_LSB R/W 0x00 See Detailed Description section for details.

R Divider LSB

7 RSVD 0 Reserved

User Auto Format

0x57 N Divider MSB 6:0 USR_DIV_N1_MSB R/W 0000000 See Detailed Description section for details.

User Auto Format

0x58 7:0 USR_DIV_N1_LSB R/W 0x00 See Detailed Description section for details.

N Divider LSB

User Auto Format

0x59 7:0 USR_ICP R/W 0x00 See Detailed Description section for details.

Charge Pump Current

7:5 RSVD 000 Reserved

User Auto Format

0x5A LPF MSB 4:0 USR_TOF_LPF_MSB R/W 00000 See Detailed Description section for details.

User Auto Format

0x5B 7:0 USR_TOF_LPF_MSB R/W 0x00 See Detailed Description section for details.

LPF LSB

User Auto Format

0x5C 7:0 USR_TOF4 R/W 0x00 See Detailed Description section for details.

AFS

Enables the Auto Format Detection User Mode.

7 EN_USERMODE R/W 0 0 = disabled

1 = enabled

6:5 RSVD 00 Reserved

User Auto Format Sets the INTERLACED value to output from LUT1 if the

0x5D Misc INPUT_FORMAT register is set to the user code. This bit also

4 USR_IINTERLACED R/W 0 specifies the value that the Auto Format Detection must see

on the interlaced signal to detect the user defined mode.

Sets the INPUT_VS_CODE value to output from LUT1 if the

3:0 USR_IN_VS_CODE R/W 0000 INPUT_FORMAT registers is set to the user code.

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Table 4. Crosspoint Output Selection Table

0000 (default) 0 0 PLL2 PLL3

0001 1 1 PLL1 PLL1

0010 0 1 PLL2 PLL2

0011 1 0 PLL3 PLL3

0100 0 0 PLL3 PLL2

0101 1 0 PLL1 PLL3

0110 0 1 PLL2 PLL1

0111 0 1 PLL1 PLL2

1000 1 0 PLL3 PLL1

1001 Reserved Reserved Reserved Reserved

1010 Reserved Reserved Reserved Reserved

1011 Reserved Reserved Reserved Reserved

1100 Reserved Reserved Reserved Reserved

1101 Reserved Reserved Reserved Reserved

1110 Reserved Reserved Reserved Reserved

1111 Reserved Reserved Reserved Reserved

(1) PLL2_Disable and PLL3_Disable can be forced via register writes to the PLLx_DISABLE registers independently of the status of the

Crosspoint Mode bits.

Table 5. Vsync Codes

Vsync CODE FRAME RATE (Hz)

NUMBER (BINARY)(1)

0 (0000) 23.98 Hz

1 (0001) 24 Hz

2 (0010) 25 Hz

3 (0011) 29.97 Hz

4 (0100) 30 Hz

5 (0101) 50 Hz

6 (0110) 59.94 Hz

7 (0111) 60 Hz

(1) Vsync codes are used by Registers 0x21 (Output Frame Lookup –

Input Vsync Code), 0x22 (Output Frame Lookup – PLL2 Vsync

Code), and 0x23 (Output Frame Lookup – PLL3 Vsync Code).

Product Folder Links: LMH1983

LOOP

FILTER 27 MHz

VCXO

LMH1983

FPGA

A/V Frame Sync with

Downconverter,

Audio Embedder and

De-embedder

1080p/59.94 SDI out

+ embedded audio

LMH1981

Sync

Separator

H sync

V sync

525i

Analog

ref. in F sync

27 MHz (PLL1)

148.5 MHz (PLL2)

148.35 MHz (PLL3)

24.576 MHz (PLL4)

1080p/59.94 SDI in

+ embedded audio

Genlocked to video ref. in

525i/29.97 SDI out

+ embedded audio

CLKout1

CLKout4

CLKout2

CLKout3

Hin

Vin

Fin

29.97 Hz (TOF1)

29.97 Hz (TOF2)

59.94 Hz (TOF3)

5.994 Hz

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a

variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The

LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with

programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-

stage PLL architecture to attenuate input timing jitter for minimum jitter transfer. The combination of the external

VCXO, external loop filter, and programmable PLL parameters provides flexibility to optimize the loop bandwidth

and loop response for design applications.

9.2 Typical Applications

9.2.1 Typical Genlock Timing Generation with NTSC 525i/29.97 High Speed Reference

The LMH1983 is commonly used with Hsync, Vsync, and Fsync timing signals as a reference for genlock. Once

these signals are provided, the LMH1983 can produce a specific set of clock output signals required by a

downstream endpoint. In some video applications, a multi-format video sync separator is used to derive the

Hsync, Vsync, and Fsync signals from a standard analog SD/ED/HD video signal. In Figure 22, a LMH1981

multi-format sync separator is used to provide HIN, VIN, and FIN for the LMH1983. In this case, LMH1983 PLLs 1-

4 provide a 27 MHz/29.97 Hz, 148.5 MHz/29.97 Hz, 148.35 MHz/59.94 Hz, and 24.576 MHz/5.994 Hz output,

respectively, to an A/V Frame Synchronizer. Another example of this application can be seen in Figure 23, where

HIN, VIN, and FIN signals are provided directly from an FPGA SDI RX without a sync separator. In the latter

example, the NTSC 525i/29.97 HIN, VIN, and FIN parameters are provided individually for the LMH1983, after

which the LMH1983 provides 3G, 3G/1.001, and Audio Clock Generation.

Figure 22. LMH1983 Video Genlock Timing Generation for A/V Frame Synchronizer

Product Folder Links: LMH1983

LOOP

FILTER 27 MHz

VCXO

LMH1983 HD-SDI Upconverter

(HD/SD Simulcast)

with Audio Embedder

525i/29.97 SDI out

+ embedded audio

H blank

V blank

525i/29.97 digital

blanking pulse inputs

from FPGA SDI RX F blank

27 MHz

148.5 MHz (PLL2)

148.35 MHz (PLL3)

24.576 MHz 525i/29.97 SDI in

+ embedded audio

A/V clock signals

genlocked to SDI in

1080i/29.97 SDI out

+ embedded audio

PLL1 Ref. In Format = 525i/29.97

PLL2 Video Format = 525i/29.97*

PLL3 Video Format = 1080i/29.97*

PLL4 Audio Format = 24.576 MHz with 48 kHz word clock

* GHQRWHV³3*&/.´PRGH(148.5 or 148.35 MHz)

CLKout1

CLKout4

CLKout2

CLKout3

Hin

Vin

Fin

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

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Typical Applications (continued)

Figure 23. LMH1983 Video Timing Generation for HD-SDI Up-Conversion with Audio Embed/De-embed

9.2.1.1 Design Requirements

When designing for the LMH1983, it is essential to choose the correct VCXO and external loop filter capacitors.

The following subsections provide guidance regarding how to select these components to improve timing stability

and accuracy.

9.2.1.1.1 VCXO Selection Criteria

The recommended VCXO is CTS part number 357LB3C027M0000, which has an absolute pull range of ±50 ppm

and a temperature range of –20°C to +70°C. A VCXO with a smaller APR can provide better frequency stability

and slightly lower jitter, but the APR must be larger than the anticipated variation of the input frequency range.

9.2.1.1.2 Loop Filter Capacitors

The most common types of capacitors used in many circuits today are ferroelectric ceramic capacitors such as

X7R, Y5V, X5R, Y5U, and so on. These capacitors suffer from piezoelectric effects, which generate an electrical

signal in response to mechanical vibration, stress, and shock. This effect can adversely affect the jitter

performance when presented to the control input to the VCXO. The easiest way to eliminate this effect is to use

tantalum capacitors that do not exhibit the piezoelectric effect.

9.2.1.2 Detailed Design Procedure

Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should

be referenced to Table 2 to determine whether NTSC 525i/29.97 sync format is supported. This video format is a

supported video format for automatic detection under Auto Format Detection Code 0, so it is not necessary to

override the input auto-detection feature.

Once PLL1 has genlocked to the chosen NTSC, 525i input reference signal, PLLs 2-3 can be set according to

the desired output signals specified in Figure 23. Refer to Table 6 and Table 7 for a list of possible input and

output formats available for auto-format detection in Figure 22 and Figure 23, respectively. The format code can

be applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2

(Register 0x07) and PLL3 (Register 0x08).

Table 6. Relevant Auto-Format Detection Codes for Figure 22

PLLx HSync PERIOD

FORMAT CODE DESCRIPTION

(INPUT/OUTPUT) (in 27 MHz CLOCKS)

PLL1 (Input) 0 525I29.97 1716

PLL2 (Output) 0 525I29.97 1716

PLL3 (Output) 13 1080P59.94 400.4

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Table 7. Relevant Auto-Format Detection Codes for Figure 23

PLLx HSync PERIOD

FORMAT CODE DESCRIPTION

(INPUT/OUTPUT) (in 27 MHz CLOCKS)

PLL1 (Input) 0 525I29.97 1716

PLL2 (Output) 0 525I29.97 1716

PLL3 (Output) 21 1080I29.97 800.8

To ensure correct auto-detection and CLKout signaling desired in Figure 22 and Figure 23, the following SMBus

Table 8. SMBus Register Settings for Figure 22

0x05[5] 1'b Auto Format Detect enabled

0x05[4:3] 01'b PLL1 operating in Genlock mode

0x05[1] 1'b Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

0x07[5:0] 000000'b Set PLL2 Output to Format Detection Code 0 (0x00)

0x08[5:0] 001101'b Set PLL3 Output to Format Detection Code 13 (0x0D)

0x11[5:4] 10'b Set to always align when misaligned

0x11[3:2] 01'b Drift lock (small misalignment), crash lock (large misalignment)

0x12[5:4] 10'b Set TOF2 to always align when misaligned

0x13[5:4] 10'b Set TOF3 to always align when misaligned

0x14[5:4] 10'b Set AFS_Align_Mode to always align when misaligned

0x34[7:4] 0010'b Set PLL4_DIV to divide-by-4 for 24.576 MHz

Table 9. SMBus Register Settings for Figure 23

0x05[5] 1'b Auto Format Detect enabled

0x05[4:3] 01'b PLL1 operating in Genlock mode

0x05[1] 1'b Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

0x07[5:0] 000000'b Set PLL2 Output to Format Detection Code 0 (0x00)

0x08[5:0] 010101'b Set PLL3 Output to Format Detection Code 21 (0x15)

0x11[5:4] 10'b Set to always align when misaligned

0x11[3:2] 01'b Drift lock (small misalignment), crash lock (large misalignment)

0x12[5:4] 10'b Set TOF2 to always align when misaligned

0x13[5:4] 10'b Set TOF3 to always align when misaligned

0x14[5:4] 10'b Set AFS_Align_Mode to always align when misaligned

0x34[7:4] 0010'b Set PLL4_DIV to divide-by-4 for 24.576 MHz

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9.2.1.3 Application Curves

10 ns / div 20 µs / div

Traces 1-4: 1V / div Traces 1-3: 2V / div

Figure 24. CLKout 1-4 Signals after Genlock to 525i/29.97 Figure 25. TOF1 Falling Edge Alignment with HSync and

Input Reference VSync Reference Timing

20 µs / div 20 µs / div

Traces 1-3: 2 V / div Traces 1-4: 2 V / div

Figure 26. TOF1 Alignment Comparison to HSync and Figure 27. TOF1 and TOF3 Alignment on Rising Edge

VSync Reference Timing

Product Folder Links: LMH1983

LOOP

FILTER 27 MHz

VCXO

LMH1983

Other clock inputs supported

32, 44.1, 48 or 96 kHz (Audio)

27 MHz (Video)

10 MHz (GPS)

27 MHz

74.25 MHz (PLL2)

74.176 MHz (PLL3)

98.304 MHz

A/V clock signals

genlocked to

clock ref. in

PLL1 Ref. In Format = Audio word, 27 MHz, or 10 MHz clock

PLL2 Video Format = 1080i/25

PLL3 Video Format = 1080i/29.97

PLL4 Audio Format = 98.304 MHz with 48 kHz word clock

CLKout1

CLKout4

CLKout2

CLKout3

Hin

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

9.2.2 A/V Clock Generation with Recognized Clock-based Input Reference

The LMH1983 is shown in the following application example where the HIN input reference timing signal is clock-

based. After achieving genlock, the LMH1983 can produce a specific set of clock output signals required

downstream. In this case, LMH1983 PLLs 1-4 provide a 27 MHz, 74.25 MHz, 74.176 MHz, and 98.304 MHz

output, respectively.

Figure 28. LMH1983 A/V Clock Generation with Non-Format Specific Input Clock Reference

9.2.2.1 Design Requirements

When designing for the LMH1983, it is essential to ensure that the correct VCXO and external loop filter

capacitors are chosen. Refer to VCXO Selection Criteria and Loop Filter Capacitors for guidance regarding how

to select these components to improve timing stability and accuracy.

9.2.2.2 Detailed Design Procedure

Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should

be referenced to the "Supported Formats Lookup Table (LUT)" (see Table 2) to determine whether the video

clock, GPS clock, and audio clock are supported by automatic format detection. From Table 2 and the Auto

Format Detection Codes, all of the reference clock inputs mentioned in this application are supported under the

auto format detection feature. Once PLL1 has genlocked to the chosen HIN signal, PLLs 2-3 can be set

according to the desired output signals specified in Auto Format Detection Codes. Refer to Table 10 for a list of

possible input and output formats available for auto-format detection in this application. The format code can be

applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2 (Register

0x07) and PLL3 (Register 0x08).

Table 10. Relevant Auto-Format Detection Codes for Figure 28

HSync PERIOD

PLLx (INPUT/OUTPUT) FORMAT CODE DESCRIPTION (in 27 MHz CLOCKS)

PLL2 (Output) 22 1080I25 960

PLL3 (Output) 21 1080I29.97 800.8

PLL1 (Input) 25 48 kHz Audio 562.5

PLL1 (Input) 26 96 kHz Audio 281.25

PLL1 (Input) 27 44.1 kHz Audio 612.244898

PLL1 (Input) 28 32 kHz Audio 843.75

PLL1 (Input) 29 27 MHz HSync 1

PLL1 (Input) 30 10 MHz HSync 2.7

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To ensure correct auto-detection and the correct CLKout signaling desired in Figure 28, the following SMBus

Table 11. SMBus Register Settings for Figure 28

0x05[5] 1'b Auto Format Detect enabled

0x05[4:3] 01'b PLL1 operating in Genlock mode

0x05[1] 0'b Allow PLL2 and PLL3 to use the native clock rates

0x07[5:0] 010110'b Set PLL2 Output to Format Detection Code 22 (0x16)

0x08[5:0] 010101'b Set PLL3 Output to Format Detection Code 21 (0x15)

0x11[5:4] 10'b Set to always align when misaligned

0x11[3:2] 01'b Drift lock (small misalignment), crash lock (large misalignment)

0x12[5:4] 10'b Set TOF2 to always align when misaligned

0x13[5:4] 10'b Set TOF3 to always align when misaligned

0x14[5:4] 10'b Set AFS_Align_Mode to always align when misaligned

0x2E[4] 1'b Set PLL2_DIV to divide-by-2 for 74.25 MHz

0x31[4] 1'b Set PLL3_DIV to divide-by-2 for 74.176 MHz

0x34[7:4] 0000'b Set PLL4_DIV to divide-by-1 for 98.304 MHz

9.2.2.3 Application Curve

10ns / div

Traces 1-4: 1V / div

Figure 29. CLKout 1-4 Signals after Genlock to Clock-Based Reference

Product Folder Links: LMH1983

TCXO

27 MHz

±1ppm

LMH1983

27 MHz

148.5 MHz (PLL2)

148.35 MHz (PLL3)

98.304 MHz

A/V clock

signals will

track the TCXO

and have the

same accuracy

PLL1 Mode = Free run

PLL2 Video Format = 1080p/50

PLL3 Video Format = 1080p/59.94

PLL4 Audio Format = 98.304 MHz with 48 kHz word clock

CLKout1

CLKout4

CLKout2

CLKout3

Hin

Vin

Fin

No input

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

9.2.3 A/V Clock Generation Using Free-Run Mode

The LMH1983 can be used in free-run mode, as shown in the following application example. No HIN, VIN, and FIN

input reference timing signals are provided. Instead, the LMH1983 tracks a 27 MHz TCXO reference, which

replaces the external VCXO and loop filter mentioned in previous applications. The LMH1983 can still produce a

specific set of clock output signals required by a downstream endpoint. In this application, LMH1983 PLLs 1-4

provide a 27 MHz, 148.5 MHz, 148.35 MHz, and 98.304 MHz output, respectively.

Figure 30. High-Precision, Stable A/V Clock Generation Using a 27 MHz TCXO Reference

9.2.3.1 Design Requirements

This application requires less components than the previous applications mentioned in this section. This is

because there is no HIN reference, external VCXO, or loop filter. However, the PLL1 signal is still applied via the

27 MHz TCXO clock signal on the XOin± pins. Using a TCXO for reference allows a stable, standalone clock

generation for PLLs 2-4.

9.2.3.2 Detailed Design Procedure

Since no HIN input timing signaling is provided, this application example cannot use the "Supported Formats

Lookup Table (LUT)" (see Table 2) for automatic format detection. However, PLLs 2-4 can still be manually

programmed to output the correct output format using Auto Format Detection Codes. To output the desired video

and audio formats from PLLs 2-3, the following output codes should be used:

Table 12. Auto-Format Detection Output Codes for Figure 30

PLLx HSync PERIOD

FORMAT CODE DESCRIPTION

(INPUT/OUTPUT) (in 27 MHz CLOCKS)

PLL2 (Output) 14 1080P50 480

PLL3 (Output) 13 1080P59.94 400.4

To ensure correct auto-detection and the correct CLKout signaling desired in Figure 30, the following SMBus

Product Folder Links: LMH1983

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

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Table 13. SMBus Register Settings for Figure 30

0x05[5] 1'b Auto Format Detect enabled

0x05[4:3] 00'b PLL1 operating in Free-run mode

0x05[1] 1'b Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz

0x07[5:0] 001110'b Set PLL2 Output to Format Detection Code 14 (0x0E)

0x08[5:0] 001101'b Set PLL3 Output to Format Detection Code 13 (0x0D)

0x11[5:4] 10'b Set to always align when misaligned

0x11[3:2] 01'b Drift lock (small misalignment), crash lock (large misalignment)

0x12[5:4] 10'b Set TOF2 to always align when misaligned

0x13[5:4] 10'b Set TOF3 to always align when misaligned

0x34[7:4] 0000'b Set PLL4_DIV to divide-by-1 for 98.304 MHz

9.2.3.3 Application Curve

10 ns / div

Traces 1-4: 1 V / div

Figure 31. CLKout 1-4 Signals after Tracking 27 MHz TCXO Reference

Product Folder Links: LMH1983

VDD_IO

(Pin 2, 10)

Cbyp2

(Pin 27)

Cbyp3

(Pin 25)

Cbyp4

(Pin 26)

3.3 V

0.1 µF

Internal

LDO

regulator

Place 1 µF and 0.1 µF

bypass capacitors as close to

the Cbyp Pin as possible.

0.1 µF

1 µF

3.3 V

0.1 µF

10 µF

Capacitors can be

either tantalum or an

ultra-low ESR ceramic.

VDD

PLL2

(Pin 32)

Internal

LDO

regulator

3.3 V

0.1 µF

10 µF

Internal

LDO

regulator

0.1 µF

1 µF

0.1 µF

1 µF

VDD

PLL3,

PLL4

(Pin 19)

3.3 V

0.1 µF

10 µF

VDD

PLL1

(Pin 1)

3.3 V

0.1 µF

10 µF

VDD

CLKout2

(Pin 31)

3.3 V

0.1 µF

10 µF

VDD

CLKout1

(Pin 38)

VDD

CLKout4

(Pin 16)

3.3 V

0.1 µF

10 µF

VDD

CLKout3

(Pin 20)

3.3 V

0.1 µF

10 µF

LMH1983

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SNLS309I –APRIL 2010–REVISED DECEMBER 2014

10 Power Supply Recommendations

It is important to ensure that the LMH1983 is provided with an adequate power supply that provides the cleanest

voltage to the VDD_IO and VDD supply pins. One potential source of jitter on a multiple clock system such as

the LMH1983 is interference among the four PLLs on the chip. To help reduce this effect, each PLL is run from a

separate power supply internally on the LMH1983, and each supply has its own internal regulator. These

regulators each require their own external bypass as seen in Figure 32 with bypass capacitors.

Figure 32. LMH1983 Power Supply Connection Diagram

11 Layout

11.1 Layout Guidelines

When designing the PCB layout for the LMH1983, it is important to follow these the guidelines:

• Whenever possible, dedicate an entire layer to each power supply. This will reduce the inductance in the

supply plane.

• Use surface mount components whenever possible.

• Place bypass capacitors and filter components as close as possible to each power pin.

• Place the loop filter components, including the buffer amplifier, and VCXO as close as possible to the

LMH1983.

• Do not allow discontinuities in the ground planes – return currents follow the path of least resistance. For high

frequency signals this will be the path of least inductance.

• Make sure to match the trace lengths of all differential traces.

• Remember that vias have significant inductance — when using a via to connect to a power supply or ground

layer, two in parallel will reduce the inductance over a single via.

• Connect the pad on the bottom of the package to a solid ground connection. This contact is used as a major

ground connection as well as providing a thermal conduit which helps to maintain a constant die temperature.

• See Application Note: AN-1187, Leadless Leadframe Package (LLP) (SNOA401) for more Information on the

LLP (WQFN) style package.

Product Folder Links: LMH1983

V+

V-

LMP7711MK

10.0k

47 µF

17.4k

1 µF

GND

21 GND

39 DAP

VDD_PLL1 1

VDD_IO 2

VDD_IO 10

VDD_CLK4 16

VDD_PLL34 19

VDD_CLK3 20

VDD_CLK2 31

VDD_PLL2 32

VDD_CLK1 38

CLKout1+ 36

CLKout1- 35

Fout1 37

CLKout2+ 28

CLKout2- 29

Fout2 30

Fout3 22

CLKout3+ 23

CLKout3- 24

CLKout4- 14

CLKout4+ 15

Fout4/OSCin 17

Hin

3Vin

Fin

INIT

ADDR

SDA

SCL

NO_LOCK 11

NO_ALIGN 12

NO_REF 13

Cbyp3 25

Cbyp4 26

Cbyp2 27

XOin-

33 XOin+

VC_LPF 40

LMH1983SQ

Vdd3_3

0.1 µF

C12

GND

VC 1

OUT

GND

EN 2

VCC 6

OUTA

357LB3I027M0000

49.9

R10

GND

CLK4_N

CLK4_P

Fout4

CLK3_N

CLK3_P

Fout3

CLK2_N

CLK2_P

Fout2

CLK1_N

CLK1_P

Fout1

0.1 µF

C2 1 µFC1

1 µFC3

1 µFC6

GND

Vdd3_3

0.1 µF

1 µF

GND

VddCLK2

VddCLK3

VddCLK4

VddCLK1

VddPLL3

VddPLL2

VddPLL1

Hsync

Vsync

Fsync

INIT

SDA

SCL

Do Not Load 0

Do Not Load

GND

Vdd3_3

GND

VddVCXO

3.0k

1.8k

GND

Vdd3_3

NOREF

NOALIGN

NOLOCK

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

11.2 Layout Example

Figure 33. LMH1983 Typical Interface Circuit

An example of a typical application circuit for the LMH1983 is shown in the Figure 33. When performing PCB

layout, key areas to consider regarding this circuit are the loop filter – which consists of RS, CS, CPand the

LM7711 Operational Amplifier which buffers the loop filter output prior to driving the control voltage input of the

VCXO. Care must be taken in the component selection for the loop filter components (see VCXO Selection

Criteria and Loop Filter Capacitors). The CLKout outputs are differential LVDS signals and should be treated as

differential signals. These signals may be laid out as fully differential lines, in which the characteristic impedance

between the two lines is nominally 100 Ω. Alternately, loosely coupled lines may be used, in which case the

characteristic impedance of each line should be 50 Ωreferenced to GND. In either case, care should be taken to

match the lengths of the traces as closely as possible. Trace length mismatches on a differential line will add to

the jitter seen on that line. Jitter is also added to the clock outputs if other signals are allowed to interfere with the

signal traces. Therefore, to the greatest extent possible, the clock traces should be isolated from other signals.

Long parallel runs should also be avoided. In places where a hostile signal must cross a sensitive clock signal, it

should be routed such that it crosses as closely as possible to a 90° crossing.

When performing board layouts with the LMH1983, stencil parameters such as aperture area ratio and the

fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of

the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings

are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture

opening and via locations are shown in Figure 34.

Product Folder Links: LMH1983

LMH1983

www.ti.com

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

Layout Example (continued)

Figure 34. No Pullback LLP, Single Row Reference Diagram

Table 14. No Pullback LLP Stencil Aperture Summary for LMH1983

DEVICE PIN MKT. PCB I/O PCB PCB STENCIL STENCIL NUMBER of GAP BETWEEN

COUNT DWG. PAD SIZE PITCH DAP SIZE I/O DAP DAP DAP APERTURE

(mm) (mm) (mm) APERTURE APERTURE APERTURE (DIM A mm)

(mm) (mm) OPENINGS

LMH1983 40 SNA40A 0.25 x 0.6 0.5 4.6 x 4.6 0.25 x 0.7 1.0 x 1.0 16 0.2

Figure 35. 40-Pin WQFN Stencil Example of Via and Opening Placement

The following PCB layout example is derived from the layout design of the LMH1983 in the SD1983EVK

Evaluation Module User's Guide (SNLU001). This graphic and additional layout board description demonstrates

both proper routing and solder techniques when designing in this clock generator.

Product Folder Links: LMH1983

LMH1983

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

Figure 36. LMH1983 Example Layout

Product Folder Links: LMH1983

LMH1983

www.ti.com

SNLS309I –APRIL 2010–REVISED DECEMBER 2014

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

•Absolute Maximum Ratings for Soldering (SNOA549).

•Generating 44.1 kHz Based Clocks with the LMH1983, Application Note AN–2108 (SNLA129).

•Leadless Leadframe Package (LLP), Application Note AN-1187 (SNOA401).

•SD1983EVK/LMH1983 Evaluation Kit User Guide (SNLU001).

•Semiconductor and IC Package Thermal Metrics (SPRA953).

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMH1983

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH1983SQ/NOPB ACTIVE WQFN RTA 40 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LMH1983

LMH1983SQE/NOPB ACTIVE WQFN RTA 40 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LMH1983

LMH1983SQX/NOPB ACTIVE WQFN RTA 40 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LMH1983

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH1983SQ/NOPB WQFN RTA 40 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1

LMH1983SQE/NOPB WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1

LMH1983SQX/NOPB WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Sep-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH1983SQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0

LMH1983SQE/NOPB WQFN RTA 40 250 210.0 185.0 35.0

LMH1983SQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Sep-2016

Pack Materials-Page 2

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