dsPIC30F6011A/6012A/6013A/6014A
DS70143E-page 226 © 2011 Microchip Technology Inc.
Alignment (Figure) ...................................................... 35
Effect of Invalid Memory Accesses (Table)................. 34
MCU and DSP (MAC Class) Instructions Example..... 34
Memory Map ............................................................... 31
Memory Map for dsPIC30F6011A/6013A ................... 32
Memory Map for dsPIC30F6012A/6014A ................... 33
Near Data Space ........................................................ 35
Software Stack............................................................ 35
Spaces ........................................................................ 31
Width........................................................................... 34
Data Converter Interface (DCI) Module ............................ 123
Data EEPROM Memory ...................................................... 57
Erasing........................................................................ 58
Erasing, Block ............................................................. 58
Erasing, Word ............................................................. 58
Protection Against Spurious Write .............................. 60
Reading....................................................................... 57
Write Verify ................................................................. 60
Writing......................................................................... 59
Writing, Block .............................................................. 60
Writing, Word .............................................................. 59
DC Characteristics ............................................................ 174
Brown-out Reset ............................................... 181, 182
I/O Pin Input Specifications....................................... 180
I/O Pin Output Specifications .................................... 180
Idle Current (IIDLE) .................................................... 177
Low-Voltage Detect................................................... 180
LVDL ......................................................................... 181
Operating Current (IDD)............................................. 176
Power-Down Current (IPD) ........................................ 178
Program and EEPROM............................................. 182
DCI Module
Bit Clock Generator................................................... 127
Buffer Alignment with Data Frames .......................... 129
Buffer Control............................................................ 123
Buffer Data Alignment............................................... 123
Buffer Length Control................................................ 129
COFS Pin.................................................................. 123
CSCK Pin.................................................................. 123
CSDI Pin ................................................................... 123
CSDO Mode Bit ........................................................ 130
CSDO Pin ................................................................. 123
Data Justification Control Bit..................................... 128
Device Frequencies for Common Codec CSCK Frequen-
cies (Table) ....................................................... 127
Digital Loopback Mode ............................................. 130
Enable....................................................................... 125
Frame Sync Generator ............................................. 125
Frame Sync Mode Control Bits ................................. 125
I/O Pins ..................................................................... 123
Interrupts................................................................... 130
Introduction ............................................................... 123
Master Frame Sync Operation.................................. 125
Operation .................................................................. 125
Operation During CPU Idle Mode ............................. 130
Operation During CPU Sleep Mode .......................... 130
Receive Slot Enable Bits........................................... 128
Receive Status Bits................................................... 129
Register Map............................................................. 132
Sample Clock Edge Control Bit................................. 128
Slave Frame Sync Operation.................................... 126
Slot Enable Bits Operation with Frame Sync ............ 128
Slot Status Bits.......................................................... 130
Synchronous Data Transfers .................................... 128
Timing Characteristics
AC-Link Mode................................................... 197
Multichannel, I2S Modes................................... 195
Timing Requirements
AC-Link Mode................................................... 197
Multichannel, I2S Modes................................... 196
Transmit Slot Enable Bits ......................................... 128
Transmit Status Bits.................................................. 129
Transmit/Receive Shift Register ............................... 123
Underflow Mode Control Bit...................................... 130
Word Size Selection Bits .......................................... 125
Development Support ....................................................... 169
Device Configuration
Register Map ............................................................ 160
Device Configuration Registers ........................................ 158
FBORPOR................................................................ 158
FBS........................................................................... 158
FGS .......................................................................... 158
FOSC........................................................................ 158
FSS........................................................................... 158
FWDT ....................................................................... 158
Device Overview................................................................. 91
Disabling the UART .......................................................... 105
Divide Support .................................................................... 20
Instructions (Table)..................................................... 20
DSP Engine ........................................................................ 20
Multiplier ..................................................................... 22
Dual Output Compare Match Mode .................................... 86
Continuous Pulse Mode.............................................. 86
Single Pulse Mode...................................................... 86
E
Electrical Characteristics .................................................. 173
AC............................................................................. 183
DC ............................................................................ 174
Enabling and Setting Up UART
Setting Up Data, Parity and Stop Bit Selections....... 105
Enabling the UART ........................................................... 105
Equations
ADC Conversion Clock ............................................. 135
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 127
COFSG Period.......................................................... 125
Serial Clock Rate...................................................... 100
Time Quantum for Clock Generation ........................ 117
Errata .................................................................................... 9
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 191
External Clock Timing Requirements ............................... 184
Type A Timer ............................................................ 191
Type B Timer ............................................................ 192
Type C Timer ............................................................ 192
External Interrupt Requests ................................................ 49
F
Fast Context Saving ........................................................... 49
Flash Program Memory ...................................................... 51
Control Registers........................................................ 52
NVMADR ............................................................ 52
NVMADRU ......................................................... 52
NVMCON............................................................ 52
NVMKEY ............................................................ 52
I
I/O Pin Specifications
Input.......................................................................... 180
Output....................................................................... 180