DS92LV090A
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SNLS025D –APRIL 2000–REVISED APRIL 2013
DS92LV090A 9 Channel Bus LVDS Transceiver
Check for Samples: DS92LV090A
1FEATURES DESCRIPTION
The DS92LV090A is one in a series of Bus LVDS
2• Bus LVDS Signaling transceivers designed specifically for the high speed,
• 3.2 Nanosecond Propagation Delay Max low power proprietary backplane or cable interfaces.
• Chip to Chip Skew ±800ps The device operates from a single 3.3V power supply
and includes nine differential line drivers and nine
• Low Power CMOS Design receivers. To minimize bus loading, the driver outputs
• High Signaling Rate Capability (Above 100 and receiver inputs are internally connected. The
Mbps) separate I/O of the logic side allows for loop back
• 0.1V to 2.3V Common Mode Range for VID =support. The device also features a flow through pin
200mV out which allows easy PCB routing for short stubs
between its pins and the connector.
• ±100 mV Receiver Sensitivity The driver translates 3V TTL levels (single-ended) to
• Supports Open and Terminated Failsafe on differential Bus LVDS (BLVDS) output levels. This
Port Pins allows for high speed operation, while consuming
• 3.3V Operation minimal power with reduced EMI. In addition, the
• Glitch Free Power Up/Down (Driver & Receiver differential signaling provides common mode noise
Disabled) rejection of ±1V.
• Light Bus Loading (5 pF Typical) per Bus The receiver threshold is less than ±100 mV over a
LVDS Load ±1V common mode range and translates the
differential Bus LVDS to standard (TTL/CMOS)
• Designed for Double Termination Applications levels. (See Applications Information Section for more
• Balanced Output Impedance details.)
• Product Offered in 64 Pin LQFP Package
• High Impedance Bus Pins on Power off (VCC =
0V)
• Driver Channel to Channel Skew (Same
Device) 230ps Typical
• Receiver Channel to Channel Skew (Same
Device) 370ps Typical
Simplified Functional Diagram
Figure 1.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS92LV090A
SNLS025D –APRIL 2000–REVISED APRIL 2013
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Connection Diagram
Figure 2. Top View
Package Number PM0064
PIN DESCRIPTIONS
Pin Name Pin # Input/Output Descriptions
DO+/RI+ 27, 31, 35, 37, 41, 45, I/O True Bus LVDS Driver Outputs and Receiver Inputs.
47, 51, 55
DO−/RI−26, 30, 34, 36, 40, 44, I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
46, 50, 54
DIN 2, 6, 12, 18, 20, 22, 58, I TTL Driver Input.
60, 62
RO 3, 7, 13, 19, 21, 23, 59, O TTL Receiver Output.
61, 63
RE 17 I Receiver Enable TTL Input (Active Low).
DE 16 I Driver Enable TTL Input (Active High).
GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board). These pins
connected internally.
VCC 10, 15, 24, 57, 64 Power VCC for digital circuitry (must connect to VCC on PC board). These pins
connected internally.
AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board). These pins
connected internally.
AVCC 29, 32, 42, 48, 52 Power Analog VCC (must connect to VCC on PC board). These pins connected
internally.
NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)(2)(3)
Supply Voltage (VCC) 4.0V
Enable Input Voltage (DE, RE) −0.3V to (VCC +0.3V)
Driver Input Voltage (DIN)−0.3V to (VCC +0.3V)
Receiver Output Voltage (ROUT)−0.3V to (VCC +0.3V)
Bus Pin Voltage (DO/RI±) −0.3V to +3.9V
ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV
Driver Short Circuit Duration momentary
Receiver Short Circuit Duration momentary
Maximum Package Power Dissipation at 25°C LQFP 1.74 W
Derate LQFP Package 13.9 mW/°C
θja 71.7°C/W
θjc 10.9°C/W
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 4 sec.) 260°C
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD,ΔVOD and VID.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device
operation.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions Min Max Units
Supply Voltage (VCC) 3.0 3.6 V
Receiver Input Voltage 0.0 2.4 V
Operating Free Air Temperature −40 +85 °C
Maximum Input Edge Rate (20% to 80%) (1) Δt/ΔV
Data 1.0 ns/V
Control 3.0 ns/V
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO= 50Ω, tr, tf= <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
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DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)(2)
Symbol Parameter Conditions Pin Unit
Min Typ Max s
VOD Output Differential Voltage RL= 27Ω,Figure 3 DO+/RI+, 240 300 460 mV
DO−/RI−
ΔVOD VOD Magnitude Change 27 mV
VOS Offset Voltage 1.1 1.3 1.5 V
ΔVOS Offset Magnitude Change 5 10 mV
VOH Driver Output High Voltage(3) RL= 27Ω1.4 1.65 V
VOL Driver Output Low Voltage(3) RL= 27Ω0.95 1.1 V
IOSD Output Short Circuit Current (4) VOD = 0V, DE = VCC, Driver outputs |36| |65| mA
shorted together
VOH Voltage Output High (5) VID = +300 mV IOH =−400 µA ROUT VCC−0.2 V
Inputs Open VCC−0.2 V
Inputs Terminated, VCC−0.2 V
RL= 27Ω
VOL Voltage Output Low IOL = 2.0 mA, VID =−300 mV 0.05 0.075 V
IOD Receiver Output Dynamic VID = 300mV, VOUT = VCC−1.0V −110 |75| mA
Current (4) VID =−300mV, VOUT = 1.0V |75| 110 mA
VTH Input Threshold High DE = 0V, VCM = 1.5V DO+/RI+, +100 mV
DO−/RI−
VTL Input Threshold Low −100 mV
VCMR Receiver Common Mode Range |VID|/2 2.4 −V
|VID|/2
IIN Input Current DE = 0V, RE = 2.4V, −20 ±1 +20 µA
VIN = +2.4V or 0V
VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA
VIH Minimum Input High Voltage DIN, DE, RE 2.0 VCC V
VIL Maximum Input Low Voltage GND 0.8 V
IIH Input High Current VIN = VCC or 2.4V −20 ±10 +20 µA
IIL Input Low Current VIN = GND or 0.4V −20 ±10 +20 µA
VCL Input Diode Clamp Voltage ICLAMP =−18 mA −1.5 −0.8 V
ICCD Power Supply Current Drivers No Load, DE = RE = VCC, VCC 55 80 mA
Enabled, Receivers Disabled DIN = VCC or GND
ICCR Power Supply Current Drivers DE = RE = 0V, VID = ±300mV 73 80 mA
Disabled, Receivers Enabled
ICCZ Power Supply Current, Drivers DE = 0V; RE = VCC,35 80 mA
and Receivers TRI-STATE DIN = VCC or GND
ICC Power Supply Current, Drivers DE = VCC; RE = 0V,
and Receivers Enabled DIN = VCC or GND, 170 210 mA
RL= 27Ω
IOFF Power Off Leakage Current VCC = 0V or OPEN, DO+/RI+,
DIN, DE, RE = 0V or OPEN, DO−/RI− −20 +20 µA
VAPPLIED = 3.6V (Port Pins)
COUTPUT Capacitance @ Bus Pins DO+/RI+, 5 pF
DO−/RI−
cOUTPUT Capacitance @ ROUT ROUT 7 pF
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD,ΔVOD and VID.
(2) All typicals are given for VCC = +3.3V and TA= +25°C, unless otherwise stated.
(3) The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.
(4) Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
(5) VOH failsafe terminated test performed with 27Ωconnected between RI+ and RI−inputs. No external voltage is applied.
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AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to Low (2) RL= 27Ω, 0.6 1.4 2.2 ns
Figure 4,Figure 5,
tPLHD Differential Prop. Delay Low to High (2) 0.6 1.4 2.2 ns
CL= 10 pF
tSKD1 Differential Skew |tPHLD–tPLHD|(3) 80 ps
tSKD2 Chip to Chip Skew (4) 1.6 ns
tSKD3 Channel to Channel Skew (5) 0.25 0.45 ns
tTLH Transition Time Low to High 0.6 1.2 ns
tTHL Transition Time High to Low 0.5 1.2 ns
tPHZ Disable Time High to Z RL= 27Ω, 3 8 ns
Figure 6,Figure 7,
tPLZ Disable Time Low to Z 3 8 ns
CL= 10 pF
tPZH Enable Time Z to High 3 8 ns
tPZL Enable Time Z to Low 3 8 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to Low (2) Figure 8,Figure 9, 1.6 2.4 3.2 ns
CL= 35 pF
tPLHD Differential Prop Delay Low to High (2) 1.6 2.4 3.2 ns
tSDK1 Differential Skew |tPHLD–tPLHD|(3) 80 ps
tSDK2 Chip to Chip Skew (4) 1.6 ns
tSDK3 Channel to Channel Skew (5) 0.35 0.60 ns
tTLH Transition Time Low to High 1.5 2.5 ns
tTHL Transition Time High to Low 1.5 2.5 ns
tPHZ Disable Time High to Z RL= 500Ω, 4.5 10 ns
Figure 10,Figure 11,
tPLZ Disable Time Low to Z 3.5 8 ns
CL= 35 pF
tPZH Enable Time Z to High 3.5 8 ns
tPZL Enable Time Z to Low 3.5 8 ns
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO= 50Ω, tr, tf= <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) Propagation delays are specified by design and characterization.
(3) tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.
(4) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
(5) Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device,
either edge.
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APPLICATIONS INFORMATION
General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028),
AN-903 (SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008).
There are a few common practices which should be implied when designing PCB for Bus LVDS signaling.
Recommended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface
mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer
ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and
ground. The capacitors should be as close as possible to the VCC pin.
– Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors.
– In addition, randomly distributed by-pass capacitors should be used.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• Use controlled impedance media. The backplane and connectors should have a matched differential
impedance.
Table 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
Table 2. Transmitter Mode
INPUTS OUTPUTS
DE DIN DO+ DO−
H L L H
H H H L
H 0.8V< DIN <2.0V X X
L X Z Z
Table 3. Receiver Mode(1)
INPUTS OUTPUT
RE (RI+) – (RI−)
L L (< −100 mV) L
L H (> +100 mV) H
L−100 mV < VID < +100 mV X
H X Z
(1) X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
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Test Circuits and Timing Waveforms
Figure 3. Differential Driver DC Test Circuit
Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms
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Figure 6. Driver TRI-STATE Delay Test Circuit
Figure 7. Driver TRI-STATE Delay Waveforms
Figure 8. Receiver Propagation Delay and Transition Time Test Circuit
Figure 9. Receiver Propagation Delay and Transition Time Waveforms
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Figure 10. Receiver TRI-STATE Delay Test Circuit
Figure 11. Receiver TRI-STATE Delay Waveforms
Typical Bus Application Configurations
Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications
Figure 13. Multi-Point Bus Applications
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS92LV090ATVEH/NOPB ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV090A
TVEH
DS92LV090ATVEHX/NOPB ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV090A
TVEH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS92LV090ATVEHX/NOP
BLQFP PM 64 1000 330.0 24.4 12.35 12.35 2.2 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS92LV090ATVEHX/NOP
BLQFP PM 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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