General Description
The MAX6880–MAX6883 dual-/triple-voltage monitors
are designed to sequence power supplies during
power-up condition. When all of the voltages exceed
their respective thresholds, these devices turn on volt-
ages to the system sequentially, enhancing n-channel
MOSFETs used as switches. The time between each
sequenced voltage is determined by an external
capacitor, thus allowing flexibility in delay timing. The
MAX6880/MAX6881 sequence three voltages and the
MAX6882/MAX6883 sequence two voltages.
These devices initially monitor all of the voltages and
when all of them are within their tolerances, the inter-
nal charge pumps enhance external n-channel
MOSFETs in a sequential manner to apply the volt-
ages to the system. Internal charge pumps drive the
gate voltages 5V above the respective input voltage
thereby ensuring the MOSFETs are fully enhanced to
reduce the on-resistance.
The MAX6880–MAX6883 feature capacitor-adjustable
slew-rate control to provide controlled turn-on charac-
teristics. After all of the voltages reach 92.5% of their
final value, a power-good output (MAX6880/MAX6882)
signal is active. The power-good output (PG/RST) can
be delayed with an external capacitor to create a
power-on reset delay. After the initial power-up phase,
the MAX6880–MAX6883 continue to monitor the volt-
ages. If any of the voltages falls below its threshold, the
MOSFETs are quickly turned off and the voltages are
tracked down together. An internal 100Ωpulldown
resistor ensures that the capacitance at the MOSFET’s
source is discharged quickly. The power-good output
goes low to provide a system reset.
The MAX6880–MAX6883 are available in small 4mm x
4mm 24-pin and 16-pin thin QFN packages and speci-
fied over the -40°C to +85°C extended operating tem-
perature range.
Applications
Multivoltage Systems
Networking Systems
Telecom
Storage Equipment
Servers/Workstations
Features
♦Capacitor-Adjustable Power-Up Sequencing
Delay
♦Internal Charge Pumps to Enhance External
n-Channel FETs
♦Capacitor-Adjustable Timeout Period Power-Good
Output (MAX6880/MAX6882)
♦Adjustable Undervoltage Lockout or
Logic-Enable Input
♦Internal 100ΩPulldown for Each Output to
Discharge Capacitive Load Quickly
♦0.5V to 5.5V Nominal IN_/OUT_ Range
♦2.7V to 5.5V Operating Voltage Range
♦Immune to Short Voltage Transients
♦Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN
Packages
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
________________________________________________________________ Maxim Integrated Products 1
23
24
22
21
8
7
9
ABP
SET2
SET1
EN/UV
10
N.C.
GATE3
N.C.
PG/RST
OUT2
MARGIN
12
IN3
456
1718 16 14 13
IN2
IN1
TIMEOUT
*EXPOSED PADDLE CONNECTED TO GND.
SLEW
DELAY
GND
EP*
+
MAX6880
SET3 OUT3
3
15
GATE1
20 11 N.C.
OUT1
19 12 N.C.
GATE2
4mm x 4mm THIN QFN
TOP VIEW
Pin Configurations
Ordering Information
19-3772; Rev 1; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+Denotes lead-free package.
Selector Guide appears at end of data sheet.
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX6880ETG+
-40°C to +85°C 24 Thin QFN
T2444-4
MAX6881ETE+
-40°C to +85°C 16 Thin QFN
T1644-4
MAX6882ETE+
-40°C to +85°C 16 Thin QFN
T1644-4
MAX6883ETE+
-40°C to +85°C 16 Thin QFN
T1644-4
Pin Configurations continued at end of data sheet.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA= -40°C to +85°C, unless otherwise specified. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN1, IN2, IN3.............................................................-0.3V to +6V
ABP .........................................-0.3V to the highest of VIN1 - VIN3
SET1, SET2, SET3 ....................................................-0.3V to +6V
GATE1, GATE2, GATE3 .........................................-0.3V to +12V
OUT1, OUT2, OUT3 .................................................-0.3V to +6V
MARGIN ...................................................................-0.3V to +6V
PG/RST, EN/UV ........................................................-0.3V to +6V
DELAY, SLEW, TIMEOUT .........................................-0.3V to +6V
OUT_ Current....................................................................±50mA
GND Current.....................................................................±50mA
Input/Output Current (all pins except
OUT_ and GND) ...........................................................±20mA
Continuous Power Dissipation (TA= +70°C)
16-Pin 4mm x 4mm Thin QFN
(derate 16.9mW/°C above +70°C).............................1349mW
24-Pin 4mm x 4mm Thin QFN
(derate 20.8mW/°C above +70°C).............................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Voltage on the highest of IN_ to ensure that
PG/RST is valid and GATE_ = 0 1.4
Operating Voltage Range IN_
Voltage on the highest of IN_ to ensure the
device is fully operational 2.7 5.5
V
Supply Current ICC IN1 = 5.5V, IN2 = IN3 = 3.3V, no load 1.1 1.8 mA
SET_ falling, TA = +25oC
0.4925
0.5
0.5075
SET_ Threshold Range VTH SET_ falling, TA = -40 °C to +85°C
0.4875
0.5
0.5125
V
SET_ Threshold Hysteresis
VTH_HYST
SET_ rising 0.5 %
SET_ Input Current ISET SET_ = 0.5V
-100 +100
nA
VEN_R Input rising
1.286
EN/UV Input Voltage VEN_F Input falling
1.22 1.25 1.28
V
EN/UV Input Current IEN -5 +5 µA
EN/UV Input Pulse Width tEN EN/UV falling, 100mV overdrive 7 µs
DELAY, TIMEOUT Output Current
ID(Notes 2, 3)
2.12
2.5
2.88
µA
DELAY, TIMEOUT Threshold
Voltage VCC = 3.3V
1.25
V
SLEW Output Current IS( N ote 4)
22.5
25
27.5
µA
Sequence Slew-Rate Timebase
Accuracy SR CSLEW = 200pF -15
+15
%
Timebase/CSLEW Ratio 100pF < CSLEW < 1nF 104 kΩ
S l ew - Rate Accur acy d ur i ng P ow er -
U p and P ow er - D ow nCSLEW = 200pF, VIN_ = 5.5V ( N ote 4) -50
+50
%
(All voltages referenced to GND, unless otherwise noted.)
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 3
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at TA= +25°C and TA= +85°C.
Specifications at TA= -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
least one of IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
Note 2: A current ID= 2.5µA ±15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a refer-
ence for tDELAY and tTIMEOUT.
Note 3: The total DELAY is tDELAY = 200µs + (500kΩx CDELAY). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is
tTIMEOUT = 200µs + (500kΩx CTIMEOUT). Leave TIMEOUT unconnected for 200µs timeout.
Note 4: A current IS= 25µA ±10% is generated internally and used as a reference for tFAULT, tRETRY, and slew rate.
Note 5: During power-up, only the condition OUT_ < ramp - VTRK is checked in order to stop the ramp. However, both conditions
OUT_ < ramp – VTRK_F and OUT_ > ramp + VTRK_F cause a fault. During power-down, only the condition OUT > ramp +
VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x VTRK_F, a fault condition is asserted.
Note 6: A 100Ωpulldown to GND activated by a fault condition. See the Internal Pulldown section.
ELECTRICAL CHARACTERISTICS (continued)
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA= -40°C to +85°C, unless otherwise specified. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 1)
Power-Good Threshold VTH_PG VOUT_ falling
91.5
92.5
93.5
%
Power-Good Threshold Hysteresis VHYS_PG
VOUT_ rising 0.5 %
GATE_ Output High VGOH ISOURCE = 0.5µA IN_ +
4.2
IN_ +
5.0
IN_ +
5.8 V
GATE_ Pullup Current IGUP During power-up and power-down,
VGATE_ = 1V 2.5 4 µA
IGD During power-up and power-down,
VGATE_ = 5V 2.5 4 µA
When disabled, VGATE_ = 5V, VIN_ ≥ 2.7V 9.5
GATE_ Pulldown Current
IGDS When disabled, VGATE_ = 5V, VIN_ ≥ 4V 20 mA
SET_ to GATE_ Delay tD-GATE SET falling, 25mV overdrive 10 µs
VIN_ ≥ 2.7V, ISINK = 1mA, output asserted 0.3
PG/RST Output Low VOL VIN_ ≥ 4.0V, ISINK = 4mA, output asserted 0.4 V
Tracking Differential Voltage Stop
Ramp VTRK
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 1 (Note 5)
75
125
180 mV
Tracking Differential Fault Voltage
VTRK_F Differential between each of the OUT_ and
the ramp voltage, Figure 1 (Note 5)
200 250
310 mV
Power-Low Threshold VTH_PL OUT_ falling
125 142
170 mV
Power-Low Hysteresis
VTH_PLHYS
OUT_ rising 10 mV
OUT to GND Pulldown Impedance
IN_ > 2.7V (Note 6)
100
Ω
MARGIN Pullup Current IIN 71013µA
VIL 0.8
MARGIN Input Voltage VIH 2.0 V
MARGIN Glitch Rejection
100
ns
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
4 _______________________________________________________________________________________
250mV DOWN =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
125mV DOWN =
STOP RAMP THRESHOLD
125mV UP =
STOP RAMP THRESHOLD
250mV UP =
FAULT THRESHOLD
250mV UP =
FAULT THRESHOLD
REFERENCE RAMP REFERENCE RAMP
POWER-UP POWER-DOWN
Figure 1. Stop Ramp/Fault Window During Power-Up and Power-Down
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
IN_
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
OUT_
OUT1 = 3.3V
OUT2 = 1.8V
OUT3 = 0.7V
CAPACITOR-
ADJUSTED
SLEW RATE
PG/RST
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
tDELAY
tDELAY
tDELAY
tTIMEOUT
VEN_R
EN/UV
VEN_F
Figure 2. Sequencing In Normal Mode
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 5
IN_
VEN_R
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
OUT_
OUT2 = 1.8V
OUT3 = 0.7V
OUT1 = 3.3V
EN/UV EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1
OUT_ FORCED
BELOW VTH_PG
CAPACITOR-
ADJUSTED
SLEW RATE
PG/RST
tDELAY tDELAY
tDELAY
tTIMEOUT
Figure 3. Sequencing In Fast Shutdown Mode
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
6 _______________________________________________________________________________________
BUS VOLTAGE MONITORED
THROUGH EN/UV INPUT
IN_
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
OUT_
OUT1 = 3.3V
OUT2 = 1.8V
OUT3 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
EN/UV EN/UV
PG/RST = LOW
CAPACITOR-
ADJUSTED
SLEW RATE
tDELAY tDELAY tDELAY
tTIMEOUT
VEN_R VEN_F
Figure 4. Timing Diagram (Aborted Sequencing)
OUT1
OUT2
OUT3 IS SLOW
OUT_
OUT1
OUT2
OUT3 IS SLOW
tDELAY
tDELAY
tDELAY
tDELAY tDELAY
tFAULT
tFAULT AND tRETRY NOT TO SCALE
ALL SET > 0.5V AND IN_ ≥ 2.7V
tFAULT
tRETRY tDELAY
EN/UV
VEN_R
Figure 5. tFAULT and tRETRY Timing Diagram in Sequencing
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 7
VCC SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX6880 toc01
INPUT VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
5.04.54.03.53.0
0.9
1.0
1.1
1.2
1.3
1.4
0.8
2.5 5.5
TA = +85°C
TA = -40°C
TA = +25°C
NORMALIZED POWER-GOOD TIMEOUT
vs. TEMPERATURE
MAX6880 toc02
TEMPERATURE (°C)
NORMALIZED POWER-GOOD TIMEOUT
6035-15 10
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
0.75
-40 85
POWER-GOOD TIMEOUT
vs. CTIMEOUT
MAX6880 toc03
CDELAY (µF)
POWER-GOOD TIMEOUT (ms)
0.10.010.001
1
10
100
1000
0.1
0.0001 1
NORMALIZED SET_ THRESHOLD
vs. TEMPERATURE
MAX6880 toc04
TEMPERATURE (°C)
NORMALIZED SET_ THRESHOLD
603510-15
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
0.995
-40 85
NORMALIZED DELAY TIMEOUT
vs. TEMPERATURE
MAX6880 toc05
TEMPERATURE (°C)
NORMALIZED DELAY TIMEOUT
603510-15
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
0.75
-40 85
SLEW RATE
vs. CSLEW
MAX6880 toc06
CSLEW (pF)
SLEW RATE (V/s)
100 1000
100
1000
10,000
10
10 10,000
DELAY TIMEOUT
vs. CDELAY
MAX6880 toc07
CDELAY (µF)
DELAY TIMEOUT (ms)
0.10.010.001
1
10
100
1000
0.1
0.0001 1
NORMALIZED EN/UV THRESHOLD
vs. TEMPERATURE
MAX6880 toc08
TEMPERATURE (°C)
NORMALIZED EN_/UV THRESHOLD
603510-15
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
0.995
-40 85
IN_ TRANSIENT DURATION
vs. IN THRESHOLD OVERDRIVE
MAX6880 toc09
IN_ THRESHOLD OVERDRIVE (mV)
IN_ TRANSIENT DURATION (µs)
25020015010050
3
6
9
12
15
18
21
24
27
30
0
0 300
PG/RST GOES LOW ABOVE THE CURVE
IN_ = 3.3V
Typical Operating Characteristics
(VIN_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA= +25°C, unless otherwise noted.)
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA= +25°C, unless otherwise noted.)
GATE_ VOLTAGE LOW
vs. SINK CURRENT
MAX6880 toc10
GATE SINK CURRENT (mA)
GATE_ VOLTAGE LOW (V)
981 2 3 5 64 7
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
010
GATE_ OUTPUT VOLTAGE HIGH
vs. GATE SOURCE CURRENT
MAX6880 toc11
GATE SOURCE CURRENT (µA)
GATE VOLTAGE (V)
2.52.01.51.00.5
1
2
3
4
5
6
7
8
9
10
0
0 3.0
SEQUENCING MODE
MAX6880 toc12
20ms/div
OUT1
1V/div
OUT2
1V/div
EN/UV
2V/div
OUT3
1V/div
FAST SHUTDOWN WITH RETRY
MAX6880 toc13
40ms/div
OUT1
1V/div
OUT2
1V/div
EN/UV
2V/div
OUT3
1V/div
FAST SHUTDOWN WITH RETRY
MAX6880 toc14
100ms/div
PG/RST
1V/div
OUT2
2V/div
OUT1
2V/div
OUT3
2V/div
OUT3 PULLED BELOW
92.5% OF IN3 FOR
SEQUENCING MODE
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 9
Pin Description
PIN
MAX6880 MAX6881 MAX6882 MAX6883 NAME
FUNCTION
1, 11,
12, 15 ——
1, 8, 9, 10
N.C. No Connection. Not internally connected.
2 — 1 — ABP
Internal Supply Bypass Input. Bypass ABP with a 1µF capacitor to
GND. ABP maintains the device supply voltage during rapid power-
down conditions.
3 2 — — SET3
4 3 2 2 SET2
5 4 3 3 SET1
Externally Adjusted IN_ Undervoltage Lockout Threshold. Connect
SET_ to an external resistor-divider network to set the desired
undervoltage threshold for each IN_ supply (see the Typical
Application Circuit). All SET_ inputs must be above the internal
SET_ threshold (0.5V) to enable sequencing functionality.
6544
EN/UV
Logic-Enable Input or Undervoltage Lockout Monitor Input. EN/UV
must be high (EN/UV > VEN_R) to enable voltage sequencing
power-up operation. OUT_ begins tracking down when EN/UV <
VEN_F. Connect EN/UV to an external resistor-divider network to set
the external UVLO threshold.
7 6 5 5 GND Ground
8766
DELAY
Sequence Delay Select Input. Connect a capacitor from DELAY
to GND to select the desired delay period before sequencing is
enabled (after all SET_ inputs and EN/UV are above their respective
thresholds) or between supply sequences. Leave DELAY
unconnected for the default 200µs delay period.
9 8 7 7 SLEW Slew-Rate Adjustment Input. Connect a capacitor from SLEW
to GND to select the desired OUT_ slew rate.
10 — 8 —
TIMEOUT
PG/RST Timeout Period Adjust Input. PG/RST asserts high after the
timeout period when all OUT_ exceed their IN_ referenced
threshold. Connect a capacitor from TIMEOUT to GND to set the
desired timeout period. Leave TIMEOUT unconnected for the
default 200µs delay period.
13 — 9 —
MARGIN
Margin Input, Active-Low. Drive MARGIN low to enable margin
mode (see the Margin Input (
MARGIN
) (MAX6880/MAX6882)
section). The MARGIN functionality is disabled (returns to normal
monitoring mode) after MARGIN returns high. MARGIN is internally
pulled up to ABP through a 10µA current source.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX6880
MAX6881 MAX6882 MAX6883 NAME
FUNCTION
14 — 10 —
PG/RST
Power-Good Output, Open-Drain. PG_RST asserts high tTIMEOUT
after all OUT_ voltages exceed the VTH_PG thresholds.
16 9 — — OUT3
Channel 3 Monitored Output Voltage. Connect OUT3 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
17 10 — —
GATE3
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE3 to VIN3 + 5V to fully enhance the external n-channel
FET when power-up is complete.
18 11 11 11 OUT2
Channel 2 Monitored Output Voltage. Connect OUT2 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
19 12 12 12
GATE2
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE2 to VIN2 + 5V to fully enhance the external n-channel
FET when power-up is complete.
20 13 13 13 OUT1
Channel 1 Monitored Output Voltage. Connect OUT1 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
21 14 14 14
GATE1
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE1 to VIN1 + 5V to fully enhance the external n-channel
FET when power-up is complete.
22 15 — — IN3
23 16 15 15 IN2
24 1 16 16 IN1
Supply Input Voltage. IN1, IN2, or IN3 must be greater than the
internal undervoltage lockout (VABP = 2.7V) to enable the
sequencing functionality. Each IN_ input is simultaneously
monitored by SET_ inputs to ensure all supplies have stabilized
before power-up is enabled. If IN_ is connected to ground or left
unconnected and SET_ is above 0.5V, then no sequencing control
is performed on that channel. Each IN_ is internally pulled down by
a 100kΩ resistor.
EP EP EP EP EP Exposed Paddle. Connect exposed paddle to ground.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 11
CONTROL
LOGIC
INTERNAL
VCC/UVLO
SEQUENCING
MONITOR
PG CIRCUIT
CHARGE
PUMP
GATE
CONTROLLER
OUT1
OUT2
OUT3
IN1
IN2
IN3
VREF
IN1
IN1
IN2 IN3
ABP GATE1 OUT1
GATE2
OUT2
GATE3
OUT3
PG/RST
DELAY SLEW
MARGIN
VBUS
EN/UV
SET3
SET2
IN2
SET1
GND
CSLEW
TIMEOUT
CTIMEOUT
TO LOAD
IN1
MAX6880
IN3
COMP
COMP
COMP
COMP
IN3 TO OUT3
CONTROL BLOCK
IN2 TO OUT2
CONTROL BLOCK
RAMP
GENERATOR
Functional Diagram
MAX6880–MAX6883
Detailed Description
The MAX6880–MAX6883 multivoltage power
sequencers/supervisors monitor three (MAX6880/
MAX6881) and two (MAX6882/MAX6883) system volt-
ages and provide proper power-up and power-down
control for systems requiring voltage sequencing. These
devices ensure the controlled voltages sequence in the
proper order as system power supplies are enabled.
The MAX6880–MAX6883 generate all required voltages
and timing to control up to three external n-channel
pass FETs for the OUT1/OUT2/OUT3 supply voltages.
The MAX6880–MAX6883 feature adjustable undervolt-
age thresholds for each input supply. When all of the
voltages are above the adjusted thresholds these
devices turn on the external n-channel MOSFETs to
sequence the voltages to the system. The outputs are
turned on one after the other, OUT1 first and OUT3 last.
The MAX6880–MAX6883 feature internal charge pumps
to fully enhance the external FETs for low-voltage drops
at highpass currents. The MAX6880/MAX6882 also fea-
ture a power-good output (PG/RST) with a selectable
timeout period that can be used for system reset.
The MAX6880–MAX6883 monitor up to three voltages.
Devices may be configured to exclude any IN_. To dis-
able sequencing operation of any IN_, connect the IN_
to ground (or leave unconnected) and connect SET_ to
a voltage greater than 0.5V. The channel exclusion fea-
ture adds more flexibility to the device in a variety of
different applications. As an example, the MAX6880
can sequence two voltages using IN1 and IN2 while
IN3 is left disabled.
Powering the MAX6880–MAX6883
These devices derive power from either IN1, IN2, or IN3
voltage inputs (see the Functional Diagram). In order to
ensure proper operation, at least one of the IN_ inputs
must be at least +2.7V.
The highest input voltage on IN1/IN2/IN3 supplies
power to the devices. Internal hysteresis ensures that
the supply input that initially powers these devices con-
tinues to power the MAX6880–MAX6883 when multiple
input voltages are within 100mV (typ) of each other.
Sequencing
The sequencing operation can be initiated after all
input conditions for power-up are met VEN/UV > 1.25V
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period is waited (pro-
grammable by connecting a capacitor from DELAY to
ground. The power-up phase for each channel ends
when its output voltage exceeds a fixed percentage
(VTH_PG) of the corresponding IN_ voltage. When all
channels have exceeded these thresholds, PG/RST
asserts high after tTIMEOUT, indicating a successful
sequence.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
The power-supply sequencing operation should be
completed within the selected fault timeout period
(tFAULT) (see Figure 5). The total sequencing time is
extended when the devices must vary the control slew
rate to allow slow supplies to catch up. If the external
FET is too small (RDS is too high for the selected load
current and IN_ source current), the OUT_ voltage may
never reach the control ramp voltage. For a slew rate of
935V/s, a fault is signaled if all outputs have not stabi-
lized within 22ms. For a slew rate of 93.5V/s, a fault is
signaled if sequencing takes too long (more than
219ms).
The fault time period (tFAULT) is set through the capaci-
tor at SLEW (CSLEW). Use the following formula to esti-
mate the fault timeout period:
tFAULT = 2.191 x 108x CSLEW
Autoretry Function
The MAX6880/MAX6881/MAX6882 feature autoretry
modes to power-on again after a fault condition has been
detected (see the Typical Operating Characteristics).
When a fault is detected, for a period of tRETRY, GATE_
remains off and the 100Ωpulldowns are turned on.
After the tRETRY period, the device waits tDELAY and
retry sequencing if all power-up conditions are met
(see Figure 5). These include all VSET_ > 0.5V, EN/UV >
VEN_R, and OUT_ voltages < VTH_PL. The autoretry
period tRETRY is a function of CSLEW (see Table 1).
Power-Up and Power-Down
During power-up, OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must
be completed within the adjustable fault timeout period
(tFAULT); otherwise, the part forces a shutdown on all
GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing VEN/UV below VEN_F. The
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
12 ______________________________________________________________________________________
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than VTRK, the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
VTRK_F, a fault is signaled and the fast-shutdown mode
is initiated. In fast-shutdown mode, a 100Ωpulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_, and GATE_ is pulled low
with a strong IGDS current (see Figure 3).
Figure 4 shows the aborted sequencing mode. When
EN/UV goes low before tTIMEOUT expires, all the out-
puts go low, and the device goes into fast shutdown.
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ωinternal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below VTH_PL
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
Stability Comment
No external compensation is required for sequencing
or slew-rate control.
Inputs
IN1/IN2/IN3
The highest voltage on IN1, IN2, or IN3 supplies power
to the device. The undervoltage threshold for each IN_
supply is set with an external resistor-divider from each
IN_ to SET_ to ground. To disable sequencing on any
IN_, connect IN_ to ground (or leave unconnected) and
connect SET_ to a voltage greater than 0.5V.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6880/MAX6881 feature three and the MAX6882/
MAX6883 feature two externally adjustable IN_ under-
voltage lockout thresholds (SET1/SET2/SET3). The 0.5V
SET_ threshold enables monitoring IN_ voltages as low
as 0.5V. The undervoltage threshold for each IN_ sup-
ply is set with an external resistor-divider from each IN_
to SET_ to ground (see Figure 6). All SET_ inputs must
be above the internal SET_ threshold (0.5V) to enable
sequencing functionality. Use the following formula to
set the UVLO threshold:
VIN_ = VTH (R1 + R2) / R2
where VIN_ is the undervoltage lockout threshold and
VTH is the 500mV SET threshold.
Margin Input (MMAARRGGIINN) (MAX6880/MAX6882)
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST does not change
while MARGIN is low. PG/RST and all monitoring func-
tions are disabled while MARGIN is low. MARGIN
makes it possible to vary the supplies without a need to
adjust the thresholds to prevent sequencer alerts. Drive
MARGIN high or leave it unconnected for normal oper-
ating mode.
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(CSLEW) from SLEW to ground. Use the following for-
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10-8)/ CSLEW
where slew rate is in V/s and CSLEW is in farads.
The capacitor at CSLEW also sets the retry timeout peri-
od (tRETRY), see Table 1.
For example, if CSLEW = 100pF, we have tRETRY =
350ms, tFAULT = 21.91ms, slew rate = 935V/s. For
example, if CSLEW = 1nF, we have tRETRY = 3.5s, slew
rate = 93.5V/s.
CSLEW is the capacitor on SLEW pad, and must be
large enough so the parasitic PC board capacitance is
negligible. CSLEW should be in the range of 100pF <
CSLEW < 1nF.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 13
IN_
R1
R2
VIN_
SET_
MAX6880–
MAX6883
Figure 6. Setting the Undervoltage (UVLO) Thresholds
MAX6880–MAX6883
Limiting Inrush Current
The capacitor (CSLEW) at SLEW to ground, controls the
OUT_ slew rate, thus controlling the inrush current
required to charge the load capacitor at OUT_. Using
the programmed slew rate, limit the inrush current by
using the following formula:
IINRUSH = COUT x SR
where IINRUSH is in amperes, COUT is in farads, and SR
is in V/s.
Delay Time Input (DELAY)
To adjust the desired delay period (tDELAY) before
sequencing is enabled, connect a capacitor (CDELAY)
between DELAY to ground (see Figures 2 to 5). The
selected delay time is also enforced when EN/UV rises
from low to high when all the input voltages are present.
Use the following formula to calculate the delay time:
tDELAY = 200µs + (500kΩx CDELAY)
where tDELAY is in µs and CDELAY is in farads. Leave
DELAY unconnected for the default 200µs delay.
Timeout Period Input (TIMEOUT)
(MAX6880/MAX6882)
These devices feature a PG/RST timeout period.
Connect a capacitor (CTIMEOUT) from TIMEOUT to
ground to program the PG/RST timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(VTH_PG), PG/RST remains low for the selected timeout
period tTIMEOUT (see Figure 3).
tTIMEOUT = 200µs + (500kΩx CTIMEOUT)
where tTIMEOUT is in µs and CTIMEOUT is in farads.
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
Logic-Enable Input (EN/UUVV)
Drive logic EN/UV input above VEN_R to initiate voltage
sequencing during power-up operation. Drive logic
EN/UV below VEN_F to initiate tracking power-down
operation. Connect EN/UV to an external resistor-
divider network to set the external undervoltage lockout
threshold.
ABP Input (MAX6880/MAX6882)
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_. Do not use ABP to provide power to external cir-
cuitry. ABP maintains the device supply voltage during
rapid power-down conditions.
OUT1/OUT2/OUT3
The MAX6880/MAX6881 monitor three OUT_ and the
MAX6882/MAX6883 monitor two OUT_ outputs to con-
trol the sequencing performance. After the internal sup-
ply (ABP) exceeds the minimum voltage (2.7V)
requirements, EN/UV > VEN_R, and IN1/IN2/IN3 are all
greater than their adjusted SET_ thresholds, OUT1/
OUT2/OUT3 begin to sequence.
During fault conditions, an internal pulldown resistor
(100Ω) on OUT_ is enabled to help discharge load
capacitance (100Ωis connected for fast power-down
control).
Outputs
GATE_
The MAX6880–MAX6883 feature up to three GATE_ out-
puts to drive up to three external n-channel FET gates.
The following conditions must be met before GATE_
begins enhancing the external n-channel FET_:
1) All SET_ inputs (SET1/SET2/SET3) are above their
0.5V thresholds.
2) At least one IN_ input is above the minimum operat-
ing voltage (2.7V).
3) EN/UV > 1.25V.
At power-up mode, GATE_ voltages are enhanced by
control loops so all OUT_ voltages sequence at a
capacitor-adjusted slew rate. Each GATE_ is internally
pulled up to 5V above its relative IN_ voltage to fully
enhance the external n-channel FET when power-up is
complete.
Power-Good Output (PG/RST) (MAX6880/MAX6882)
The MAX6880/MAX6882 include a power-good (PG/RST)
output. PG/RST is an open-drain output and requires an
external pullup resistor.
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x VTH_PG) for the selected reset timeout
period tTIMEOUT (see the TIMEOUT Period Input sec-
tion) before PG/RST asserts high. PG/RST stays low for
the selected reset timeout period (tTIMEOUT) after all
the OUT_ voltages exceed their IN_ referenced thresh-
olds. PG/RST goes low when VSET_ < VTH or VEN/UV <
VEN_R (see Figure 2).
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
14 ______________________________________________________________________________________
Table 1. CSLEW Timing Formulas
TIME PERIOD FORMULAS
Slew Rate (9.35 x 10-8) / CSLEW
tRETRY 3.506 x 109 x CSLEW
tFAULT 2.191 x 108 x CSLEW
Applications Information
MOSFET Selection
The external pass MOSFET is connected in series with
the sequenced power-supply source. Since the load
current and the MOSFET drain-to-source impedance
(RDS) determine the voltage drop, the on characteris-
tics of the MOSFET affect the load supply accuracy.
The MAX6880–MAX6883 fully enhance the external
MOSFET out of its linear range to ensure the lowest
drain-to-source on-impedance. For highest supply
accuracy/lowest voltage drop, select a MOSFET with
an appropriate drain-to-source on-impedance with a
gate-to-source bias of 4.5V to 6.0V.
Layout and Bypassing
For better noise immunity, bypass each of the IN_
inputs to GND with 0.1µF capacitors installed as close
to the device as possible. Bypass ABP to GND with a
1µF capacitor installed as close to the device as possi-
ble. ABP is an internally generated voltage and must
not be used to supply power to external circuitry.
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 15
Selector Guide
PART CHANNEL TIMEOUT
SELECTABLE PG/RST MARGIN PG THRESHOLD
VOLTAGE (%)
MAX6880 3 Yes Yes Yes 92.5
MAX6881 3 No No No —
MAX6882 2 Yes Yes Yes 92.5
MAX6883 2 No No No —
Chip Information
PROCESS: BiCMOS
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
16 ______________________________________________________________________________________
SET1
IN1
IN1
IN2
IN3
SET2
SET3
EN/UV
OUT1
OUT1
OUT2
OUT3
ABP SLEW DELAY TIMEOUTGND
OUT2
OUT3
PG/RST
VBUS
IN2
0.1µF
1µF
0.1µF0.1µF
IN3 GATE1 GATE2 GATE3
MARGIN
MAX6880
Typical Application Circuit
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 17
15
16
14
13
6
5
7
SET3
SET1
8
IN1
OUT2
OUT3
GATE2
12
GATE1
4
12 11 9
IN3
IN2
SLEW
DELAY
GND
EN/UV
MAX6881
SET2 GATE3
3
10
OUT1
4mm x 4mm THIN QFN
TOP VIEW
EP*
15
16
14
13
6
5
7
SET2
EN/UV
8
ABP
OUT2
MARGIN
GATE2
12
GATE1
4
12 11 9
IN2
IN1
TIMEOUT
SLEW
DELAY
GND
MAX6882
SET1 PG/RST
3
10
OUT1
4mm x 4mm THIN QFN
EP*
15
16
14
13
6
5
7
SET2
EN/UV
8
N.C.
OUT2
N.C.
GATE2
12
GATE1
4
12 11 9
IN2
IN1
N.C.
SLEW
DELAY
GND
MAX6883
SET1 N.C.
3
10
OUT1
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
EP*
+ +
+
Pin Configurations (continued)
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
18 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE,
21-0139 2
1
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2005 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Heaney
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
21-0139
2
2
E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
