FEATURES
Access time : 55 ns
Low power consumption:
Operatingcurrent : 30 mA (TYP.)
Standby current : 4 µA(TYP.)
Single 2.7V ~ 5.5Vpower supply
All outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage :1.5V(MIN.)
All products ROHS Compliant
GENERAL DESCRIPTION
The AS6C4008 is a 4,194,304-bit low power
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C4008 is well designed for very low power
system applications, and particularly well suited for
battery back-up non-volatile memory application.
The AS6C4008 operates from a single power
supply of 2.7V~ 5.5Vand all inputs and outputs are
fully TTL compatible
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512Kx8
MEMORY ARRAY
COLUMN I/O
A0-A18
Vcc
Vss
DQ0-DQ7
CE#
WE#
OE#
PIN DESCRIPTION**
AUGUST 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG/09, v 1.4
Alliance Memory Inc
Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
32-pin 400 mil TSOP-II
SYMBOL DESCRIPTION
A0 - A18 Address Inputs
DQ0 – DQ7 Data Inputs/Outputs
CE# Chip Enable Inputs
WE# Write Enable Input
OE# Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature Vcc Range Speed Standby(ISB1TYP.) Operating(Icc,TYP.)
AS6C4008-40 ~ +85 ℃ 2.7 ~ 5.5V 55ns 4µA(LL) 30mA
Page 1 of 14
PIN CONFIGURATION
AUGUST 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG/09, v 1.4
Alliance Memory Inc
Page 2 of 14
AS6C4008
AS6C4008
AS6C4008
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
A14
Vcc
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
SOP/ P-DIP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
A13
CE#
OE#
WE#
A16
A18
29
32
30
31
A17
A15
TSOP-I/STSOP
DQ3
A11
A9
A8
A13
DQ2
A10
A14
A12
A7
A6
A5
Vcc
DQ7
DQ6
DQ5
DQ4
Vss
DQ1
DQ0
A0
A1
A2
A4 A3
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
OE#
WE#
CE#
A17
A15
A16
A18
32
31
29
30
A14
A16
A18
A13A7
A6
A5
A4
A3
DQ3
DQ0
A8
A9
A10
A11
OE#
CE#
TSOP-II
21
10
9
8
7
6
5
4
3
2
1
12
11
15
14
7161
18
19
20
DQ1
A12
A1
A0
VCC
A15
DQ6
A2
DQ2
VSS
DQ5
DQ7
25
22
23
24
32
29
30
31
26
27
28
DQ4
WE#
A17
13
TFBGA
OE#
WE#
A12A11 A13
NC
A18
A10 A14
A15
DQ5
DQ6
DQ7
A9
Vss
A8
A16
DQ4
Vcc
Vcc
DQ3
A17
Vss
A7
A0
DQ2
DQ1
DQ0
A6A1 A3
A5NC
A4A2
1234 5 6
H
G
C
D
E
F
A
B
CE#
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS VTERM -0.5 to 6.5 V
0 to 70(C grade)
TerutarepmeTgnitarepO A
-40 to 85(I grade)
TerutarepmeTegarotS STG -65 to 150
C
PnoitapissiDrewoP D1 W
ItnerruCtuptuOCD OUT 50 mA
Soldering Temperature (under 10 sec) TSOLDER 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE CE# OE# WE# I/O OPERATION SUPPLY CURRENT
Standby H X X High-Z ISB1
Output Disable L H H High-Z ICC,ICC1
Read L L H DOUT ICC,ICC1
Write L X L DIN ICC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. *3 MAX. UNIT
Supply Voltage VCC V5.50.37.2
Input High Voltage VIH*1 0.7*Vcc - VCC+0.3 V
Input Low Voltage VIL*1 V6.0-2.0-
Input Leakage Current ILI VCC ≧VIN ≧VSS - 1 - 1 µA
Output Leakage
Current ILO VCC ≧VOUT ≧VSS,
Output Disabled - 1 - 1 µA
Output High Voltage VOH IOH V--4.2Am1-=
Output Low Voltage VOL IOL = 2mA - - 0.4 V
- 55 - 30 60 mA
ICC
Cycle time = Min.
CE# = 0.2V, II/O = 0mA
o
ther pins at 0.2V or VCC - 0.2V
Average Operating
Power supply Current
ICC1
Cycle time = 1µs
CE# = 0.2V, II/O = 0mA
other pins at 0.2V or VCC - 0.2V
- 4 10 mA
-LL - 4 50 *4 µA
Standby Power
Supply Current ISB1 CE# V≧CC - 0.2V -LLE/-LLI - 4 50 *4 µA
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
2. Over/Undershoot specifications are characterized, not 100% tested.
3. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA= 25?
4. 25µA for special request
o
Co
Co
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG/09, v 1.4
Alliance Memory Inc
Page 3 of 14
CAPACITANCE(TA= 25 , f℃ = 1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
C ecnaticapaC tupnI IN -6 pF
Input/Output Capacitance CI/O -8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
V ot V2.0 sleveL esluP tupnI CC - 0.2V
sn3 semiT llaF dna esiR tupnI
Input and Output Timing Reference Levels 1.5V
C daoL tuptuO L = 30pF + 1TTL, IOH/IOL = -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE AS6C4008-55
-55
PARAMETER SYM. MIN. MAX. UNIT
t emiT elcyC daeR RC 55 -
Address Access Time tAA - 55
Chip Enable Access Time tACE - 55
Output Enable Access Time tOE - 30
Chip Enable to Output in Low-Z tCLZ* 10 -
Output Enable to Output in Low-Z tOLZ* 5 -
Chip Disable to Output in High-Z tCHZ* - 20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable to Output in High-Z tOHZ* - 20
Output Hold from Address Change tOH 10 -
(2) WRITE CYCLE AS6C4008
MIN. MAX. UNIT
t emiT elcyC etirW WC 55 - ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write tAW 50 -
Chip Enable to End of Write tCW
50 -
Address Set-up Time tAS 0 -
t htdiW esluP etirW WP
45 -
Write Recovery Time tWR 0
-
Data to Write Time Overlap tDW
25 -
Data Hold from End of Write Time tDH 0
Output Active from End of Write tOW* 5 -
Write to Output in High-Z tWHZ* - 20
*These parameters are guaranteed by device characterization, but not production tested.
PARAMETER SYM.
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 4 of 14
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
DoutData Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
DoutData Valid
tOH
OE#
tACE
CE#
tAA
Address
tRC
High-ZHigh-Z
tCLZ
tOLZ
tOE
tCHZ
tOHZ
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZand tOHZ are specified with CL= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 5 of 14
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
DinData Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE#
tWRtAS
tAW
Address
tWC
(4)
TOW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE# tWRtAS
tAW
Address
tWC
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 6 of 14
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
VCC for Data Retention VDR CE# V≧CC - 0.2V 1.5 - 5.5 V
-LL - 2 30 µA
Data Retention Current IDR VCC = 1.5V
CE# V≧CC - 0.2V -LLE/-LLI - 2 30 µA
Chip Disable to Data
Retention Time tCDR See Data Retention
Waveforms (below) 0 - - ns
Recovery Time tRtRC* - - ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE#
VDR ≧ 1.5V
CE# V≧cc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 7 of 14
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM. INCH.(BASE) MM(REF)
A0.118 (MAX) 2.997 (MAX)
A1 0.004(MIN) 0.102(MIN)
A2 0.111(MAX) 2.82(MAX)
b0.016(TYP) 0.406(TYP)
c0.008(TYP) 0.203(TYP)
D0.817(MAX) 20.75(MAX)
E0.445 ±0.005 11.303 ±0.127
E1 0.555 ±0.012 14.097 ±0.305
e0.050(TYP) 1.270(TYP)
L0.0347 ±0.008 0.881 ±0.203
L1 0.055 ±0.008 1.397 ±0.203
S0.026(MAX) 0.660 (MAX)
y0.004(MAX) 0.101(MAX)
Θ0o -10o 0o -10o
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 8 of 14
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYM. INCH(BASE) MM(REF)
A0.047 (MAX) 1.20 (MAX)
A1 0.004 ±0.002 0.10 ±0.05
A2 0.039 ±0.002 1.00 ±0.05
b0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
c0.005 (TYP) 0.127 (TYP)
D0.724 ±0.004 18.40 ±0.10
E0.315 ±0.004 8.00 ±0.10
e0.020 (TYP) 0.50 (TYP)
HD 0.787 ±0.008 20.00 ±0.20
L0.0197 ±0.004 0.50 ±0.10
L1 0.0315 ±0.004 0.08 ±0.10
y0.003 (MAX) 0.076 (MAX)
Θ0o～5o 0o～5o
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 9 of 14
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16 17
32
c
L
HD
D
"A"
E
e
12° (2x)12° (2x)
Seating Plane y
32
17
16
1
c
A2A1
L
A
0.254
0
GAUGE PLANE
12° (2X)
12° (2X)
SEATING PLANE
"A" DETAIL VIEW L1
b
UNIT
SYM. INCH(BASE) MM(REF)
A0.049 (MAX) 1.25 (MAX)
A1 0.005 ±0.002 0.130 ±0.05
A2 0.039 ±0.002 1.00 ±0.05
b0.008 ±0.01 0.20±0.025
c0.005 (TYP) 0.127 (TYP)
D0.465 ±0.004 11.80 ±0.10
E0.315 ±0.004 8.00 ±0.10
e0.020 (TYP) 0.50 (TYP)
HD 0.528±0.008 13.40 ±0.20.
L0.0197 ±0.004 0.50 ±0.10
L1 0.0315 ±0.004 0.8 ±0.10
y0.003 (MAX) 0.076 (MAX)
Θ0o～5o 0o～5o
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 10 of 14
36 ball 6mm × 8mm TFBGA Package Outline Dimension
$8*867 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 11 of 14
32-pin 400mil TSOP-Ⅱ Package Outline Dimension
AUGUST 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG/09, v 1.0.a
Alliance Memory Inc
Page 12 of 14
AUGUST 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 13 of 14
32 pin 600 mil P-DIP Package Outline Dimension
32 pin 600 mil P-DIP Package Outline Dimension
Note : D/E1/S dimension do not include mold flash.
UNIT
SYM. INCH(BASE) MM(REF)
A1 0.001 (MIN) 0.254 (MIN)
A2 0.150 ± 0.005 3.810 ± 0.127
B 0.018 ± 0.005 0.457 ± 0.127
D 1.650 ± 0.005 41.910 ± 0.127
E 0.600 ± 0.010 15.240 ± 0.254
E1 0.544 ± 0.004 13.818 ± 0.102
e 0.100 (TYP) 2.540 (TYP)
eB 0.640 ± 0.020 16.256 ± 0.508.
L 0.130 ± 0.010 3.302 ± 0.254
S 0.075 ± 0.010 1.905 ± 0.254
Q1 0.070 ± 0.005 1.778 ± 0.127
AUGUST 2009
512K X 8 BIT LOW POWER CMOS SRAM
AS6C4008
AUG09 v1.4
Alliance Memory Inc
Page 14 of 14
ORDERING
PART NUMBERING SYSTEM
INFORMATION
Alliance Organization VCC Package Operating
Temp Speed
ns
AS6C4008-55PCN 512k x 8 5V 32pin 600mil DIP Commercial ~
0º C to 70º C 55
AS6C4008-55SIN 512k x 8 5V 32pin 450mil SOP Industrial ~
-40ºC to 85º C 55
AS6C4008-55TIN 512k x 8 5V 32pin TSOP 1 (8 x 20 mm) Industrial ~
-40ºC to 85º C 55
AS6C4008-55STIN 512k x 8 5V 32pin sTSOP (8 x 13.4 mm) Industrial ~
-40ºC to 85º C 55
AS6C4008-55BIN 512k x
512k x 8
8 5V 36pin TFBGA (6mm x 8mm) Industrial ~
-40ºC to 85º C
Industrial ~
-40ºC to 85º C
55
55
AS6C4008-55ZIN
5V 32-pin 400mil TSOP 11
AS6C 4008 - 55 X X N
Temperature Range:
C = Commercial
(0ºC to +70º C)
I = Industrial
(-40º to +85º C)
N = Lead
Free ROHS
Compliant
Part
low
power
SRAM
prefix
Device
Number
40 = 4M
08 = by 8
Access
Time
Package Options:
P = 32 pin 600 mil P-DIP
S = 32 pin 450 mil SOP
T =
Z = 32-pin 400mil TSOP 11
32 pin TSOP 1 (8mm x 20 mm)
ST = 32 pin sTSOP (8mm x 13.4 mm)
B = 36 pin TFBGA (6mm x 8mm)
