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LM8262
SNOS975G –MAY 2001–REVISED AUGUST 2015
LM8262 Dual RRIO, High Output Current and Unlimited Cap Load Op Amp in VSSOP
1 Features 3 Description
The LM8262 is a Rail-to-Rail input and output Op
1(VS= 5V, TA= 25°C, Typical Values Unless Amp which can operate with a wide supply voltage
Specified). range. This device has high output current drive,
• GBWP 21MHz greater than Rail-to-Rail input common mode voltage
• Wide Supply Voltage Range 2.5 V to 22 V range, unlimited capacitive load drive capability, and
provides tested and ensured high speed and slew
• Slew Rate 12V/µs rate. It is specifically designed to handle the
• Supply Current/channel 1.15 mA requirements of flat panel TFT panel VCOM driver
• Cap Load Limit Unlimited applications as well as being suitable for other low
power and medium speed applications which require
• Output Short Circuit Current +53mA/−75 mA ease of use and enhanced performance over existing
• +/−5% Settling Time 400ns (500 pF, 100 mVPP devices.
step) Greater than Rail-to-Rail input common mode voltage
• Input Common Mode Voltage 0.3 V Beyond Rails range with 50 dB of Common Mode Rejection allows
• Input Voltage Noise 15nV/√Hz high side and low side sensing for many applications
• Input Current Noise 1pA/√Hz without concern for exceeding the range and with no
compromise in accuracy. In addition, most device
• THD+N < 0.05% parameters are insensitive to power supply variations.
This design enhancement is yet another step in
2 Applications simplifying its usage. The output stage has low
• TFT-LCD Flat Panel VCOM driver distortion (0.05% THD+N) and can supply a
respectable amount of current (15 mA) with minimal
• A/D Converter Buffer headroom from either rail (300 mV).
• High Side/low Side Sensing The LM8262 is offered in the space saving VSSOP
• Headphone Amplifier package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM8262 VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Output Response with Heavy Capacitive Load
Gain/Phase vs. Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM8262
SNOS975G –MAY 2001–REVISED AUGUST 2015
www.ti.com
Table of Contents
6.5 2.7V Electrical Characteristics................................. 5
1 Features.................................................................. 16.6 5V Electrical Characteristics.................................... 6
2 Applications ........................................................... 16.7 +/−11V Electrical Characteristics............................. 7
3 Description............................................................. 16.8 Typical Performance Characteristics ........................ 9
4 Revision History..................................................... 27 Device and Documentation Support.................. 12
5 Pin Configuration and Functions......................... 37.1 Community Resources............................................ 12
6 Specifications......................................................... 47.2 Trademarks............................................................. 12
6.1 Absolute Maximum Ratings ..................................... 47.3 Electrostatic Discharge Caution.............................. 12
6.2 ESD Ratings.............................................................. 47.4 Glossary.................................................................. 12
6.3 Recommended Operating Conditions....................... 48 Mechanical, Packaging, and Orderable
6.4 Thermal Information.................................................. 4Information........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2014) to Revision G Page
• Changed pin 5 From: -IN B To: +IN B Non-Inverting Input B in the Pin Functions table....................................................... 3
• Changed pin 6 From: +IN B To: -IN B Inverting Input B in the Pin Functions table............................................................... 3
• Moved "Storage temperature range" to the Absolute Maximum Ratings (1)(2) ....................................................................... 4
• Changed Handling Ratings To: ESD Ratings ........................................................................................................................ 4
Changes from Revision E (April 2013) to Revision F Page
• Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device and
Documentation Support; Mechanical, Packaging, and Ordering Information......................................................................... 1
• Changed from "Junction Temperature Range" to "Operating Temperature Range".............................................................. 4
• Deleted TJ= 25°C, ................................................................................................................................................................. 5
• Deleted TJ= 25°C, ................................................................................................................................................................. 6
• Deleted TJ= 25°C................................................................................................................................................................... 7
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 10
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SNOS975G –MAY 2001–REVISED AUGUST 2015
5 Pin Configuration and Functions
8-Pin
VSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NUMBER NAME
1 OUT A O Output A
2 -IN A I Inverting Input A
3 +IN A I Non-Inverting Input A
4 V- I Negative Supply
5 +IN B I Non-Inverting Input B
6 -IN B I Inverting Input B
7 OUT B O Output B
8 V+ I Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings (1)(2)
over operating free-air temperature range (unless otherwise noted) (3)
MIN MAX UNIT
VIN Differential +/−10 V
Output Short Circuit Duration See (4) (5)
Supply Voltage (V+- V−) 24 V
Voltage at Input/Output pins V++0.8, V−−0.8 V
Junction Temperature (6) +150 °C
Storage temperature range, Tstg −65 +150 °C
Soldering Information: Infrared or Convection (20 sec.) 235 °C
Wave Soldering (10 sec.) 260 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) Output short circuit duration is infinite for VS≤6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(6) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings VALUE UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000
V(ESD) Electrostatic discharge(1) V
Machine Model (MM)(3) ±200
(1) Human Body Model, 1.5 kΩin series with 100 pF. Machine Model, 0 Ωis series with 200 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Supply Voltage (V+- V−) 2.5 22 V
Operating Temperature Range(1) −40 +85 °C
(1) The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information DGK
THERMAL METRIC(1) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance(2) 235 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(max),RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
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6.5 2.7V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 2.7V, V−= 0V, VCM = 0.5V, VO= V+/2, and RL> 1MΩto V−.Boldface
limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage VCM = 0.5V & VCM = 2.2V +/−5 mV
– +/−0.7 +/−7
TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 2.2V µV/C
– +/−2 –
(3)
IBInput Bias Current VCM = 0.5V −2.00
–−1.20
(4) −2.70 µA
VCM = 2.2V +1.00
– +0.49
(4) +1.60
IOS Input Offset Current VCM = 0.5V & VCM = 2.2V 250 nA
– 20 400
CMRR Common Mode Rejection Ratio VCM stepped from 0V to 1.0V 76 100 –
60
VCM stepped from 1.7V to 2.7V – 100 – dB
VCM stepped from 0V to 2.7V 58 70 –
50
+PSRR Positive Power Supply Rejection V+= 2.7V to 5V 78 dB
104 –
Ratio 74
CMVR Input Common-Mode Voltage CMRR > 50dB −0.1 V
–−0.3
Range 0.0
2.8 V
3.0 –
2.7
AVOL Large Signal Voltage Gain VO= 0.5 to 2.2V, 70 dB
78 –
RL= 10k to V−67
VO= 0.5 to 2.2V, 67 dB
73 –
RL= 2k to V−63
VOOutput Swing RL= 10k to V−2.49 2.59 –
High 2.46 V
RL= 2k to V−2.45 2.53 –
2.41
Output Swing RL= 10k to V−100 mV
– 90
Low 120
ISC Output Short Circuit Current Sourcing to V−30 48 –
VID = 200mV (5)(6) 20 mA
Sinking to V+50 65 –
VID =−200mV (5)(6) 30
ISSupply Current (both amps) No load, VCM = 0.5V 2.5 mA
– 2.0 3.0
SR Slew Rate (7) AV= +1,VI= 2VPP – 9 – V/µs
fuUnity Gain-Frequency VI= 10mV, RL= 2kΩto V+/2 – 10 – MHz
GBWP Gain Bandwidth Product f = 50KHz 15.5 MHz
21 –
14
PhimPhase Margin VI= 10mV – 50 – Deg
enInput-Referred Voltage Noise f = 2KHz, RS= 50Ω– 15 – nV/ √Hz
inInput-Referred Current Noise f = 2KHz – 1 – pA/ √Hz
fmax Full Power Bandwidth ZL= (20pF || 10kΩ) to V+/2 – 1 – MHz
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS≤6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 5V, V−= 0V, VCM = 1V, VO= V+/2, and RL> 1MΩto V−.Boldface limits
apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage VCM = 1V & VCM = 4.5V +/−5 mV
– +/−0.7 +/−7
TC VOS Input Offset Average Drift VCM = 1V & VCM = 4.5V µV/°C
– +/−2 –
(3)
IBInput Bias Current VCM = 1V −2.00
–−1.18
(4) −2.70 µA
VCM = 4.5V +1.00
– +0.49
(4) +1.60
IOS Input Offset Current VCM = 1V & VCM = 4.5V 250 nA
– 20 400
CMRR Common Mode Rejection Ratio VCM stepped from 0V to 3.3V 84 110 –
72
VCM stepped from 4V to 5V – 100 – dB
VCM stepped from 0V to 5V 64 80 –
61
+PSRR Positive Power Supply Rejection V+= 2.7V to 5V, VCM = 0.5V 78 dB
104 –
Ratio 74
CMVR Input Common-Mode Voltage CMRR > 50dB −0.1 V
–−0.3
Range 0.0
5.1 V
5.3 –
5.0
AVOL Large Signal Voltage Gain VO= 0.5 to 4.5V, 74 84 –
RL= 10k to V−70 dB
VO= 0.5 to 4.5V, 70 80 –
RL= 2k to V−66
VOOutput Swing RL= 10k to V−4.75 4.87 –
High 4.72 V
RL= 2k to V−4.70 4.81 –
4.66
Output Swing RL= 10k to V−125 mV
– 86
Low 135
ISC Output Short Circuit Current Sourcing to V−35 53 –
VID = 200mV (5)(6) 20 mA
Sinking to V+60 75 –
VID =−200mV (5)(6) 50
ISSupply Current (both amps) No load, VCM = 1V 2.8 mA
– 2.3 3.5
SR Slew Rate (7) AV= +1, VI= 5VPP 10 V/µs
12 –
7
fuUnity Gain Frequency VI= 10mV, MHz
– 10.5 –
RL= 2kΩto V+/2
GBWP Gain-Bandwidth Product f = 50KHz 16 MHz
21 –
15
PhimPhase Margin VI= 10mV – 53 – Deg
enInput-Referred Voltage Noise f = 2KHz, RS= 50Ω– 15 – nV/ √Hz
inInput-Referred Current Noise f = 2KHz – 1 – pA/ √Hz
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS≤6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= 5V, V−= 0V, VCM = 1V, VO= V+/2, and RL> 1MΩto V−.Boldface limits
apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
fmax Full Power Bandwidth ZL= (20pF || 10kΩ) to V+/2 – 900 – KHz
tSSettling Time (+/−5%) 100mVPP Step, 500pF load – 400 – ns
THD+N Total Harmonic Distortion + Noise RL= 1kΩto V+/2 – 0.05% –
f = 10KHz to AV= +2, 4VPP swing
6.7 +/−11V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 11V, V−=−11V, VCM = 0V, VO= 0V, and RL> 1MΩto 0V. Boldface
limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage VCM =−10.5V & VCM = 10.5V +/−7 mV
– +/−0.7 +/−9
TC VOS Input Offset Average Drift VCM =−10.5V & VCM = 10.5V µV/°C
– +/−2 –
(3)
IBInput Bias Current VCM =−10.5V −2.00
–−1.05
(4) −2.80 µA
VCM = 10.5V +1.00
– +0.49
(4) +1.50
IOS Input Offset Current VCM =−10.5V & VCM = 10.5V 275 nA
– 30 550
CMRR Common Mode Rejection Ratio VCM stepped from −11V to 9V 84 100 –
80
VCM stepped from 10V to 11V – 100 – dB
VCM stepped from −11V to 11V 74 88 –
72
+PSRR Positive Power Supply Rejection V+= 9V to 11V 70 dB
100 –
Ratio 66
−PSRR Negative Power Supply Rejection V−=−9V to −11V 70 dB
100 –
Ratio 66
CMVR Input Common-Mode Voltage CMRR > 50dB −11.1 V
–−11.3
Range −11.0
11.1 V
11.3 –
11.0
AVOL Large Signal Voltage Gain VO= 0V to +/−9V, 78 85 –
RL= 10kΩ74 dB
VO= 0V to +/−9V, 72 79 –
RL= 2kΩ66
VOOutput Swing RL= 10kΩ10.65 10.77 –
High 10.61 V
RL= 2kΩ10.6 10.69 –
10.55
Output Swing RL= 10kΩ −10.75
–−10.98
Low −10.65 V
RL= 2kΩ −10.65
–−10.91 −10.6
(1) All limits are ensured by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(4) Positive current corresponds to current flowing into the device.
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+/−11V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= 11V, V−=−11V, VCM = 0V, VO= 0V, and RL> 1MΩto 0V. Boldface
limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
ISC Output Short Circuit Current Sourcing to ground 40 60 –
VID = 200mV (5)(6) 25 mA
Sinking to ground 65 100 –
VID = 200mV (5)(6) 55
ISSupply Current No load, VCM = 0V 4 mA
– 2.5 5
SR Slew Rate AV= +1, VI= 16VPP 10 V/µs
15 –
(7) 8
fUUnity Gain Frequency VI= 10mV, RL= 2kΩ– 13 – MHz
GBWP Gain-Bandwidth Product f = 50KHz 18 MHz
24 –
16
PhimPhase Margin VI= 10mV – 58 – Deg
enInput-Referred Voltage Noise f = 2KHz, RS= 50Ω– 15 – nV/ √Hz
inInput-Referred Current Noise f = 2KHz – 1 – pA/ √Hz
tSSettling Time (+/−1%, AV= +1) Positive Step, 5VPP – 320 – ns
Negative Step, 5VPP – 600 –
THD+N Total Harmonic Distortion +Noise RL= 1kΩ, f = 10KHz, – 0.01% –
AV= +2, 15VPP swing
CTREJ Cross-Talk Rejection f = 5MHz, Driver dB
– 68 –
RL= 10kΩ
(5) Short circuit test is a momentary test.
(6) Output short circuit duration is infinite for VS≤6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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6.8 Typical Performance Characteristics
TA= 25°C, Unless Otherwise Noted
Figure 1. VOS vs. VCM for 3 Representative Units Figure 2. VOS vs. VCM for 3 Representative Units
Figure 4. VOS vs. VSfor 3 Representative Units
Figure 3. VOS vs. VCM for 3 Representative Units
Figure 5. VOS vs. VSfor 3 Representative Units Figure 6. VOS vs. VSfor 3 Representative Units
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Typical Performance Characteristics (continued)
TA= 25°C, Unless Otherwise Noted
Figure 7. IBvs. VCM Figure 8. IBvs. VS
Figure 9. ISvs. VCM Figure 10. ISvs. VCM
Figure 11. ISvs. VCM Figure 12. ISvs. VS(PNP side)
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Typical Performance Characteristics (continued)
TA= 25°C, Unless Otherwise Noted
Figure 13. ISvs. VS(NPN side) Figure 14. Gain/Phase vs. Frequency
Figure 15. Unity Gain Frequency vs. VSFigure 16. Phase Margin vs. VS
Figure 17. Unity Gain Freq. and Phase Margin vs. VS
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7 Device and Documentation Support
7.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
7.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
7.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM8262MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 A46
LM8262MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A46
LM8262MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A46
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM8262MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM8262MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM8262MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM8262MM VSSOP DGK 8 1000 210.0 185.0 35.0
LM8262MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM8262MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2015
Pack Materials-Page 2
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