PHK18NQ03LT,518 - NXP Semiconductors

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using Trench MOS technology. This product is designed and qualified for use in

computing, communications, consumer and industria l applications only.

1.2 Features and benefits

High efficiency due to low switching

and conduction losses

Suitable for logic level gate drive

sources

1.3 Applications

DC-to-DC converters

Notebook computers

Switched-mode power supplies

Voltage regulators

1.4 Quick reference data

PHK18NQ03LT

N-channel TrenchMOS logic level FET

Rev. 02 — 21 December 2010 Product data sheet

SO8

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150°C --30V

IDdrain current Tsp =25°C; V

GS =10V;

see Figure 1 --20.3A

Ptot total power dissipation Tsp =25°C; see Figure 2 --6.25W

Static characteristics

RDSon drain-source on-state

resistance VGS =10V; I

D=25A;

Tj=25°C; see Figure 5 -7.18.9mΩ

Dynamic characteristics

QGD gate-drain charge VGS =4.5V; I

D=15A;

VDS =12V; see Figure 6 -2.5-nC

Product data sheet Rev. 02 — 21 December 2010 2 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

2. Pinning information

3. Ordering information

4. Limiting values

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphi c sy mbol

1Ssource

SOT96-1 (SO8)

2Ssource

3Ssource

4 G gate

5 D drain

6 D drain

7 D drain

8 D drain

bb076

Table 3. Ordering information

Type number Package

Name Description Version

PHK18NQ03LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - 30 V

VDGR drain-gate voltage Tj≥25 °C; Tj≤150 °C; RGS =20kΩ-30V

VGS gate-source voltage -20 20 V

IDdrain current Tsp =100°C; V

GS = 10 V; see Figure 1 - 12.1 A

Tsp =25°C; V

GS =10V; see Figure 1 - 20.3 A

IDM peak drain current Tsp = 25 °C; pulsed; tp≤10 µs - 80 A

Ptot total power dissipation Tsp =25°C; see Figure 2 -6.25W

Tstg storage temperature -55 150 °C

Tjjunction temperature -55 150 °C

Source-drain diode

ISsource current Tsp =25°C - 5.2 A

ISM peak source current Tsp = 25 °C; pulsed; tp≤10 µs - 20.8 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain -source

avalanche energy VGS =10V; T

j(init) =25°C; I

D= 31.5 A;

Vsup ≤25 V; unclamped; tp= 0.07 ms;

RGS =50Ω

-50mJ

Product data sheet Rev. 02 — 21 December 2010 3 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

Fig 1. Normalized continuous drain current as a

function of mounting base temperature Fig 2. Normalized total po we r dis sipa tion as a

function of solder point temperature

Tsp (°C)

0 20015050 100

03aa25

120

Ider

(%)

Tsp (°C)

0 20015050 100

03aa17

120

Pder

(%)

Product data sheet Rev. 02 — 21 December 2010 4 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-sp) thermal resistance from junction to solder

point --20K/W

Product data sheet Rev. 02 — 21 December 2010 5 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown voltage ID= 250 µA; VGS =0V; T

j= -55 °C 27 - - V

ID= 250 µA; VGS =0V; T

j=25°C 30--V

VGS(th) gate-source threshold voltage ID=1mA; V

DS =V

GS; Tj=150°C;

see Figure 3; see Figure 4 0.8--V

ID=1mA; V

DS =V

GS; Tj=25°C;

see Figure 3; see Figure 4 1.3 1.7 2.15 V

ID=1mA; V

DS =V

GS; Tj=-55°C;

see Figure 3; see Figure 4 --2.6V

IDSS drain leakage current VDS =30V; V

GS =0V; T

j=25°C --1µA

IGSS gate leakage current VGS =16V; V

DS =0V; T

j= 25 °C - - 100 nA

VGS =-16V; V

DS =0V; T

j= 25 °C - - 100 nA

RDSon drain-source on-state resistance VGS =10V; I

D=25A; T

j=150°C;

see Figure 5 - 12.1 15.1 mΩ

VGS =4.5V; I

D=25A; T

j=25°C;

see Figure 5 - 10.1 12.5 mΩ

VGS =10V; I

D=25A; T

j=25°C;

see Figure 5 -7.18.9mΩ

IDSS drain leakage current VDS =30V; V

GS =0V; T

j= 150 °C - - 100 µA

RGgate resistance f = 1 MHz - 1.6 - Ω

Dynamic characteristics

QG(tot) total gate charge ID=15A; V

DS =12V; V

GS =4.5V;

see Figure 6 - 10.6 - nC

QGS gate-source charge - 4.85 - nC

QGS1 pre-threshold gate-source charge - 2.4 - nC

QGS2 post-threshold gate-source

charge -2.45-nC

QGD gate-drain charge - 2.5 - nC

VGS(pl) gate-source plateau voltage ID=15A; V

DS =12V; see Figure 6 -3-V

Ciss input capacitance VDS =12V; V

GS =0V; f=1MHz;

Tj=25°C - 1380 - pF

VDS =0V; V

GS = 0 V; f = 1 MHz;

Tj=25°C - 1590 - pF

Coss output capacitance VDS =12V; V

GS =0V; f=1MHz;

Tj=25°C - 290 - pF

Crss reverse transfer capacitance - 135 - pF

td(on) turn-on delay time VDS =12V; R

L=0.8Ω; VGS =4.5V;

RG(ext) =5.6Ω

-19-ns

trrise time - 22 - ns

td(off) turn-off delay time - 19 - ns

tffall time - 11 - ns

Product data sheet Rev. 02 — 21 December 2010 6 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

Source-drain diode

VSD source-drain voltage IS=20A; V

GS =0V; T

j= 25 °C - 0.95 12 V

trr reverse recovery time IS=15A; dI

S/dt = -100 A/µs; VGS =0V;

VDS =30V -34-ns

Qrrecovered charge IS=15A; dI

S/dt = -100 A/µs; VGS =0V - 14 - nC

Table 6. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit

Fig 3. Gate-source threshold voltage as a function of

junction temperature Fig 4. Sub-threshold drain current as a function of

gate-source voltage

Fig 5. Normalized drain-source on-state resistance

factor as a function of junction temperature Fig 6. Gate charge waveform definitions

Tj (°C)

-60 180120060

003aab272

0.5

1.5

VGS(th)

(V)

max

typ

min

003aab271

10-6

10-5

10-4

10-3

10-2

10-1

0123

VGS (V)

(A)

maxtypmin

Tj (°C)

−60 180120060

003aab467

0.8

1.2

0.4

1.6

003aaa508

VGS

VGS(th)

QGS1 QGS2

QGD

VDS

QG(tot)

QGS

VGS(pl)

Product data sheet Rev. 02 — 21 December 2010 7 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

7. Package outline

Fig 7. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6

0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15 0.05 0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

O8: plastic small outline package; 8 leads; body width 3.9 mm SOT96

-1

99-12-27

03-02-18

Product data sheet Rev. 02 — 21 December 2010 8 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PHK18NQ03LT v.2 20101221 Product data sheet - PHK18NQ03LT v.1

Modifications: •Various changes to content.

PHK18NQ03LT v.1 20061218 Product data sheet - -

Product data sheet Rev. 02 — 21 December 2010 9 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The p r oduct status of device(s) described in t his document may have changed since this document was publis hed and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specifica t io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semico nductors’ aggregate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (prope r)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 02 — 21 December 2010 10 of 11

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by cust omer.

No offer to sell or license — Nothing in this document ma y be interpret ed or

construed as an of fer to se ll product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) d escribed herein may

be subject to export control regulat i ons. Export might require a prior

authorization from national authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

9.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PHK18NQ03LT

N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 December 2010

Document identifier: P HK18NQ03LT

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .7

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . .8

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . . .9

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . .9

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .10

10 Contact information. . . . . . . . . . . . . . . . . . . . . .10