PF1329-01 S1C33301 32-bit Single Chip Microcomputer DESCRIPTION 32-bit S1C33000 RISC Core Low Power Consumption Multiply Accumulation Built-in 8K-byte RAM 10-bit ADC 4-ch. SIO High-speed DMA, Intelligent DMA The S1C33301 is a Seiko Epson original 32-bit microcomputer. It features high speed, low power consumption, and low-voltage operation, and is ideal for portable products that require high-speed data processing. The S1C33301 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral circuits including a bus control unit, DMA controller, interrupt controller, timers, serial interface with FIFO, A/D converter, and SmartMedia interface, and also RAM. A high-speed oscillation circuit, PLL, and a low-speed oscillation circuit are also included, supporting advanced operation, power-saving operation, and high-performance realtime clock functions. Use of the internal MAC (multiplication and accumulation) function in combination with the A/D converter also facilitates the design of systems requiring DSP functions, such as speech recognition and synthesis applications. FEATURES CMOS LSI 32-bit parallel processing ............. S1C33000 RISC Core Main clock ....................................................... 50MHz (Max., up to 33MHz external clock input) Sub clock ........................................................ 32.768kHz (Typ., crystal) Instruction set .................................................. 16-bit fixed length, 105 instructions (MAC instruction is included, 2 cycles) Internal RAM size ............................................ 8,192 bytes Clock timer ...................................................... 1 channel Programmable timer ....................................... 8 bits x 6 channels and 16 bits x 6 channels Watchdog timer ............................................... Realized with a 16-bit programmable timer Serial interface ................................................ 4 channels Clock synchronization type and asynchronization type are selectable. Usable as an infrared ray (IrDA) interface. Ch.0 is selectable between a built-in buffer type (a 4 bytes of receive-data buffer and a 2 bytes of transmit-data buffer) and no buffer type. SmartMedia interface ...................................... 1 channel Allows direct connection of a SmartMedia 10-bit A/D converter ........................................ Successive approximation type 8 input channels (QFP15-128pin) 4 input channels (PFBGA-121pin) High-speed DMA ............................................. 4 channels Intelligent DMA ................................................ 128 channels I/O port ............................................................ Input port : 13 bits 9 bits I/O port : 47 bits 44 bits (QFP15-128pin) (PFBGA-121pin) (QFP15-128pin) (PFBGA-121pin) Interrupt controller ........................................... External interrupts : 10 types Internal interrupts : 40 types 1 S1C33301 External bus interface ..................................... 26-bit address bus, 16-bit data bus, 7 chip enable pins SRAM and Burst ROM may be connected directly. Shipping form .................................................. QFP15-128pin, PFBGA-121pin Supply voltage ................................................ Core voltage : 1.65 to 1.95V (1.80.15V) I/O voltage : 2.70 to 3.60V (3.0/3.30.3V) Power consumption ........................................ SLEEP state : 5.4W (1.8V, 50MHz) RUN state : 40mW (1.8V, 50MHz) BLOCK DIAGRAM VDD VSS VDDE S1C33301 A[25:18](P40-P47), A[17:1], A0/#BSL D[15:0] #RD #WRL/#WR #WRH/#BSH #CE10EX #CE[9:4](P55-P50) #WAIT(P30) #GAAS(P21) #GARD(P31) BCLK(P60) OSC3 OSC4 PLLS0 PLLC OSC1 OSC2 FOSC1(P14/P60) #RESET #NMI #X2SPD EA10MD[1:0] #BUSREQ(P34) #BUSACK(P35) #BUSGET(P31) DSIO DST[2:0](P10-12) DPCO(P13) DCLK(P14) TST S1C33000 CPU Core Bus Control Unit OSC3/PLL Interrupt Controller Prescaler 16-bit Programmable Timer (6 ch.) EXCLx(P10-13, P15, P16) TMx(P22-27) OSC1 8-bit Programmable Timer (6 ch.) T8UFx(P10-13) Clock Timer Serial Interface Standard (4 ch.) Built-in FIFO (1 ch.) Intelligent DMA (128 ch.) A/D Converter (8 ch.) #DMAREQx(K50, K51, K53, K54) #DMAACKx(P32, P33, P04, P06) #DMAENDx(P15, P16, P05, P07) High-speed DMA (4 ch.) Input Port #SMWE(P34) #SMRE(P35) SmartMedia Interface Pull-up InputControl Port RAM 8KB I/O Port Fig. 1 S1C33301 Functional Block Diagram 2 SINx(P00, P04, P27, P33), FSIN0(P00) SOUTx(P01, P05, P26, P16), FSOUT0(P01) #SCLKx(P02, P06, P25, P15), #FSCLK0(P02) #SRDYx(P03, P07, P24, P32), #FSRDY0(P03) AD0-7(K60-67) #ADTRG(K52) AVDDE K50-54 K60-67 P00-07, P10-16 P20-27, P30-35 P40-47, P50-55 P60-63 S1C33301 PIN LAYOUT QFP15-128pin 96 65 97 64 S1C33301 INDEX 128 33 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name A0(#BSL) A1 VSS A2 A3 A4 A5 A6 A7 VDD A8 A9 A10 A11 A12 A13 A14 VDDE A15 A16 A17 A18(P47) A19(P46) A20(P45) A21(P44) #NMI EA10MD0 EA10MD1 PLLS0 PLLC VSS TST No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name #RESET P30(#WAIT/#CE4&5) P31(#BUSGET/#GARD) P32(#DMAACK0/#SRDY3) P33(#DMAACK1/SIN3) VSS OSC4 OSC3 #X2SPD P34(#BUSREQ/#CE6/#SMWE) P35(#BUSACK/#SMRE) D0 D1 VDDE D2 D3 D4 D5 D6 D7 VDD #WRL(#WR/#WE) #WRH(#BSH) #RD #CE10EX(#CE9&10EX) BCLK(P60/FOSC1) P61 P62 P63 VSS #CE4(#CE11/#CE11&12/P50) #CE5(#CE15/#CE15&16/P51) 32 No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin name No. Pin name #CE6(#CE7&8/P52) 97 P24(TM2/#SRDY2) #CE7(#RAS0/#CE13/#RAS2/P53) 98 P25(TM3/#SCLK2) #CE8(#RAS1/#CE14/#RAS3/P54) 99 P26(TM4/SOUT2) #CE9(#CE17/#CE17&18/P55) 100 P27(TM5/SIN2) VSS 101 VSS D8 102 K50(#DMAREQ0) D9 103 K51(#DMAREQ1) D10 104 K52(#ADTRG) D11 105 K53(#DMAREQ2) VDDE 106 K54(#DMAREQ3) D12 107 DSIO D13 108 DST0(P10/EXCL0/T8UF0) D14 109 DST1(P11/EXCL1/T8UF1) D15 110 DST2(P12/EXCL2/T8UF2) A22(P43) 111 VDDE A23(P42) 112 DPCO(P13/EXCL3/T8UF3) #LCAS(P41/A24) 113 DCLK(P14/FOSC1) #HCAS(P40/A25) 114 P15(EXCL4/#DMAEND0/#SCLK3) P00(SIN0/FSIN0) 115 P16(EXCL5/#DMAEND1/SOUT3) P01(SOUT0/FSOUT0) 116 VSS P02(#SCLK0/#FSCLK0) 117 OSC2 P03(#SRDY0/#FSRDY0) 118 OSC1 VDD 119 VDD P04(SIN1/#DMAACK2) 120 K60(AD0) P05(SOUT1/#DMAEND2) 121 K61(AD1) P06(#SCLK1/#DMAACK3) 122 K62(AD2) P07(#SRDY1/#DMAEND3) 123 K63(AD3) VSS 124 K64(AD4) P20(#DRD) 125 K65(AD5) P21(#DWE/#GAAS) 126 K66(AD6) P22(TM0) 127 K67(AD7) P23(TM1) 128 AVDDE Bold: The terminal (signal) name of a default setup. Fig. 2 Pin Layout Diagram (QFP15-128pin) 3 S1C33301 PFBGA-121pin 11 VSS P23 (TM1) P20 (#DRD) VDD 10 P25 (TM3/ #SCLK2) P24 (TM2/ #SRDY2) P21 (#DWE/ #GAAS) P01 (SOUT0/ FSOUT0) D15 D13 D10 D8 #CE7 VSS (#RAS0/#CE13/ #RAS2/P53) P05 P02 (SOUT1/ (#SCLK0/ #DMAEND2) #FSCLK0) A22 (P43) VDDE D9 P26 P22 9 K50 (#DMAREQ0) (TM4/SOUT2) (TM0) P06 (#SCLK1/ #DMAACK3) A23 (P42) D12 D11 8 K52 (#ADTRG) K51 P27 (#DMAREQ1) (TM5/SIN2) P07 P04 (#SRDY1/ (SIN1/ #DMAEND3) #DMAACK2) #LCAS (P41/A24) D14 #RD #CE8 (#RAS1/ #CE14/ #RAS3/P54) #CE9 (#CE17/ #CE17&18/ P55) #CE10EX (#CE9&10EX) #CE6 #CE5 (#CE7&8/P52) #CE15/ #CE15&16/ P51) #CE4 BCLK (#CE11/ (P60/FOSC1) #CE11&12/ P50) #WRH #WRL (#WR/#WE) (#BSH) 7 DSIO K54 K53 DST0 VSS (#DMAREQ3) (#DMAREQ2) (P10/EXCL0/ T8UF0) #HCAS (P40/A25) D5 VSS D7 D6 VDD 6 VDDE DST1 DCLK DPCO DST2 P00 D0 (P11/EXCL1/ (P14/FOSC1) (P13/EXCL3/ (P12/EXCL2/ (SIN0/FSIN0) T8UF1) T8UF3) T8UF2) D1 D4 D2 D3 5 OSC2 VSS P35 (#BUSACK/ #SMRE) #X2SPD VDDE 4 OSC1 K60 (AD0) P34 (#BUSREQ/ #CE6/ #SMWE) P30 (#WAIT/ #CE4&5) P31 (#BUSGET/ #GARD) OSC3 P33 (#DMAACK1/ SIN3) 3 K61 (AD1) Top View 11 10 9 8 7 6 5 4 3 2 1 Index A B C D E F G H J K L A1 Corner Bottom View 11 10 9 8 7 6 5 4 3 2 1 P16 (EXCL5/ #DMAEND1/ SOUT3) VSS P15 (EXCL4/ #DMAEND0/ #SCLK3) VDD A10 VDDE A19 (P46) A8 A13 A18 (P47) K63 (AD3) A2 A5 A6 A12 A17 #NMI #RESET P32 OSC4 (#DMAACK0/ #SRDY3) 2 AVDDE K62 (AD2) A0 (#BSL) A3 VDD A11 A15 A21 (P44) EA10MD0 PLLS0 TST 1 VSS A1 A4 A7 A9 A14 A16 A20 (P45) EA10MD1 PLLC VSS L K J H G F E D C B A A1 Corner P03 (#SRDY0/ #FSRDY0) A B C D E F G H J K L Bold: The terminal (signal) name of a default setup. Fig. 3 Pin Layout Diagram (PFBGA-121pin) NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2003, All right reserved. SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com IC Marketing & Engineering Group ED International Marketing Department 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5117 Issue July, 2003 Printed in Japan L