General Description
The MAX5181 is a 10-bit, current-output digital-to-ana-
log converter (DAC) designed for superior performance
in signal reconstruction or arbitrary waveform genera-
tion applications requiring analog signal reconstruction
with low distortion and low-power operation. The
MAX5184 provides equal specifications, with on-chip
precision resistors for voltage-output operation. The
MAX5181/MAX5184 are designed for a 10pVs glitch
operation to minimize unwanted spurious signal com-
ponents at the output. An on-board 1.2V bandgap cir-
cuit provides a well-regulated, low-noise reference that
can be disabled for external reference operation.
The devices are designed to provide a high level of sig-
nal integrity for the least amount of power dissipation.
They operate from a single 2.7V to 3.3V supply.
Additionally, these DACs have three modes of opera-
tion: normal, low-power standby, and full shutdown,
which provides the lowest possible power dissipation
with a 1µA (max) shutdown current. A fast wake-up time
(0.5µs) from standby mode to full DAC operation facili-
tates power conservation by activating the DAC only
when required.
The MAX5181/MAX5184 are available in 24-pin QSOP
packages and are specified for the extended (-40°C to
+85°C) temperature range. Additionally, the MAX5184
is also available in a 24-pin thin QFN with exposed pad-
dle (EP) and is specified for the extended (-40°C to
+85°C) temperature range. For lower resolution, 8-bit
versions, refer to the MAX5187/MAX5190 data sheet.
Applications
Signal Reconstruction
Arbitrary Waveform Generators (AWGs)
Direct Digital Synthesis
Imaging Applications
Features
♦2.7V to 3.3V Single-Supply Operation
♦Wide Spurious-Free Dynamic Range:
70dB at fOUT = 2.2MHz
♦Fully Differential Output
♦Low-Current Standby or Full Shutdown Modes
♦Internal 1.2V, Low-Noise Bandgap Reference
♦Small 24-Pin QSOP and Thin QFN Packages
10-Bit, 40MHz, Current/Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
REFO
REFR
DGND
DVDD
AGND
OUTN
OUTP
CREF
TOP VIEW
D9
D8
D7
D6CS
PD
DACEN
AVDD
16
15
14
13
9
10
11
12
D5
D4
D3
D2D1
D0
REN
CLK
QSOP
MAX5181
MAX5184
19-1579; Rev 4; 4/03
Pin Configurations
Ordering Information
MAX5181/MAX5184
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5181BEEG -40°C to +85°C 24 QSOP
MAX5184BEEG -40°C to +85°C 24 QSOP
MAX5184ETG -40°C to +85°C 24 Thin QFN-EP*
*EP = Exposed paddle.
Pin Configurations continued at end of data sheet.
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ωdifferential output, CL= 5pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD to AGND, DGND .................................-0.3V to +6V
Digital Inputs to DGND.............................................-0.3V to +6V
OUTP, OUTN, CREF to AGND .................................-0.3V to +6V
VREF to AGND ..........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AVDD to DVDD.................................................................... ±3.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.50mW/°C above +70°C) ........762mW
24-Pin Thin QFN
(derate 20.8mW/°C above +70°C) ............................1667mW
Operating Temperature Range
MAX518_BEEG................................................-40°C to +85°C
MAX5184ETG ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution N 10 Bits
Integral Nonlinearity INL -2 ±0.5 +2 LSB
Differential Nonlinearity DNL Guaranteed monotonic -1 ±0.5 1 LSB
MAX5181 -2 +2
Zero-Scale Error MAX5184 -8 +8 LSB
Full-Scale Error (Note 1) -40 ±15 +40 LSB
DYNAMIC PERFORMANCE
Output Settling Time To ±0.5LSB error band 25 ns
Glitch Impulse 10 pVs
fCLK = 40MHz, fOUT = 500kHz 72
Spurious-Free
Dynamic Range to
Nyquist
SFDR fCLK = 40MHz,
fOUT = 2.2MHz, TA = +25°C57 70 dBc
fCLK = 40MHz, fOUT = 500kHz -70
MAX518_BEEG fCLK = 40MHz,
fOUT = 2.2MHz, TA = +25°C-68 -63
Total Harmonic Distortion to
Nyquist THD
MAX5184ETG fCLK = 40MHz,
fOUT = 2.2MHz, TA = +25°C-68 -57
dBc
fCLK = 40MHz, fOUT = 500kHz 61
MAX518_BEEG fCLK = 40MHz,
fOUT = 2.2MHz, TA = +25°C56 59
Signal-to-Noise Ratio to
Nyquist SNR
MAX5184ETG fCLK = 40MHz, fOUT = 2.2MHz 59
dB
Clock and Data Feedthrough All 0s to all 1s 50 nVs
Output Noise 10 pA/√Hz
ANALOG OUTPUT
Full-Scale Output Voltage VFS 400 mV
Voltage Compliance of Output -0.3 0.8 V
Output Leakage Current DACEN = 0, MAX5181 only -1 1 µA
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ωdifferential output, CL= 5pF, TA= TMIN to TMAX, unless
otherwise noted. Typical values are at TA= +25°C.)
Note 1: Excludes reference and reference resistor (MAX5184) tolerance.
TIMING CHARACTERISTICS
Output Voltage Temperature
Drift TCVREF 50 ppm/°C
Reference Supply Rejection 0.5 mV/V
Current Gain (IFS / IREF) 8 mA/mA
PARAMETER SYMBOL MIN TYP MAX UNITS
Digital Supply Current IDVDD 4.2 5.0 mA
Digital Power-Supply Voltage DVDD 2.7 3.3 V
Analog Supply Current IAVDD 1.7 4.0 mA
Analog Power-Supply Voltage AVDD 2.7 3.3 V
Standby Current ISTANDBY 1.0 1.5 mA
Shutdown Current ISHDN 0.5 1 µA
Digital Input Voltage High VIH 2 V
Output Voltage Range VREF 1.12 1.2 1.28 V
Reference Output Drive
Capability IREFOUT 10 µA
Digital Input Voltage Low VIL 0.8 V
Digital Input Current IIN ±1 µA
Digital Input Capacitance CIN 10 pF
DAC DATA to CLK Rise Setup
Time tDS 10 ns
DAC CLK Rise to DATA Hold
Time tDH 0ns
CS Fall to CLK Rise Time 5ns
CS Fall to CLK Fall Time 5ns
DACEN Rise Time to VOUT 0.5 µs
PD Fall Time to VOUT 50 µs
Clock Period tCLK 25 ns
Clock High Time tCH 10 ns
Clock Low Time tCL 10 ns
CONDITIONS
PD = 0, DACEN = 1, digital inputs at 0 or DVDD
VIN = 0 or DVDD
PD = 0, DACEN = 1, digital inputs at 0 or DVDD
PD = 0, DACEN = 0, digital inputs at 0 or DVDD
PD = 1, DACEN = X,digital inputs at 0
or DVDD (X = don’t care)
Full-Scale Output Current IFS 0.5 1 1.5 mAMAX5181 only
DAC External Output Resistor
load RL400 ΩMAX5181 only
REFERENCE
POWER REQUIREMENTS
LOGIC INPUTS AND OUTPUTS
TIMING CHARACTERISTICS
3.0
2.5
1.5
2.0
1.0
-40 35-15 10 60 85
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
MAX5181/4toc04
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX5181
MAX5184
8
7
6
5
4
3
2.5 4.03.0 3.5 4.5 5.0 5.5
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5181/4toc05
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX5184
MAX5181
4.00
3.75
3.25
3.50
3.00
-40 35-15 10 60 85
DIGITAL SUPPLY CURRENT vs.
TEMPERATURE
MAX5181/4toc06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX5184
MAX5181
610
600
590
580
570
2.5 4.03.0 3.5 4.5 5.0 5.5
STANDBY CURRENT vs.
SUPPLY VOLTAGE
MAX5181/4toc07
SUPPLY VOLTAGE (V)
STANDBY CURRENT (µA)
MAX5184
MAX5181
600
590
570
560
580
550
-40 35-15 10 60 85
STANDBY CURRENT vs.
TEMPERATURE
MAX5181/4toc08
TEMPERATURE (°C)
STANDBY CURRENT (µA)
MAX5184
MAX5181
0.14
0.12
0.10
0.06
0.08
0.04
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
MAX5181/4toc09
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
MAX5184
MAX5181
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
4 _______________________________________________________________________________________
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY vs.
INPUT CODE
MAX5181/4toc01
INPUT CODE
INL (LSB)
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0 128 256 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY vs.
INPUT CODE
MAX5181/4toc02
INPUT CODE
DNL (LSB)
3.0
2.5
2.0
1.5
1.0
2.5 4.03.0 3.5 4.5 5.0 5.5
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5181/4toc03
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
MAX5184
MAX5181
Typical Operating Characteristics
(AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400Ωdifferential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 5
0.13
0.11
0.07
0.05
0.09
0.03
-40 35-15 10 60 85
SHUTDOWN CURRENT vs.
TEMPERATURE
MAX5181/4toc10
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
MAX5184
MAX5181
1.28
1.27
1.26
1.25
1.24
1.23
2.5 4.03.0 3.5 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX5181/4toc11
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX5184
MAX5181
1.28
1.27
1.25
1.24
1.26
1.23
-40 35-15 10 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5181/4toc12
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX5184
MAX5181
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400Ωdifferential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
4
3
1
2
0
0 400300100 200 500
OUTPUT CURRENT vs.
REFERENCE CURRENT
MAX5181/4toc13
REFERENCE CURRENT (µA)
OUTPUT CURRENT (mA)
DYNAMIC RESPONSE RISE TIME
MAX5181/4toc14
500ns/div
OUTP
150mV/
div
OUTN
150mV/
div
DYNAMIC RESPONSE FALL TIME
MAX5181/4toc15
500ns/div
OUTP
150mV/
div
OUTN
150mV/
div
SETTLING TIME
MAX5181/4toc16
12.5ns/div
OUTN
100mV/
div
OUTP
100mV/
div
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
02468101214
16 18 20
FFT PLOT
MAX5181/4toc17
OUTPUT FREQUENCY (MHz)
(dBc)
fOUT = 2.2MHz
fCLK = 40MHz
100
90
70
60
50
80
40
10 20 25 30 35 40 45 50 55 6015
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
MAX5181/4toc18
CLOCK FREQUENCY (MHz)
SFDR (dBc)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
6 _______________________________________________________________________________________
66
68
72
70
76
74
78
500 1300900 1700 2100
MAX5181/4toc19
OUTPUT FREQUENCY (kHz)
SFDR (dBc)
SPURIOUS-FREE DYNAMIC RANGE vs.
OUTPUT FREQUENCY AND CLOCK FREQUENCY
fCLK = 40MHz
fCLK = 20MHz
fCLK = 50MHz
fCLK = 30MHz
fCLK = 10MHz
fCLK = 60MHz
62.4
62.0
62.2
61.4
61.6
61.2
61.0
61.8
60.8
0 1500500 1000 2000 2500
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
MAX5181/4toc20
OUPUT FREQUENCY (kHz)
SIINAD (dB)
-140
-100
-120
-60
-80
-20
0
-40
20
06421081412 1816 20
MAX5181/4toc21
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
MULTITONE SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
60
62
64
66
68
70
72
74
0.5 0.75 1.0 1.25 1.5
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
MAX5181/84-22
FULL-SCALE OUTPUT CURRENT (mA)
SFDR (dBc)
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, AGND = DGND = 0, IFS = 1mA, 400Ωdifferential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
FUNCTION
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 7
Pin Description
20 D9 Data Bit D9 (MSB)
1CREF REFO
2OUTP Positive Analog Output. Current output for MAX5181; voltage output for MAX5184.
3OUTN Negative Analog Output. Current output for MAX5181; voltage output for MAX5184.
4AGND Analog Ground. Exposed paddle must be connected to AGND.
8CS Active-Low Chip Select
7PD
Power-Down Select
0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD)
1: Enter shutdown mode
6DACEN
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGND
1: Power-up DAC with PD = DGND
X: Enter shutdown mode with PD = DVDD (X = don’t care)
5AVDD Analog Positive Supply, 2.7V to 3.3V
12–19 D1–D8 Data Bits D1–D8
11 D0 Data Bit D0 (LSB)
10 REN Active-Low Reference Enable. Connect to DGND to activate on-chip 1.2V reference.
9CLK Clock Input
21 DVDD Digital Supply, 2.7V to 3.3V
22 DGND Digital Ground
23 REFR Reference Input
24 REFO Reference Output
17
22
23
PIN
24
1, EP
5
4
3
2
9–16
8
7
6
18
19
20
21
NAME FUNCTION
QSOP THIN QFN
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
8 _______________________________________________________________________________________
Detailed Description
The MAX5181/MAX5184 are 10-bit digital-to-analog con-
verters (DACs) capable of operating with clock speeds
up to 40MHz. Each converter consists of separate input
and DAC registers, followed by a current source array
capable of generating up to 1.5mA full-scale output cur-
rent (Figure 1). An integrated 1.2V voltage reference and
control amplifier determine the data converters’ full-scale
output currents/voltages. Careful reference design
ensures close gain matching and excellent drift charac-
teristics. The MAX5184’s voltage output operation fea-
tures matched 400Ωon-chip resistors that convert the
current-array current into a voltage.
Internal Reference and
Control Amplifier
The MAX5181/MAX5184 provide an integrated 50ppm/°C,
1.2V, low-noise bandgap reference that can be dis-
abled and overridden by an external reference voltage.
REFO serves either as an external reference input or an
integrated reference output. If REN is connected to
DGND, the internal reference is selected and REFO
provides a 1.2V output. Due to its limited 10µA output
drive capability, REFO must be buffered with an exter-
nal amplifier, if heavier loading is required.
The MAX5181/MAX5184 also employ a control amplifier
designed to regulate simultaneously the full-scale out-
put current (IFS) for both outputs of the devices. The
output current is calculated as follows:
IFS = 8 ✕IREF
where IREF is the reference output current (IREF =
VREFO/RSET) and IFS is the full-scale output current.
RSET is the reference resistor that determines the
amplifier’s output current on the MAX5181 (Figure 2).
This current is mirrored into the current source array,
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5184 converts this output current into a differ-
ential output voltage (VOUT) with two internal, ground-
referenced 400Ωload resistors. Using the internal 1.2V
reference voltage, the MAX5184’s integrated
9.6kΩ*
REFR
REFO
1.2V REF
REN
CURRENT-
SOURCE ARRAY
DAC SWITCHES
400Ω*
OUTP
OUTN
400Ω*
MSB
DECODE
CLK
OUTPUT
LATCHES
OUTPUT
LATCHES
INPUT
LATCHES
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5184 ONLY.
INPUT
LATCHES
AVDD AGND CS DACEN PD
DVDD DGND
CREF
MAX5181
MAX5184
MSB
DECODE
D9–D0
Figure 1. Functional Diagram
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 9
reference output-current resistor (RSET = 9.6kΩ) sets
IREF to 125µA and IFS to 1mA.
External Reference
To disable the MAX5181/MAX5184’s internal reference,
connect REN to DVDD. A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower-power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. The
MAX5181/MAX5184 typically require 50µs to wake up
and let both outputs and the reference settle.
Shutdown Mode
For lowest power consumption, the MAX5181/MAX5184
provide a power-down mode in which the reference, con-
trol amplifier, and current array are inactive and the DAC
supply current is reduced to 1µA. To enter this mode,
connect PD to DVDD. To return to active mode, connect
PD to DGND and DACEN to DVDD. About 50µs are
required for the parts to leave shutdown mode and settle
to their outputs’ values prior to shutdown. Table 1 lists the
power-down mode selection.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5181/MAX5184. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D9 through D0. The content of the input latch is
then shifted to the DAC register, and the output up-
dates at the rising edge of the next clock.
Outputs
The MAX5181 output is designed to supply full-scale
output currents of 1mA into 400Ωloads in parallel with
a capacitive load of 5pF. The MAX5184 features inte-
grated 400Ωresistors that restore the array current to
proportional, differential voltages of 400mV. These dif-
ferential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed oper-
ational amplifier to convert the differential voltage into a
single-ended voltage.
RSET**
9.6kΩ
IFS
RSET
CCOMP*
REFR
AGND
AGND
DGND
IREF
REFO
MAX4040
RSET
1.2V
BANDGAP
REFERENCE
REN
CURRENT-
SOURCE ARRAY
*COMPENSATION CAPACITOR (CCOMP = 100nF) **9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
RSET FOR MAX5181.
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5181
MAX5184
Figure 2. Setting IFS with the Internal 1.2V Reference and the Control Amplifier
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
10 ______________________________________________________________________________________
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Table 1. Power-Down Mode Selection
X = Don’t care.
9.6kΩ*
IFS
0.1µF10µF
DVDD
RSET
REFR
AVDD
REFO
1.2V
BANDGAP
REFERENCE
REN DGND
AGND
AGND
CURRENT-
SOURCE ARRAY
EXTERNAL
1.2V
REFERENCE
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
RSET FOR MAX5181.
MAX5181
MAX5184
MAX6520
Figure 3. MAX5181/MAX5184 with External Reference
Wake-Up
High-Z
High-Z
MAX5181
MAX5181
AGNDMAX5184
ShutdownX1
Last state prior to standby mode10
AGND
MAX5184
Standby00
OUTPUT STATEPOWER-DOWN MODEDACEN (DAC ENABLE)
PD
(POWER-DOWN SELECT)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 11
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion com-
ponent.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
I/Q Reconstruction
in a QAM Application
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) archi-
tectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90°phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
THD 20 log (V V V V )
V
22324252
1
=× +++
Figure 4. Timing Diagram
CLK
D0–D9
OUT N - 1
N - 1
N
N
N + 1
N + 1
tDS tDH
tCH
tCL
tCLK
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
12 ______________________________________________________________________________________
The I/Q reconstruction system is completed by a quad-
rature modulator that combines the reconstructed com-
ponents with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Using the MAX5181/MAX5184 for
Arbitrary Waveform Generation
Designing a traditional arbitrary waveform generator
(AWG) requires five major functional blocks (Figure 8a):
clock generator, counter, waveform memory, DAC for
waveform reconstruction, and output filter. The wave-
form memory contains the sequentially stored digital
replica of the desired analog waveforms. This memory
shares a common clock with the DAC.
For each clock cycle, a counter adds one count to the
address for the waveform memory. The memory then
loads the next value to the DAC, which generates an
analog output voltage corresponding to that data value.
A DAC output filter can either be a simple or complex
lowpass filter, depending on the AWG requirements for
waveform function and frequencies. The main limita-
tions of the AWG’s flexibility are DAC resolution and
dynamic performance, memory length, clock frequen-
cy, and the filter characteristics.
Although the MAX5181/MAX5184 offer high-frequency
operation and excellent dynamics, they are suitable for
relaxed requirements in resolution (10-bit AWGs). To
increase an AWG’s high-frequency accuracy, tempera-
0
2
1
4
3
7
6
5
000 010001 011 100 101 110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
0
2
1
4
3
6
5
000 010001 011 100 101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
1 LSB
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 5a. Integral Nonlinearity Figure 5b. Differential Nonlinearity
0
2
1
3
000 010001 011
ACTUAL
DIAGRAM
IDEAL DIAGRAM
ACTUAL
OFFSET
POINT OFFSET ERROR
(+1 1/4 LSB)
IDEAL OFFSET
POINT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
0
5
4
6
7
000 101100 110 111
IDEAL DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL FULL-SCALE OUTPUT
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 5c. Offset Error Figure 5d. Gain Error
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 13
Figure 7. Using the MAX5181/MAX5184 for I/Q Signal Reconstruction
BP
FILTER
DVDD
AVDD CARRIER
FREQUENCY
MAX2452
IF
10
Q COMPONENT
BP
FILTER
DVDD
AVDD
+3V
10
DIGITAL
SIGNAL
PROCESSOR
QUADRATURE
MODULATOR
I COMPONENT
0°
90°Σ
+3V
MAX5181
MAX5184
MAX5181
MAX5184
400Ω*
400Ω*
REN AGNDDGND
+5V
-5V
402Ω
402Ω
402Ω
402Ω
OUTP
CLK
OUTN
0.1µF
DVDD
AVDD
AVDD
RSET**
OUTPUT
*400Ω RESISTORS INTERNAL TO MAX5184 ONLY.**MAX5181 ONLY
MAX5181
MAX5184
10µF
+3V
+
+
+3V
0.1µF0.1µF
0.1µF
REFR
REFO
CREF
D0–D9
10µF
MAX4108
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
14 ______________________________________________________________________________________
ture stability, wide-band tuning, and past phase-contin-
uos frequency switching, the user may approach a
direct digital synthesis (DDS) AWG (Figure 8b). This
DDS loop supports standard waveforms that are repeti-
tive, such as sine, square, TTL, and triangular wave-
forms. DDS allows for precise control of the
data-stream input to the DAC. Data for one complete
output waveform cycle is sequentially stored in a RAM.
As the RAM addresses are changing, the DAC con-
verts the incoming data bits into a corresponding volt-
age waveform. The resulting output signal frequency is
proportional to the frequency rate at which the RAM
addresses are changed.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the MAX5181/MAX5184’s performance. Unwanted
digital crosstalk may couple through the input, refer-
ence, power-supply, and ground connections, which
may affect dynamic specifications like SNR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX5181/
MAX5184. Therefore, grounding and power-supply
decoupling guidelines for high-speed, high-frequency
applications should be closely followed.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
Figure 8b. Direct Digital Synthesis AWG
Figure 8a. Traditional Arbitrary Waveform Generation
9.6kΩ*
400Ω*
WAVEFORM
MEMORY
(RAM)
DVDD
AVDD
*MAX5181 ONLY
MAX5181
MAX5184
10ADR
FILTERED
WAVEFORM
(ANALOG OUTPUT)
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
fc
COUNTER
CLOCK
GENERATOR
DATA
9.6kΩ*
400Ω*
WAVEFORM
MEMORY
(RAM)
DVDD
AVDD
*MAX5181 ONLY
MAX5181
MAX5184
10
DATA
ADR
A
D
D
E
R
FILTERED
WAVEFORM
(ANALOG OUTPUT)
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
fc
PHASE
ACCUMULATOR
ACCUMULATOR
FEEDBACK LOOP
FOR DATA BITS
CLOCK
GENERATOR
PIR
PHASE
INCREMENT
REGISTER
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 15
directly above the ground plane. Since the MAX5181/
MAX5184 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
VDD (AVDD) and digital VDD (DVDD). Each AVDD input
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close as possible to the ground plane.
The DVDD pins should also have separate 10µF and
0.1µF capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper opera-
tion. For best performance, bypass with low-ESR 0.1µF
capacitors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network can
also improve performance.
24
23
22
21
20
19
OUTN
OUTP
CREF
REFO
REFR
DGND
7
8
9
10
11
12
REN
D0
D1
D2
D3
D4
13
14
15
16
17
18
D5
D6
D7
D8
D9
DVDD
6
5
4
3
2
1
CLK
CS
PD
DACEN
AVDD
AGND
MAX5184
THIN QFN
TOP VIEW
Pin Configurations (continued) Chip Information
TRANSISTOR COUNT: 9464
SUBSTRATE CONNECTED TO AGND
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
16 ______________________________________________________________________________________
QSOP.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 17
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
21-0139 A
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
A21-0139
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm