IRLR/U2905PbF
HEXFET® Power MOSFET
S
D
G
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.4
RθJA Case-to-Ambient (PCB mount)** ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
Thermal Resistance
VDSS = 55V
RDS(on) = 0.027Ω
ID = 42A
Description
12/7/04
www.irf.com 1
D-Pak
TO-252AA
I-Pak
TO-251AA
lLogic-Level Gate Drive
lUltra Low On-Resistance
lSurface Mount (IRLR2905)
lStraight Lead (IRLU2905)
lAdvanced Process Technology
lFast Switching
lFully Avalanche Rated
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 42
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 30 A
IDM Pulsed Drain Current 160
PD @TC = 25°C Power Dissipation 110 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy210 mJ
IAR Avalanche Current25 A
EAR Repetitive Avalanche Energy11 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
PD- 95084A
lLead-Free
IRLR/U2905PbF
2www.irf.com
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 25A, VGS = 0V
trr Reverse Recovery Time ––– 80 120 ns TJ = 25°C, IF = 25A
Qrr Reverse RecoveryCharge ––– 210 320 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
42
160
A
VDD = 25V, starting TJ = 25°C, L =470µH
RG = 25Ω, IAS = 25A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
Uses IRLZ44N data and test conditions.
ISD ≤ 25A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Notes:
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.070 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.027 VGS = 10V, ID = 25A
––– ––– 0.030 W VGS = 5.0V, ID = 25A
––– ––– 0.040 VGS = 4.0V, ID = 21A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 21 ––– ––– S VDS = 25V, ID = 25A
––– ––– 25 µA VDS = 55V, VGS = 0V
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
QgTotal Gate Charge ––– ––– 48 ID = 25A
Qgs Gate-to-Source Charge ––– ––– 8.6 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 25 VGS = 5.0V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 11 ––– VDD = 28V
trRise Time ––– 84 ––– ns ID = 25A
td(off) Turn-Off Delay Time ––– 26 ––– RG = 3.4Ω, VGS = 5.0V
tfFall Time ––– 15 ––– RD = 1.1Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 1700 ––– VGS = 0V
Coss Output Capacitance ––– 400 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 150 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
nH
IGSS
S
D
G
LSInternal Source Inductance ––– 7.5 –––
RDS(on) Static Drain-to-Source On-Resistance
LDInternal Drain Inductance 4.5
IDSS Drain-to-Source Leakage Current
Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
IRLR/U2905PbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 25°C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
1
10
100
1000
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 175°C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
J
1
10
100
1000
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
T = 25°C
J
GS
V , Gate-to-Source Voltage (V)
D
I , Drain-to-Source Current (A)
T = 175°C
J
A
V = 25V
20µs PULSE WIDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
V = 10V
GS
A
I = 41A
D
IRLR/U2905PbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
400
800
1200
1600
2000
2400
2800
1 10 100
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
3
6
9
12
15
0 10203040506070
Q , Total Gate Charge (nC)
G
V , Gate-to-Source Voltage (V)
GS
A
FOR TEST CIRCUIT
SEE FIGURE 13
V = 44V
V = 28V
I = 25A
DS
DS
D
10
100
1000
0.4 0.8 1.2 1.6 2.0 2.4
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
A
T = 175°C
J
1
10
100
1000
1 10 100
V , Drain-to-Source Voltage (V)
DS
I , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 25°C
T = 175°C
Single Pulse
C
J
IRLR/U2905PbF
www.irf.com 5
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
5V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
10
20
30
40
50
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRLR/U2905PbF
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
0
100
200
300
400
500
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
A
Starting T , Junction Temperature (°C)
I
TOP 10A
17A
BOTTOM 25A
V = 25V
D
DD
IRLR/U2905PbF
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRLR/U2905PbF
8www.irf.com
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
IN THE ASSEMBLY LINE "A"
AS S EMBLED ON WW 16, 1999
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFR120
LOT CODE 1234
YEAR 9 = 1999
DAT E CODE
WE E K 16
PART NUMBER
LOGO
INTERNATIONAL
RECTIFIER
ASSEMBLY
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DATE CODE
OR
P = DE S I GNAT E S L E AD- F R E E
PRODUCT (OPT IONAL)
Note: "P" in assembly line position
i ndi cates "L ead-F ree"
12 34
WEEK 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
ASSEMBLY
INT ERNAT IONAL
RECT IFIER
IRLR/U2905PbF
www.irf.com 9
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFU120
YEAR 9 = 1999
DAT E CODE
LINE A
WEEK 19
IN THE ASSEMBLY LINE "A"
AS SEMBL E D ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRF U120
INTERNATIONAL
LOGO
RECT IFIER
LOT CODE
919A
78
Note: "P" in assembly line
position indicates "Lead-Free"
OR
56 78
ASSEMBLY
LOT CODE
RECT IFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMBER
WE EK 19
DAT E CODE
YEAR 9 = 1999
A = ASSEMBLY SITE CODE
P = DE S I GNAT E S L E AD- F R E E
PRODUCT (OPTIONAL)
IRLR/U2905PbF
10 www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
