TPS92314
DOUT
T1
RAUX1
RAUX2
DSN
DVCC
D1
ZSN
R1b
LED+
LED-
6 ± 7
LED
AC
IN
LPLS
LAUX
COUTa
R1a
COUTb
CCOMP RDLY
DZCD
CVCC
CY1
RISNS
RFILTER
AGND
VCC
ZCD
COMP
GATE
ISNS
PGND
DLY
Q1
RVCC
CIN
TPS92314
TPS92314A
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Off-Line Primary Side Sensing Controller with PFC
Check for Samples: TPS92314,TPS92314A
1FEATURES DESCRIPTION
The TPS92314/14A is an off-line controller
2• Regulates LED Current Without Secondary specifically designed to drive high power LEDs for
Side Sensing lighting applications. Features include adaptive
• Adaptive ON-time Control with Inherent PFC constant on-time control and quasi-resonant
• Critical-Conduction-Mode (CRM) with Zero- switching. Resonant switching allows for a reduced
EMI signature and increased system efficiency. Thus,
Current Detection (ZCD) for Valley Switching the device introduces a low external parts count and
• Programmable Switch Turn ON Delay high level of integration. The control algorithm of
• Programmable Constant ON-Time (COT) TPS92314/14A adjusts the on time with reference to
• Over Current Limit Options: the primary side inductor peak current and secondary
side inductor discharge time dynamically, the
– TPS92314: 1.15V response time of which is set by an external
– TPS92314A: 2.0V capacitor.
• Advanced Over Current and Over Voltage The over current protection is implemented by a cycle
Protection by cycle current limit of the primary inductor current.
• Internal Over-temperature Protection TPS92314A has a higher OCP threshold which is
more suitable for universal line application and
• 8-Pin SOIC Package TPS92314 can optimize the system cost. Other
supervisory features of the TPS92314/14A include
APPLICATIONS VCC over voltage protection and under-voltage
• Residential LED Lamps: A19 (E26/27, E14), lockout, output LEDs over-voltage protection and
PAR30/38, GU10 controller thermal shutdown. The TPS92314/14A is
available in 8-pin SOIC package.
• Solid State Lighting spacer
TYPICAL APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
4
3
2
8
5
6
7
COMP DLY
ZCD PGND
VCC GATE
AGND ISNS
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
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Figure 1. 8-Pin SOIC (Top View)
See D Package
PIN DESCRIPTIONS
Pin Name Description Application Information
1 VCC Power supply Input This pin provides power to the internal control , connect a 10μF~20μF capacitor
to ground for filtering.
2 AGND Small signal Ground Control signal ground return.
3 ZCD Zero crossing detection input The pin senses the voltage of the auxiliary winding for zero current detection.
4 COMP Compensation network Output of the error amplifier. Connect a capacitor from this pin to ground to
determine the frequency response of average current control loop.
5 DLY Delay control input Connect a resistor from this pin to ground to set the delay between switching
ON and OFF periods.
6 PGND Power Ground Gate driver ground return.
7 ISNS Current sense voltage feedback Switching MOSFET current sense pin.
8 GATE Gate driver output The output provides the gate driver of the power switching MOSFET.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE / UNITS
VCC to GND –0.3V to 40V
DLY,COMP,ZCD to GND –0.3V to 7V
ISNS to GND –0.3V to 7V
GATE to GND (5ns,-6V) -0.3V to 12V
ESD Susceptibility: HBM (2) ±2 kV
Storage Temperature Range –65°C to +150°C
Junction Temperature (TJ-MAX) +150°C
Maximum Lead Temperature (Solder and Reflow) 260°C
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified.
(2) Human Body Model, applicable std. JESD22-A114-C.
RECOMMENDED OPERATING CONDITIONS VALUE / UNITS
Supply Voltage range VCC 13V to 35V
Junction Temperature (TJ) -40°C to +125°C
Thermal Resistance (θJA)(1) 162°C/W
(1) This RθJA typical value determined using JEDEC specifications JESD51-1 to JESD51-11. However junction-to-ambient thermal
resistance is highly board layout dependent. In applications where high maximum power dissipation exists, special care must be paid to
thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
ELECTRICAL CHARACTERISTICS
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Symbol Parameter Conditions Min Typ (1) Max Units
SUPPLY VOLTAGE INPUT (VCC)
VCC-UVLO VCC Turn on threshold 22.5 / 21.7 25.4 28.3 / 29.5 V
VCCTurn off threshold 10.4 / 10.1 12.9 15.3 / 16.0 V
Hysteresis 12.5
ISTARTUP Startup Current VCC=VCC-UVLO–3.0V 22.2 25.8 µA
VCC-OVP Over voltage protection threshold 32.7 35.5 38.0 V
IVCC Operating supply current Not switching 0.8 1.2 1.8 mA
65kHz switching 2.3 3.0 mA
ZERO CROSS DETECT (ZCD)
IZCD ZCD bais current VZCD= 5V 0.01 1 uA
VZCD-OVP ZCD over-voltage threshold 3.9 4.3 4.7 V
TOVP Over voltage de-bounce time 3 cycle
VZCD-ARM ZCD Arming threshold VZCD = Increasing 1.04 1.23 1.42 V
VZCD-TRIG ZCD Trigger threshold VZCD = Decreasing 0.48 0.6 0.77 V
VZCD-HYS ZCD Hysteresis VZCD-ARM-VZCD-TRIG 0.61 V
COMPENSATION (COMP)
ICOMP-SOURCE Internal reference current for primary VCOMP = 2.0V, VISNS = 0V, Measure at COMP pin 27 µA
side current regulation
(1) Typical numbers are at 25°C and represent the most likely norm.
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ELECTRICAL CHARACTERISTICS (continued)
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Symbol Parameter Conditions Min Typ (1) Max Units
gmISNS ISNS error amp trans-conductance ΔVISNS to ΔICOMP at VCOMP = 2.5V 96 µmho
DELAY CONTROL (DLY)
VDLY DLY pin internal reference voltage 1.21 1.24 1.3 V
IDLY-MAX DLY source current VDLY= 0V 250 450 µA
CURRENT SENSE (ISNS)
VISNS-OCP Over Current Limit Detection Threshold TPS92314 1.07 1.15 1.22 V
VISNS-OCP Over Current Limit Detection Threshold TPS92314A 1.90 2.0 2.10 V
IISNS Current Sense Bias Current VISNS= 5V -1 1 µA
TOCP Over current Limit Detection Propagation Measure ISNS pin pulse width with VISNS = 5V 256 ns
Delay
GATE DRIVER (GATE)
VGATE-H GATE low voltage IGATE = 50mA source 7.6 9.4 V
VGATE-L GATE high drive voltage IGATE = 50mA sink 85 125 mV
tGATE-RISE Rise Time CLOAD = 1nF 94 ns
tGATE-FALL Fall Time CLOAD = 1nF 16 ns
TON-MIN Minimum ON time With ZCD signal. 311 500 900 ns
TON-MAX Maximum ON time 27 43.9 61 µs
TOFF-MIN Minimum OFF time 1.00 1.50 1.93 µs
TOFF-MAX Maximum OFF time ZCD = GND 67 117 151 µs
TOFF-START Maximum OFF time when start up. Maximum OFF time at first 511 switching after 44 78 102 µs
UVLO
TOFF-OCP Maximum OFF time when OCP OFF time when VISNS =4V. 233 µs
THERMAL SHUTDOWN
TSD Thermal shutdown temperature See (2) 165 °C
Thermal Shutdown hysteresis 20 °C
(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 165°C (typ.) and
disengages at TJ= 145°C (typ).
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-50 -25 0 25 50 75 100 125
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
IVCC-SD(mA)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
VZCD-OVP(V)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
80
90
100
110
120
130
140
150
TOFF-MAX(s)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
420
440
460
480
500
520
540
560
580
TON-MIN(ns)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
VCC-UVLO(V)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
21
22
23
24
25
26
27
28
29
VCCSTARTUP VOLTAGE (V)
TEMPERATURE (°C)
TPS92314
TPS92314A
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SNVS856B –JUNE 2012–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
VCC-UVLO vs Temperature VCC Startup Voltage vs Temperature
Figure 2. Figure 3.
TOFF-MAX vs Temperature TON-MIN vs Temperature
Figure 4. Figure 5.
IVCC-SD vs Temperature VZCD-OVP vs Temperature
Figure . Figure 6.
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-50 -25 0 25 50 75 100 125
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
VDLY(V)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
VCCOVP(V)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
VISNS-OCP(V)
TEMPERATURE (°C)
TPS92314
-50 -25 0 25 50 75 100 125
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
VISNS-OCP(V)
TEMPERATURE °C
TPS92314A
-50 -25 0 25 50 75 100 125
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
VZCD-ARM(V)
TEMPERATURE (°C)
-50 -25 0 25 50 75 100 125
0.40
0.45
0.50
0.56
0.60
0.65
0.70
0.75
0.80
VZCD-TRIG(V)
TEMPERATURE (°C)
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
VZCD-ARM vs Temperature VZCD-TRIG vs Temperature
Figure 7. Figure 8.
VISNS_OCP vs Temperature VISNS_OCP vs Temperature
Figure 9. Figure 10.
VDLY vs Temperature VCC-OVP vs Temperature
Figure 11. Figure 12.
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SIMPLIFIED INTERNAL BLOCK DIAGRAM
Figure 13. Simplified Block Diagram
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APPLICATION INFORMATION
The TPS92314/14A is an off-line controller specifically designed to drive LEDs. This device operates in Critical
Conduction Mode (CRM) with adaptive Constant ON-Time control, so that high power factor can be achieved
naturally. The TPS92314/14A can be configured as an isolated or non-isolated off-line converter. Refer to
TPS92314/14A typical schematic, on the front page, in the following discussion. The TPS92314/14A flyback
converter consists of a transformer which includes three windings LP, LSand LAUX. An external MOSFET Q1and
inductor current sensing resistor RISNS. Secondary side components are secondary side transformer winding LS,
output diode DOUT, and output capacitor COUT. An auxiliary winding is required, and serves two functions.
Auxiliary power is developed from the winding to power the TPS92314/14A after start-up, and detect the zero
crossing point due to the end of a complete switching cycle. During the on-period, Q1is turned on, and current
flows through LP, Q1and RISNS to ground, input energy is stored in the primary inductor LP. Simultaneously, the
ISNS pin of the device monitors the voltage of the current sensing resistor RISNS to perform the cycle-by-cycle
inductor current limit function. During the time MOSFET Q1is off, current flow in LPceases and the energy stored
during the on cycle is released to output and auxiliary circuits. During Q1off-time current in the secondary
winding LScharges the output capacitor COUT through DOUT and supplies the LED load. During Q1on-time, COUT
is responsible to supply load current to LED load during subsequent on-period. Also during Q1off-time current is
delivered to the auxiliary winding through DVCC and powers the TPS92314/14A. The voltage across LAUX, VLAUX
is fed back to the ZCD pin through a resistor divider network formed by RAUX1 and RAUX2 to perform zero crossing
detection of VLAUX, which determines the end of the off-period of a switching cycle. The next on period of a new
cycle will be initiated after an inserted delay of 2 x tDLY. The tDLY is programmable by a single resistor connecting
the DLY pin and ground. The setting of the delay time, tDLY will be described in a separate paragraph. The driver
signal tON time width is generated by comparing an internal generated saw-tooth waveform with the voltage on
the COMP pin (VCOMP). Since VCOMP is slow varying, tON is nearly constant within an AC line cycle. The duration
of the off-period (tOFF) is determined by the rate of discharging of the secondary current through the transformer.
Also,
where
• n is the turn ratio of LPand LS. (1)
Figure 14 shows the typical waveforms in normal operation.
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VCOMP
VSW
tON
ILED
tOFF
tDLY
VZCD
ILP
ILS
2xtDLY
VZCD-OVP
VZCD-ARM
VZCD-TRIG
VZCD-PEAK
t
t
t
t
TPS92314
TPS92314A
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SNVS856B –JUNE 2012–REVISED MAY 2013
Figure 14. Primary and Secondary Side Current Waveforms
Startup Bias and UVLO
During startup, the TPS92314/14A is powered from the AC line through R1and bridge diode D1(Typical
Application on front page). In the startup state, most of the internal circuits of the TPS92314/14A are shut down
in order to minimize internal quiescent current. When VCC reaches the rising threshold of the VCC-UVLO (typically
26V), the TPS92314/14A is operating in a low switching frequency mode, where tON and tOFF are fixed to 1.5μs
and 72μs. When VZCD–PEAK is higher than VZCD-ARM, the TPS92314/14A enters normal operation.
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VSW
tDLY
n u VLED +VIN
n u VLED
VCC
VSW
VZCD
VZCD-ARM
VZCD-OVP
26V
Startup
state
Low Freq state
Steady state
t
t
t
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
www.ti.com
Figure 15. Start up Bias Waveforms
Zero Crossing Detection
To minimized the switching loss of the power MOSFET, a zero crossing detection circuit is embedded in the
TPS92314/14A. VLAUX is AC voltage coupled from VSW by means of the transformer, with the lower part of the
waveform clipped by DZCD. VLAUX is fed back to the ZCD pin to detect a zero crossing point through a resistor
divider network which consists of RAUX1 and RAUX2. The next turn on time of Q1is selected VSW is the minimum,
an instant corresponding to a small delay after the zero crossing occurs. (Figure 15) The actual delay time
depends on the drain capacitance of the Q1and the primary inductance of the transformer (LP). Such delay time
is set by a single external resistor as described in Delay Setting section.
During the off-period at steady state, VZCD reaches its maximum VZCD-PEAK (Figure 14), which is scalable by the
turn ratio of the transformer and the resistor divider network RAUX1 and RAUX2. It is recommended that VZCD-PEAK
is set to 3V during normal operation.
Figure 16. Switching Node Waveforms
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0 400 800 1200 1600 2000
0
10
20
30
40
50
60
RDLY(k)
DELAY TIME (ns)
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Delay Time Setting
In order to reduce EMI and switching loss, the TPS92314/14A inserts a delay between the off-period and the on-
period. The delay time is set by a single resistor which connects across the DLY pin and ground, and their
relationship is shown in Figure 17. The optimal delay time depends on the resonance frequency between LPand
the drain to source capacitance of Q1(CDS). Circuit designers should optimize the delay time according to the
following equation.
(2)
(3)
After determining the delay time, tDLY can be implemented by setting RDLY according to the following equation:
where
• KDLY = 32MΩ/ns is a constant (4)
Figure 17. Delay Time Setting
Protection Features
OUTPUT OPEN CIRCUIT PROTECTION
The open circuit protection can be trigger through ZCD pin or VCC pin. If the LED string is disconnected from the
output of the TPS92314/14A, The secondly output voltage (VLED) and AUX wiring voltage VZCD-PEAK will
increases. IF VZCD-PEAK is greater than VZCD-OVP for 3 continues switching cycles or VCC voltage higher than
VCCOVP threshold, Over Voltage Protection (OVP) protection will be trigger. At the meantime, switching of Q1will
stop and VCC will decreases until it drops below the falling threshold of VCC-UVLO, the controller will restarts
automatically and enter into startup state (Figure 19).
VCC OVP PROTECTION
The TPS92314/14A has a built-in over voltage protection feature. It can be trigger through the VCC pin when
over VCC-OVP threshold. Once the VCC-OVP triggered, the output gate signal will pull low and VCC will decrease
until it drops below the VCC-UVLO, the controller will restarts automatically.
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VCC
VSW
VZCD
VZCD-ARM
VZCD-OVP
VLED
26V
13V
Steady
state Low freq
state Low freq
state
t
t
t
t
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OUTPUT SHORT CIRCUIT PROTECTION
If the LED string is shorted, the voltage of AUX wiring (VZCD-PEAK) will decrease, and as VZCD-PEAK voltage
decrease below VZCD-TRIG, the TPS92314/14A will enter low switching frequency operation. During low switching
frequency operation, power supplied from LAUX to VCC is not enough to maintain VCC. If the short remains VCC will
drop below the falling threshold of VCC-UVLO, the TPS92314/14A will attempt to restart at this time (Figure 18).
When the short is removed the TPS92314/14A will restore to steady state operation.
Figure 18. Output Short Circuit waveforms
OVER CURRENT PROTECTION
Over Current Protection (OCP) limits the drain current of MOSFET and prevents inductor / transformer
saturation. When VISNS reaches a threshold, OCP function will be triggered, controller gate drive will pull low and
OFF time will extends to 233μs, also CCOMP capacitor will be discharged by internal switch and gate drive ON
time will force to minimum in next cycle.
THERMAL PROTECTION
Thermal protection is implemented by an internal thermal shutdown circuit, which activates at 165°C (typically).
In this case, the switching power MOSFET will turn off. Capacitor CVCC will discharge until UVLO. If the junction
temperature of the TPS92314/14A falls back below 145°C, the TPS92314/14A resumes normal operation.
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VCC
VSW
VZCD
VZCD-ARM
VZCD-OVP
VLED
26V
13.2V
Steady
state
Disconnect LED Steady
state
ILED
Reconnect LED Force output short circuit Steady
state
Startup
state
Low Freq state
Steady state
OV state
Startup
state Steady
state Low
Freq
state
Startup
state Startup
state
VCC_OVP
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Figure 19. Auto Restart Operation
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Design Example
The following design example illustrates the procedures to calculate the external component values for the
TPS92314/14A isolated single stage fly-back LED driver with PFC.
•Design Specifications:
– Input voltage range, VAC_RMS = 85VAC – 132VAC
– Nominal input voltage, VAC_RMS(NOM) = 110VAC
– Number of LED in serial =7
– LED current, ILED = 350mA
– Forward voltage drop of single LED = 3.0V
– Forward voltage of LED stack, VLED = 21V
•Key operating Parameters:
– Converter minimum switching frequency, fSW = 75kHz
– Output rectifier maximum reverse voltage, VDOUT(MAX) = 100V
– Power MOSFET rating, VQ1(MAX) =800V
– Power MOSFET Output Capacitance, CDS = 37pF (estimated)
– Nominal output power, POUT = 8W
START UP BIAS RESISTOR
During start up, the VCC will be powered by the rectified line voltage through external resistor, R1. The VCC start
up current, IVCC(SU) must set in the range IVCC(MIN) > IVCC(SU) > ISTARTUP(MAX) to ensure proper restart operation
during OVP fault at maximum voltage input. In this example, a value of 0.88mA is suggested. The resistance of
R1can be calculated by dividing the nominal input voltage in RMS by the start up current suggested.
So, RAC = 132V / 0.88mA = 150KΩis recommended.
TRANSFORMER TURN RATIO
The transformer winding turn ratio, n is governed by the MOSFET Q1 maximum rated voltage, (VQ1(MAX)), highest
line input peak voltage (VAC-PEAK) and output diode maximum reverse voltage rating (VOUT(MAX)). The output diode
rating limits the lower bound of the turn ratio and the power MOSFET rating provide the upper bound of the turn
ratio. The transformer turn ratio must be selected in between the bounds. If the maximum reverse voltage of
DOUT (VDOUT(MAX)) is 100V. the minimum transformer turn ratio can be calculated with the equation in below.
(5)
In operation, the voltage at the switching node, VSW must be small than the MOSFET maximum rated voltage
VQ1(MAX) , For reason of safety, 10% safety margin is recommended. Hence, 90% of VQ1(MAX) is used in the
following equation.
(6)
where
• VOS is the maximum switching node overshoot voltage allowed, in this example, 50V is assumed. (7)
As a rule of thumb, lower turn ratio of transformer can provide a better line regulation and lower secondly side
peak current. In here, turn ratio n = 3.8 is recommended.
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SWITCHING FREQUENCY SELECTION
TPS92314/14A can operate at high switching frequency in the range of 60kHz to 150kHz. In most off-line
applications, with considering of efficiency degradation and EMC requirements, the recommended switching
frequency range will be 60kHz to 80kHz. In this design example, switching frequency at 75kHz is selected.
SWITCHING ON TIME
The maximum power switch on-time, tON depends on the low line condition of 85VAC. At 85VAC the switching
frequency was chosen at 75kHz. This transformer design will follow the formulae as shown below.
(8)
TRANSFORMER PRIMARY INDUCTANCE
The primary inductance, LPof the transformer is related to the minimum operating switching frequency fSW,
converter output power POUT, system efficiency ηand minimum input line voltage VAC_RMS(MIN). For CRM
operation, the output power, POUT can be described by the equation in below.
(9)
By re-arranging terms, the transformer primary inductance required in this design example can be calculated with
the equation follows:
(10)
The converter minimum switching frequency is 75kHz, tON is 5.3µs, VAC_RMS(MIN) = 85V and POUT = 8W, assume
the system efficiency, η= 85%. Then,
(11)
From the calculation in above, the inductance of the primary winding required is 0.81mH.
After the primary inductance and transformer turn ratio is determined, the current sensing resistor, RISNS can be
calculated.
The resistance for RISNS is governed by the output current and transformer turn ratio, the equation in below can
be used.
where
• VREF is fixed to 0.14V internally. (12)
Transformer turn ratio, NP: NSis 3.8 : 1 and ILED = 0.35A
(13)
In Figure 20, resistor RFILTER is used to reduce the high frequency noise into ISNS pin. the typical value is 300 x
RISNS .
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS92314 TPS92314A
PGNDPGNDPGND
RAUX1
RAUX2
DVCC
LAUX
DZCD
ZCD
VCC
TPS92314
RDLY RISNS
RFILTER
GATE
ISNS
PGND
DLY
Q1
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
www.ti.com
Figure 20. RISNS Resistor Interface
Figure 21. Auxiliary Winding Interface to ZCD
Auxiliary Winding Interface To ZCD
In Figure 21, RAUX1 and RAUX2 forms a resistor divider which sets the thresholds for over voltage protection of
VLED, VZCD-OVP, and VZCD-PEAK. Before the calculation, we need to set the voltage of the auxiliary winding, VLAUX at
open circuit.
• For example :
– Assume the nominal forward voltage of LED stack (VLED) is 21V.
– To avoid false triggering ZCDOVP voltage threshold at normal operation, select ZCDOVP voltage at 1.3
times of the VLED is typical in most applications. In case the transformer leakage is higher, the ZCDOVP
threshold can be set to 1.5 times of the VLED.
– In this design example, open circuit AUX winding OVP voltage threshold is set to 30V. Assume the current
through the AUX winding is 0.4mA typical.
– As a result, RAUX1 is 66kΩand RAUX2 is 12kΩ.
Auxiliary Winding Vcc Diode Selection
The VCC diode DVCC provides the supply current to the converter, low temperature coefficient , low reverse
leakage and ultra fast diode is recommended.
Compensation Capacitor And Delay Timer Resistor Selection
To achieve PFC function with a constant on time flyback converter, a low frequency response loop is required. In
most applications, a 4.7µF CCOMP capacitor is suitable for compensation.
16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Vsw
n u VLED
VOS
VSN
VMOS_BV VAC_PEAK
TPS92314
CCOMP RDLY
AGND
VCC
ZCD
COMP
GATE
ISNS
PGND
DLY
AGND
TPS92314
TPS92314A
www.ti.com
SNVS856B –JUNE 2012–REVISED MAY 2013
Figure 22. Compensation and DLY Timer connection
The resistor RDLY connecting the DLY pin to ground is used to set the delay time between the ZCD trigger to
power MOSFET turn on. The delay time required can be calculated with the parasitic capacitance at the drain of
MOSFET to ground and primary inductance of the transformer. Equation 14 can be used to find the delay time
and Figure 17 can help to find the resistance once the delay time is calculated
(14)
For example, using a transformer with primary inductance LP= 1mH, and power MOSFET drain to ground
capacitor CDS=37pF, the tDLY can be calculated by the upper equation. As a result, tDLY=302ns and RDLY is
6.31kΩ. The delay time may need to change according to the primary inductance of the transformer. The typical
level of output current will shift if inappropriate delay time is chosen.
Output Flywheel Diode Selection
To increase the overall efficiency of the system, a low forward voltage schottky diode with appropriate rating
should be used.
Primary Side Snubber Design
The leakage inductance can induce a high voltage spike when power MOSFET is turned off. Figure 23 illustrates
the operation waveform. A voltage clamp circuit is required to protect the power MOSFET. The voltage of
snubber clamp (VSN) must be higher than the sum of over shoot voltage (VOS), LED open load voltage multiplied
by the transformer turn ratio (n). In this examples, the VOS is 50V and LED maximum voltage, VLED(MAX) is 30V,
transformer turn ratio is 3.8. The snubber voltage required can be calculated with following equations.
Figure 23. Snubber Waveform
(15)
where n is the turn ratio of the transformer.
(16)
At the same time, sum of the snubber clamp voltage and VAC peak voltage (VAC_PEAK) must be smaller than the
MOSFET breakdown voltage (VMOS_BV). By re-arranging terms, equation in below can be used.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
www.ti.com
(17)
In here, snubber clamp voltage, VSN = 250V is recommended.
Output Capacitor
The capacitance of the output capacitor is determined by the equivalent series resistance (ESR) of the LED,
RLED and the ripple current allowed for the application. The equation in below can be used to calculate the
required capacitance.
(18)
Assume the ESR of the LED stack contains 7 LEDs and is 2.6Ω, AC line frequency fAC is 60Hz.
In this example, LED current ILED is 350mA and output ripple current is 30% of ILED:
(19)
Then, COUT = 480μF.
In here, a 470μF output capacitor with 10μF ceramic capacitor in parallel is suggested.
PCB Layout Considerations
The performance of any switching power supplies depend as much upon the layout of the PCB as the
component selection. Good layout practices are important when constructing the PCB. The layout must be as
neat and compact as possible, and all external components must be as close as possible to their associated
pins. High current return paths and signal return paths must be separated and connect together at single ground
point. All high current connections must be as short and direct as possible with thick traces. The drain voltage of
the MOSFET should be connected close to the transformer pin with short and thick trace to reduce potential
electromagnetic interference. For off-line applications, one more consideration is the safety requirements. The
clearance and creepage to high voltage traces must be complied to all applicable safety regulations.
18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
DOUT
1A 600V
T1
RAUX1
66 kQ
RAUX2
12 kQ
RVCC
DVCC
D1
RAC
22Q/1W
CAC
47 nF
CIN1
0.1 F
L1 3.3 mH
VR1
0.5A
R1b
75k
LED+
LED-
6 ± 7
LED
90-132VAC
LP
LAUX
COUTa
10 F
R1a
75k
COUTb
470 F
CIN2
0.1 F
CCOMP
4.7 FRDLY
6.34 kQ
DZCD
VCC
10 F
RF
120Q
AGND
VCC
ZCD
COMP
GATE
ISNS
PGND
DLY
RL
49.9 kQ
CIN3
0.1 F
2A
800V
RISNS 0.4Q
20Q
NP:NAUX = 1:1
TPS92314
DOUT
1A 100V
RAUX1
66 kQ
RAUX2
12 kQ
RVCC
DVCC
D1
RAC
22Q/1W
CAC
47 nF
CIN1
0.1 F
L1 3.3 mH
VR1
0.5A
R1b
75k
LED+
LED-
6 ± 7
LED
90-132VAC COUTa
10 F
R1a
75k
COUTb
470 F
CIN2
0.1 F
CCOMP
4.7 FRDLY
6.34 kQ
DZCD
VCC
10 F
RF
450Q
AGND
VCC
ZCD
COMP
GATE
ISNS
PGND
DLY
RL
49.9 kQ
2A
800V
RISNS 1.5Q
20Q
T1
250V
LPLS
LAUX
CY1
1A
600V
2200 pF
CIN3
0.1 F
NP : NS : NAUX = 3.8 : 1 : 1
TPS92314
TPS92314A
www.ti.com
SNVS856B –JUNE 2012–REVISED MAY 2013
Figure 24. Isolated Topology Schematic
Figure 25. Non-isolated Topology Schematic
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
SNVS856B –JUNE 2012–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (May 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 19
20 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS92314AD/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92314
A
TPS92314ADR/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92314
A
TPS92314D/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92314
TPS92314DR/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T92314
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS92314DR/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS92314DR/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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