IRF1010NS
IRF1010NL
HEXFET® Power MOSFET
02/14/02
VDSS = 55V
RDS(on) = 11mΩ
ID = 85A
S
D
G
Advanced HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET
power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device
for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of its
low internal connection resistance and can dissipate up to
2.0W in a typical surface mount application.
The through-hole version (IRF1010NL) is available for low-
profile applications.
lAdvanced Process Technology
lUltra Low On-Resistance
lDynamic dv/dt Rating
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
Description
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 85
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 60 A
IDM Pulsed Drain Current 290
PD @TC = 25°C Power Dissipation 180 W
Linear Derating Factor 1.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
IAR Avalanche Current43 A
EAR Repetitive Avalanche Energy18 mJ
dv/d t Peak Diode Recovery dv/dt 3.6 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 srew 10 l b f •in (1.1N•m)
2
D P a k
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Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.85
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)** ––– 40 °C/W
Thermal Resistance
PD - 94171
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S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 43A, VGS = 0V
trr Reverse Recovery Time ––– 69 100 ns TJ = 25°C, IF = 43A
Qrr Reverse Recovery Charge ––– 220 230 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
85
290 A
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 270µH
RG = 25 Ω, IAS = 43A, VGS=10V (See Figure 12)
ISD ≤ 43A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is a typical value at device destruction and
represents operation outside rated limits.
Notes:
This is a calculated value limited to TJ = 175°C .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Uses IRF1010N data and test conditions.
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– VV
GS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.058 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 11 mΩVGS = 10V, ID = 43A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 32 ––– ––– SV
DS = 25V, ID = 43A
––– ––– 25 µA VDS = 55V, VGS = 0V
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge ––– ––– 120 ID = 43A
Qgs Gate-to-Source Charge ––– ––– 19 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 41 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 13 ––– VDD = 28V
trRise Time ––– 76 ––– ID = 43A
td(off) Turn-Off Delay Time ––– 39 ––– RG = 3.6Ω
tfFall Time ––– 48 ––– VGS = 10V, See Fig. 10
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 3210 ––– VGS = 0V
Coss Output Capacitance ––– 690 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 140 ––– pF ƒ = 1.0MHz, See Fig. 5
EAS Single Pulse Avalanche Energy ––– 1030250mJ IAS = 4.3A, L = 270µH
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
1
10
100
1000
0.1 1 10 100
20µs PULSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
1
10
100
4 6 8 10 12
V = 25V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
85A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
020 40 60 80 100 120
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
43A
V = 11V
DS
V = 27V
DS
V = 44V
DS
0.1
1
10
100
1000
0.0 0.6 1.2 1.8 2.4
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
110 100
VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
5000
6000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + Cgd
1 10 100 1000
VDS , Drain-toSource Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
VGS
+
-
VDD
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
25 50 75 100 125 150 175
0
20
40
60
80
100
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectan
g
ular Pulse Duration
(
sec
)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
25 50 75 100 125 150 175
0
100
200
300
400
500
Startin
g
T , Junction Temperature( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
18A
30A
43A
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
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Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 14. For N-channel HEXFET® power MOSFETs
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D2Pak Package Outline
D2Pak
Part Marking Information
10.16 (.400)
R EF .
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF.
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
5.28 (.208)
4.78 (.188)
4.69 (.185)
4.20 (.165)
10.54 (.415)
10.29 (.405)
- A -
2
1 3 15.49 (.610)
14.73 (.580)
3X 0.93 (.037)
0.69 (.027)
5.08 (.200)
3X 1.40 (.055)
1.14 (.045)
1.78 (.070)
1.27 (.050)
1.40 (.055)
MAX .
NOTES:
1 DIM EN SIO NS AF TER SOL DER DIP .
2 DIM E NS IO N IN G & TO LE RA N CIN G P ER AN S I Y14.5M , 1982.
3 CONTROLLIN G DIMENSION : INCH.
4 HEATSINK & LEAD DIM ENSION S DO NOT INCLUDE BURRS.
0.55 (.022)
0.46 (.018)
0.25 (.010) M B A M MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2 X
LEAD ASSIGNMEN TS
1 - GAT E
2 - DRAIN
3 - SOUR CE
2.54 (.100)
2 X
PART NUMBER
INTERNATIONAL
RECT IF IE R
L O GO DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
AS SE MBLY
LO T C ODE
F530S
9 B 1 M
9246
A
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Package Outline
TO-262 Outline
TO-262
Part Marking Information
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IRF1010NS/IRF1010NL
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/02
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
Tape & Reel Information
D2Pak
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634 )
15.90 (.626 )
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609 )
15.22 (.6 01)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50
(
.532
)
12.80
(
.504
)
330.00
(14.173)
MAX.
27.40
(
1.079
)
23.90
(
.941
)
60.00
(
2.362
)
MIN.
30.40
(
1.197
)
MA X.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMF O RMS T O EIA-418.
2. CONTROLLING DIMENSION: MILLIM ETER.
3. DIM ENSIO N M EASUR ED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
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Note: For the most current drawings please refer to the IR website at:
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