UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
SLUS166B - NOVEMBER 1999 - REVISED NOVEMBER 2004
FEATURES
•User Programmable Soft Start With
Active Low Shutdown
•User Programmable Maximum Duty
Cycle
•Accessible 5V Reference
•Undervoltage Lockout
•Operation to 1MHz
•0.4A Source/0.8A Sink FET Driver
•Low 100µA Startup Current
Economy Primary Side Controller
1
3
2
7
FB
+
–
+
–
1V
+
–
6µA
+5V
0.5V
OSC
4
R
Q
S
–
+
5V
REF
15/8V
10/8V
VDD
8
REF
CREF
CVDD
5
+
–
VREF
SS
RT1
RT2
CSS
DISABLE
NOISE
FILTER
SLOPE
COMP
CURRENT
SENSE
FEEDBACK
RSTART
VIN
CLK
PWM
LATC H
UVLO
1V
VOUT
CT
6
17.5V
OUT
GND
TYPICAL APPLICATION DIAGRAM
UDG-99036
DESCRIPTION
The UCC3809 family of BCDMOS economy low power integrated circuits
contains all the control and drive circuitry required for off-line and isolated
DC-to-DC fixed frequency current mode switching power supplies with
minimal external parts count. Internally implemented circuits include
undervoltage lockout featuring startup current less than 100µA, a user ac-
cessible voltage reference, logic to ensure latched operation, a PWM com-
parator, and a totem pole output stage to sink or source peak current. The
output stage, suitable for driving N-Channel MOSFETs, is low in the off
state.
Oscillator frequency and maximum duty cycle are programmed with two
resistors and a capacitor. The UCC3809 family also features full cycle soft
start.
The family has UVLO thresholds and hysteresis levels for off-line and
DC-to-DC systems as shown in the table to the left.
The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP
(N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and
MSOP packages make the device ideal for applications where board
space and height are at a premium.
PART
NUMBER TURN ON
THRESHOLD TURN OFF
THRESHOLD
UCCX809-1 10V 8V
UCCX809-2 15V 8V
application
INFO
available
2
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
CONNECTION DIAGRAM
Temperature Range Available Packages
UCC1809-X –55°C to +125°C J
UCC2809-X –40°C to +85°C N, D, P, PW
UCC3809-X 0°C to +70°C N, D, P, PW
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, CVREF = 0.47 mF, VDD = 12V. TA=T
J.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Section
VDD Clamp IVDD = 10mA 16 17.5 19 V
IVDD No Load 600 900 µA
IVDD Starting (Note 1) 110 µA
IVDD Standby UCCx809-1, VDD = Start Threshold - 300mV 110 125 µA
UCCx809-2, VDD = Start Threshold - 300mV 130 170 µA
Undervoltage Lockout Section
Start Threshold (UCCx809-1) 9.4 10.4 V
UVLO Hysteresis (UCCx809-1) 1.65 V
Start Threshold (UCCx809-2) 14.0 15.6 V
UVLO Hysteresis (UCCx809-2) 6.2 V
Voltage Reference Section
Output Voltage IREF = 0mA 4.75 5 5.25 V
Line Regulation VDD = 10V to 15V 2 mV
Load Regulation IREF = 0mA to 5mA 2 mV
Comparator Section
IFB Output Off –100 nA
Comparator Threshold 0.9 0.95 1 V
OUT Propagation Delay (No Load) VFB = 0.8V to 1.2V at TR= 10ns 50 100 ns
SOIC-8, DIL-8 (Top View)
D, N and J Packages
ABSOLUTE MAXIMUM RATINGS*
VDD...........................................19V
IVDD..........................................25mA
IOUT (tpw < 1µs and Duty Cycle < 10%)........–0.4A to 0.8A
RT1, RT2, SS ......................–0.3V to REF + 0.3V
IREF.........................................–15mA
Storage Temperature ...................–65°C to +150°C
Junction Temperature...................–55°C to +150°C
Lead Temperature (Soldering, 10 sec.).............+300°C
* Values beyond which damage may occur.
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
UCC 809 –
UVLO OPTION
PACKAGE
TEMPERATURE RANGE
ORDERING INFORMATION
FB
SS
RT1
RT2
REF
VDD
OUT
GND
8
7
6
5
1
2
3
4
TSSOP-8 (Top View)
PW Package
FB
2
1
4
3
7
8
5
6
SS
RT1
RT2
REF
VDD
OUT
GND
MSOP-8 (Top View)
P Package
3
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
PIN DESCRIPTIONS
FB: This pin is the summing node for current sense
feedback, voltage sense feedback (by optocoupler) and
slope compensation. Slope compensation is derived
from the rising voltage at the timing capacitor and can be
buffered with an external small signal NPN transistor.
External high frequency filter capacitance applied from
this node to GND is discharged by an internal 250Won
resistance NMOS FET during PWM off time and offers
effective leading edge blanking set by the RC time
constant of the feedback resistance from current sense
resistor to FB input and the high frequency filter capacitor
capacitance at this node to GND.
GND: Reference ground and power ground for all
functions.
OUT: This pin is the high current power driver output. A
minimum series gate resistor of 3.9Wis recommended to
limit the gate drive current when operating with high bias
voltages.
REF: The internal 5V reference output. This reference is
buffered and is available on the REF pin. REF should be
bypassed with a 0.47mF ceramic capacitor.
RT1: This pin connects to timing resistor RT1 and
controls the positive ramp time of the internal oscillator
(Tr = 0.74 ·(CT+ 27pF) ·RT1). The positive threshold of
the internal oscillator is sensed through inactive timing
resistor RT2 which connects to pin RT2 and timing
capacitor CT.
RT2: This pin connects to timing resistor RT2 and
controls the negative ramp time of the internal oscillator
(Tf = 0.74 ·(CT+ 27pF) ·RT2). The negative threshold
of the internal oscillator is sensed through inactive timing
resistor RT1 which connects to pin RT1 and timing
capacitor CT.
SS: This pin serves two functions. The soft start timing
capacitor connects to SS and is charged by an internal
6µA current source. Under normal soft start SS is
discharged to at least 0.4V and then ramps positive to 1V
during which time the output driver is held low. As SS
charges from 1V to 2V soft start is implemented by an
increasing output duty cycle. If SS is taken below 0.5V,
the output driver is inhibited and held low. The user
accessible 5V voltage reference also goes low and IVDD
< 100mA.
VDD: The power input connection for this device. This
pin is shunt regulated at 17.5V which is sufficiently below
the voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1mF ceramic capacitor.
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, CVREF = 0.47 mF, VDD = 12V. TA=T
J.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Soft Start Section
ISS VDD = 16V, VSS = 0V; –40°Cto+85°C –4.9 –7.0 –9.1 mA
VDD = 16V, VSS = 0V; <–40°C; >+85°C –4.0 –7.0 –10.0 mA
VSS Low VDD = 7.5V, ISS = 200mA 0.2 V
Shutdown Threshold 0.44 0.48 0.52 V
Oscillator Section
Frequency RT1 = 10k, RT2 = 4.32k, CT = 820pF 90 100 110 kHz
Frequency Change with Voltage VDD = 10V to 15V 0.1 %/V
CTPeak Voltage 3.33 V
CTValley Voltage 1.67 V
CTPeak to Peak Voltage 1.54 1.67 1.80 V
Output Section
Output VSAT Low IOUT = 80mA (dc) 0.8 1.5 V
Output VSAT High IOUT = –40mA (dc), VDD – OUT 0.8 1.5 V
Output Low Voltage During UVLO IOUT = 20mA (dc) 1.5 V
Minimum Duty Cycle VFB =2V 0 %
Maximum Duty Cycle 70 %
Rise Time COUT = 1nF 35 ns
Fall Time COUT = 1nF 18 ns
Note 1. Ensured by design. Not 100% production tested.
4
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
UDG-99179
T1
80µH
5:1
C10
0.22 µF
R9
2K
3W
R13
1.1K
R11
680
Q3
IRF640
D3
SF24
Q2
2N2907A
D4
1N5240
8
7
6
5
4
3
2
1
UCC3809
U1
FB REF
SS
RT1
RT2
VDD
OUT
GND
C8
1µF
C9
0.1 µF
C7
0.47 µF
TP1
R5
470
R20
5.62K
C22
0.1 µF
Q4
2N2222A
R18
3.01K
C6
330pF
D1
5231B D2
1N5245
R7
15K
R6
1K
R8
0.15
3W
R4
6.19K
R3
12.1K
C5
1nF
C4
0.01 µF
Q1
2N2222A
R2
1.1K
ON/OFF
–VIN
C3
1µF
+VIN
C2
150 µF
C1
150 µF
R12
27K
R15
10K
C14
470pF
R16
12.1K
1%
U4
TL431
H11AV1
U3
2
1
4
5R17
12.1K
1%
C13
0.1 µF
C15
0.015 µF
R19
5.1K
3W U2
MBR2535CTL
13
2
C16
330 µF
6.3V
C17
330 µF
6.3V
C18
330 µF
6.3V
C19
330 µF
6.3V
R14
750
+V
OUT
–V
OUT
R1
5.1k
R10
10
PGND1
PGND1
APPLICATION INFORMATION
Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V to
-72V, Vout = +5V, Iout = 0A to 10A
5
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
The Typical Application Diagram shows an isolated
flyback converter utilizing the UCC3809. Note that the
capacitors CREF and CVDD are local decoupling capaci-
tors for the reference and IC input voltage, respectively.
Both capacitors should be low ESR and ESL ceramic,
placed as close to the IC pins as possible, and returned
directly to the ground pin of the chip for best stability.
REF provides the internal bias to many of the IC func-
tions and CREF should be at least 0.47µF to prevent REF
from drooping.
FB Pin
The basic premise of the UCC3809 is that the voltage
sense feedback signal originates from an optocoupler
that is modulated by an external error amplifier located
on the secondary side. This signal is summed with the
current sense signal and any slope compensation at the
FB pin and compared to a 1V threshold, as shown in the
Typical Application Diagram. Crossing this 1V threshold
resets the PWM latch and modulates the output driver
on-time much like the current sense comparator used in
the UC3842. In the absence of a FB signal, the output
will follow the programmed maximum on-time of the os-
cillator.
When adding slope compensation, it is important to use
a small capacitor to AC couple the oscillator waveform
before summing this signal into the FB pin. By correctly
selecting the emitter resistor of the optocoupler, the volt-
age sense signal can force the FB node to exceed the
1V threshold when the output that is being compared ex-
ceeds a desired level. Doing so drives the UCC3809 to
zero percent duty cycle.
Oscillator
The following equation sets the oscillator frequency:
()
()
[]FCTpFRTRT
OSC =•+ •+ −
074 27 1 2 1
.
()
DRTCTpFF
MAX OS C
=•• + •074 1 27.
Referring to Figure 2 and the waveforms in Figure 3,
when Q1is on, CT charges via the RDS(on) of Q1 and
RT1. During this charging process, the voltage of CT is
sensed through RT2. The S input of the oscillator latch,
S(OSC), is level sensitive, so crossing the upper thresh-
old (set at 2/3 VREF or 3.33V for a typical 5.0V refer-
ence) sets the Q output (CLK signal) of the oscillator
latch high. A high CLK signal results in turning off Q1 and
turning on Q2. CT now discharges through RT2 and the
RDS(on) of Q2. CT discharges from 3.33V to the lower
threshold (set at 1/3 VREF or 1.67V for a typical 5.0V
reference) sensed through RT1. The R input to the oscil-
lator latch, R(OSC), is also level sensitive and resets the
CLK signal low when CT crosses the 1.67V threshold,
turning off Q2 and turning on Q1, initiating another charg-
ing cycle.
Figure 3 shows the waveforms associated with the oscil-
lator latch and the PWM latch (shown in the Typical Ap-
plication Diagram). A high CLK signal not only initiates a
discharge cycle for CT, it also turns on the internal NMOS
FET on the FB pin causing any external capacitance
used for leading edge blanking connected to this pin to
be discharged to ground. By discharging any external
capacitor completely to ground during the external
switch’s off-time, the noise immunity of the converter is
enhanced allowing the user to design in smaller RC com-
ponents for leading edge blanking. A high CLK signal
also sets the level sensitive S input of the PWM latch,
S(PWM), high, resulting in a high output, Q(PWM), as
shown in Figure 3. This Q(PWM) signal will remain high
until a reset signal, R(PWM) is received. A high R(PWM)
signal results from the FB signal crossing the 1V thresh-
old, or during soft start or if the SS pin is disabled.
Assuming the UVLO threshold is satisfied, the OUT sig-
nal of the IC will be high as long as Q(PWM) is high and
S(PWM), also referred to as CLK, is low. The OUT sig-
nal will be dominated by the FB signal as long as the FB
signal trips the 1V threshold while CLK is low. If the FB
signal does not cross the 1V threshold while CLK is low,
the OUT signal will be dominated by the maximum duty
cycle programmed by the user. Figure 3 illustrates the
various waveforms for a design set up for a maximum
duty cycle of 70%.
APPLICATION INFORMATION (cont.)
+
–
+
–
SQ
R
Q2
Q1
3
4
RT2
CT
RT1
VREF
3.33V
1.67V
CL
K
OSC
O S C ILLATO R
LATC H
Figure 2. UCC3809 oscillator.
UDG-97195
6
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
The recommended value for CT is 1nF for frequencies in
the 100 kHz or less range and smaller CT for higher fre-
quencies. The minimum recommended values of RT1
and RT2 are 10kΩand 4.32kΩ, respectively. Using these
values maintains a ratio of at least 20:1 between the
RDS(on) of the internal FETs and the external timing resis-
tors, resulting in minimal change in frequency over tem-
perature. Because of the oscillator's susceptibility to
capacitive coupling, examine the oscillator frequency by
looking at the common RT1-RT2-CT node on the circuit
board as opposed to looking at pins 3 and 4 directly. For
good noise immunity, RT1 and RT2 should be placed as
close to pins 3 and 4 of the IC as possible. CT should be
returned directly to the ground pin of the IC with minimal
stray inductance and capacitance.
10
100
1000
100 1000 10000
CT [pF]
FREQUENCY [kHz]
Figure 4. Oscillator frequency vs. CT(RT1 = 10k,
RT2 = 4.32k)
CT
S(OSC)
R(OSC)
Q(OSC)=CLK
=S(PWM)
FB
R(PWM)
Q(PWM)
OUT
CT
CHARGING
CT
DIS CHARGING
3.33V
1.67V
1V
70%
ON
30%
OFF
F B S IG NAL DO MINANT MAX. DUTY C YC LE DO MINANT
Figure 3. Waveforms associated with the oscillator latch and the PWM latch.
APPLICATION INFORMATION (cont.)
UDG-99037
7
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
3
4
UCC3809
OS C ILLATO R
RT2
CT
RT1
1k
2N2222A
424
SYNC
PULSE
OPTION I
3
4
UCC3809
OS C ILLATO R
RT2
CT
RT1
424
SYNC
PULSE
0.1µF
2N2222A
24
+5V
OPTION II
Figure 5. UCC3809 synchronization options.
UDG-99006
Synchronization
Both of the synchronization schemes shown in Figure 5
can be successfully implemented with the internal oscilla-
tor of the UCC3809. Both schemes allow access to the
timing ramp needed for slope compensation and have
minimal impact on the programmed maximum duty cycle.
In the absence of a sync pulse, the PWM controller will
run independently at the frequency set by RT1, RT2, and
CT. This free running frequency must be approximately
15 to 20% lower than the sync pulse frequency to insure
the free running oscillator does not cross the comparator
threshold before the desired sync pulse.
Option I uses the synchronization pulse to pull pin 3 low,
triggering the internal 1.67V comparator to reset the RS
latch and initiate a charging cycle. The valley voltage of
the CT waveform is higher when synchronized using this
configuration, decreasing the ramp charge and discharge
times, thereby increasing the operating frequency; other-
wise the overall shape of the CT voltage waveform is un-
changed.
Option II uses the synchronization pulse to superimpose
the sync voltage onto the peak of the CT waveform. This
triggers the internal 3.33V comparator, initiating a dis-
charge cycle. The sync pulse is summed with the free
running oscillator waveform at the CT node, resulting in a
spike on top of the CT peak voltage.
ADDITIONAL INFORMATION
Please refer to the following Unitrode application topics
for additional information.
[1] Application Note U-165, Design Review: Isolated 50W
Flyback Converter with the UCC3809 Primary Side Con-
troller by Lisa Dinwoodie.
[2] Design Note DN-89, Comparing the UC3842,
UCC3802, and UCC3809 Primary Side PWM Controllers
by Lisa Dinwoodie.
APPLICATION INFORMATION (cont.)
8
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
0
20
40
60
80
100
120
140
160
180
-50 -25 0 25 50 75 100 125
Temperature (deg C)
Idd standby (uA)
UCC2809-2
UCC2809-1
TYPICAL CHARACTERISTICS CURVES
Figure 6. IDD (standby) vs. temperature.
0
2
4
6
8
10
12
14
16
-50 -25 0 25 50 75 100 125
Temperature (deg C)
UVLO (V)
2809-2 UVLO on
2809-1UVLO on
UVLO off
Figure 7. UVLO vs. temperature.
90
95
100
105
110
-50 -25 0 25 50 75 100 125
temperature (deg C)
Oscillator frequency (kHz)
Figure 8. Oscillator frequency vs. temperature.
REV. B 11/04
Added Ivdd Stand-by Current specifications in the Electrical Characteristics table.
Modified Ivdd Starting specifications in the Electrical Characteristics table.
Added Typical Characteristics Curves for Idd(Standby), UVLO thresholds, and Oscillator Frequency.
REVISION HISTORY
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC2809D-1 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809D-1G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809D-2 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809D-2G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809DTR-1G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809DTR-2G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC2809P-1 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809P-1G4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809P-2 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809P-2G4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809PTR-1 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809PTR-1G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809PTR-2 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809PTR-2G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC2809PW-1 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC2809PW-1G4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2809PW-2 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2809PW-2G4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2809PWTR-1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2809PWTR-1G4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809D-1 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809D-1G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809D-2 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809D-2G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809DTR-1G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809DTR-2G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC3809N-1 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3809N-1G4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3809N-2 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3809N-2G4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3809P-1 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC3809P-1G4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809P-2 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809P-2G4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809PTR-1 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809PTR-1G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809PTR-2 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809PTR-2G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
UCC3809PW-1 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809PW-1G4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809PW-2 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809PW-2G4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809PWTR-1 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3809PWTR-1G4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC2809DTR-1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC2809DTR-2 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC2809PTR-1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC2809PTR-2 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC2809PWTR-1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
UCC3809DTR-1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC3809DTR-2 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC3809PTR-1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC3809PTR-2 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC3809PWTR-1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2809DTR-1 SOIC D 8 2500 340.5 338.1 20.6
UCC2809DTR-2 SOIC D 8 2500 340.5 338.1 20.6
UCC2809PTR-1 VSSOP DGK 8 2500 367.0 367.0 35.0
UCC2809PTR-2 VSSOP DGK 8 2500 367.0 367.0 35.0
UCC2809PWTR-1 TSSOP PW 8 2000 367.0 367.0 35.0
UCC3809DTR-1 SOIC D 8 2500 340.5 338.1 20.6
UCC3809DTR-2 SOIC D 8 2500 340.5 338.1 20.6
UCC3809PTR-1 VSSOP DGK 8 2500 367.0 367.0 35.0
UCC3809PTR-2 VSSOP DGK 8 2500 367.0 367.0 35.0
UCC3809PWTR-1 TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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