1. General description
The NX3L4051-Q100 is a low-ohmic 8-channel analog switch, suitable for use as an
analog or digital multiplexer/demultiplexer. The NX3L4051-Q100 has three digital select
inputs (S1 to S3), eight independent input s/outputs (Y0 to Y7) and a common input/output
(Z). All eight switches share an enable input (E ). A HIGH on E causes all switches into the
high impedance OFF-state, independent of Sn.
Schmitt trigger action at the digit al inputs make s the circuit tolerant to slower in put rise and
fall times. Low threshold digital inputs allows this device to be driven by 1.8 V logic levels
in 3.3 V applications without significant increase in supply current ICC. This makes it
possible for the NX3L4051-Q100 to switch 4.3 V signals with a 1.8 V digital controller,
eliminating the need for logic level translation. The NX3L4051-Q100 allows signals with
amplitude up to VCC to be transmitted from Z to Yn or from Yn to Z. The low ON resistance
(0.5 ) and flatness (0.13 ), ensures minimal attenuation and distortion of transmitted
signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
1.7 (typical) at VCC =1.4V
1.0 (typical) at VCC =1.65V
0.6 (typical) at VCC =2.3V
0.5 (typical) at VCC =2.7V
0.5 (typical) at VCC =4.3V
Break-before-make switching
High noise immunity
ESD protection:
MIL-STD-883, method 3015 Class 3A exceeds 7500 V
HBM JESD22-A114F Class 3A exceeds 7500 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
CDM AEC-Q100-011 revision B exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 8000 V for switch ports
CMOS low-power consumption
NX3L4051-Q100
Single low-ohmic 8-channel analog switch
Rev. 1 — 7 August 2012 Product data sheet
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 2 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
Latch-up performance exceeds 100 mA per JESD 78B Class II Level A
1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
3. Applications
Cell phone
PDA
Portable media player
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
5. Marking
Table 1. Ordering information
Type number Package
Temperature r ange Name Description Version
NX3L4051HR-Q100 40 C to +125 C HXQFN16 plastic thermal enhanced extremely thin quad flat
package; no leads; 16 terminals;
body 3 30.5 mm
SOT1039-2
NX3L4051PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Table 2. Mark ing codes
Type number Marking code
NX3L4051HR-Q100 M41
NX3L4051PW-Q100 X3L4051
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Product data sheet Rev. 1 — 7 August 2012 3 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
6. Functional diagram
Pin numbers are shown for TSSOP16 package only. Pin numbers are shown for TSSOP16 package only.
Fig 1. Logic symbol Fig 2. Functional diagram
001aal657
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Z
E
S2
11
10
634
2
5
1
12
15
14
13
S1
S3 9
001aal658
11
16
V
CC
13 Y0
S1
1-OF-8
DECODER
LOGIC
9
S3
14 Y1
10
S2
6
8
GND
E
15 Y2
12 Y3
1Y4
5Y5
2Y6
4Y7
3Z
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Product data sheet Rev. 1 — 7 August 2012 4 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 3. Pin configu ration SOT1039-2 (HXQFN16) Fig 4. Pin configu ration SOT403-1 (TSSOP16)
1
2
3
4
Z
Y7
Y5 NX3L4051-Q100
E
12
11
10
9
Y1
Y0
Y3
S1
16
15
14
13
Y6
Y4
VCC
Y2
5
6
7
8
n.c.
GND
S3
S2
aaa-003471
Transparent top view
terminal 1
index area
NX3L4051-Q100
Y4 VCC
Y6 Y2
ZY1
Y7 Y0
Y5 Y3
ES1
n.c. S2
GND S3
aaa-003472
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 3. Pin description
Symbol Pin Description
SOT1039-2 SOT403-1
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 11, 12, 13, 10, 15, 3, 16, 2 13, 14, 15, 12, 1, 5, 2, 4 independent input or output
Z 1 3 independent output or input
E4 6 enable input (active LOW)
n.c. 5 7 not connected
GND 6 8 ground (0 V)
S1, S2, S3 9, 8, 7 11, 10, 9 select input
VCC 14 16 supply voltage
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Product data sheet Rev. 1 — 7 August 2012 5 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
8. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
9. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3] For HXQFN16 package: above 135 C the value of Ptot derates linearly with 16.9 mW/K.
[4] For TSSOP16 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 4. Function table[1]
Input Channel ON
ES3 S2 S1
LLLLY0=Z
LLLHY1=Z
LLHLY2=Z
LLHHY3=Z
LHLLY4=Z
LHLHY5=Z
LHHLY6=Z
LHHHY7=Z
HXXXswitches off
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
VIinput voltage Sn and E [1] 0.5 +4.6 V
VSW switch voltage [2] 0.5 VCC + 0.5 V
IIK input clamping current VI<0.5 V 50 - mA
ISK switch clamping current VI<0.5 V or VI>V
CC + 0.5 V - 50 mA
ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V;
source or sink current -350 mA
VSW >0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-500 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C
HXQFN16 [3] -250mW
TSSOP16 [4] -500mW
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Product data sheet Rev. 1 — 7 August 2012 6 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
10. Recommended operating conditions
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current flows from terminal Yn. In this case, there is no limit for
the voltage drop across the switch.
11. Static characteristics
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.4 4.3 V
VIinput voltage Sn and E 04.3V
VSW switch voltage [1] 0V
CC V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate Sn and E; VCC = 1.4 V to 4.3 V - 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ Max Min Max
(85 C) Max
(125 C)
VIH HIGH-level
input voltage VCC = 1.4 V to 1.6 V 0.9 - - 0.9 - - V
VCC = 1.65 V to 1.95 V 0.9 - - 0.9 - - V
VCC = 2.3 V to 2.7 V 1.1 - - 1.1 - - V
VCC = 2.7 V to 3.6 V 1.3 - - 1.3 - - V
VCC = 3.6 V to 4.3 V 1.4 - - 1.4 - - V
VIL LOW-level
input voltage VCC = 1.4 V to 1.6 V - - 0.3 - 0.3 0.3 V
VCC = 1.65 V to 1.95 V - - 0.4 - 0.4 0.3 V
VCC = 2.3 V to 2.7 V - - 0.4 - 0.4 0.4 V
VCC = 2.7 V to 3.6 V - - 0.5 - 0.5 0.5 V
VCC = 3.6 V to 4.3 V - - 0.6 - 0.6 0.6 V
IIinput leakage
current Sn and E;
VI=GNDto4.3V;
VCC = 1.4 V to 4.3 V
--- -0.5 1A
IS(OFF) OFF-state
leakage
current
Yn ports; see Figure 5
VCC = 1.4 V to 3.6 V - - 5-50 500 nA
VCC = 3.6 V to 4.3 V - - 10 - 50 500 nA
IS(ON) ON-state
leakage
current
Z port;
VCC = 1.4 V to 3.6 V;
see Figure 6
VCC = 1.4 V to 3.6 V - - 20 - 200 2000 nA
VCC = 3.6 V to 4.3 V - - 40 - 200 2000 nA
ICC supply current VI=V
CC or GND;
VSW =GNDorV
CC
VCC = 3.6 V - - 100 - 500 5000 nA
VCC = 4.3 V - - 150 - 800 6000 nA
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Product data sheet Rev. 1 — 7 August 2012 7 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
11.1 Test circuits
ICC additional
supply current VSW =GNDorV
CC
VI= 2.6 V; VCC =4.3V - 2.0 4.0 - 7 7 A
VI= 2.6 V; VCC = 3.6 V - 0.35 0.7 - 1 1 A
VI= 1.8 V; VCC = 4.3 V - 7.0 10.0 - 15 15 A
VI= 1.8 V; VCC =3.6V - 2.5 4.0 - 5 5 A
VI= 1.8 V; VCC = 2.5 V - 50 200 - 300 500 nA
CIinput
capacitance Sn and E -1.0----pF
CS(OFF) OFF-state
capacitance -35----pF
CS(ON) ON-state
capacitance -350----pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ Max Min Max
(85 C) Max
(125 C)
VI=0.3VorV
CC 0.3 V; VO=V
CC 0.3 V or 0.3 V.
Fig 5. Test circuit for measuring OFF-state leakage current
I
S
001aal661
V
IH
VO
GND
Sn
E
Z
V
IL
or V
IH
V
CC
Yn
VI
VI=0.3VorV
CC 0.3 V; VO=V
CC 0.3 V or 0.3 V.
Fig 6. Test circuit for measuring ON-state leakage current
001aal662
VIL
VO
GND
Sn
E
Z
VIL or VIH
VCC
Yn
VI
IS
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Product data sheet Rev. 1 — 7 August 2012 8 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
11.2 ON resistance
[1] For NX3L4051PW-Q100 (TSSOP16 package), all ON resistance values are up to 0.05 higher.
[2] Typical values are measured at Tamb = 25 C.
[3] Measured at identical VCC, temperature and input voltage.
[4] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
Table 8. ON resistance[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[2] Max Min Max
RON(peak) ON resistance
(peak) VI=GNDtoV
CC;
ISW = 100 mA; see Figure 7
VCC = 1.4 V - 1.7 3.7 - 4.1
VCC = 1.65 V - 1.0 1.6 - 1.7
VCC = 2.3 V - 0.6 0.8 - 0.9
VCC = 2.7 V - 0.5 0.75 - 0.9
VCC = 4.3 V - 0.5 0.75 - 0.9
RON ON resistance
mismatch
between
channels
VI=GNDtoV
CC;
ISW = 100 mA [3]
VCC =1.4V; V
SW = 0.4 V - 0.18 0.30 - 0.30
VCC =1.65V; V
SW = 0.5 V - 0.18 0.20 - 0.30
VCC =2.3V; V
SW = 0.7 V - 0.07 0.10 - 0.13
VCC =2.7V; V
SW = 0.8 V - 0.07 0.10 - 0.13
VCC =4.3V; V
SW = 0.8 V - 0.07 0.10 - 0.13
RON(flat) ON resistance
(flatness) VI=GNDtoV
CC;
ISW = 100 mA [4]
VCC = 1.4 V - 1.0 3.3 - 3.6
VCC = 1.65 V - 0.5 1.2 - 1.3
VCC = 2.3 V - 0.15 0.3 - 0.35
VCC = 2.7 V - 0.13 0.3 - 0.35
VCC = 4.3 V - 0.2 0.4 - 0.45
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Product data sheet Rev. 1 — 7 August 2012 9 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
11.3 ON resistance test circuit and graphs
RON =V
SW / ISW.(1)V
CC =1.5V.
(2) VCC =1.8V.
(3) VCC =2.5V.
(4) VCC =2.7V.
(5) VCC =3.3V.
(6) VCC =4.3V.
Measured at Tamb =25C.
Fig 7. Test circuit for measuring ON resistance Fig 8. Typical ON resistance as a function of input
voltage
V
001aal663
V
IL
GND
Sn
E
Z
V
IL
or V
IH
V
CC
VSW
Yn
VIISW
VI (V)
054312
001aag564
0.8
0.4
1.2
1.6
RON
(Ω)
0
(1)
(2)
(5) (6)
(4)
(3)
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Product data sheet Rev. 1 — 7 August 2012 10 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 9. ON resistance as a function of input voltage;
VCC =1.5V Fig 10. ON resistance as a function of input voltage;
VCC =1.8V
001aag565
VI (V)
0321
0.8
0.4
1.2
1.6
RON
(Ω)
0
(1)
(2)
(3)
(4)
001aag566
VI (V)
0321
0.4
0.6
0.2
0.8
1.0
RON
(Ω)
0
(1)
(2)
(3)
(4)
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 11. ON resistance as a function of input voltage;
VCC =2.5V Fig 12. ON resistance as a function of input voltage;
VCC =2.7V
001aag567
VI (V)
0321
0.4
0.6
0.2
0.8
1.0
RON
(Ω)
0
(1)
(2)
(3)
(4)
001aag568
VI (V)
0321
0.4
0.6
0.2
0.8
1.0
RON
(Ω)
0
(1)
(2)
(3)
(4)
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Product data sheet Rev. 1 — 7 August 2012 11 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
12. Dynamic characteristics
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 13. ON resistance as a function of input voltage;
VCC =3.3V Fig 14. ON resistance as a function of input voltage;
VCC =4.3V
VI (V)
04312
001aag569
0.4
0.6
0.2
0.8
1.0
RON
(Ω)
0
(1)
(2)
(3)
(4)
VI (V)
054231
001aaj896
0.4
0.6
0.2
0.8
1.0
RON
(Ω)
0
(1)
(2)
(3)
(4)
Table 9. Dynam ic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
ten enable time E, Sn to Z or Yn;
see Figure 15
VCC = 1.4 V to 1.6 V - 45 100 - 120 125 ns
VCC = 1.65 V to 1.95 V - 32 75 - 85 95 ns
VCC = 2.3 V to 2.7 V - 21 50 - 55 60 ns
VCC = 2.7 V to 3.6 V - 19 45 - 45 50 ns
VCC = 3.6 V to 4.3 V - 19 45 - 45 50 ns
tdis disable time E, Sn to Z or Yn;
see Figure 15
VCC = 1.4 V to 1.6 V - 25 80 - 90 105 ns
VCC = 1.65 V to 1.95 V - 15 65 - 70 75 ns
VCC = 2.3 V to 2.7 V - 9 30 - 35 40 ns
VCC = 2.7 V to 3.6 V - 8 25 - 30 35 ns
VCC = 3.6 V to 4.3 V - 8 25 - 30 35 ns
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Product data sheet Rev. 1 — 7 August 2012 12 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
[1] Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2] Break-before-make guaranteed by design.
12.1 Waveform and test circuits
tb-m break-before-make
time see Figure 16 [2]
VCC = 1.4 V to 1.6 V - 19 - 9 - - ns
VCC = 1.65 V to 1.95 V - 17 - 7 - - ns
VCC = 2.3 V to 2.7 V - 12 - 4 - - ns
VCC = 2.7 V to 3.6 V - 10 - 3 - - ns
VCC = 3.6 V to 4.3 V - 9 - 2 - - ns
Table 9. Dynam ic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 15. Enable and disable times
Table 10. Measurement points
Supply voltage Input Output
VCC VMVX
1.4 V to 4.3 V 0.5VCC 0.9VOH
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Product data sheet Rev. 1 — 7 August 2012 13 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
a. Test circuit
b. Input and output measurement points
Fig 16. Test circuit for measuring break-before-make timing
VVO
001aal665
CL
RL
GND
VEXT = 1.5 V
GVI
Sn
E
Z
VCC
VIL or VIH
VIL
Yn
001aag572
VI
tb-m
VO
0.9VO
0.9VO
0.5VI
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
VI may be connected to Sn or E.
Fig 17. Test circuit for measuring switching times
VVO
001aal666
CL
RL
GND
VEXT = 1.5 V
GVI
Sn
E
Z
VCC
VIL or VIH
VIL
Yn
Table 11. Test data
Supply voltage Input Load
VCC VItr, tfCLRL
1.4 V to 4.3 V VCC 2.5ns 35pF 50
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Product data sheet Rev. 1 — 7 August 2012 14 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
12.2 Additional dynamic characteristics
[1] fi is biased at 0.5VCC.
12.3 Test circuits
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are refe renced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specifie d ) ; tr = tf
2.5 ns; Tamb = 25
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic
distortion fi=20Hzto20 kHz; R
L=32; see Figure 18 [1]
VCC =1.4V; V
I= 1 V (p-p) - 0.15 - %
VCC =1.65V; V
I= 1.2 V (p-p) - 0.10 - %
VCC =2.3V; V
I= 1.5 V (p-p) - 0.02 - %
VCC =2.7V; V
I= 2 V (p-p) - 0.02 - %
VCC =4.3V; V
I= 2 V (p-p) - 0.02 - %
f(3dB) 3 dB frequency
response RL=50; see Figure 19 [1]
VCC = 1.4 V to 4.3 V - 15 - MHz
iso isolation (OFF-state) fi= 100 kHz; RL=50; see Figure 20 [1]
VCC = 1.4 V to 4.3 V - 90 - dB
Vct crosstalk voltage between digital inputs and switch;
fi= 1 MHz; CL= 50 pF; RL=50; see Figure 21
VCC = 1.4 V to 3.6 V - 0.2 - V
VCC = 3.6 V to 4.3 V - 0.3 - V
Xtalk crosstalk between switches;
fi= 100 kHz; RL=50;seeFigure 22 [1]
VCC = 1.4 V to 4.3 V - 90 - dB
Qinj charge injection fi= 1 MHz; CL= 0.1 nF; RL=1 M; Vgen =0V;
Rgen =0; see Figure 23
VCC = 1.5 V - 3 - pC
VCC = 1.8 V - 4 - pC
VCC =2.5V - 6 - pC
VCC =3.3V - 9 - pC
VCC =4.3V - 15 - pC
Fig 18. Test circuit for measuring total harmonic distorti on
fiD
001aal667
RL
GND
Sn
E
Z
VCC 0.5VCC
VIL
Yn
VIL or VIH
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Product data sheet Rev. 1 — 7 August 2012 15 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.
Fig 19. Test circuit for measu ring the frequency response wh en channel is in ON-state
fidB
001aal668
RL
GND
Sn
E
Z
VCC 0.5VCC
VIL
Yn
VIL or VIH
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF -state)
fidB
001aal669
RL
GND
Sn
E
Z
VCC
0.5VCC
RL
0.5VCC
VIH
Yn
VIL or VIH
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Product data sheet Rev. 1 — 7 August 2012 16 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
a. Test circuit
b. Input and output pulse definition s
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
001aal670
RL
GND
Sn
E
Z
VCC
0.5VCC
RL
0.5VCC
Yn
VIL or VIH
VVO
CL
Glogic
input
VI
001aal671
logic input
(Sn, E)
VOVct
offoff on
Fig 22. Test circuit for measuring cros stalk between switches
fi
dB
001aal672
RL
GND
Sn
E
Z
V
CC
0.5V
CC
RL
0.5V
CC
V
IH
Yn
Y0
V
IL
or V
IH
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 17 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
a. Test circuit
b. Input and output pulse definition s
Definition: Qinj =VO CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
VI may be connected to Sn or E.
Fig 23. Test circuit for measuring charge injection
V
VO
001aal673
CL
RL
Rgen
GND
Vgen
G
VI
Sn
E
Z
V
CC
V
IL
Yn
001aal674
logic input
(Sn, E)
VOVO
offoff on
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 18 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
13. Package outline
Fig 24. Package outline SOT1039-2 (HXQFN16)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1039-2 - - -- - -
sot1039-2_po
10-07-29
11-03-30
Unit
mm max
nom
min
0.5 0.05
0.00 0.127 3.1
3.0
2.9
1.95
1.85
1.75
3.1
3.0
2.9 0.5 1.5 0.40
0.35
0.30 0.1
A
Dimensions
HXQFN16: plastic thermal enhanced extremely thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.5 mm SOT1039-2
A1b
0.35
0.30
0.25
cDD
hEE
h
1.95
1.85
1.75
ee
1e2
1.5
Lv
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A
c
A1
b
e2
e1
e
e
1/2 e
1/2 e AC B
vCw
terminal 1
index area Dh
Eh
L
5 8
16 13
4
1
9
12
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Product data sheet Rev. 1 — 7 August 2012 19 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
Fig 25. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 20 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
14. Abbreviations
15. Revision history
Table 13. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
PDA Personal Digital Assistant
MIL Military
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
NX3L4051_Q100 v.1 20120807 Product data sheet - -
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 21 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — T his NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
NX3L4051_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 7 August 2012 22 of 23
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors NX3L4051-Q100
Single low-ohmic 8-channel analog switch
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2012
Document identifier: NX 3L40 51 _Q1 00
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Functional description . . . . . . . . . . . . . . . . . . . 5
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
10 Recommended operating conditions. . . . . . . . 6
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
11.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
11.3 ON resistance test circuit and graphs. . . . . . . . 9
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
12.1 Waveform and test circuits . . . . . . . . . . . . . . . 12
12.2 Additional dynamic characteristics . . . . . . . . . 14
12.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17 Contact information. . . . . . . . . . . . . . . . . . . . . 22
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23