16-Bit, 250 kSPS PulSAR® ADC in MSOP
Data Sheet AD7694
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS at 5 V
INL: ±4 LSB max
S/(N + D): 92 dB at 20 kHz
THD: –106 dB at 20 kHz
Pseudo-differential analog input range:
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply operation: 2.7 V or 5 V
Proprietary serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible1
Supply Current: 540 μA at 2.7 V/100 kSPS,
800 μA at 5 V/100 kSPS
Standby current: 1 nA
8-lead MSOP package
Improved second source to LTC1864 and LTC1864L
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7694 is a 16-bit, charge redistribution, successive
approximation, PulSAR analog-to-digital converter (ADC) that
operates from a single power supply, VDD, between 2.7 V to
5.25 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to REF with respect to a ground
sense, IN−. e reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Its power scales linearly with throughput.
The AD7694 is housed in an 8-lead MSOP package with an
operating temperature specified from −40°C to +85°C.
APPLICATION DIAGRAM
AD7694
REF
GND
VDD
IN+
IN–
SCK
SDO
CNV
3-WIRE SPI
INTERFACE
1V TO VDD 2.5V TO 5V
0 TO V
REF
05003-001
Figure 1.
Table 1. MSOP, LFCSP (QFN)/SOT-23, 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo AD7683 AD7685 AD7686
Differential/Unipolar AD7694
Unipolar AD7680
1 Protected by U.S. Patent 6,703,961.
AD7694 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Application Diagram ........................................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications ....................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Application Information ................................................................ 12
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Transfer Functions ..................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice ........................................................... 13
Voltage Reference Input ............................................................ 14
Power Supply ............................................................................... 14
Supplying the ADC from the Reference .................................. 14
Digital Interface .......................................................................... 15
Layout .......................................................................................... 15
Evaluating the AD7694 Performance ...................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
6/14—Rev. A to Rev. B
Added Patent Footnote .................................................................... 1
Changes to Evaluating the AD7694 Performance Section ........ 15
Changes to Ordering Guide .......................................................... 16
5/05—Rev. 0 to Re v. A
Updated Format .................................................................. Universal
Changes to Digital Interface Section ............................................ 14
Changes to Figure 25 ...................................................................... 15
Changes to Evaluating the AD7694’s Performance Section ...... 15
7/04—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet AD7694
SPECIFICATIONS
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 Bits
ANALOG INPUT
Voltage Range
IN+ − IN−
0
V
REF
0
V
REF
V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V
IN− −0.1 +0.1 −0.1 +0.1 V
Leakage Current at 25°C Acquisition phase 1 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 +6 −4 +4 LSB
Transition Noise
REF = VDD = 5 V
0.5
0.5
LSB
Gain Error1, TMIN to TMAX ±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 LSB
THROUGHPUT
Conversion Rate VDD = 4.75 V to 5.25 V 0 250 0 250 kSPS
VDD = 2.7 V to 4.75 V
0
150
0
150
kSPS
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, VREF = 5 V 90 88 92 dB2
f
IN
= 20 kHz, V
REF
= 2.5 V
86
87
dB
Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 dB
Total Harmonic Distortion fIN = 20 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 89 88 92 dB
fIN = 20 kHz, VREF = 2.5 V 86 87 dB
1 See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference.
2 All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. B | Page 3 of 16
AD7694 Data Sheet
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 1 VDD V
Load Current 250 kSPS, VIN+ − VIN− = VREF/2 = 2.5 V 50 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
DIGITAL INPUTS
Logic Levels
VIL VDD = 4.75 V 0.8 V
VDD = 2.7 V 0.45 V
VIH VDD = 5.25 V 3.15 V
VDD = 3.3 V 1.9 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
V
OL
SINK
0.4
V
VOH ISOURCE = −500 µA VDD − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.7 5.25 V
Operating Current
VDD VDD = 5 V, 100 kSPS throughput 0.8 1.2 mA
VDD = 2.7 V, 100 kSPS throughput 540 960 µA
Standby Current1, 2 VDD = 5 V, 25°C 1 50 nA
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VDD or GND, as required.
2 During acquisition phase.
Rev. B | Page 4 of 16
Data Sheet AD7694
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V; TA = −40°C to +85°C, unless otherwise stated.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 µs
Time Between Conversions tCYC 4 µs
SCK Period tSCK 50 ns
SCK Low Time tSCKL 20 ns
SCK High Time tSCKH 20 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO 20 ns
CNV Low to SDO, D15 MSB Valid tEN 60 ns
CNV High to SDO High Impedance tDIS 60 ns
VDD = 2.7 V to 4.75 V; TA = −40°C to +85°C, unless otherwise stated.
Table 5.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 4.66 µs
Time Between Conversions tCYC 6.66 µs
SCK Period
t
SCK
125
ns
SCK Low Time tSCKL 50 ns
SCK High Time tSCKH 50 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO 50 ns
CNV Low to SDO, D15 MSB Valid
t
EN
120
ns
CNV High to SDO High Impedance tDIS 120 ns
Rev. B | Page 5 of 16
AD7694 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1 GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +7 V
Digital Inputs to GND
−0.3 V to VDD + 0.3 V
Digital Outputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-8)
θJC Thermal Impedance 44°C/W (MSOP-8)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
05003-002
500µA IOL
500µAIOH
1.4V
TO SDO CL
50pF
Figure 2. Load Circuit for Digital Interface Timing
VIL
V
IH
V
OH
V
OL
V
OL
V
OH
t
DELAY
t
DELAY
05003-003
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
Rev. B | Page 6 of 16
Data Sheet AD7694
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05003-004
REF 1
IN+ 2
IN– 3
GND 4
VDD
8
SCK
7
SDO
6
CNV
5
AD7694
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI Reference Input Voltage. The REF range is from 1 V to VDD. It is referred to the GND pin. This pin should be
decoupled closely to the pin with a ceramic capacitor of a few µF.
2 IN+ AI Analog Input. It is referred to in IN−. The voltage range, that is, the difference between IN+ and IN−, which
is 0 V to VREF.
3 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
4 GND P Power Supply Ground.
5 CNV DI Convert Input. On its leading edge, it initiates the conversions. It enables the SDO pin when low.
6 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
7 SCK DI Serial Data Clock Input. When CNV is low, the conversion result is shifted out by this clock.
8 VDD P Power Supply.
1AI = analog input; DI = digital input; DO = digital output; and P = power.
Rev. B | Page 7 of 16
AD7694 Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale to positive full scale.
The point used as negative full scale occurs ½ LSB before the
first code transition. Positive full scale is defined as a level
1 ½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(see Figure 19).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1 ½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N + D) by
ENOB = (S/[N + D]dB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N + D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
the time between the rising edge of the CNV input and the time
the input signal is held for conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function is applied.
Rev. B | Page 8 of 16
Data Sheet AD7694
TYPICAL PERFORMANCE CHARACTERISTICS
4
–4
–3
–2
–1
0
1
2
3
03276816384 49152 65536
05003-005
CODE
INL (LSB)
POSITIVE INL = +0.68 LSB
NEGATIVE INL = –1.14 LSB
Figure 5. Integral Nonlinearity vs. Code
12000
10000
8000
6000
4000
2000
024E0 24E1 24E2 24E3 24E4 24E5 24E6 24E7 24E8
05003-006
CODE IN HEX
COUNTS
0 0 1 0 0
12500
10003
0
108568 VDD = REF = 5V
Figure 6. Histogram of a DC Input at the Code Center
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
0 20 40 60 80 100 120
05003-007
FREQUENCY (kHz)
AMPLITUDE (dB OF FULL SCALE)
16384 POINT FFT
VDD = REF = 5V
f
S = 250kSPS
f
IN = 20.43kHz
SNR = 92.5dB
THD = –109.9dB
SFDR = –111.0dB
Figure 7. FFT Plot
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 3276816384 49152 65536
05003-008
CODE
DNL (LSB)
POSITIVE DNL = +0.59 LSB
NEGATIVE DNL = –0.56 LSB
Figure 8. Differential Nonlinearity vs. Code
8000
7000
6000
5000
4000
3000
2000
1000
0
251B 251C 251D 251E 251F 2520 2521 2522 2523 2524 2525 2526
05003-009
CODE IN HEX
COUNTS
VDD = REF = 2.5V
0 0 27 2808 50 100
28148
65487
2133
32418
Figure 9. Histogram of a DC Input at the Code Center
0
–180
–160
–140
–120
–100
–80
–60
–40
–20
0 10 20 30 40 50 60 70
05003-010
FREQUENCY (kHz)
AMPLITUDE (dB OF FULL SCALE)
16384 POINT FFT
VDD = REF = 2.5V
f
S = 150kSPS
f
IN = 20.43kHz
SNR = 88.5dB
THD = –102.7dB
SFDR = –105.1dB
Figure 10. FFT Plot
Rev. B | Page 9 of 16
AD7694 Data Sheet
100
95
90
85
80
17
16
15
14
13
2.5 3.0 3.5 4.0 4.5 5.0
05003-011
REFERENCE VOLTAGE (V)
SNR, S/[N+D] (dB)
ENOB (Bits)
SNR
S/[N+D] ENOB
Figure 11. SNR, S/(N + D), and ENOB vs. Reference Voltage
100
95
90
85
80
75
700 50 100 150 200
05003-012
FREQUENCY (kHz)
S/[N+D] (dB)
V
REF
= 2.5V, –1dB
V
REF
= 5V, –10dB
V
REF
= 5V, –1dB
Figure 12. S/[N + D] vs. Frequency
–80
–115
–110
–105
–100
–95
–90
–85
0 40 80 120 160 200
05003-013
FREQUENCY (kHz)
THD (dB)
V
REF
= 5V, –1dB
V
REF
= 2.5V, –1dB
Figure 13. THD vs. Frequency
1200
1000
800
600
400
200
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
05003-014
SUPPLY (V)
OPERATING CURRENT (µA)
fS = 100kSPS
Figure 14. Operating Current vs. Supply
800
900
400
500
600
700
300
200
100
0
–55 125105
856545
255–15–35
05003-015
TEMPERATURE (°C)
OPERATING CURRENT (µA)
VDD = 5V, f
S
= 100kSPS
VDD = 2.7V, f
S
= 100kSPS
Figure 15. Operating Current vs. Temperature
1000
0
250
500
750
–55 –35 –15 5 25 45 65 85
105 125
05003-016
TEMPERATURE (°C)
POWER-DOWN CURRENT (nA)
Figure 16. Power-Down Current vs. Temperature
Rev. B | Page 10 of 16
Data Sheet AD7694
6
–6
–4
–2
0
2
4
–55 12510585654525
5
–15
–35
05003-017
TEMPERATURE (°C)
OFFSET ERROR, GAIN ERROR (LSB)
OFFSET ERROR
GAIN ERROR
Figure 17. Offset and Gain Error vs. Temperature
Rev. B | Page 11 of 16
AD7694 Data Sheet
APPLICATION INFORMATION
SW+
MSB
16,384C
IN+
LSB
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C CC32,768C
SW–
MSB
16,384C
LSB
4C 2C CC32,768C
05003-018
Figure 18. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7694 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of con-
verting 250,000 samples per second (250 kSPS) and powers
down between conversions. When operating at 100 SPS, for
example, it typically consumes 4 µW, ideal for battery-powered
applications.
The AD7694 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7694 is specified from 2.7 V to 5.25 V. It is housed in an
8-lead MSOP. The AD7694 is an improved second source to
LTC1864 and LTC1864L. For even better performance, the
AD7685 should be considered.
CONVERTER OPERATION
The AD7694 is a successive approximation ADC based on a
charge redistribution DAC. Figure 18 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase begins. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Thus, the differential voltage between the inputs, IN+
and IN−, captured at the end of the acquisition phase applies to
the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65536). The
control logic toggles these switches, starting with the MSB, in
order to bring the comparator back into a balanced condition.
After the completion of this process, the part returns to the
acquisition phase and the control logic generates the ADC
output code.
Because the AD7694 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7694 is shown in
Figure 19 and Table 8.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (STRAIGHT BINARY)
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
05003-019
Figure 19. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FSR – 1 LSB
4.999924 V
FFFF
1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR
0 V
00002
1 This is also the code for an overranged analog input (VIN+ – VIN– above
VREF – VGND).
2 This is also the code for an underranged analog input (VIN+ – VIN– below VGND).
Rev. B | Page 12 of 16
Data Sheet AD7694
05003-020
AD7694
REF
GND
VDD
IN–
IN+
SCK
SDO
CNV
3-WIRE INTERFACE
100nF 2.7V TO 5.25V
2.2 TO 10µF
(NOTE 2)
REF
0 TO V
REF
33Ω
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
NOTES
1. SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
Figure 20. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 20 shows an example of the recommended application
diagram for the AD7694.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7694 input
structure. The two diodes, D1 and D2, provide ESD protection
for the analog inputs, IN+ and IN−. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V, because this will cause these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit,
current limitation can be used to protect the part.
05003-021
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN–
GND
VDD
Figure 21. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected. For instance, by using IN− to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated. During the acquisition
phase, the impedance of the analog input IN+ can be modeled
as a parallel combination of the capacitor CPIN and the network
formed by the series connection of RIN and CIN. CPIN is primarily
the pin capacitance. RIN is typically 600 Ω and is a lumped
component made up of some serial resistors and the on
resistance of the switches. CIN is typically 30 pF and is mainly
the ADC sampling capacitor. During the conversion phase,
where the switches are opened, the input impedance is limited
to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces
undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7694 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7694 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7694. Note that the AD7694
has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system perfor-
mance. The noise coming from the driver is filtered by the
AD7694 analog input circuit 1-pole, low-pass filter made
by R1 and C2 or by the external filter, if one is used.
• For ac applications, the driver needs to have a THD
performance suitable to that of the AD7694. Figure 13
gives the THD vs. frequency that the driver should exceed.
• For multichannel, multiplexed applications, the driver
amplifier and the AD7694 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Rev. B | Page 13 of 16
AD7694 Data Sheet
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply and low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7694 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, an unbuffered reference voltage like the low
temperature drift ADR43x reference or a reference buffer using
the AD8031 or the AD8605), a 10 µF (X5R, 0805 size) ceramic
chip capacitor is appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7694 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 22. This makes the part
ideal for a low sampling rate (even a few Hz) and low battery-
powered applications.
10,000
1,000
100
10
1
0.1
0.0110 100 1k 10k 100k 1M
05003-022
SAMPLING RATE (SPS)
OPERATING CURRENT (µA)
VDD = 5V
VDD = 2.7V
Figure 22. Operating Current vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7694, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 23. The reference line can be driven by either
• The system power supply directly
• A reference voltage with enough current output capability,
such as the ADR43x
• A reference buffer, such as the AD8031, that can also filter
the system power supply, as shown in Figure 23
05003-023
AD8031
AD7694
REF VDD
2.2
TO
10µF1µF
10Ω
10kΩ
5V OR 3V
5V
OR
3V
5V OR 3V
1µF
(NOTE 1)
NOTES
1. OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 23. Example of an Application Circuit
Rev. B | Page 14 of 16
Data Sheet AD7694
05003-025
SDO
1
SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW.
D15 D14 D13 D1 D0
tDIS
SCK 12 3 14 15 16
1
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
tACQ
tEN
Figure 24. Serial Interface Timing
DIGITAL INTERFACE
The AD7694 is compatible with SPI, QSPI, digital hosts, and
DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. The
connection diagram is shown in Figure 25 and the
corresponding timing diagram is shown in Figure 24.
A rising edge on CNV initiates a conversion and forces SDO to
high impedance. When the conversion is complete, the AD7694
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are clocked by SCK falling edges. The data is valid on both SCK
edges.
05003-024
CNV
SCK
SDO DATA IN
CLK
CONVERT
DIGITAL HOST
AD7694
Figure 25. Connection Diagram
LAYOUT
The printed circuit board that houses the AD7694 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7694 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7694 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7694s.
The AD7694 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7694 should be
decoupled with a ceramic capacitor, typically 100 nF. This
capacitor should be placed close to the AD7694 and connected
using short and large traces to provide low impedance paths
and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7694 PERFORMANCE
Other recommended layouts for the AD7694 are outlined in the
evaluation board for the AD7694 (EVAL -AD7694SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the E VA L -SDP-CB1Z.
Rev. B | Page 15 of 16
AD7694 Data Sheet
OUTLINE DIMENSIONS
0.80
0.60
0.40
8°
0°
4
8
1
5
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 26. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions Shown in Millimeters
ORDERING GUIDE
Model1, 2, 3
Integral
Nonlinearity Temperature Range
Package
Description
Package
Option
Transport Media,
Quantity Branding
AD7694ARMZ ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 Tube, 50 C4K
AD7694ARMZRL7 ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 Reel, 1,000 C4K
AD7694BRMZ ±4 LSB max –40°C to +85°C 8-Lead MSOP RM-8 Tube, 50 C4L
AD7694BRMZRL7 ±4 LSB max –40°C to +85°C 8-Lead MSOP RM-8 Reel, 1,000 C4L
EVAL-AD7694SDZ
Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliance Part.
2 The EVAL-AD7694SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in SD designators.
©2004–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05003-0-6/14(B)
Rev. B | Page 16 of 16