74HC21D,653 - NXP Semiconductors

1. General description

The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power

Schottky TTL (LSTTL).

The 74HC21 provide the 4-input AND function.

2. Features

nLow-power dissipation

nComplies with JEDEC standard no. 7A

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

nMultiple package options

nSpeciﬁed from −40 °Cto+80°C and from −40 °C to +125 °C.

3. Ordering information

74HC21

Dual 4-input AND gate

Rev. 05 — 7 May 2009 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC21N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HC21D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

74HC21DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm SOT337-1

74HC21PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

Product data sheet Rev. 05 — 7 May 2009 2 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Functional diagram Fig 2. Logic symbol

001aab975

52A

12 8

001aab973

52A

12 8

Fig 3. IEC Logic symbol Fig 4. Logic diagram

001aab974

001aab976

Fig 5. Pin conﬁguration SOT27-1 and SOT108-1 Fig 6. Pin conﬁguration SOT337-1 and SOT402-1

1A VCC

1B 2D

n.c. 2C

1C n.c.

1D 2B

1Y 2A

GND 2Y

001aab972

7 8

74HC21

1A VCC

1B 2D

n.c. 2C

1C n.c.

1D 2B

1Y 2A

GND 2Y

001aai659

Product data sheet Rev. 05 — 7 May 2009 3 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

Table 2. Pin description

Symbol Pin Description

1A, 1B, 1C, 1D 1, 2, 4, 5 data input

n.c. 3, 11 not connected

1Y 6 data output

GND 7 ground (0 V)

2Y 8 data output

2A, 2B, 2C, 2D 9, 10, 12, 13 data input

VCC 14 supply voltage

Table 3. Function table[1]

Input Output

nA nB nC nD nY

LXXXL

XLXXL

XXLXL

XXXLL

HHHHH

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input clamping current VI < −0.5 V or VI>V

CC + 0.5 V [1] -±20 mA

IOK output clamping current VO<−0.5 V or VO>V

CC + 0.5 V [1] -±20 mA

IOoutput current −0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 50 mA

IGND ground current −50 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation [2]

DIP14 package - 750 mW

SO14 and (T)SSOP14

packages - 500 mW

Product data sheet Rev. 05 — 7 May 2009 4 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.0 5.0 6.0 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

∆t/∆V input transition rise and fall

rate VCC = 2.0 V - - 625 ns/V

VCC = 4.5 V - 1.67 139 ns/V

VCC = 6.0 V - - 83 ns/V

Tamb ambient temperature −40 - +125 °C

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI = VIH or VIL

IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC = 6.0 V --±0.1 - ±1-±1µA

ICC supply current VI = VCC or GND; IO=0A;

VCC = 6.0 V - - 2.0 - 20 - 40 µA

CIinput

capacitance - 3.5 - - - - - pF

Product data sheet Rev. 05 — 7 May 2009 5 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

10. Dynamic characteristics

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in µW):

PD=C

PD ×VCC2×fi×N+∑ (CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

Table 7. Dynamic characteristics

GND = 0 V; test circuit see Figure 8.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

tpd propagation

delay nA, nB, nC or nD to nY;

see Figure 7 [1]

VCC = 2.0 V - 33 110 - 140 - 165 ns

VCC = 4.5 V - 12 22 - 28 - 33 ns

VCC = 6.0 V - 10 19 - 24 - 28 ns

VCC = 5.0 V; CL=15pF-10-----ns

tttransition time nY output; see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

CPD power

dissipation

capacitance

VI= GND to VCC [3] -15-----pF

Product data sheet Rev. 05 — 7 May 2009 6 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output

transition times

001aab977

nA, nB, nC,

nD input

nY output

tPHL

tTHL tTLH

tPLH

VOH

VOL

GND

Table 8. Measurement points

Type Input Output

VMVMVXVY

74HC21 0.5VCC 0.5VCC 0.1VCC 0.9VCC

Product data sheet Rev. 05 — 7 May 2009 7 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 8. Test circuit for measuring switching times

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 % VMVM

VCC

DUT

VIVO

Table 9. Test data

Type Input Load Test

VItr, tfCL

74HC21 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL

Product data sheet Rev. 05 — 7 May 2009 8 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

12. Package outline

Fig 9. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 05 — 7 May 2009 9 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

Fig 10. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 05 — 7 May 2009 10 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

Fig 11. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 05 — 7 May 2009 11 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

Fig 12. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 05 — 7 May 2009 12 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC21_5 20090507 Product data sheet - 74HC21_4

Modiﬁcations: Table 1: Type number 74HCT21PW changed to 74HC21PW.

74HC21_4 20090407 Product data sheet - 74HC21_3

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Added type number 74HC21PW (TSSOP14 package).

74HC21_3 20041112 Product data sheet - 74HC_HCT21_CNV_2

74HC_HCT21_CNV_2 19970828 Product speciﬁcation - 74HC_HCT21_1

74HC_HCT21_1 19901201 Product speciﬁcation - -

Product data sheet Rev. 05 — 7 May 2009 13 of 14

NXP Semiconductors 74HC21

Dual 4-input AND gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC21

Dual 4-input AND gate

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 May 2009

Document identifier: 74HC21_5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16 Contact information. . . . . . . . . . . . . . . . . . . . . 13

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14