DRV103U/2K5G4 - Texas Instruments

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

PWM LOW-SIDE DRIVER (1.5A and 3A)

for Solenoids, Coils, Valves, Heaters, and Lamps

FEATURES

●HIGH OUTPUT DRIVE: 1.5 A and 3 A Versions

●WIDE SUPPLY RANGE: +8V to +32V

●COMPLETE FUNCTION

Digitally Controlled Input

PWM Output

Adjustable Internal Oscillator: 500Hz to 100kHz

Adjustable Delay and Duty Cycle

●FULLY PROTECTED

Thermal and Current Limit Shutdown with

Status OK Indicator Flag

●PACKAGES:

SO-8 and PowerPAD™ SO-8

APPLICATIONS

●ELECTROMECHANICAL DRIVER:

Solenoids, Valves, Positioners, Actuators,

Relays, Power Contactor Coils, Heaters, Lamps

●HYDRAULIC AND PNEUMATICS SYSTEMS

●PART HANDLERS AND SORTERS

●CHEMICAL PROCESSING

●ENVIRONMENTAL MONITORING AND HVAC

●THERMOELECTRIC COOLERS

●DC MOTOR SPEED CONTROLS

●MEDICAL AND SCIENTIFIC ANALYZERS

●FUEL INJECTOR DRIVERS

DESCRIPTION

The DRV103 is a low-side DMOS power switch employing

a pulse-width modulated (PWM) output. Its rugged design is

optimized for driving electromechanical devices such as

valves, solenoids, relays, actuators, motors, and positioners.

The DRV103 is also ideal for driving thermal devices such

as heaters, coolers, and lamps. PWM operation conserves

power and reduces heat rise, resulting in higher reliability. In

addition, adjustable PWM allows fine control of the power

delivered to the load. DC-to-PWM output delay time and

oscillator frequency are also externally adjustable.

The DRV103 can be set to provide a strong initial closure,

automatically switching to a “soft” hold mode for power

savings. A resistor, analog voltage, or Digital-to-Analog

(D/A) converter can control the duty cycle. An output OK flag

indicates when thermal shutdown or over current occurs.

Two packages provide a choice of output current:

1.5A (SO-8) or 3A (PowerPAD™ SO-8 with exposed metal

heat sink).

The DRV103 is specified for –40°C to +85°C.

Delay

Adj

CDRPWM

Input

Off

Thermal Shutdown

Over Current

Status OK

Flag

Load

+VS

Oscillator

VREF

PWM

GND

OUT

Flyback

Diode

DMOS

ESD

Osc Freq

Adj Duty Cycle

Adj

RFREQ

Delay

DRV103

SBVS029A – JUNE 2001

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

DRV103

2SBVS029A

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

DRV103U SO-8 182 –40°C to +85°C DRV103U DRV103U Rails

" " " " " DRV103U/2K5 Tape and Reel

DRV103H PowerPAD™ SO-8 DDA –40°C to +85°C DRV103H DRV103H Rails

" " " " " DRV103H/2K5 Tape and Reel

NOTES: (1) Models with a slash ( / ) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500

pieces of “DRV103U/2K5” will get a single 2500-piece Tape and Reel.

Supply Voltage, VS(2) ......................................................................... +40V

Input Voltage ..................................................................–0.2V to +5.5V(3)

PWM Adjust Input ..........................................................–0.2V to +5.5V(3)

Delay Adjust Input ..........................................................–0.2V to +5.5V(3)

Frequency Adjust Input ..................................................–0.2V to +5.5V(3)

Status OK Flag and OUT.................................................... –0.2V to VS(4)

Operating Temperature Range ......................................–55°C to +125°C

Storage Temperature Range .........................................–65°C to +150°C

Junction Temperature.................................................................... +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may de-

grade device reliability. (2) See Bypassing section for discussion about

operating near maximum supply voltage. (3) Higher voltage may be applied

if current is limited to 2mA. (4) The Status OK Flag will internally current limit

at about 10mA.

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

DRV103 3

SBVS029A

ELECTRICAL CHARACTERISTICS

At TC = +25°C, VS = +24V, Load = 100Ω, and 4.99kΩ “OK Flag” pullup to +5V, Delay Adj Capacitor = 100pF to Ground, Freq Adj Resistor = 205kΩ to Ground,

Duty Cycle Adj Resistor = 137kΩ to Ground, unless otherwise noted.

DRV103U, H

PARAMETER CONDITIONS MIN TYP MAX UNITS

OUTPUT

Output Current(1) SO-8 Package (U) 1.5 A

PowerPAD™ SO-8 Package (H) 3 A

Output Saturation Voltage, Source IO = 1A +0.4 +0.6 V

IO = 0.1A +0.05 +0.07 V

Current Limit(2), (10) 3 3.5 4.2 A

Leakage Current DMOS Output Off, VO = +32V ±1±10 µA

DIGITAL CONTROL INPUT(3)

VCTR Low (output disabled) 0 +1.2 V

VCTR High (output enabled) +2.2 +5.5 V

ICTR Low (output disabled) VCTR = 0V 0.01 1 µA

ICTR High (output enabled) VCTR = +5.5V 120 150 µA

Propagation Delay On-to-Off and Off-to-On 1 µs

DELAY TO PWM(4) DC to PWM Mode

Delay Equation(5) See Note (6) s

Delay Time CD = 0.1µF 90 110 140 ms

Minimum Delay Time(7) CD = 0 18 µs

DUTY CYCLE ADJUST

Duty Cycle Range 10 to 90 %

Duty Cycle Accuracy 50% Duty Cycle, 25kHz ±2%

vs Supply Voltage 50% Duty Cycle, VS = VO = +8V to +32V ±2%

Nonlinearity(8) 10% to 90% Duty Cycle 1 % FSR

DYNAMIC RESPONSE

Output Voltage Rise Time VO = 10% to 90% of VS0.2 2 µs

Output Voltage Fall Time VO = 90% to 10% of VS0.2 2 µs

Oscillator Frequency Range External Adjust 0.5 to 100 kHz

Oscillator Frequency ROSC = 205kΩ20 25 30 kHz

OK FLAG

Normal Operation 20kΩ Pull-Up to +5V +4.5 5.0 V

Fault(90) Sinking 1mA +0.22 +0.4 V

Sink Current VOKFLAG = 0.4V 2 mA

Over-Current Flag: Set 5µs

THERMAL SHUTDOWN

Junction Temperature

Shutdown +160 °C

Reset from Shutdown +140 °C

POWER SUPPLY

Specified Operating Voltage +24 V

Operating Voltage Range +8 +32 V

Quiescent Current IO = 0 0.4 0.8 mA

TEMPERATURE RANGE

Specified Range –40 +85 °C

Operating Range –55 +125 °C

Storage Range –65 +150 °C

Thermal Resistance,

SO-8 (U) 1in2 0.5oz. Copper on PCB 150 °C/W

PowerPAD™ SO-8 (H)(10) 1in2 0.5oz. Copper on PCB 68 °C/W

NOTES: (1) Output current is limited by internal current limit and by DRV103 power dissipation. (2) Output current resets to zero when current limit is reached.

(3) Logic High enables output (normal operation). (4) Constant DC output to PWM (Pulse-Width Modulated) time. (5) Maximum delay is determined by an external

capacitor. Pulling the Delay Adjust Pin LOW corresponds to an infinite (continuous) delay. (6) Delay to PWM ≈ C

D • 106 (CD in

F • 1.1). (7) Connecting the Delay Adjust Pin to +5V reduces delay time to less than 1µs. (8) VIN at pin 3 to percent of duty cycle at pin 6. (9) OK Flag LOW indicates

fault from over-temperature or over-current conditions. (10) PowerPAD™ SO-8 (H) package has highest continuous current (2A) because the chip operates at a

lower junction temperature when underside metal tab is connected to a heat sink or heat spreader.

JA = 68°C/W measured on DRV103 demo board;

JA = 58°C/W measured on JEDEC standard test board. H package

JC = 16.7°C/W.

DRV103

4SBVS029A

PIN # NAME DESCRIPTION

Pin 1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF) current source from VS. The voltage at this node linearly

sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The

active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, output duty cycle is near

90%. At 1.5V, output duty cycle is near 10%.

Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results

in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than

1µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 2.6V threshold comparator. When

the pin voltage is below 2.6V, the output device is 100% ON. The PWM oscillator is not synchronized to the Input (pin 1), so the

duration of the first pulse may be any portion of the programmed duty cycle.

Pin 3 Oscillator PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz

Frequency Adjust to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors

higher than 10M will be required. The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup

and PCB leakage currents.

Pin 4 GND This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load

current when the power DMOS transistor is switched on.

Pin 5 OUT The output is the drain of a power DMOS transistor with its source connected to ground. Its low on-resistance (0.5Ω typ) assures

low power dissipation in the DRV103. Gate drive to the power device is controlled to provide a slew-rate limited rise and fall time.

This reduces radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off

cycle. The external diode should be selected for low forward voltage and low storage time. The internal clamp diode (an ESD

protection diode) provides some degree of back-EMF protection but it should not be used as a flyback diode.

Pin 6 +VSThis is the power supply pin. Operating range is +8V to +32V. +VS must be ≥ the supply voltage to the load.

Pin 7 Status OK Flag Normally HIGH (active LOW), a Flag LOW signals either an over-temperature or over-current fault. The over-current flag (Status

OK) is LOW only when the output is ON (constant DC output or the “ON” portion of PWM mode). A thermal fault (thermal shutdown)

occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-

up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA typical.

Pin 8 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the

typical switching threshold, 1.7V. Below this level, the output is disabled. Input current is typically 10nA when driven HIGH and 10 nA

with the input LOW. The input should not be directly connected to the power supply (VS) or damage will occur.

PIN DESCRIPTIONS

LOGIC BLOCK DIAGRAM

PIN CONFIGURATION

Top View

Duty Cycle Adj

Delay Adj

Osc Freq Adj

GND

Input

Status OK Flag

+VS

OUT

Delay

Adj

PWM

Input

Off

Thermal Shutdown

Over Current

Status OK

Flag

Load

Oscillator

1.3V V

REF

PWM

GND

OUT

Flyback

Diode

DMOS

ESD

Osc Freq

Adj Duty Cycle

Adj

2.75 • I

REF

FREQ

Delay

DRV103

REF

DRV103 5

SBVS029A

TYPICAL CHARACTERISTICS

At TC = +25°C and VS = +24V, unless otherwise noted.

OUT

& I

OUT

WAVEFORMS

SOLENOID LOAD

Off

AVG

PWM Mode

Delay

Pull-In

OUT

(A)

Time (ms) 1000

VOUT & IOUT WAVEFORMS

RESISTIVE LOAD

Off

IAVG

PWM Mode

Delay

IOUT (A)

Time (ms) 1000

+VS

CURRENT LIMIT SHUTDOWN WAVEFORMS

OK OK

Off Off

PWM

= 25kHz

DC = 50%

Delay = 150µs

Reset Period = 1/F

PWM

(V) V

OUT

(V)

Time (µs) 1000

OUT

= 0A

= 3.5A

Status

Flag Reset Period

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0–10–60

IQ (mA)

40 90 140

QUIESCENT CURRENT

vs JUNCTION TEMPERATURE

Temperature (°C)

32V

8V to 24V

40V (Absolute Maximum)

3.8

3.7

3.6

3.5

3.4

3.3 –10–60

Current (A)

40 90 140

CURRENT LIMIT

vs JUNCTION TEMPERATURE

Temperature (°C)

150

145

140

135

130

125

120

115

110

105

100 –10–60

Delay (ms)

40 90 140

DELAY vs JUNCTION TEMPERATURE

Temperature (°C)

CD = 0.1µF

+VS = 8V

+VS = 30V

+VS = 24V

+VS = 40V (Absolute Maximum)

DRV103

6SBVS029A

TYPICAL CHARACTERISTICS (Cont.)

At TC = +25°C and VS = +24V, unless otherwise noted.

0–10–60

Min Delay (µs)

40 90 140

MINIMUM DELAY vs JUNCTION TEMPERATURE

Temperature (°C)

= 0pF

25.5

25.3

25.1

24.9

24.7 –10–60

Frequency (kHz)

40 90 140

OSCILLATOR FREQUENCY

vs JUNCTION TEMPERATURE

Temperature (°C)

50.8

50.6

50.4

50.2

50.0

49.8

49.6

49.4

49.2 –10–60

Duty Cycle (%)

40 90 140

DUTY CYCLE vs JUNCTION TEMPERATURE

Temperature (°C)

RPWM = 137kΩ

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–10–60

VSAT (V)

40 90 140

VSAT vs JUNCTION TEMPERATURE

Temperature (°C)

IO = 3A

IO = 1.5A

IO = 0.1A

IO = 0.5A

1.287

1.286

1.285

1.284

1.283

1.282

1.281

1.280

1.279

1.278

1.277

1.276 –10–60

VFREQ (V)

40 90 140

VFREQ vs JUNCTION TEMPERATURE

Temperature (°C)

300

250

200

150

100

–50 4.54

Input Current (µA)

5 5.5 6

INPUT CURRENT vs INPUT VOLTAGE

Input Voltage (V)

DRV103 7

SBVS029A

BASIC OPERATION

The DRV103 is a low-side, DMOS power switch employing

a Pulse-Width Modulated (PWM) output for driving electro-

mechanical and thermal devices. Its design is optimized for

two types of applications: a two-state driver (open/close) for

loads such as solenoids and actuators; and a linear driver for

valves, positioners, heaters, and lamps. Its low 0.5Ω “ON”

resistance, small size, adjustable delay to PWM mode, and

adjustable duty cycle make it suitable for a wide range of

applications.

Figure 1 shows the basic circuit connections to operate the

DRV103. A 1µF (22µF when driving high current loads) or

larger tantalum bypass capacitor is recommended on the

power-supply pin.

Input (pin 8) is level-triggered and compatible with standard

TTL levels. An input voltage between +2.2V and +5.5V

turns the device’s output ON, while a voltage of 0V to

+1.2V shuts the DRV103’s output OFF. Input bias current is

typically 1pA. Delay Adjust (pin 2) and Duty Cycle Adjust

(pin 1) allow external adjustment of the PWM output signal.

The Delay Adjust pin can be left floating for minimum delay

to PWM mode (typically 18µs) or a capacitor can be used to

FIGURE 2. Typical DRV103 Timing Diagram, with CD = 3.9nF, OscFreq = 1kHz, and 75% Duty Cycle.

set a longer delay time. A resistor, analog voltage, or a

voltage from a D/A converter can be used to control the duty

cycle of the PWM output. The D/A converter must be able

to sink a current 2.75 • IREF (IREF = 1.3V/RFREQ).

Figure 2 illustrates a typical timing diagram with the Delay

Adjust pin connected to a 3.9nF capacitor, the duty cycle set

to 75%, and oscillator frequency set to 1kHz. See the “Delay

Adjust” and “Duty Cycle Adjust” text for equations and

further explanation. Ground (pin 4) must be connected to

system ground for the DRV103 to function. This serves as

the load current path to ground, as well as the DRV103

signal ground. The load (relay, solenoid, valve, etc.) should

be connected between the supply (pin 5) and output (pin 6).

For an inductive load, an external “flyback” diode is re-

quired, as shown in Figure 1. The diode serves to maintain

continuous current flow in the inductive load during OFF

periods of PWM operation. For remotely located loads, the

external diode is ideally located next to the DRV103. The

internal ESD clamp diode between the output and supply is

not intended to be used as a “flyback diode.” The Status OK

Flag (pin 7) provides fault status for over-current and

thermal shutdown conditions. This pin is active LOW with

output voltage of typically +0.3V during a fault condition.

Delay

Adj

PWM

TTL IN

Relay

GND

OUT

Status

Flyback

Diode

(1)

+8V to +32V

Osc Freq

Adj Duty Cycle

Adj

FREQ

DRV103

1µF

4132

LED

OK = LED “on”

2mA

NOTE: (1) Motorola MSRS1100T3 (1A, 100V)

Motorola MBRS360T3 (3A, 60V)

Microsemi SK34MS (3A, 40V)

FIGURE 1. DRV103 Basic Circuit Connections.

OFF

OFF Period = = T

+ T

OFF

FREQ

Duty Cycle = T

+ T

OFF

Delay Time

(V)

(A)

TTL HIGH

Input (V)

TTL LOW

0 1 2 3 4

Time (ms) 5 6 7 8 9

DRV103

8SBVS029A

The internal Delay Adjust circuitry is composed of a 3µA

current source and a 2.6V comparator, as shown in Figure 3.

Thus, when the pin voltage is less than 2.6V, the output

device is 100% ON (DC output mode).

OSCILLATOR FREQUENCY ADJUST

The DRV103 PWM output frequency can be easily pro-

grammed over a wide range by connecting a resistor (RFREQ)

between the Osc Freq Adj pin (pin 3) and ground. A range of

500Hz to 100kHz can be achieved with practical resistor

values, as shown in Table II. Refer to “PWM Frequency vs

RFREQ” typical performance curve shown in Figure 4 for

additional information. Although oscillator frequency opera-

tion below 500Hz is possible, resistors higher than 10M will

be required. The pin becomes a very high impedance node and

is, therefore, sensitive to noise pickup and PCB leakage

currents if very high resistor values are used. Refer to Figure

3 for a simplified circuit of the frequency adjust input.

APPLICATIONS INFORMATION

POWER SUPPLY

The DRV103 operates from a single +8V to +32V supply

with excellent performance. Most behavior remains un-

changed throughout the full operating voltage range. Param-

eters that vary significantly with operating voltage are shown

in the Typical Performance Curves. The DRV103 supply

voltage should be ≥ the supply voltage on the load.

ADJUSTABLE DELAY TIME (INITIAL 100% DUTY CYCLE)

A unique feature of the DRV103 is its ability to provide an

initial constant DC output (100% duty cycle) and then

switch to PWM mode output to save power. This function is

particularly useful when driving solenoids that have a much

higher pull-in current requirement than continuous hold

requirement.

The duration of this constant DC output (before PWM

output begins) can be externally controlled by a capacitor

connected from Delay Adjust (pin 2) to ground according to

the following equation:

Delay Time ≈ CD • 106

(time in seconds, CD in Farads • 1.1)

Leaving the Delay Adjust pin open results in a constant

output time of approximately 18µs. The duration of this

initial output can be reduced to less than 1µs by connecting

the pin to 5V. Table I provides examples of delay times

(constant output before PWM mode) achieved with selected

capacitor values.

INITIAL CONSTANT

OUTPUT DURATION CD

1µs Pin 2 Tied to +5V

18µs Pin 2 Open

110µs 100pF

1.1ms 1nF

11ms 10nF

110ms 100nF

1.1s 1µF

11s 10µF

TABLE I. Delay Adjust Times.

FIGURE 3. Simplified Delay Adjust and Frequency Adjust Inputs.

3µA

RFREQ

VFREQ

IREF

+VS

VREF

Reset

+2.6V

+1.3V

Input

1000M

100M

10M

100k

10k

1k 100 1k10

RFREQ (Ω)

10k 100k 1M

PWM FREQUENCY vs RFREQ

Frequency (Hz)

FIGURE 4. Using a Resistor to Program Oscillator Frequency.

RFREQ (kΩ) = 6808417/F(1.0288)

OSCILLATOR FREQUENCY RFREQ (nearest 1% values)

(Hz) (Ω)

100k 47.5k

50k 100k

25k 205k

10k 523k

5k 1.07M

500 11.3M

TABLE II. Oscillator Frequency Resistance.

DRV103 9

SBVS029A

A 100pF capacitor in parallel with RPWM is recommended

when switching a high load current to maintain a clean

output switching waveform, as shown in Figure 6.

The DRV103’s adjustable PWM output frequency allows it

to be optimized for driving virtually any type of load.

ADJUSTABLE DUTY CYCLE (PWM Mode)

The DRV103’s externally adjustable duty cycle provides an

accurate means of controlling power delivered to a load.

Duty cycle can be set over a range of at least 10% to 90%

with an external resistor, analog voltage, or the voltage

output of a D/A converter. A low duty cycle results in

reduced power dissipation in the load. This keeps the DRV103

and the load cooler, resulting in increased reliability for both

devices.

Resistor Controlled Duty Cycle

Duty cycle is easily programmed by connecting a resistor

(RPWM) between the Duty Cycle Adjust pin (pin 1) and

ground. High resistor values correspond to high duty cycles.

Table III provides resistor values for typical duty cycles.

Resistor values for additional duty cycles can be obtained

from Figure 5. For reference purposes, the equation for

calculating RPWM is included in Figure 5.

DUTY CYCLE RPWM (Nearest 1% Values)

(%) 5kHz 25kHz 100kHz

5 374k 75k 16.9k

10 402k 80.6k 19.1k

20 475k 95.3k 22.6k

30 549k 110k 26.1k

40 619k 124k 29.4k

50 681k 137k 33.2k

60 750k 150k 37.4k

70 825k 165k 40.2k

80 887k 182k 44.2k

90 953k 196k 47.5k

95 1M 200k 49.9k

TABLE III. Duty Cycle Adjust Resistance.

FIGURE 5. Using a Resistor to Program Duty Cycle.

At 25kHz: RPWM (kΩ) = 67.46 + 1.41 • %DC.

100k

10k 20 400

PWM

(Ω)

60 80 100

DUTY CYCLE vs R

PWM

Duty Cycle (%)

5kHz

25kHz

100kHz

PWM

only on

Pin 1

With

100pF in

Parallel with

PWM

Time (10µs)

FIGURE 6. Output Waveform at High Load Current.

100

021

Duty Cycle (%)

1.5

0.5

–0.5

–1

–1.5

–2

Duty Cycle Error (%)

DUTY CYCLE AND DUTY CYCLE ERROR

vs VOLTAGE

PWM

(V)

FIGURE 7. Using a Voltage to Program Duty Cycle.

At VS = 24V and F = 25kHz: VPWM = 1.25 +

0.026 • %DC.

Voltage Controlled Duty Cycle

Duty cycle can also be programmed by an analog voltage,

VPWM. With VPWM ≈ 3.56V, duty cycle is about 90%.

Decreasing this voltage results in decreased duty cycles.

Table IV provides VPWM values for typical duty cycles. The

“Duty Cycle vs Voltage” typical performance curve for

additional duty cycles is shown in Figure 7.

DUTY CYLE VPWM

(%) (V)

5 1.344

10 1.518

20 1.763

40 2.283

60 2.788

80 3.311

90 3.561

95 3.705

TABLE IV. Duty Cycle Adjust Voltage.

DRV103

10 SBVS029A

The Duty Cycle Adjust pin is internally driven by an

oscillator frequency dependent current source and connects

to the input of a comparator as shown in Figure 8. The

DRV103’s PWM adjustment is inherently monotonic. That

is, a decreased voltage (or resistor value) always produces

an increased duty cycle.

DRV103

Thermal Shutdown

Over Current

PWM

OUT

5kΩ

Pull-Up

+5V

TTL or HCT

FIGURE 9. Non-Latching Fault Monitoring Circuit.

FIGURE 10. Latching Fault Monitoring Circuit.

5kΩ

+5V

(LED)

HLMP-Q156

DRV103

Thermal Shutdown

Over Current

5OUT

PWM

FIGURE 11. LED to Indicate Fault Condition.

20kΩ

+5V

CLR

OK Reset

CLK

GND K

74XX76A

(1)

NOTE: (1) Small capacitor (10pF) may be required in noisy environments.

DRV103

Thermal Shutdown

Over Current

5OUT

PWM

2.75 • I

REF

PWM

OSC 3.9V

1.3V

FIGURE 8. Simplified Duty Cycle Adjust Input.

STATUS FLAG

The OK Flag (pin 7) provides a fault indication for over-

current and thermal shutdown conditions. During a fault

condition, the Status OK Flag output is driven LOW (pin

voltage typically drops to 0.3V). A pull-up resistor, as

shown in Figure 9, is required to interface with standard

logic. Figure 9 also gives an example of a non-latching fault

monitoring circuit, while Figure 10 provides a latching

version. The OK Flag pin can sink up to 10mA, sufficient

to drive external logic circuitry, a reed relay, or an LED, as

shown in Figure 11, to indicate when a fault has occurred.

In addition, the OK Flag pin can be used to turn off other

DRV103s in a system for chain fault protection.

Over Current Fault

An over-current fault occurs when the PWM peak output

current is greater than approximately 3.75A. The OK flag is

not latched. Since current during PWM mode is switched on

and off, the OK flag output will be modulated with PWM

timing (see OK flag waveforms in the Typical Performance

Curves).

Avoid adding capacitance to pin 6 (Out) as it may cause

momentary current limiting.

Over-Temperature Fault

A thermal fault occurs when the die reaches approximately

160°C, producing a similar effect as pulling the input low.

Internal shutdown circuitry disables the output. The OK

Flag is latched in the LOW state (fault condition) until the

die has cooled to approximately 140°C.

DRV103 11

SBVS029A

PACKAGE MOUNTING

Figure 12 provides recommended PCB layouts for both the

SO-8 (U) and the PowerPAD™ SO-8 (H) packages. Al-

though the metal pad of the PowerPAD™ SO-8 (H) package

is electrically connected to ground (pin 4), no current should

flow in this pad. Do NOT use the exposed metal pad as a

power ground connection or erratic operation will result. For

lowest overall thermal resistance, it is best to solder the

PowerPAD™ directly to a circuit board, as illustrated in

Figure 13. Increasing the “heat sink” copper area improves

heat dissipation. Figure 14 shows typical junction-to-ambi-

ent thermal resistance as a function of the PC board copper

area.

POWER DISSIPATION

DRV103 power dissipation depends on power supply, signal,

and load conditions. Power dissipation (PD) is equal to the

product of output current times the voltage across the conduct-

ing DMOS transistor times the duty cycle. Using the lowest

possible duty cycle necessary to assure the required hold force

can minimize power dissipation in both the load and in the

DRV103. For low current, the output DMOS transistor on-

resistance is 0.5Ω, increasing to 0.6Ω at high output current.

At very high oscillator frequencies, the energy in the DRV103’s

linear rise and fall times can become significant and cause an

increase in PD.

Application Bulletin SBFA002 at www.ti.com, explains how to

calculate or measure power dissipation with unusual signals

and loads.

THERMAL PROTECTION

Power dissipated in the DRV103 will cause its internal junction

temperature to rise. The DRV103 has an on-chip thermal

shutdown circuitry that protects the IC from damage. The

thermal protection circuitry disables the output when the junc-

tion temperature reaches approximately +160°C, allowing the

device to cool. When the junction temperature cools to approxi-

mately +140°C, the output circuitry is again enabled. Depend-

ing on load and signal conditions, the thermal protection circuit

may cycle on and off. This limits the dissipation of the driver

but may have an undesirable effect on the load.

Any tendency to activate the thermal protection circuit indi-

cates excessive power dissipation or an inadequate heat sink.

For reliable operation, junction temperature should be limited

to +125°C, maximum. To estimate the margin of safety in a

complete design (including heat sink), increase the ambient

temperature until the thermal protection is triggered. Use

worst-case load and signal conditions. For good reliability,

thermal protection should trigger more than 40°C above the

maximum expected ambient condition of your application.

This produces a junction temperature of 125°C at the maxi-

mum expected ambient condition.

THERMAL RESISTANCE vs

CIRCUIT BOARD COPPER AREA

Thermal Resistance, θJA (°C/W)

012345

Copper Area (inches2)

DRV103 (H)

Power PAD

Surface-Mount Package

1oz. copper

FIGURE 12. Recommended PCB Layout.

FIGURE 13. PowerPAD Heat Transfer.

FIGURE 14. Heat Sink Thermal Resistance vs Circuit Board

Copper Area.

150 (ref)

C - C

215 (ref)

95 x 95

DRV103(H)

Package

60 (ref)

50 nom 18

273

277

153

158

Copper Traces

Signal Trace

Copper Pad

Thermal Vias

DRV103 Die

Pad-to-Board

Solder

DRV103

12 SBVS029A

The internal protection circuitry of the DRV103 was designed

to protect against overload conditions. It was not intended to

replace proper heat sinking. Continuously running the

DRV103 into thermal shutdown will degrade reliability.

HEAT SINKING

Most applications will not require a heat sink to assure that

the maximum operating junction temperature (125°C) is not

exceeded. However, junction temperature should be kept as

low as possible for increased reliability. Junction tempera-

ture can be determined according to the equation:

TJ = TA + PD

JA (1)

where,

JA =

JC +

CH +

HA (2)

TJ= Junction Temperature (°C)

TA= Ambient Temperature (°C)

PD= Power Dissipated (W)

JC = Junction-to-Case Thermal Resistance (°C/W)

CH = Case-to-Heat Sink Thermal Resistance (°C/W)

HA =

Heat Sink-to-Ambient Thermal Resistance (°C/W)

JA = Junction-to-Air Thermal Resistance (°C/W)

Using a heat sink significantly increases the maximum

allowable power dissipation at a given ambient temperature.

The answer to the question of selecting a heat sink lies in

determining the power dissipated by the DRV103. For DC

output into a purely resistive load, power dissipation is simply

the load current times the voltage developed across the

conducting output transistor times the duty cycle. Other loads

are not as simple. For further insight on calculating power

dissipation, refer to Application Bulletin SBFA002 at

www.ti.com. Once power dissipation for an application is

known, the proper heat sink can be selected.

Heat Sink Selection Example

A PowerPAD™ SO-8 (H) package is dissipating 2W. The

maximum expected ambient temperature is 35°C. Find the

proper heat sink to keep the junction temperature below

125°C.

Combining Equations 1 and 2 gives:

TJ = TA + PD(

JC +

CH +

HA)(3)

TJ, TA, and PD are given.

JC is provided in the specification

table, 16.7°C/W.

CH depends on heat sink size, area, and

material used. A semiconductor’s package type and mount-

ing can also affect

CH. A typical

CH for a soldered-in-place

PowerPAD™ SO-8 (H) package is 2°C/W. Now we can

solve for

HA:

θθθ

HA JA

DJC CH

WCW CW

()

=°° °+°

()

=°

––

––. / /

125 35

216 7 2

26 3

(4)

To maintain junction temperature below 125°C, the heat

sink selected must have a

HA less than 26.3°C/W. In other

words, the heat sink temperature rise above ambient must be

less than 52.6°C (26.3°C/W • 2W).

Another variable to consider is natural convection versus

forced convection air flow. Forced-air cooling by a small fan

can lower

CA (

CH +

HA) dramatically.

As mentioned earlier, once a heat sink has been selected, the

complete design should be tested under worst-case load and

signal conditions to ensure proper thermal protection.

RFI/EMI

Any switching system can generate noise and interference

by radiation or conduction. The DRV103 is designed with

controlled slew rate current switching to reduce these ef-

fects. By slowing the rise and fall times of the output to

0.3µs, much lower switching noise is generated.

Radiation from the DRV103-to-load wiring (the “antenna”

effect) can be minimized by using “twisted pair” cable or by

shielding. Good PCB ground planes are recommended for

low noise and good heat dissipation. Refer to Bypassing

section for notes on placement of the flyback diode.

BYPASSING

A 1µF tantalum bypass capacitor is adequate for uniform

duty cycle control when switching loads of less than 0.5

amps. Larger bypass capacitors are required when switching

high current loads. A 22µF tantalum capacitor is recom-

mended for heavy-duty (3A) applications. It may also be

desirable to run the DRV103 and the load on separate power

supplies at high load currents. Near the absolute maximum

supply voltage of 40V, bypassing is especially critical. In the

event of a current overload, the DRV103 current limit

responds in microseconds, dropping the load current to zero.

With inadequate bypass, energy stored in the supply line

inductance can lift the supply sufficiently to exceed voltage

breakdown with catastrophic results.

Place the flyback diode at the DRV103 end when driving

long (inductive) cables to a remotely located load. This

minimizes RFI/EMI and helps protect the output DMOS

transistor from breakdown caused by dI/dt transients. Fast

rectifier diodes such as epitaxial silicon or Schottky types

are recommended as flyback diodes.

DRV103 13

SBVS029A

Delay

Adj

0.22µF205kΩ

+12V

GND

OUT

Input

+VS

Microsemi

SK34MS

3A 40V Schottky

Duty Cycle

Adj Freq

Adj

137kΩ

47µF

Tantalum

DRV103

22µF

312

81.7V 5

1MΩ

316kΩ

"Fault"

HLMP-0156 +

CTCT (µF)

4.7

2.2

TON (s)

0.5

5.6kΩ

Relay

Delay

Adj Duty Cycle

Adj Freq

Adj

0.1µF205kΩ

GND

OUT

Input

137kΩ

DRV103

22µF

312

24kΩ

3.9kΩ

+28V

Housing

Relay

FIGURE 15. Time Delay Relay Driver.

FIGURE 16. Remotely Operated Solenoid Valve or Relay.

APPLICATIONS CIRCUITS

DRV103

14 SBVS029A

Delay

Adj

CD10MΩ

+12V

GND

OUT

Input

+VS

Duty Cycle

Adj Freq

Adj

RPWM

3kΩ

DRV103

22µF

312

LOAD

(1)

TTLIN

High = Load ON

Low = Load OFF

NOTE: (1) Flyback diode required for inductive loads: IXYS DSE160-06A.

F ~ 500Hz

IRF4905

12V

70A

TTL IN

Linear

Valve

Actuator

OUT 5

213NC

Status

+8V to +32V

DRV103

22µF

Microsemi

SK34MS

3A 40V

Schottky

HLMP-Q156 “Fault”

2mA

Delay

Adj

205kΩ

GND

Duty Cycle

Adj Freq

Adj

High = ON

Low = OFF

1.3V ≅ 5% Duty Cycle

3.7V ≅ 95% Duty Cycle

DACDATA

FIGURE 17. High Power High Side Driver.

FIGURE 18. Linear Valve Driver.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

DRV103H ACTIVE SO

Power

PAD

DDA 8 75 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

DRV103H/2K5 ACTIVE SO

Power

PAD

DDA 8 2500 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

DRV103H/2K5G3 ACTIVE SO

Power

PAD

DDA 8 2500 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

DRV103HG3 ACTIVE SO

Power

PAD

DDA 8 75 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

DRV103U ACTIVE SOIC D 8 75 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DRV103U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DRV103U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

DRV103UG4 ACTIVE SOIC D 8 75 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2010

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DRV103H/2K5 SO

Power

PAD

DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

DRV103U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV103H/2K5 SO PowerPAD DDA 8 2500 367.0 367.0 35.0

DRV103U/2K5 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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