CY7C960-UM - AnalogicTech

Low Cost VMEbus Interface

Controller Famil

ax id: 5603

CY7C960

CY7C961

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Decembe r 1994 – Revised December 4

1997

Features

• 80-Mbyt e-per-second block transfer rate s

• All VME64 tr ansactions provided, inc luding A64/D64,

A40/MD 32 transfers

• A uto Slot ID

• CR/CSR space

• All standard (Rev C) VMEbus transactions implemented

• VMEbus Inter rupter

• No local CPU required

• Programmable from VMEbus, serial PROM, or local bus

• DRAM controller, inc ludi ng refresh

• On-chip DMA controller

• Lo cal I /O controller

• Flexible VMEb us address scheme

• User- configured VMEbus response

• 64-pin TQFP, 10x10mm (CY7C960)

• 100-pi n TQ FP, 14x14mm (C Y7C961)

Functional Descripti on

The CY7C960 Slav e VMEbus Interface Controller provides the

board designer with an integrated, full-featured VME64 inter-

face. This 64-pin device can be programmed to handle every

tran sacti on d efined in t he VME64 specif ication . The CY7C961

is based upon the CY7C960: additional features include Re-

mote Master capability whereby the CY7C961 can be com-

manded to move data as a VMEbus master. The CY7C961 is

packaged in a 100-pin outline.

The CY7C960 conta ins all the circui try needed to co ntrol large

DRAM arrays and local I/O circu it ry wi thout the int ervention of

a local CPU. There are no registers to read or write, no com-

plex command blocks to be constructed in memory. The

CY7C960 simply fetches its own configuration parameters

during the power-on reset period. After reset the CY7C960

responds appropriately to VMEbus activity and controls local

circuitry transparently.

VMECONTROL

INTERF

ACE

CY7C960 Logic Block Diagram

c960–1

REGION/

AM TABLE CY7C964CONTROLLER

POWER-ON

RESET

GENERATOR

AM [5:0]

SYSRESET*

AS*

DS0*

DS1*

DTACK*

WRITE*

CLK

REGION[3:0]

IRQ*

IACK*

IACKIN*

IACKOUT*

LOCAL ADDRESS

CONTROLLER

CHIP SELECT

OUTPUT PATTERN

TABLE

DATA BYTE

ENABLE

CONTROLLER

DATABYTE

LANE

DECODER

LOCAL

CONTROL

CIRCUIT

DRAM

CONTROLLER

REFRESH

CONTROLLER

TIMING

GENERATOR

VME INTERRUPT

INTERFACE

CS[5:0]

DBE[3:0]

LACK*

LDEN*

PREN*

SWDEN*

R/W

RAS*

CAS*

ROW

COL

LIRQ*

D64

STROBE

DENO*

DENIN*

DENIN1*

LADI

LAEN

LEDI

LEDO

ABEN*

LDS

LA[7:1]

LWORD

CY7C960

CY7C961

REGION/

AMTABLE CY7C964 CONTROLLER

POWER-ON

RESET

GENERATOR

AM[5:0]

SYSRESET*

AS*

DS0*

DS1*

DTACK*

WRITE*

BR*

BBSY*

BERR*

BGIN*

BGOUT*

CLK

REGION[3:0]

IRQ*

IACK*

IACKIN*

IACKOUT*

DATA BYTE

ENABLE

CONTROLLER

DATABYTE

LANE

DECODER

LOCAL

CONTROL

CIRCUIT

DRAM

CONTROLLER

REFRESH

CONTROLLER

TIMING

GENERATOR

VME

CONTROL

INTERFACE

VME

INTERRUPT

INTERFACE

CS[5:0]

DBE[3:0]

LACK*

LBERR*

LDEN*

PREN*

SWDEN*

R/W

RAS*

CAS*

ROW

COL

LIRQ*

D64

STROBE

DENO*

DENIN*

DENIN1*

LADI

LAEN

LEDI

LEDO

ABEN*

LDS

MWB*

BLT

LADO

FC1

LAEN321

VMECNT

LA[7:1]

LWORD

LOCAL

ADDRESS

CONTROLLER

CHIPSELECT

OUTPUT

PATTERN TABLE

LD[7:0]

DMA CHANNEL

REGISTERS

DMA

CONTROLLER

LOCK

CONTROLLER

Top View

TQFP

c960–2

64 63 6162 60

32 33

3130

59 58

18 19 2120 22 23 2625 2728 2924

53 52 5051 4957 56 LA7

AM1

GND

R/W

SWDEN*

RAS*/CS4

CAS*/CS5

AM2

ROW/CS2

PREN*

LA6

LA5

LA4

IRQ*

LA3

LA1

AM5

VCC

DS1*

LWORD

LAEN

LA2

DTACK*

D64

LEDO

LEDI

IACKOUT*

IACKIN*

IACK*

AS*

LADI

DENO*

LACK*

LIRQ*

LDEN*

CS0

CS1

AM3

GND

REGION1

REGION0

DENIN*

REGION2

5455

COL/CS3

GND

AM0

VCC

DBE1

DBE2

DBE3

DBE0

STROBE

ABEN*

GND

DS0*

VCC

LDS

DENIN1*

VCC

WRITE*

REGION3/CS2

AM4

CY7C960 Pin Configuration

CY7C961 Logic Block Diagram

c960–3

SYSRESET*

CLK

SELECTLM

CY7C960

CY7C961

Functional Description (contin ued)

The CY7C960 controls a bridge be tween the VMEb us and lo-

cal DRAM and I/O. Once programmed, the CY7C960 pro vides

acti vities such as DRAM refresh and l ocal I/O handshaking i n

a manner that requires no additional local circuitry. The VME-

bus control signals are connected directly to the CY7C960.

The VM Ebus add res s and data signal s ar e connect ed to com -

panion address/data transceivers w hich are controlled by t he

CY7C960. The CY7C964 VMEb us Interf ace Logi c Circuit is an

idea l com panion de vic e: the CY7C964 prov ides a sl ice o f dat a

and address logic that has been optimized for VM E64 trans-

actions. In addition to providing the specified drive strength

and ti m ing for VME64 transactions , th e CY7C964 contains al l

the circuitry needed to mu lt iplex the address/data bus for m ul-

tiplexed VMEbus transactions. It contains counters and latch-

es need ed during BLT operations; and it al so contain s address

com parators which can be used in the board’s Slave Address

Decoder. For a 6U or 9U application, four CY7C964 devices

are controlled by a single CY7C960. For 3U applications, the

CY7C960 controls two CY7C964 devices and an address

latch.

The desi gn of the CY7C96 0 makes it u nnecessary to kno w the

details of the VMEbus transaction timing and protocol. The

com ple x VMEb us acti vities ar e tr anslat ed by CY7C960 t o s im-

ple l ocal cycles invol ving a f ew f amili ar control signal s. Simil ar-

ly, it is not necessary to understand the operation of the com-

panion de vice, CY7C964: all control sequences for the part are

genera ted automati cally by the CY7C960 in r esponse to VME-

bu s or local acti vity. If more information is desired, consult the

CY7C964 chapt er in the

VIC64 Desi gn Notes

(a v ail ab l e sep a-

rately).

VMEbus transactions supported by the CY7C960 include D8,

D16, D32 (incl. UAT), MD32, D64, A16, A24, A32, A40, A64

single-cycle and block-transfer reads and wr ites, Read-Modi-

fy-Write cycles (incl. multiplexed), and Address-only (with or

without Handshake). The CY7C960 functions as a VMEbus

Interrupter, and supports the new Auto Slot ID standard and

CR/CSR space. The CY7C960 also han dles LOCK cycl es, al -

though full LOCK support is not possible within the constrai nts

of the CY7C960 pi nout. Full LOCK support is pro vided by the

CY7C961.

On the lo cal side , no CPU is needed to pro gram the CY7C960 ,

nor to man age transac tions. All prog rammable par ameters are

initialized through the use of either the VMEb us, a serial PROM, or

some other local circuit. As the CY7C960 incorporates a reliable

pow er - on re se t c ir cui t , par a met ers ar e sel f -lo ad ed by th e de vi c e at

power-up or after a system reset. If the VMEbus is used to provide

par amet ers , a VM Ebus Master pro vides the progr ammin g inf orma-

tion using a protocol, described in the User’s Gu ide, w hich is com-

pliant with the Auto Slot ID protocol from the new VME64 specifica-

tion.

Top View

TQFP

10099 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 3637 3833

89 88 8687 8593 92 84 LA7

AM2

DBE0

AM0

SWDEN*

RAS*/CS4

LD3

CAS*/CS5

LD4

PREN*

LA6

LA5

LD7

LA4

SELECTLM*

LAEN321

IRQ*

LA3

GND

AM5

VCC

LA1

DTACK*

GND

DS0*

IACKOUT*

IACKIN*

BGOUT*

IACK*

MWB*

DENO*

LACK*

LIRQ*

LDEN*

LD1

CS0

VCC

AM3

AM4

BERR*

GND

VMECNT

REGION2

REGION3/CS2

9091

LBERR*

LD5

COL/CS3

AM1

GND

BR*

ROW/CS2

AS*

LADI

STROBE

BGIN*

LA2

BBSY*

VCC

LD2

CS1

DS1*

LWORD

FC1

LDS

DENIN1*

LAEN

VCC

LD6

DBE1

GND

DBE2

DBE3

R/W

LD0

CLK

WRITE*

REGION1

REGION0

DENIN*

VCC

BLT

SYSRESET*

LADO

D64

LEDO

83 82 81 80 79 78 77 76

43 44 4546 47 48 49

LEDI

c960–4

CY7C961 Pin Configuration

ABEN*

CY7C960

CY7C961

To assist in generating the configuration file, a Win-

dows™-based program is available which guides the user through

the process of selecting appropriate options. Contact your Sales

Office for further details.

The CY7C961 is a true s uperset of t he CY7C960. Signal pins

hav e been add ed to cont rol CY7C964 DMA fu nctions. Existin g

VMEbus input pins have been changed to bidirectional and

augmented to complete a master interface. A data port and

chip select signal (SELECTLM*) complete the pin additions.

As a VMEbus Slave, the CY7C961 behaves in every respect

like the CY7C960. It simply has more pins, a master block

tr ansfer facility, and (becau se of the addit ion of t he BBSY* con-

necti on) full lock cycle suppor t.

F r om a system persp ect iv e, the CY7C961 ma ster b loc k tr ans-

f er capabi lit y can be v ie wed as a DMA ch annel that resi des on

the slave card, but is controlled over the VMEbus by one or

more VM Ebus masters or programmed from the local bus.

The CY7C961 master b l ock f ac ility provi des “b loc k tran sf er on

demand” capability for slave cards built around the Cypress

CY7C961/CY7C964 chipset. This facility allows one or many

VMEbus masters to write short series of commands to the

slave card, telling it how much data to move, where to get it

from, where to put it, and what transfer protocol to use while

moving it. Block s can b e moved ov er th e VMEbus as indiv isib le

single cycles or BLTs. The protocol menu includes D8, D16,

D32, MD32, or D64. A16, A24, A32, A40, and A64 address

spaces can be specified. Burst lengths from 16 bytes to 8

megab ytes can be re quested. Eight regis ters accessible from

the VMEbus make the facility simple to configure and simple

to con trol . The f ac ility has a b usy semap hore, a VMEb us Int er-

rupt on completion feature with a programmable Status/ID

byte, and a built in requester and bus grant daisy chain.

System Diagram Using the CY7C960

SWDEN

DBE[3:0], RW

LACK*

RAS*,CAS*, ROW,COL

LA[31:0]

D[31:16]

SWAP

BUFFER

LD[15:0]

LA[31:0]

CY7C964

DRAMMEMORY I/O

LIRQ*

DECODER

REGION

LA [7:1, LWORD]

A [31:1], LWORD*

VMEINTERRUPT BUS

VME ADDRESS BUS

VMEDATABUS

CY7C964 CY7C964CY7C964 CY7C960

CS[2:0]

IRQ*

IACK*

IACKIN*

IACKOUT*

DS1/0*

DTACK

WRITE*

SYSRESET*

D[31:0]

AM[5:0]

AS*

D[7:0]

D[15:8]

A[7:1], LWORD*

A[15:8]

D[23:16]

A[23:16]

D[31:24]

A[31:24]

c960–5

VCOMP

CY7C960

CY7C961

DC Specifications - VMEbus Signals AS*, DS1*, DS0*, DTACK*, BBSY

Parameter Description Test Conditions Comm. Industrial Military Units

VIH Minimum High-Level

Input Voltage 2.0 2.0 2.0 V

VIL Maximum Low-Level

Input Voltage 0.8 0.8 0.8 V

VOH Minimum High-Level

Output V oltage VCC = Min.,

IOH = 2.4

–16 mA 2.4

–10 mA 2.4

–9 mA V

VOL Maximum Low-Lev el

Outp ut Vo lt ag e VCC = Min.,

IOL = 0.6

64 mA 0.6

60 mA 0.6

52 mA V

ILMaximum Input

Leakage Current VCC = Max.,

GND < VIN < VCC ±5 ±5 ±5 µA

VIK Input Clamp Voltage VCC = Min., IIN = –18 mA –1.2 –1.2 –1.2 V

IOZ Maximum Output

Leakage Current VCC = Max.

GND < VOUT < VCC

Outputs Disabled

±10 ±10 ±10 µA

DC Specifications - VMEbus Signals AM5, AM4, AM3, AM2, AM1, AM0, IRQ*, BERR*, Write , BR[1]

Parameter Description Test Conditions Comm. Industrial Military Units

VIH Maximum High-Level

Input Voltage 2.0 2.0 2.0 V

VIL Maximum Low-Level

Input Voltage 0.8 0.8 0.8 V

VOH Mi nim um H igh -Le vel

Output V oltage VCC = Min.,

IOH = 2.4

–16 mA 2.4

–10 mA 2.4

–9 mA V

VOL Mi ni m u m Low-Lev e l

Outp ut Vo lt ag e VCC = Min.,

IOL = 0.6

48 mA 0.6

44 mA 0.6

38 mA V

ILMaximum Input

Leakage Current VCC = Max.,

GND < VIN < VCC ±5 ±5 ±5 µA

VIK Input Clamp Voltage VCC = Min., IIN = –18 mA –1.2 –1.2 –1.2 V

IOZ Maximum Output

Leakage Current VCC = Max.

GND < VOUT < VCC

Outputs Disabled

±5 ±5 ±10 µA

DC Specifi cati ons - All Other Output Signals[2]

Parameter Description Test Conditions Comm. Industrial Military Units

VIH Maximum High-Level

Input Voltage 2.0 2.0 2.0 V

VIL Maximum Low-Level

Input Voltage 0.8 0.8 0.8 V

VOH Mi nim um H igh -Le vel

Output V oltage VCC = Min.,

IOH = 2.4

–16 mA 2.4

–10 mA 2.4

–9 mA V

VOL Mi ni m u m Low-Lev e l

Outp ut Vo lt ag e VCC = Min.,

IOL = 0.6

20 m A 0.6

18 mA 0.6

16 mA V

ILMaximum Input

Leakage Current VCC = Max.,

GND < VIN < VCC ±5 ±5 ±5 µA

VIK Input Clamp Voltage VCC = Min., IIN = –18 mA –1.2 –1.2 –1.2 V

IOZ Maximum Output

Leakage Current VCC = Max.

GND < VOUT < VCC

Outputs Disabled

±5 ±5 ±10 µA

Notes:

1. The BERR* signal has an on-chip pull-up resistor. For this signal the IOZ value is modified by Pullup/Pulldown Current.

2. Some signals have an on-chip pull-up or pull-down resistors. For these signals IOZ value is modified.

CY7C960

CY7C961