Mitsubishi single-chip microcomputer
Mitsubishi Electric Corporation Kitaitami Works
Mitsubishi Electric Semiconductor System Corporation
REV.A1
M30218 Group
User’s manual (tentative)
Specifications written in this user's manual are believed to be accurate, but are
not guaranteed to be entirely free of error.
Specifications in this manual may be changed for functional or performance im-
provements. Please make sure your manual is the latest edition.
Keep safety first in your circuit designs!
Notes regarding these materials
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
●These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.
●Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
●All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication
of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
by various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).
●When using any or all of the information contained in these materials, including
product data, diagrams, charts, programs, and algorithms, please be sure to evaluate
all information as a total system before making a final decision on the applicability of
the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information
contained herein.
●Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
●The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
or reproduce in whole or in part these materials.
●If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
ductor product distributor for further details on these materials or the products con
tained therein.
Preface
This user's manual describes the function and
features of the Mitsubishi M30218 Group CMOS
16-bit microcomputer. The software features are
explained to help designers take full advantage
of the M16C functions.
For details about the software, please refer to
the “M16C/60, M16C/20 series software manual”,
and for the development support tools, please
refer to the related instruction manual.
How to Use This Manual
This user's manual is written for the M30218 group.
The reader of this manual is expected to have the basic knowledge of electric and logic
circuits and microcomputers.
This manual is for the use of the models below.
• M30217MA-XXXXFP
• M30218MC-XXXXFP
• M30218FCFP
These products have similar features except for the memories, which differ from one product to
another. This manual gives descriptions of M30218MC-XXXXFP. Memories built-in are as shown
below. Be careful when writing a program, as the memories have different capacities.
The figure of each register configuration describes its functions, contents at reset, and attributes
as follows :
• Bit attribute R.....Read W.....Write
O.....Possible to read O.....Possible to write
X.....Impossible to read X.....Impossible to write
Bit attribute
RAM size
(Byte)
12K
1K
512
M30218MC-XXXXFP
M30218FCFP
128K ROM size
(Byte)
M30217MA-XXXXFP
5K
96K
T
A
1
O
S
T
A
2
O
S
T
A
0
O
S
O
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
gS
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
O
N
S
F0
3
8
21
60
0
X
0
0
0
0
02
T
i
m
e
r
A
0
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
1
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
2
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
3
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
4
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
A
3
O
S
T
A
4
O
S
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
T
A
0
T
G
L
T
A
0
T
G
H
0
0
:
I
n
p
u
t
o
n
T
A
0I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
4
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
1
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
T
i
m
e
r
A
0
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
b
7
b
6
N
o
t
e
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
W
h
e
n
T
A
iI
N
i
s
s
e
l
e
c
t
e
d
,
T
A
iO
U
T
a
s
s
i
g
n
e
d
o
n
s
a
m
e
p
i
n
c
a
n
n
o
t
b
e
u
s
e
d
.
(
i
=
0
t
o
4
)
W
R
1
:
T
i
m
e
r
s
t
a
r
t
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
i
s
“
0
”
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e@i
n
d
e
t
e
r
m
i
n
a
t
e
.
This manual comprises of five chapters. Use the suggested chapters as a reference for the
following topics:
* To understand hardware specifications ................................................... Chapter 1 Hardware
* To understand the basic way of using peripheral
features and the operation timing................................Chapter 2 Peripheral Functions Usage
* To observe applications of
peripheral features ........................Chapter 3 Examples of Peripheral Functions Applications
* To understand interrupt timing in detail ....................................................Chapter 4 Interrupts
* To understand standard data............................................Chapter 5 Standard Characteristics
This manual includes a quick reference immediately following the Table of Contents, indicate
the page of the topic to be pursued.
* To find a page describing a specific register
by the register address............................... Quick Reference to Pages Classified by Address
M16C Family-related document list
Usages
(Microcomputer development flow)
Outline design
of system
Selection of
microcomputer
Detail design
of system
Hard-
ware
devel-
opment
System
evaluation
Soft-
ware
devel-
opment
Contents
Hardware specifications (pin assignment,
memory map, specifications of peripheral func-
tions, electrical characteristics, timing charts)
Detailed description about hardware specifica-
tions, operation, and application examples
(connection with peripherals, relationship with
software)
Method for creating programs using assembly
and C languages
Detailed description about operation of each
instruction (assembly language)
Hardware
Type of document
Data sheet and
data book
User’s manual
Software
M16C Family M16C/80 Series M16C/80 Group
M16C/60 Series M16C/60 Group
M16C/61 Group
M16C/62 Group
M16C/20 Series M16C/20 Group
M16C/21 Group
M16C Family Line-up
Programming
manual
Software manual
Table of Contents
Chapter 1 Hardware ________________________________________
Description ............................................................................................................................................2
Pin Description......................................................................................................................................7
Memory .................................................................................................................................................9
Central Processing Unit (CPU) ...........................................................................................................12
Reset...................................................................................................................................................15
Software Reset ...................................................................................................................................18
Clock Generating Circuit.....................................................................................................................19
Clock Output .......................................................................................................................................23
Stop Mode ..........................................................................................................................................23
Wait Mode...........................................................................................................................................23
Status Transition Of BCLK..................................................................................................................24
Power Control .....................................................................................................................................25
Protection............................................................................................................................................27
Overview of Interrupt...........................................................................................................................28
Watchdog Timer..................................................................................................................................46
DMAC .................................................................................................................................................48
FLD Controller.....................................................................................................................................54
Timer...................................................................................................................................................71
Timer A ...............................................................................................................................................72
Timer B ...............................................................................................................................................82
Serial I/O.............................................................................................................................................88
Serial I/O2.........................................................................................................................................102
A-D Converter...................................................................................................................................115
D-A Converter...................................................................................................................................125
CRC Calculation Circuit ....................................................................................................................127
Programmable I/O Ports ...................................................................................................................129
Exclusive High-breakdown-voltage Output Ports .............................................................................129
MASK OPTION OF PULL-DOWN RESISTOR (object product: mask ROM version) ......................135
Flash Memory ...................................................................................................................................154
Chapter 2 Peripheral Functions Usage ________________________
2.1 Protect ........................................................................................................................................178
2.1.1 Overview..............................................................................................................................178
2.1.2 Protect Operation.................................................................................................................178
2.2 Timer A .......................................................................................................................................180
2.2.1 Overview..............................................................................................................................180
2.2.2 Operation of Timer A (timer mode) ......................................................................................186
2.2.3 Operation of Timer A (timer mode, gate function selected) .................................................188
2.2.4 Operation of Timer A (timer mode, pulse output function selected) ....................................190
2.2.5 Operation of Timer A (event counter mode, reload type selected) ......................................192
2.2.6 Operation of Timer A (event counter mode, free run type selected)....................................194
2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode se-
lected)..................................................................................................................................196
2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode
selected) ..............................................................................................................................198
2.2.9 Operation of Timer A (one-shot timer mode) .......................................................................200
2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected).............................202
2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) ..........204
2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) ............206
2.2.13 Precautions for Timer A (timer mode)................................................................................208
2.2.14 Precautions for Timer A (event counter mode)..................................................................209
2.2.15 Precautions for Timer A (one-shot timer mode).................................................................210
2.2.16 Precautions for Timer A (pulse width modulation mode) ...................................................211
2.3 Timer B .......................................................................................................................................212
2.3.1 Overview..............................................................................................................................212
2.3.2 Operation of Timer B (timer mode) ......................................................................................216
2.3.3 Operation of Timer B (event counter mode) ........................................................................218
2.3.4 Operation of Timer B (pulse period measurement mode) ...................................................220
2.3.5 Operation of Timer B (pulse width measurement mode) .....................................................222
2.3.6 Precautions for Timer B (timer mode, event counter mode)................................................224
2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) ...........................225
2.4 Clock-Synchronous Serial I/O.....................................................................................................226
2.4.1 Overview..............................................................................................................................226
2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) .....................232
2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock
output from multiple pins function selected) ........................................................................236
2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)...........................240
2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) ................................................244
2.5 Clock-Asynchronous Serial I/O (UART)......................................................................................246
2.5.1 Overview..............................................................................................................................246
2.5.2 Operation of Serial I/O (transmission in UART mode).........................................................254
2.5.3 Operation of Serial I/O (reception in UART mode) ..............................................................258
2.6 Serial I/O2...................................................................................................................................262
2.6.1 Overview..............................................................................................................................262
2.6.2 Serial I/O2 connection examples .........................................................................................267
2.6.3 Serial I/O2 modes ................................................................................................................269
2.6.4 Serial I/O2 Operations (transmission in 8-bit serial I/O mode) ...........................................270
2.6.5 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode)......274
2.6.6 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode, using
handshake signal) ...............................................................................................................278
2.6.7 Precautions for Serial I/O2...................................................................................................282
2.7 FLD (VFD) Controller ..................................................................................................................286
2.7.1 Overview..............................................................................................................................286
2.7.2 FLD operation (FLD automatic display and key-scan using segments) ..............................296
2.7.3 FLD operation (FLD automatic display and key-scan using digits)......................................302
2.7.4 FLD operation (FLD display and key-scan using segment by software) .............................306
2.7.5 FLD operation (Display with digit expander M35501FP) .....................................................312
2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy) ...................318
2.7.7 Precautions for FLD controller .............................................................................................325
2.8 A-D Converter.............................................................................................................................326
2.8.1 Overview..............................................................................................................................326
2.8.2 Operation of A-D converter (one-shot mode) ......................................................................332
2.8.3 Operation of A-D Converter (in repeat mode)......................................................................334
2.8.4 Operation of A-D Converter (in single sweep mode) ...........................................................336
2.8.5 Operation of A-D Converter (in repeat sweep mode 0) .......................................................338
2.8.6 Operation of A-D Converter (in repeat sweep mode 1) .......................................................340
2.8.7 Precautions for A-D Converter.............................................................................................342
2.8.8 Method of A-D Conversion (10-bit mode) ............................................................................343
2.8.9 Method of A-D Conversion (8-bit mode) ..............................................................................345
2.8.10 Absolute Accuracy and Differential Non-Linearity Error ....................................................347
2.8.11 Internal Equivalent Circuit of Analog Input.........................................................................349
2.8.12 Sensor’s Output Impedance under A-D Conversion..........................................................350
2.9 D-A Converter.............................................................................................................................352
2.9.1 Overview..............................................................................................................................352
2.9.2 D-A Converter Operation .....................................................................................................353
2.10 DMAC .......................................................................................................................................354
2.10.1 Overview............................................................................................................................354
2.10.2 Operation of DMAC (one-shot transfer mode)...................................................................358
2.10.3 Operation of DMAC (repeated transfer mode)...................................................................360
2.11 CRC Calculation Circuit ............................................................................................................362
2.11.1 Overview............................................................................................................................362
2.11.2 Operation of CRC Calculation Circuit ................................................................................363
2.12 Watchdog Timer .......................................................................................................................364
2.12.1 Overview............................................................................................................................364
2.12.2 Operation of Watchdog Timer............................................................................................366
2.13 Address Match Interrupt ...........................................................................................................368
2.13.1 Overview............................................................................................................................368
2.13.2 Operation of Address Match Interrupt................................................................................370
2.14 Power Control ...........................................................................................................................372
2.14.1 Overview............................................................................................................................372
2.14.2 Stop Mode Set-Up .............................................................................................................377
2.14.3 Wait Mode Set-Up .............................................................................................................378
2.14.4 Precautions in Power Control ............................................................................................379
2.15 Programmable I/O Ports ...........................................................................................................380
2.15.1 Overview............................................................................................................................380
Chapter 3 Examples of Peripheral functions Applications ________
3.1 Long-Period Timers ................................................................................................................388
3.2 Variable-Period Variable-Duty PWM Output...........................................................................392
3.3 Delayed One-Shot Output ......................................................................................................396
3.4 Buzzer Output.........................................................................................................................400
3.5 Solution for External Interrupt Pins Shortage .........................................................................402
3.6 Memory to Memory DMA Transfer .........................................................................................404
3.7 Controlling Power Using Stop Mode.......................................................................................408
3.8 Controling Power Using Wait Mode........................................................................................412
Chapter 4 Interrupt_________________________________________
4.1 Overview of Interrupt ..................................................................................................................408
4.1.1 Type of Interrupts.................................................................................................................408
4.1.2 Software Interrupts ..............................................................................................................409
4.1.3 Hardware Interrupts .............................................................................................................420
4.1.4 Interrupts and Interrupt Vector Tables .................................................................................421
4.2 Interrupt Control..........................................................................................................................423
4.2.1 Interrupt Enable Flag ...........................................................................................................425
4.2.2 Interrupt Request Bit............................................................................................................425
4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) ....................426
4.2.4 Rewrite the interrupt control register....................................................................................427
4.3 Interrupt Sequence .....................................................................................................................428
4.3.1 Interrupt Response Time .....................................................................................................428
4.3.2 Variation of IPL when Interrupt Request is Accepted ..........................................................429
4.3.3 Saving Registers..................................................................................................................430
4.4 Returning from an Interrupt Routine ...........................................................................................432
4.5 Interrupt Priority ..........................................................................................................................432
4.6 Multiple Interrupts .......................................................................................................................434
4.7 Precautions for Interrupts ...........................................................................................................436
Chapter 5 Standard Characteristics___________________________
5.1 Standard DC Characteristics ......................................................................................................440
5.1.1 Standard Ports Characteristics ............................................................................................440
5.1.2 Characteristics of ICC-f(XIN) ...............................................................................................444
5.2 Standard Characteristics of A-D Converter ................................................................................446
5.3 Standard Characteristics of D-A Converter ................................................................................448
5.4 Standard Characteristics of Pull-Up Resistor .............................................................................451
This page kept blank for layout purposes.
Quick Reference to Pages Classified by Address
0
0
4
0
1
6
0
0
4
1
1
6
0
0
4
2
1
6
0
0
4
3
1
6
0
0
4
4
1
6
0
0
4
5
1
6
0
0
4
6
1
6
0
0
4
7
1
6
0
0
4
8
1
6
0
0
4
9
1
6
0
0
4
A
1
6
0
0
4
B
1
6
0
0
4
C
1
6
0
0
4
D
1
6
0
0
4
E
1
6
0
0
4
F
1
6
0
0
5
0
1
6
0
0
5
1
1
6
0
0
5
2
1
6
0
0
5
3
1
6
0
0
5
4
1
6
0
0
5
5
1
6
0
0
5
6
1
6
0
0
5
7
1
6
0
0
5
8
1
6
0
0
5
9
1
6
0
0
5
A
1
6
0
0
5
B
1
6
0
0
5
C
1
6
0
0
5
D
1
6
0
0
5
E
1
6
0
0
5
F
1
6
0
3
4
0
1
6
0
3
4
1
1
6
0
3
4
2
1
6
0
3
4
3
1
6
0
3
4
4
1
6
0
3
4
5
1
6
0
3
4
6
1
6
0
3
4
7
1
6
0
3
4
8
1
6
0
3
4
9
1
6
0
3
4
A
1
6
0
3
4
B
1
6
0
3
4
C
1
6
0
3
4
D
1
6
0
3
4
E
1
6
0
3
4
F
1
6
0
3
5
0
1
6
0
3
5
1
1
6
0
3
5
2
1
6
0
3
5
3
1
6
0
3
5
4
1
6
0
3
5
5
1
6
0
3
5
6
1
6
0
3
5
7
1
6
0
3
5
8
1
6
0
3
5
9
1
6
0
3
5
A
1
6
0
3
5
B
1
6
0
3
5
C
1
6
0
3
5
D
1
6
0
3
5
E
1
6
0
3
5
F
1
6
0
0
0
0
1
6
0
0
0
1
1
6
0
0
0
2
1
6
0
0
0
3
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
0
A
1
6
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
0
0
0
E
1
6
0
0
0
F
1
6
0
0
1
0
1
6
0
0
1
1
1
6
0
0
1
2
1
6
0
0
1
3
1
6
0
0
1
4
1
6
0
0
1
5
1
6
0
0
1
6
1
6
0
0
1
7
1
6
0
0
1
8
1
6
0
0
1
9
1
6
0
0
1
A
1
6
0
0
1
B
1
6
0
0
1
C
1
6
0
0
1
D
1
6
0
0
1
E
1
6
0
0
1
F
1
6
I
N
T
1
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
1
I
C
)
T
i
m
e
r
B
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
B
0
I
C
)
T
i
m
e
r
B
2
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
B
2
I
C
)
T
i
m
e
r
A
1
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
A
1
I
C
)
T
i
m
e
r
A
3
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
A
3
I
C
)
U
A
R
T
0
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
0
T
I
C
)
I
N
T
2
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
2
I
C
)
I
N
T
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
0
I
C
)
T
i
m
e
r
B
1
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
B
1
I
C
)
T
i
m
e
r
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
A
0
I
C
)
T
i
m
e
r
A
2
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
A
2
I
C
)
T
i
m
e
r
A
4
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
A
4
I
C
)
U
A
R
T
0
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
0
R
I
C
)
U
A
R
T
1
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
T
I
C
)
U
A
R
T
1
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
R
I
C
)
D
M
A
1
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
M
1
I
C
)
D
M
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
M
0
I
C
)
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
I
C
)
D
M
A
0
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
M
0
C
O
N
)
D
M
A
0
s
o
u
r
c
e
p
o
i
n
t
e
r
(
S
A
R
0
)
D
M
A
0
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
T
C
R
0
)
D
M
A
0
d
e
s
t
i
n
a
t
i
o
n
p
o
i
n
t
e
r
(
D
A
R
0
)
D
M
A
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
M
1
C
O
N
)
D
M
A
1
s
o
u
r
c
e
p
o
i
n
t
e
r
(
S
A
R
1
)
D
M
A
1
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
T
C
R
1
)
D
M
A
1
d
e
s
t
i
n
a
t
i
o
n
p
o
i
n
t
e
r
(
D
A
R
1
)
W
a
t
c
h
d
o
g
t
i
m
e
r
s
t
a
r
t
r
e
g
i
s
t
e
r
(
W
D
T
S
)
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
W
D
C
)
P
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
0
(
P
M
0
)
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
0
(
R
M
A
D
0
)
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
1
(
R
M
A
D
1
)
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
C
M
0
)
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
C
M
1
)
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
(
A
I
E
R
)
P
r
o
t
e
c
t
r
e
g
i
s
t
e
r
(
P
R
C
R
)
P
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
1
(
P
M
1
)
0
0
2
0
1
6
0
0
2
1
1
6
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
0
0
2
9
1
6
0
0
2
A
1
6
0
0
2
B
1
6
0
0
2
C
1
6
0
0
2
D
1
6
0
0
2
E
1
6
0
0
2
F
1
6
0
0
3
0
1
6
0
0
3
1
1
6
0
0
3
2
1
6
0
0
3
3
1
6
0
0
3
4
1
6
0
0
3
5
1
6
0
0
3
6
1
6
0
0
3
7
1
6
0
0
3
8
1
6
0
0
3
9
1
6
0
0
3
A
1
6
0
0
3
B
1
6
0
0
3
C
1
6
0
0
3
D
1
6
0
0
3
E
1
6
0
0
3
F
1
6
4
3
5
0
5
1
5
1
5
1
5
0
5
1
5
1
5
1
4
7
1
8
2
2
4
3
2
7
4
3
3
4
5
7
5
8
5
9
A
d
d
r
e
s
sR
e
g
i
s
t
e
rP
a
g
eA
d
d
r
e
s
sR
e
g
i
s
t
e
rP
a
g
e
I
N
T
3
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
3
I
C
)
I
N
T
4
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
4
I
C
)
I
N
T
5
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
N
T
5
I
C
)3
4
3
4
S
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
S
I
O
I
C
)
F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
F
L
D
I
C
)
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
3
F
P
R
)
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
(
P
5
D
O
R
)
T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
O
F
F
2
)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
(
F
L
D
D
P
)
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
F
L
D
C
O
N
)
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
(
P
6
D
O
R
)
P
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
4
F
P
R
)
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
2
F
P
R
)
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
D
I
S
P
)
T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
O
F
F
1
)
F
L
D
m
o
d
e
r
e
g
i
s
t
e
r
(
F
L
D
M
)
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
(
S
I
O
2
D
P
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
S
I
O
2
C
O
N
1
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
S
I
O
2
C
O
N
2
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
/
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
S
I
O
2
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
(
S
I
O
2
C
O
N
3
)
5
7
5
7
5
6
1
0
5
1
0
5
1
0
4
1
0
4
1
0
5
Quick Reference to Pages Classified by Address
A
d
d
r
e
s
sR
e
g
i
s
t
e
rP
a
g
eA
d
d
r
e
s
sR
e
g
i
s
t
e
rP
a
g
e
0
3
8
0
1
6
0
3
8
1
1
6
0
3
8
2
1
6
0
3
8
3
1
6
0
3
8
4
1
6
0
3
8
5
1
6
0
3
8
6
1
6
0
3
8
7
1
6
0
3
8
8
1
6
0
3
8
9
1
6
0
3
8
A
1
6
0
3
8
B
1
6
0
3
8
C
1
6
0
3
8
D
1
6
0
3
8
E
1
6
0
3
8
F
1
6
0
3
9
0
1
6
0
3
9
1
1
6
0
3
9
2
1
6
0
3
9
3
1
6
0
3
9
4
1
6
0
3
9
5
1
6
0
3
9
6
1
6
0
3
9
7
1
6
0
3
9
8
1
6
0
3
9
9
1
6
0
3
9
A
1
6
0
3
9
B
1
6
0
3
9
C
1
6
0
3
9
D
1
6
0
3
9
E
1
6
0
3
9
F
1
6
0
3
A
0
1
6
0
3
A
1
1
6
0
3
A
2
1
6
0
3
A
3
1
6
0
3
A
4
1
6
0
3
A
5
1
6
0
3
A
6
1
6
0
3
A
7
1
6
0
3
A
8
1
6
0
3
A
9
1
6
0
3
A
A
1
6
0
3
A
B
1
6
0
3
A
C
1
6
0
3
A
D
1
6
0
3
A
E
1
6
0
3
A
F
1
6
0
3
B
0
1
6
0
3
B
1
1
6
0
3
B
2
1
6
0
3
B
3
1
6
0
3
B
4
1
6
0
3
B
5
1
6
0
3
B
6
1
6
0
3
B
7
1
6
0
3
B
8
1
6
0
3
B
9
1
6
0
3
B
A
1
6
0
3
B
B
1
6
0
3
B
C
1
6
0
3
B
D
1
6
0
3
B
E
1
6
0
3
B
F
1
6
D
M
A
1
r
e
q
u
e
s
t
c
a
u
s
e
s
e
l
e
c
t
r
e
g
i
s
t
e
r
(
D
M
1
S
L
)
D
M
A
0
r
e
q
u
e
s
t
c
a
u
s
e
s
e
l
e
c
t
r
e
g
i
s
t
e
r
(
D
M
0
S
L
)
U
A
R
T
0
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
(
U
0
M
R
)
U
A
R
T
0
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
U
0
T
B
)
U
A
R
T
0
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
U
0
R
B
)
U
A
R
T
1
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
(
U
1
M
R
)
U
A
R
T
1
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
U
1
T
B
)
U
A
R
T
1
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
U
1
R
B
)
T
i
m
e
r
A
0
(
T
A
0
)
T
i
m
e
r
A
1
(
T
A
1
)
T
i
m
e
r
A
2
(
T
A
2
)
T
i
m
e
r
B
0
(
T
B
0
)
T
i
m
e
r
B
1
(
T
B
1
)
T
i
m
e
r
B
2
(
T
B
2
)
C
o
u
n
t
s
t
a
r
t
f
l
a
g
(
T
A
B
S
R
)
O
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
(
O
N
S
F
)
T
i
m
e
r
A
0
m
o
d
e
r
e
g
i
s
t
e
r
(
T
A
0
M
R
)
T
i
m
e
r
A
1
m
o
d
e
r
e
g
i
s
t
e
r
(
T
A
1
M
R
)
T
i
m
e
r
A
2
m
o
d
e
r
e
g
i
s
t
e
r
(
T
A
2
M
R
)
T
i
m
e
r
B
0
m
o
d
e
r
e
g
i
s
t
e
r
(
T
B
0
M
R
)
T
i
m
e
r
B
1
m
o
d
e
r
e
g
i
s
t
e
r
(
T
B
1
M
R
)
T
i
m
e
r
B
2
m
o
d
e
r
e
g
i
s
t
e
r
(
T
B
2
M
R
)
U
p
-
d
o
w
n
f
l
a
g
(
U
D
F
)
T
i
m
e
r
A
3
(
T
A
3
)
T
i
m
e
r
A
4
(
T
A
4
)
T
i
m
e
r
A
3
m
o
d
e
r
e
g
i
s
t
e
r
(
T
A
3
M
R
)
T
i
m
e
r
A
4
m
o
d
e
r
e
g
i
s
t
e
r
(
T
A
4
M
R
)
T
r
i
g
g
e
r
s
e
l
e
c
t
r
e
g
i
s
t
e
r
(
T
R
G
S
R
)
U
A
R
T
0
b
i
t
r
a
t
e
g
e
n
e
r
a
t
o
r
(
U
0
B
R
G
)
U
A
R
T
0
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
U
0
C
0
)
U
A
R
T
0
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
U
0
C
1
)
U
A
R
T
1
b
i
t
r
a
t
e
g
e
n
e
r
a
t
o
r
(
U
1
B
R
G
)
U
A
R
T
1
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
U
1
C
0
)
U
A
R
T
1
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
U
1
C
1
)
U
A
R
T
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
U
C
O
N
)
C
R
C
d
a
t
a
r
e
g
i
s
t
e
r
(
C
R
C
D
)
C
R
C
i
n
p
u
t
r
e
g
i
s
t
e
r
(
C
R
C
I
N
)
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
(
C
P
S
R
F
)7
3
7
4
7
3
7
3
8
3
7
2
8
2
9
1
9
0
9
1
9
2
9
0
9
1
9
0
9
1
9
2
9
0
9
2
5
0
5
0
1
2
7
0
3
E
0
1
6
0
3
E
1
1
6
0
3
E
2
1
6
0
3
E
3
1
6
0
3
E
4
1
6
0
3
E
5
1
6
0
3
E
6
1
6
0
3
E
7
1
6
0
3
E
8
1
6
0
3
E
9
1
6
0
3
E
A
1
6
0
3
E
B
1
6
0
3
E
C
1
6
0
3
E
D
1
6
0
3
E
E
1
6
0
3
E
F
1
6
0
3
F
0
1
6
0
3
F
1
1
6
0
3
F
2
1
6
0
3
F
3
1
6
0
3
F
4
1
6
0
3
F
5
1
6
0
3
F
6
1
6
0
3
F
7
1
6
0
3
F
8
1
6
0
3
F
9
1
6
0
3
F
A
1
6
0
3
F
B
1
6
0
3
F
C
1
6
0
3
F
D
1
6
0
3
F
E
1
6
0
3
F
F
1
6
0
3
C
0
1
6
0
3
C
1
1
6
0
3
C
2
1
6
0
3
C
3
1
6
0
3
C
4
1
6
0
3
C
5
1
6
0
3
C
6
1
6
0
3
C
7
1
6
0
3
C
8
1
6
0
3
C
9
1
6
0
3
C
A
1
6
0
3
C
B
1
6
0
3
C
C
1
6
0
3
C
D
1
6
0
3
C
E
1
6
0
3
C
F
1
6
0
3
D
0
1
6
0
3
D
1
1
6
0
3
D
2
1
6
0
3
D
3
1
6
0
3
D
4
1
6
0
3
D
5
1
6
0
3
D
6
1
6
0
3
D
7
1
6
0
3
D
8
1
6
0
3
D
9
1
6
0
3
D
A
1
6
0
3
D
B
1
6
0
3
D
C
1
6
0
3
D
D
1
6
0
3
D
E
1
6
0
3
D
F
1
6
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
3
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
4
)
P
o
r
t
P
5
(
P
5
)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
7
(
P
7
)
P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
7
)
P
o
r
t
P
8
(
P
8
)
P
o
r
t
P
8
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
8
)
P
o
r
t
P
9
(
P
9
)
P
o
r
t
P
9
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
9
)
P
o
r
t
P
1
0
(
P
1
0
)
P
o
r
t
P
1
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
D
1
0
)
P
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
P
U
R
0
)
P
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
P
U
R
1
)
A
-
D
r
e
g
i
s
t
e
r
7
(
A
D
7
)
A
-
D
r
e
g
i
s
t
e
r
0
(
A
D
0
)
A
-
D
r
e
g
i
s
t
e
r
1
(
A
D
1
)
A
-
D
r
e
g
i
s
t
e
r
2
(
A
D
2
)
A
-
D
r
e
g
i
s
t
e
r
3
(
A
D
3
)
A
-
D
r
e
g
i
s
t
e
r
4
(
A
D
4
)
A
-
D
r
e
g
i
s
t
e
r
5
(
A
D
5
)
A
-
D
r
e
g
i
s
t
e
r
6
(
A
D
6
)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
A
D
C
O
N
0
)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
A
D
C
O
N
1
)
D
-
A
r
e
g
i
s
t
e
r
0
(
D
A
0
)
D
-
A
r
e
g
i
s
t
e
r
1
(
D
A
1
)
D
-
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
A
C
O
N
)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
A
D
C
O
N
2
)
1
1
8
1
1
8
1
1
7
1
2
6
1
2
6
1
2
6
1
3
2
1
3
2
1
3
2
1
3
2
1
3
3
F
l
a
s
h
m
e
m
o
r
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
F
C
O
N
0
)
(
N
o
t
e
)
F
l
a
s
h
m
e
m
o
r
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
F
C
O
N
1
)
(
N
o
t
e
)
F
l
a
s
h
c
o
m
m
a
n
d
r
e
g
i
s
t
e
r
(
F
C
M
D
)
(
N
o
t
e
)
N
o
t
e
:
T
h
i
s
r
e
g
i
s
t
e
r
i
s
o
n
l
y
e
x
i
s
t
i
n
f
l
a
s
h
m
e
m
o
r
y
v
e
r
s
i
o
n
.
1
5
5
1
3
2
1
3
2
Chapter 1
Hardware
2
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
------Table of Contents------
Description
The M30218 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These
single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They
also feature a built-in multiplier and DMAC, making them ideal for controlling musical instruments, house-
hold appliances and other high-speed processing applications.
The M30218 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Basic machine instructions .............Compatible with the M16C/60 series
• Memory capacity ............................ROM / RAM (See figure memory expansion)
• Shortest instruction execution time.100ns (f(XIN)=10MHz)
• Supply voltage ................................4.0V to 5.5V (f(XIN)=10MHz)
2.7V to 5.5V (f(XIN)=3.5MHz)(Note)
• Interrupts ........................................19 internal and 6 external interrupt sources, 4 software
• Multifunction 16-bit timer ................Timer A X 5, Timer B X 3
• FLD conrtoller .................................total 56 pins
(high-breakdown-voltage P-channel open-drain output : 52pins)
• Serial I/O.........................................2 channels for UART or clock synchronous,
1 channels for clock synchronous
(max.256 bytes automatic transfer function)
• DMAC .............................................2 channels (triggers: 15 sources)
• A-D converter .................................10 bits X 8 channels
• D-A converter .................................8 bits X 2 channels
• CRC calculation circuit ...................1 circuit
• Watchdog timer ..............................1 pin
• Programmable I/O ..........................48 pins
• High-breakdown-voltage output......52 pins
• Clock generating circuit ..................2 built-in clock generation circuit
(built-in feedback resistor, and external ceramic or quartz oscillator)
Note: Only mask ROM version.
Applications
Household appliances, office equipment, Audio etc.
Timer.............................................................71
Serial I/O .......................................................88
A-D Converter .............................................115
D-A Converter .............................................125
CRC Calculation Circuit ..............................127
Programmable I/O Ports .............................129
Flash memory .............................................154
Central Processing Unit (CPU) .....................12
Reset.............................................................15
Clock Generating Circuit ...............................19
Protection......................................................27
Interrupts.......................................................28
Watchdog Timer............................................46
DMAC ...........................................................48
FLD controller ...............................................54
Specifications written in this manual are believed
to be accurate, but are not guaranteed to be en-
tirely free of error.
Specifications in this manual may be changed for
functional or performance improvements. Please
make sure your manual is the latest edition.
3
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Pin Configuration
Figure 1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
Figure 1. Pin configuration (top view)
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
10
0
M
3
0
2
1
8
M
C
-XX
X
X
F
P
P
6
0
/
F
L
D
0
P
6
1
/
F
L
D
1
P
6
2
/
F
L
D
2
P
6
3
/
F
L
D
3
P
6
4
/
F
L
D
4
P
6
5
/
F
L
D
5
P
6
6
/
F
L
D
6
P
6
7
/
F
L
D
7
P
5
0
/
F
L
D
8
V
C
C
X
I
N
R
E
S
E
T
X
O
U
T
V
S
S
C
N
V
S
S
P
8
6
/
X
C
O
U
T
P
8
7
/
X
C
I
N
P
9
0
/
S
R
D
Y
2
P
7
6
/
T
A
3
I
N
/
T
A
1
O
U
T
/
C
L
K
1
P
7
7
/
T
A
4
I
N
/
T
A
2
O
U
T
/
C
T
S
1
/
R
T
S
1
/
C
L
K
S
1
P
9
4
/
S
O
U
T
2
P
9
5
/
S
C
L
K
2
1
P
9
6
/
D
A
1
/
S
C
L
K
2
2
P
9
7
/
D
A
0
/
C
L
K
O
U
T
/
D
I
M
O
U
T
P
9
2
/
S
S
T
B
2
P
9
3
/
S
I
N
2
P
7
3
/
T
A
0
I
N
/
T
A
3
O
U
T
P
7
2
/
T
B
2
I
N
P
9
1
/
S
B
U
S
Y
2
P
a
c
k
a
g
e
:
1
0
0
P
6
S
-
A
V
E
E
P
1
0
7
/
A
N
7
P
1
0
6
/
A
N
6
P
1
0
5
/
A
N
5
P
1
0
3
/
A
N
3
P
1
0
2
/
A
N
2
P
1
0
4
/
A
N
4
P
1
0
1
/
A
N
1
A
V
S
S
P
1
0
0
/
A
N
0
V
R
E
F
A
V
C
C
P
5
1
/
F
L
D
9
P
5
2
/
F
L
D
1
0
P
5
3
/
F
L
D
1
1
P
5
4
/
F
L
D
1
2
P
5
5
/
F
L
D
1
3
P
5
6
/
F
L
D
1
4
P
5
7
/
F
L
D
1
5
P
0
0
/
F
L
D
1
6
P
0
1
/
F
L
D
1
7
P
0
2
/
F
L
D
1
8
P
0
3
/
F
L
D
1
9
P
0
4
/
F
L
D
2
0
P
0
5
/
F
L
D
2
1
P
0
6
/
F
L
D
2
2
V
S
S
P
0
7
/
F
L
D
2
3
V
C
C
P
1
0
/
F
L
D
2
4
P
1
1
/
F
L
D
2
5
P
1
2
/
F
L
D
2
6
P
1
3
/
F
L
D
2
7
P
1
4
/
F
L
D
2
8
P
1
5
/
F
L
D
2
9
P
1
6
/
F
L
D
3
0
P
1
7
/
F
L
D
3
1
P
2
0
/
F
L
D
3
2
P
2
1
/
F
L
D
3
3
P
2
2
/
F
L
D
3
4
P
2
3
/
F
L
D
3
5
P
2
4
/
F
L
D
3
6
P
2
5
/
F
L
D
3
7
P
2
6
/
F
L
D
3
8
P
2
7
/
F
L
D
3
9
P
3
0
/
F
L
D
4
0
P
3
1
/
F
L
D
4
1
P
3
2
/
F
L
D
4
2
P
3
3
/
F
L
D
4
3
P
3
4
/
F
L
D
4
4
P
3
5
/
F
L
D
4
5
P
3
6
/
F
L
D
4
6
P
3
7
/
F
L
D
4
7
P
4
0
/
F
L
D
4
8
P
4
1
/
F
L
D
4
9
P
4
2
/
F
L
D
5
0
P
4
3
/
F
L
D
5
1
P
4
4
/
T
X
D
0
/
F
L
D
5
2
P
4
5
/
R
X
D
0
/
F
L
D
5
3
P
4
6
/
C
L
K
0
/
F
L
D
5
4
P
4
7
/
C
T
S
0
/
R
T
S
0
/
F
L
D
5
5
P
7
5
/
T
A
2
I
N
/
T
A
0
O
U
T
/
R
X
D
1
P
7
4
/
T
A
1
I
N
/
T
A
4
O
U
T
/
T
X
D
1
P
7
1
/
T
B
1
I
N
P
7
0
/
T
B
0
I
N
P
8
5
/
I
N
T
5
P
8
4
/
I
N
T
4
P
8
3
/
I
N
T
3
P
8
2
/
I
N
T
2
P
8
1
/
I
N
T
1
P
8
0
/
I
N
T
0
4
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Block Diagram
Figure 2 shows a block diagram of the M30218 group.
Block diagram of the M30218 group
Figure 2. Block diagram of M30218 group
AAAA
AAAA
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits
X
8 channels
)
SI/O2 (clock
synchronous
)
(256 bytes automatic transfer)
System clock generator
X
IN
-X
OUT
X
CIN
-X
COUT
M16C/60 series16-bit CPU core
I/O ports
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
8
R0LR0H
R1
HR1L
R
2
R
3
A0
A1
FB
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
Vector table
INTB
CRC arithmetic circuit (CCITT)
(Polynomial : X
16
+X
12
+X
5
+1)
Multiplier
888
Port P10
Port P9
Port P8
Port P7
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
Memory
ROM
(Note 1)
RAM (Note 2)
(includes FLDC,ASI/O RAM)
SB FLG
PC
Program counter
Fluorescent display function
(56 contorol pins)
(52 high-breakdown-voltage ports)
Serial I/O
UART/clock synchronous SI/O
(8 bits
X
2 channels)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
5
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
ROM
RAM
P3, P4, P7 to P10
P0 to P2, P5, P6
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
UART0, UART1
SI/O2
Table 1. Performance outline of M30218 group
Performance Outline
Table 1 shows a performance outline of M30218 group.
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 100ns(f(XIN)=10MHz)
See figure memory expansion
See figure memory expansion
8 bits x 6
8 bit x 5
16 bits x 5
16 bits x 3
(UART or clock synchronous) x 2
(Clock synchronous) x 1
(with automatic transfer function)
Fluorescent display 56 pins
A-D converter 10 bits x 8 channels
D-A converter 8 bits x 2
DMAC 2 channels (triggers :15 sources)
CRC calculation circuit 1 circuit (polynomial: X16 + X12 + X5 + 1)
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt
19 internal and 6 external sources, 4 software sources, 7 levels
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Supply voltage 4.0 to 5.5V (f(XIN)=10MHz)
2.7 to 5.5V (f(XIN)=3.5MHz) (Note)
Power consumption 18 mW (VCC=3V, f(XIN)=5MHz)
V
CC
-48V (output ports : P0 to P2, P5, P6, I/O ports : P3, P4
0
to P4
3
)
0 to VCC (I/O ports :P44 to P47, P7 to P10)
- 18mA (P0 to P3, P40 to P43, P5, P6)
:high-breakdown-voltage, P-channel open-drain
- 5mA (P44 to P47, P7 to P10)
5mA (P44 to P47, P7 to P10)
Operating ambient temperature –20 to 85oC
Device configuration CMOS silicon gate
Package 100-pin plastic mold QFP
Memory
capacity
I/O port
Output port
Multifunction
timer
Serial I/O
I/O withstand voltage
Output current
I/O
characteristics
H
L
Note: Only mask ROM version.
6
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Mitsubishi plans to release the following products in the M30218 group:
(1) Support for mask ROM version and flash memory version
(2) Memory capacity
(3) Package
100P6S : Plastic molded QFP (mask ROM version and flash memory version)
Figure 4. Type No., memory size, and package
Figure 3. ROM expansion
RAM size
(Byte)
12K
1K
512
M30218MC-XXXXFP
M30218FCFP
128K ROM size
(Byte)
M30217MA-XXXXFP
5K
96K
Package type:
FP : Package 100P6S-A
ROM No.
Omitted for flash memory version
ROM capacity:
2 : 16K bytes
4 : 32K bytes
6 : 48K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Type No. M 3 0 2 1 8 M C – X X X X F P
M16C/21 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Shows pull-down option type
7
Pin Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Pin Description
V
CC
, V
SS
CNV
SS
X
IN
X
OUT
AV
CC
AV
SS
V
EE
P0
0
/FLD
16
to
P0
7
/FLD
23
P1
0
/FLD
24
to
P1
7
/FLD
31
P2
0
/FLD
32
to
P2
7
/FLD
39
P3
0
/FLD
40
to
P3
7
/FLD
47
P4
0
/FLD
48
to
P4
7
/FLD
56
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
Analog power
supply input
pull-down
power source
Output port P0
Output port P1
Output port P2
I/O port P3
I/O port P4
Supply 2.7V(Note1) to 5.5 V to the V
CC
pin. Supply 0 V to the V
SS
pin.
Connect a bypass capacitor across the V
CC
pin and V
SS
pin.
Function
Connect it to the V
SS
pin.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X
IN
and the X
OUT
pins. To
use an externally derived clock, input it to the X
IN
pin and leave the
X
OUT
pin open.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS
.
This is an 8-bit CMOS output port and high-breakdown-voltage P-
channel open-drain output structure. A pull-down resistor is built in
between port P0 and V
EE
pin. At reset, this port is set to V
EE
level. P0
function as FLD controller output pins as selected by software.
This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
This is an 8-bit output port equivalent to P0. A pull-down resistor is not
built in between P2 and V
EE
pin (Note2). Pins in this port also function
as FLD controller output pins as selected by software.
This is an 8-bit I/O port. A pull-down resistor is not built in between P3
and V
EE
pin (Note2). It has an input/output port direction register that
allows the user to set each pin for input or output. This is low-voltage
input level, and high-breakdown-voltage P-channel open-drain output
structure. Pins in this port also function as FLD controller output pins as
selected by software.
This is an 8-bit I/O port equivalent to P3. This is low-voltage input level.
P4
0
to P4
3
is high-breakdown-voltage P-channel open-drain output
structure, P4
4
to P4
7
is CMOS output. A pull-down resistor is not built
in between P4(P4
0
to P4
3
) and V
EE
pin (Note2). Pins in this port also
function as FLD controller output pins as selected by software. P4
4
to
P4
7
also function as UART0 I/O pins as selected by software. When
set for input, the user can specify in units of four bits by software
whether or not they are tied to a pull-up resistor.
Pin name
Input
Input
Input
Output
Output
Output
Output
I/O type
Analog power
supply input
Input/output
Input/output
RESET
V
REF
This pin is a reference voltage input for the A-D converter.
Input
Reference
voltage input
Apply voltage supplied to pull-down resistors of ports P0 to P1,P5,P6.
P5
0
/FLD
8
to
P5
7
/FLD
15
Output port P5 This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
Output
P6
0
/FLD
0
to
P6
7
/FLD
7
Output port P6 This is an 8-bit output port equivalent to P0. Pins in this port also
function as FLD controller output pins as selected by software.
Output
8
Pin Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Pin Description
Signal name FunctionPin name I/O type
Input/output
Input/output
I/O port P9
I/O port P10
P9
0
to P9
7
P10
0
to P10
7
This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. P9
7
function as D-A converter output pins, clock
output pins (same frequency of X
IN
/8, X
IN
/32 or X
CIN
) and DIM signal
output pin of FLD controller as selected by software. P9
6
function as D-
A converter output pins and clock I/O pin of serial I/O with automatic
transfer as selected by software. P9
0
to P9
5
function as I/O pin of serial
I/O with automatic transfer as selected by software.
This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. Pins in this port also function as A-D converter
input pins as selected by software.
P7
0
to P7
7
I/O port P7 This is an 8-bit I/O port equivalent to P3. This is CMOS input/output.
When set for input, the user can specify in units of four bits by software
whether or not they are tied to a pull-up resistor. P7
0
to P7
2
function as
TimerB0 to B2 input pins as selected by software. P7
3
function as
TimerA0 I/O pin as selected by software. P7
4
to P7
7
function as
TimerA1 to A4 I/O pins, and UART1 I/O pins as selected by software.
Input/output
P8
0
to P8
7
I/O port P8 This is an 8-bit I/O port equivalent to P7. When set for input, the user
can specify in units of four bits by software whether or not they are tied
to a pull-up resistor. P8
0
to P8
5
function as external interrupt input pins
as selected by software. P8
6
,P8
7
function as sub-clock input pin as
selected by software. In this case, connect a quarts oscillator between
P8
6
(X
OUT
pin) and P8
7
(X
CIN
pin)
Input/output
Note 1: Supply 4.0V to 5.5V to the V
CC
pin in flash memory version.
Note 2: Port P2
0
to P2
7
, P3
0
to P3
7
, and P4
0
to P4
3
can be selected whether pull-down resistors are built-in or not by the
mask option specification. Flash memor
y
version does not have this option.
9
Memory
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Operation of Functional Blocks
The M30218 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, FLD controller, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 5 is a memory map of the M30218 group. The address space extends the 1M bytes from address
0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30218MC-XXXFP, there is 128K
bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as the reset are
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
From 0040016 up is RAM. For example, in the M30218MC-XXXFP, there is 12K bytes of internal RAM from
0040016 to 033FF16. In addition to storing data, the RAM also stores the stack used when calling subrou-
tines and when interrupts are generated. (From 0040016 to 004FF16 is RAM for SIO2. From 0050016 to
005DF16 is RAM for FLD.)
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
Figure 5. Memory map
0
0
0
0
0
1
6
X
X
X
X
X
1
6
F
F
F
F
F
1
6
0
0
4
0
0
1
6
0
0
5
0
0
1
6
0
0
5
E
0
1
6
Y
Y
Y
Y
Y
1
6
I
n
t
e
r
n
a
l
R
O
M
a
r
e
a
S
F
R
a
r
e
a
(F
o
r
d
e
t
a
i
l
s
,
s
e
e
F
i
g
u
r
e
s
6
a
n
d
7
)
R
A
M
a
r
e
a
f
o
r
S
I
/
O
2
F
F
E
0
0
1
6
F
F
F
D
C
1
6
F
F
F
F
F
1
6
U
n
d
e
f
i
n
e
d
i
n
s
t
r
u
c
t
i
o
n
O
v
e
r
f
l
o
w
B
R
K
i
n
s
t
r
u
c
t
i
o
n
A
d
d
r
e
s
s
m
a
t
c
h
S
i
n
g
l
e
s
t
e
p
W
a
t
c
h
d
o
g
t
i
m
e
r
R
e
s
e
t
S
p
e
c
i
a
l
p
a
g
e
v
e
c
t
o
r
t
a
b
l
e
D
B
C
T
y
p
e
N
o
.A
d
d
r
e
s
s
X
X
X
X
X
1
6
M
3
0
2
1
8
M
C
M
3
0
2
1
8
F
CE0
0
0
0
1
6
A
d
d
r
e
s
s
Y
Y
Y
Y
Y
1
6
0
3
3F
F
1
6
I
n
t
e
r
n
a
l
R
A
M
a
r
e
a
R
A
M
a
r
e
a
f
o
r
F
L
D
(
2
2
4
b
y
t
e
s
)
M
3
0
2
1
7
M
AE80
0
0
1
6
0
1
7
F
F
1
6
10
Memory
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 6. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A1 interrupt control register (TA1IC)
Timer A3 interrupt control register (TA3IC)
UART0 transmit interrupt control register (S0TIC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
Timer A4 interrupt control register (TA4IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
DMA1 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
A-D conversion interrupt control register (ADIC)
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA0 destination pointer (DAR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
INT4 interrupt control register (INT4IC)
INT3 interrupt control register (INT3IC)
INT5 interrupt control register (INT5IC)
SI/O automatic transfer interrupt control register (ASIOIC)
FLD interrupt control register (FLDIC)
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
P3 FLD/port switch register (P3FPR)
P5 digit output set register (P5DOR)
Toff2 time set register (TOFF2)
FLD data pointer (FLDDP)
FLD output control register (FLDCON)
P6 digit output set register (P6DOR)
P4 FLD/port switch register (P4FPR)
P2 FLD/port switch register (P2FPR)
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
FLD mode register (FLDM)
Serial I/O2 automatic transfer data pointer
(SIO2DP)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register / transfer counter (SIO2)
Serial I/O2 control register 3 (SIO2CON3)
11
Memory
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 7. Location of peripheral unit control registers (2)
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
DMA1 request cause select register (DM1SL)
DMA0 request cause select register (DM0SL)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Timer A3 (TA3)
Timer A4 (TA4)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Trigger select register (TRGSR)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
CRC data register (CRCD)
CRC input register (CRCIN)
Clock prescaler reset flag (CPSRF)
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
Port P0 (P0)
Port P1 (P1)
Port P2 (P2)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P6 (P6)
Port P7 (P7)
Port P7 direction register (PD7)
Port P8 (P8)
Port P8 direction register (PD8)
Port P9 (P9)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
A-D control register 2 (ADCON2)
Flash memory control register 0 (FCON0) (Note)
Flash memory control register 1 (FCON1) (Note)
Flash command register (FCMD) (Note)
Note: This re
g
ister is only exist in flash memory version.
12
CPU
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 8. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Figure 8. Central processing unit register
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R0
(Note)
AAAAAAA
HL
b15 b8 b7 b0
R1
(Note)
R2
(Note)
AAAAAAA
AAAAAAA
b15 b0
R3
(Note)
AAAAAAA
b15 b0
A0
(Note)
AAAAAAA
AAAAAAA
b15 b0
A1
(Note)
AAAAAAA
AAAAAAA
b15 b0
FB
(Note)
AAAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These re
g
isters consist of two re
g
ister banks.
A
A
AA
AA
AA
AA
AA
AA
AAAAAA
AAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL
13
CPU
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure CA-2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
14
CPU
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 9. Flag register (FLG)
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
C
a
r
r
y
f
l
a
g
D
e
b
u
g
f
l
a
g
Z
e
r
o
f
l
a
g
S
i
g
n
f
l
a
g
R
e
g
i
s
t
e
r
b
a
n
k
s
e
l
e
c
t
f
l
a
g
O
v
e
r
f
l
o
w
f
l
a
g
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
f
l
a
g
S
t
a
c
k
p
o
i
n
t
e
r
s
e
l
e
c
t
f
l
a
g
R
e
s
e
r
v
e
d
a
r
e
a
P
r
o
c
e
s
s
o
r
i
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
R
e
s
e
r
v
e
d
a
r
e
a
F
l
a
g
r
e
g
i
s
t
e
r
(
F
L
G
)
CDZSBOIU
I
P
L
b
0b
1
5
15
Reset
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 10 shows the example reset circuit. Figure 11 shows the reset sequence.
Figure 10. Example reset circuit
RESET V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when f
(
X
IN
)
= 10MHz and V
CC
= 5V
.
BCLK
Address
BCLK 24cycles
FFFFC
16
FFFFE
16
Content of reset vector
X
IN
RESET
More than 20 cycles are needed
(Internal clock)
(Internal address
s
i
g
n
a
l
)
Figure 11. Reset sequence
16
Reset
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 12. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset.
The initial values must therefore be set.
(1) (0004
16
)···Processor mode register 0
(2) (0005
16
)···Processor mode register 1 00
(3) (0006
16
)···System clock control register 0 10000100
(4) (0007
16
)···System clock control register 1 00010000
(5)
(6)
(0009
16
)···Address match interrupt enable register 00
(7)
(12)
(13)
(21)
(22)
(23)
(20)
(8)
(0012
16
)··· 0
(000F
16
)···Watchdog timer control register 00?0????
(0010
16
)···Address match interrupt register 0
(0011
16
)···
00
16
00
16
0 0 0
(14)
(9) (0014
16
)···Address match interrupt register 1
(0015
16
)···
(0016
16
)··· 0
00
16
00
16
0 0 0
(002C
16
)···DMA0 control register 00000?00
(003C
16
)···DMA1 control register 00000?00
(0044
16
)···INT3 interrupt control register 00?000
(15)
(16)
(17)
(18)
(19)
(0048
16
)···INT4 interrupt control register 00?000
(0049
16
)···INT5 interrupt control register 00?000
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
(38)
Timer B2 interrupt control register
(39)
INT0 interrupt control register
(40)
INT1 interrupt control register
(41)
INT2 interrupt control register
(45)
FLDC mode register
(46)
FLD output control register
Serial I/O 2 control register 2
(43)
Serial I/O 2 control register 3
(44)
(42)
Serial I/O 2 control register 1
(47)
Tdisp time set register
Toff1 time set register
Toff2 time set register
P2 FLD/port switch register
P4 FLD/port switch register
P6 digit output set register
(0055
16
)···
(0056
16
)···
(0057
16
)···
(0058
16
)···
(0059
16
)···
(005A
16
)···
(005B
16
)···
(005C
16
)···
(005D
16
)···
(005E
16
)···
(005F
16
)···
(0350
16
)···
(0351
16
)···
(0344
16
)···
(0348
16
)···
(0342
16
)···
(0352
16
)···
(0354
16
)···
(0356
16
)···
(0359
16
)···
(035B
16
)···
(035D
16
)···
(035A
16
)···
P3 FLD/port switch register
A-D conversion interrupt control register
SI/O automatic transfer interrupt
control register
FLD interrupt control register
(004E
16
)··· ? 0 0 0
(004F
16
)···
(0050
16
)···
? 0 0 0
? 0 0 0
UART0 transmit interrupt control register
UART0 receive interrupt control register
(0051
16
)···
(0052
16
)···
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
?00000
?00000
?00000
P5 digit output set register (035C
16
)···
(000A
16
)···Protect register 000
(10)
(11)
(004B
16
)···DMA0 interrupt control register ? 0 0 0
(004C
16
)···DMA1 interrupt control register ? 0 0 0
UART1 transmit interrupt control register
UART1 receive interrupt control register
(0053
16
)···
(0054
16
)···
? 0 0 0
? 0 0 0
(24)
(25)
(26)
(27)
(28)
0
00
0
0
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
00
16
00
16
00
16
00
16
00
16
17
Reset
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 13. Device's internal status after a reset is cleared
(038316)···Trigger select flag
(038416)···Up-down flag(52)
(51)
(039616)···Timer A0 mode register(53)
(039716)···Timer A1 mode register(54)
(039816)···Timer A2 mode register
(57)
(039B16)···Timer B0 mode register(58)
(039C16)···Timer B1 mode register
(039D16)···Timer B2 mode register
(70)
(55)
(039916)···Timer A3 mode register(56)
(039A16)···Timer A4 mode register
(038216)···One-shot start flag(50)
0016
0016
0
0016
0016
0016
0016
0016
0? 0000
00? 0000
00? 0000
(03AC16)···UART1 transmit/receive control register 0
(75)
(03AD16)···UART1 transmit/receive control register 1
(76)
(03B016)···UART transmit/receive control register 2
(77)
(03B816)···DMA0 cause select register
(78)
(03BA16)···DMA1 cause select register
(79)
0
(03A016)···UART0 transmit/receive mode register
(71)
(03A416)···UART0 transmit/receive control register 0
(72)
(03A516)···UART0 transmit/receive control register 1
(73)
0016
000 1000
000 0010
0
0
(03A816)···UART1 transmit/receive mode register
(74)
0016
000 1000
000 0010
0
0
0 00000
0016
0016
(03D416)···
A-D control register 2
(80)
(03D616)···
A-D control register 0
(81)
(03D716)···
A-D control register 1
(82)
0
000 0???0
0016
0000000
Count start flag (038016)··· 0016
0
(038116)···Clock prescaler reset flag
(48)
(49)
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset.
The initial values must therefore be set.
(84)
(85)
(86)
(03E716)···Port P3 direction register
(87)
(03EA16)···Port P4 direction register
(88)
(89)
(03EF16)···Port P7 direction register
(03F216)···Port P8 direction register
(03F316)···Port P9 direction register
(03F616)···Port P10 direction register
(03FD16)···Pull-up control register 0
(03FE16)···Pull-up control register 1
0016
0016
0016
0016
0016
0016
0016
Frame base register (FB)
Address registers (A0/A1)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
000016
000016
0000016
000016
000016
000016
000016
Data registers (R0/R1/R2/R3) 000016
(03DC16)···
D-A control register 0016
(62)
(61)
(63)
(64)
(67)
(68)
(65)
(66)
(60)
(59)
(69)
(83)
0016
Flash memory control register 0
(Note )
Flash memory control register 1
(Note)
Flash command register (Note)
Note: This re
g
ister is onl
y
exist in flash memor
y
version.
(03B416)··· 01 00000
(03B516)··· 0
(03B616)···
0
0016
(90)
(91)
(92)
0
18
Software Reset
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software reset) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 14 shows the processor mode register 0 and 1.
Figure 14. Processor mode register 0 and 1
Processor mode register 0 (Note)
Symbol Address When reset
PM0 0004
16
XXXX0000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PM03
Reserved bit
Software reset bit The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Note: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
Symbol Address When reset
PM1 0005
16
00XXXXX0
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Reserved bit Must always be set to “0”
0
Note: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values
to this register.
A
A
A
A
A
A
A
A
Must always be set to “0”
0
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
0000
0
Reserved bit Must always be set to “0”
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
19
Clock Generating Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 2. Main clock and sub clock generating circuits
Main clock generating circuit Sub clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after rese
t Oscillating Stopped
Other Externally derived clock can be input
Example of oscillator circuit
Figure 15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 16 shows some examples of sub clock
circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock
for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values recom-
mended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
CIN
and X
COUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
(Note)
C
CIN
C
COUT
R
Cd
Figure 15. Examples of main clock
Figure 16. Examples of sub clock
20
Clock Generating Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 “1”
Write signal
1/32
X
COUT
QS
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
QS
R
Interrupt request
level judgment output
RESET
Software reset f
C
CM07=0
CM07=1
f
AD
AAA
AAA
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
BCLK
f
8SIO2
f
1SIO2
Clock Control
Figure 17 shows the block diagram of the clock generating circuit.
Figure 17. Clock generating circuit
21
Clock Generating Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, fAD, f1SIO2, f8SIO2)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
22
Clock Generating Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16
48
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P9
7
/DA
0
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit 0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with X
IN
, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
OUT
turns “H”. The built-in feedback resistor remains being connected, so X
IN
turns
pulled up to X
OUT
(“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 0007
16
20
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note4) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is
“0”. If
“1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, X
OUT
turns “H”, and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-
impedance state.
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
00
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Figure 18. Clock control registers 0 and 1
23
Clock Output
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Clock Output
The clock output function select bit (bit 0,1 at address 000616) allows you to choose the clock from f8, f32, or
fc to be output from the P97/DA0/CLKOUT/DIMOUT pin. When the WAIT peripheral function clock stop bit
(bit 2 at address 000616) is set to “1”, the output of f8 and f32 stop by executing of WAIT instruction.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation of BCLK, f1 to f32, fC32, and fAD stops in stop mode, peripheral functions such as
the fluorescent display function, serial I/O 2, A-D converter and watchdog timer do not function. However,
timer A and timer B operate provided that the event counter mode is set to an external pulse, and UART0
and UART2 functions provided an external clock is selected. Table 3 shows the status of the ports in stop
mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 3. Port status during stop mode
Pin States
Port Retains status before stop mode
CLKOUT When fC selected “H”
When f8, f32 selected Retains status before stop mode
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode,
oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock
stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions,
allowing power dissipation to be reduced. Table 4 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 4. Port status during wait mode
Pin States
Port Retains status before wait mode
CLKOUT When fC selected Does not stop
When f8, f32 selected Does not stop when the WAIT
peripheral function clock stop bit is
“0”. (Note)
When the WAIT peripheral function clock
stop bit is “1”, the status immediately prior
to entering wait mode is maintained.
Note: Attention that reducing the power dissipation is impossible.
24
Status Transition of BCLK
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK
0 1 0 0 0 Invalid Division by 2 mode
1 0 0 0 0 Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
1 1 0 0 0 Invalid Division by 16 mode
0 0 0 0 0 Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
Table 5. Operating modes dictated by settings of system clock control registers 0 and 1
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table WA-4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
25
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Power Control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-
ates according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 19 shows the state transition diagram of the above modes.
26
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 19. State transition diagram of Power control mode
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
All oscillators stopped CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0” BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
CIN
)
CM07 = “1”
BCLK : f(X
CIN
)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0” CM05 = “1”
CM04 = “0” CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0” CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
27
Protection
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 20 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), and system clock control register 1 (address 000716) can only be changed when
the respective bit in the protect register is set to “1”.
The system clock control registers 0 and 1 write-enable bit (bit 0 at address 000A16) and processor mode
register 0 and 1 write-enable bit (bit 1 at address 000A16) do not automatically return to “0” after a value has
been written to an address. The program must therefore be written to return these bits to “0”.
Figure 20. Protect register
P
r
o
t
e
c
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
R
C
R0
0
0
A
1
6
X
X
X
X
X
0
0
0
2
B
i
t
n
a
m
eB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
0
:
W
r
i
t
e
-
i
n
h
i
b
i
t
e
d
1
:
W
r
i
t
e
-
e
n
a
b
l
e
d
P
R
C
1
P
R
C
0
E
n
a
b
l
e
s
w
r
i
t
i
n
g
t
o
p
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
s
0
a
n
d
1
(
a
d
d
r
e
s
s
e
s
0
0
0
4
1
6
a
n
d
0
0
0
5
1
6
)
F
u
n
c
t
i
o
n
0
:
W
r
i
t
e
-
i
n
h
i
b
i
t
e
d
1
:
W
r
i
t
e
-
e
n
a
b
l
e
d
E
n
a
b
l
e
s
w
r
i
t
i
n
g
t
o
s
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
0
a
n
d
1
(
a
d
d
r
e
s
s
e
s
0
0
0
6
1
6
a
n
d
0
0
0
7
1
6
)
WR
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
28
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 21. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 21 shows the types of interrupts.
29
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-
ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-
rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/
O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
30
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset ____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt
This is an interrupt that the SI/O automatic transfer generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT5 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
31
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
- FFFF816 to FFFFB16 -
Reset FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
Figure 22. Format for specifying interrupt vector addresses
M
i
d
a
d
d
r
e
s
s
L
o
w
a
d
d
r
e
s
s
0
0
0
0H
i
g
h
a
d
d
r
e
s
s
0
0
0
0 0
0
0
0
V
e
c
t
o
r
a
d
d
r
e
s
s
+
0
V
e
c
t
o
r
a
d
d
r
e
s
s
+
1
V
e
c
t
o
r
a
d
d
r
e
s
s
+
2
V
e
c
t
o
r
a
d
d
r
e
s
s
+
3
L
S
B
M
S
B
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 22 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 6 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 6. Interrupts assigned to the fixed vector tables and addresses of vector tables
32
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 7. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number Interrupt source
Vector table address
Address (L) to address (H)
Remarks
Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0
+44 to +47 (Note) Software interrupt number 11
+48 to +51 (Note)Software interrupt number 12
+56 to +59 (Note)Software interrupt number 14
+68 to +71 (Note)Software interrupt number 17
+72 to +75 (Note)Software interrupt number 18
+76 to +79 (Note)Software interrupt number 19
+80 to +83 (Note)Software interrupt number 20
+84 to +87 (Note)Software interrupt number 21
+88 to +91 (Note)Software interrupt number 22
+92 to +95 (Note)Software interrupt number 23
+96 to +99 (Note)Software interrupt number 24
+100 to +103 (Note)Software interrupt number 25
+104 to +107 (Note)Software interrupt number 26
+108 to +111 (Note)Software interrupt number 27
+112 to +115 (Note)Software interrupt number 28
+116 to +119 (Note)Software interrupt number 29
+120 to +123 (Note)Software interrupt number 30
+124 to +127 (Note)Software interrupt number 31
+128 to +131 (Note)Software interrupt number 32
+252 to +255 (Note)Software interrupt number 63
to
Note : Address relative to address in interrupt table register (INTB).
Cannot be masked I flag
to
A-D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer B0
Timer B1
INT0
INT1
Software interrupt
+28 to +31 (Note) INT3Software interrupt number 7
+32 to +35 (Note) INT4Software interrupt number 8
+36 to +39 (Note) INT5Software interrupt number 9
DMA0
DMA1
+60 to +63 (Note)Software interrupt number 15 SI/O automatic transfer
+64 to +67 (Note)Software interrupt number 16 FLD
Timer A4
Timer B2
INT2
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 7 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
33
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 23 shows the memory map of the interrupt control registers.
34
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 23. Interrupt control registers
Symbol Address When reset
INTiIC(i=0 to 5) 005D
16
to 005F
16
XX00X000
2
0047
16
to 0049
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
ILVL0
IR
POL
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
(Note1)
Interrupt control register(Note2)
b7 b6 b5 b4 b3 b2 b1 b0
A
AA
AA
A
Bit name FunctionBit symbol
WR
Symbol Address When reset
DMiIC(i=0, 1) 004B
16
to 004C
16
XXXXX000
2
ADIC 004E
16
XXXXX000
2
ASIOIC 004F
16
XXXXX000
2
FLDIC 0050
16
XXXXX000
2
SiTIC(i=0, 1) 0051
16
, 0053
16
XXXXX000
2
SiRIC(i=0, 1) 0052
16
, 0054
16
XXXXX000
2
TAiIC(i=0 to 4) 0055
16
to 0059
16
XXXXX000
2
TBiIC(i=0 to 2) 005A
16
to 005C
16
XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
(Note1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
35
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Table 9.
Interrupt levels enabled according
to the contents of the IPL
Table 8. Settings of interrupt priority levels
Interrupt priority
level select bit Interrupt priority
level Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
2
IPL
1
IPL
0
IPL
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 8 shows the settings of interrupt priority levels and Table 9 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
36
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ;
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
37
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 24 shows the interrupt response time.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 24. Interrupt response time
38
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt sources without priority levels
7
Value set in the IPL
Watchdog timer
Other Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 11 shows set in the IPL.
Table 11. Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) valueInterrupt vector address 16-Bit bust 8-Bit bus
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Table 10. Time required for executing the interrupt sequence
Reset
Indeterminate
123456789 101112 13 14 15 16 17 18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000 Indeterminate SP-2 SP-4 vec vec+2 PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction.
Time (b) is as shown in Table 10.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 25. Time required for executing the interrupt sequence
39
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 26 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLG
L
)
Content of previous stack
Stack area
Flag register
(FLG
H
)Program
counter (PC
H
)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB LSB
Program counter (PC
L
)
Program counter (PC
M
)
Figure 26. State of stack before and after acceptance of interrupt request
40
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 27. Operation of saving registers
(2) Stack pointer (SP) contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)Program
counter (PC
H
)
Flag register
(FLG
H
)Program
counter (PC
H
)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or oDD- If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 27 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
41
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 28 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 29 shows the circuit that judges the interrupt priority level.
Figure 28. Hardware interrupts priorities
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
42
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 29. Maskable interrupts priorities
Timer B0
Timer A3
INT2
Timer B1
INT3
UART1 reception
UART0 reception
FLD
Timer A0
UART1 transmission
UART0 transmission
SI/O2 automatic transfer
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
Timer B2
INT0
Watchdog timer
Reset
DBC
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O
interrupts
(if priority levels are same)
Address match
INT1
Timer A1
INT4
Timer A4
Timer A2
INT5
A-D conversion
DMA1
DMA0
Interrupt request level judgment output
43
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 30 shows the address match interrupt-related registers.
B
i
t
n
a
m
eB
i
t
s
y
m
b
o
l
S
y
m
b
o
lA
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
A
I
E
R0
0
0
9
1
6
X
X
X
X
X
X
0
0
2
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
F
u
n
c
t
i
o
nWR
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
0
e
n
a
b
l
e
b
i
t
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
A
I
E
R
0
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
1
e
n
a
b
l
e
b
i
t
A
I
E
R
1
S
y
m
b
o
lA
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
R
M
A
D
00
0
1
2
1
6
t
o
0
0
1
0
1
6
X
0
0
0
0
0
1
6
R
M
A
D
10
0
1
6
1
6
t
o
0
0
1
4
1
6
X
0
0
0
0
0
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
WR
A
d
d
r
e
s
s
s
e
t
t
i
n
g
r
e
g
i
s
t
e
r
f
o
r
a
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
i
(
i
=
0
,
1
)
0
0
0
0
0
1
6
t
o
F
F
F
F
F
1
6
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
b
0b
7b
0b
3
(
b
1
9
)(
b
1
6
)b
7b
0
(
b
1
5
)(
b
8
)
b
7
(
b
2
3
)
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
Figure 30. Address match interrupt-related registers
Address Match Interrupt
44
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
______
Figure 31. Switching condition of INT interrupt request
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt priority level to level 0
(Disable
INTi
interrupt)
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt enable flag to “1”
(Enable interrupt)
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
(3) External interrupt ________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT5 regardless of the CPU operation clock.
________ ________
• When the polarity of the INT0 through INT5 pins is changed, the interrupt request bit is sometimes set to
“1”. After changing the polarity, set the interrupt request bit to “0”. Figure 31 shows the procedure for
______
changing the INT interrupt generate factor.
Precautions for Interrupts
45
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Precautions for Interrupts
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ;
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
46
Watchdog Timer
Figure 32. Block diagram of watchdog timer
BCLK
Write to the watchdog timer
start register
(address 000E16)
RESET
Watchdog timer
interrupt request
Watchdog timer
Set to
“7FFF16”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
1/2
Prescaler
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu-
lated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler.
For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 32 shows the block diagram of the watchdog timer. Figure 33 shows the watchdog timer-related
registers.
With XIN chosen for BCLK
Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768)
BCLK
47
Watchdog Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 33. Watchdog timer control and start registers
Watchdog timer control register
Symbol Address When reset
WDC 000F
16
000XXXXX
2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E
16
Indeterminate
WR
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
16
”
regardless of whatever value is written.
Reserved bit
Reserved bit Must always be set to “0”
Must always be set to “0”
00
AA
AA
A
AA
AA
A
A
AA
AA
A
A
A
48
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 34. Block diagram of DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 34 shows the block diagram of the
DMAC. Table 12 shows the DMAC specifications. Figure 35 to Figure 36 show the registers used by the
DMAC.
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAA
AAAAAA
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
AAAAAAA
Data bus high-order bits
A
A
A
A
A
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
Address bus
A
A
A
A
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
AA
AA
AA
AA
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
AA
AA
(addresses 002916, 002816)
(addresses 003916, 003816)
(addresses 002216 to 002016)
(addresses 002616 to 002416)
(addresses 003216 to 003016)
(addresses 003616 to 003416)
Note: Pointer is incremented b
y
a DMA re
q
uest.
AA
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
A
A
A
A
AA
AA
AA
A
A
A
A
A
A
A
A
49
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space • From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
________ ________ ________ ________
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit 8 bits or 16 bits
Transfer address direction forward or fixed (forward direction cannot be specified for both source
and destination simultaneously)
Transfer mode • Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing
When an underflow occurs in the transfer counter
Active When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active,
re
the value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer,and the value
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Table 12. DMAC specifications
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
Forward address pointer and
load timing for transfer
counter
50
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 35. DMAC-related registers (1)
DMAi request cause select register
Symbol Address When reset
DMiSL(i=0,1) 03B8
16
,03BA
16
00
16
Bit name Function R
Bit symbol
W
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
DSEL1
DSEL2
DSEL3
Software DMA request bit If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DSR
DMAi control register
Symbol Address When reset
DMiCON(i=0,1) 002C
16
, 003C
16
00000X00
2
Bit name FunctionBit symbol R W
b7 b6 b5 b4 b3 b2 b1 b0
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit 0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1) 0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3) 0 : Fixed
1 : Forward
DSD
DAD
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART1 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Inhibited
Note: Address 03B8
16
is for INT0; address 03BA
16
is for INT1.
(Note 2)
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
51
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 36. DMAC-related registers (2)
b7 b0 b7 b0
(b8)(b15)
Function
RW
• Transfer counter
Set a value one less than the transfer count
Symbol Address When reset
TCR0 0029
16
, 0028
16
Indeterminate
TCR1 0039
16
, 0038
16
Indeterminate
DMAi transfer counter (i = 0, 1)
Transfer count
specification
0000
16
to FFFF
16
b7
(b23) b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function
RW
• Source pointer
Stores the source address
Symbol Address When reset
SAR0 0022
16
to 0020
16
Indeterminate
SAR1 0032
16
to 0030
16
Indeterminate
DMAi source pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Symbol Address When reset
DAR0 0026
16
to 0024
16
Indeterminate
DAR1 0036
16
to 0034
16
Indeterminate
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
RW
• Destination pointer
Stores the destination address
DMAi destination pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
A
A
AA
AA
A
AA
A
AA
52
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 37. Example of transfer cycles for a source read (the state of internal bus)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Note: The same timin
g
chan
g
es occur with the respective conditions at the destination as at the source.
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
Figure 37 shows the example of the transfer cycles (a state of internal bus) for a source read. For conve-
nience, the destination write cycle is shown as one cycle and the source read cycles for the different
conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source
read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember
to apply the respective conditions to both the destination write cycle and the source read cycle.
53
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) DMAC Transfer
Any combination of even or odd transfer read and write addresses is possible. Table 13 shows the num-
ber of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 13. No. of DMAC transfer cycles singelchip mode
Transfer unit Access address No. of No. of
read cycles write cycles
8-bit transfers Even 1 1
(DMBIT="1") Odd 1 1
16-bit transfers Even 1 1
(DMBIT="0") Odd 2 2
Internal memory
Internal ROM/RAM SFR area
12
Coefficient j, k
54
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
FLD Controller
The M30218 group has fluorescent display (FLD) drive and control circuits.
Table 14 shows the FLD controller specifications.
Specification
• 52 pins ( 20 pins can switch general purpose port)
• 4 pins ( 4 pins can switch general purpose port)
(A driver must be installed externally)
• Used FLD output
28 segment X 28 digit (segment number + digit number ≤ 56)
• Used digit output
40 segment X 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501
56 segment X (connect number of M35501) digit
(segment number ≤ 56, digit number ≤ number of M35501 X 16)
• Used P44 to P47 expansion
52 segment X 16 digit (segment number ≤ 52, digit number ≤ 16)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan used digit
• Key-scan used segment
• Digit pulse output function
This function automatically outputs digit pulse.
• M35501 connect function
The number of digits can be increased easily by using the output of
DIMOUT(P97) as CLK for the M35501.
• Toff section generate / not generate function
This function does not generate Toff1 section when the connected outputs
are the same.
• Gradation display function
This function allows each segment to be set for dark or bright display.
• P44 to P47 expansion function
This function provides 16 lines of digit outputs from four ports by attaching a
4 16 decoder.
Item
FLD
controller
port
High-breakdown-volt-
age output port
CMOS port
Display pixel number
Period
Dimmer time
Interrupt
Key-scan
Expand function
Table 14. FLD controller specifications
55
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 38. Block Diagram for FLD Control Circuit
03E8
16
035B
16
8
P4
0
/FLD
48
P4
1
/FLD
49
P4
2
/FLD
50
P4
3
/FLD
51
P4
4
/FLD
52
P4
5
/FLD
53
P4
6
/FLD
54
P4
7
/FLD
55
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0500
16
05DF
16
03E1
16
8
P1
0
/FLD
24
P1
1
/FLD
25
P1
2
/FLD
26
P1
3
/FLD
27
P1
4
/FLD
28
P1
5
/FLD
29
P1
6
/FLD
30
P1
7
/FLD
31
Main address bus
Local address bus
FLD automatic display RAM
P6
0
/FLD
0
P6
1
/FLD
1
P6
2
/FLD
2
P6
3
/FLD
3
P6
4
/FLD
4
P6
5
/FLD
5
P6
6
/FLD
6
P6
7
/FLD
7
035D
16
8
03E9
16
8
P5
0
/FLD
8
P5
1
/FLD
9
P5
2
/FLD
10
P5
3
/FLD
11
P5
4
/FLD
12
P5
5
/FLD
13
P5
6
/FLD
14
P5
7
/FLD
15
Main
data bus Local
data bus
FLD blanking interrupt
FLD digit interrupt
FLDC mode register
(0350
16
)
FLD data pointer
reload register
(0358
16
)
FLD data pointer
(0358
16
)
Timing generator
Address
decoder
03E4
16
0359
16
8
P2
0
/FLD
32
P2
1
/FLD
33
P2
2
/FLD
34
P2
3
/FLD
35
P2
4
/FLD
36
P2
5
/FLD
37
P2
6
/FLD
38
P2
7
/FLD
39
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
03E5
16
035A
16
8
P3
0
/FLD
40
P3
1
/FLD
41
P3
2
/FLD
42
P3
3
/FLD
43
P3
4
/FLD
44
P3
5
/FLD
45
P3
6
/FLD
46
P3
7
/FLD
47
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
03E0
16
8
P0
0
/FLD
16
P0
1
/FLD
17
P0
2
/FLD
18
P0
3
/FLD
19
P0
4
/FLD
20
P0
5
/FLD
21
P0
6
/FLD
22
P0
7
/FLD
23
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
035C
16
03EC
16
FLD/port switch register
Digit output set register
56
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 39. FLDC-related Register(1)
FLDC mode register
Symbol Address When reset
FLDM 0350
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Automatic display
control bit 0 : General-purpose mode
1 : Automatic display mode
FLDM0
FLDM1
FLDM2
FLDM3
Display start bit 0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits 00 : FLD digit interrupt
(at rising edge of each digit)
01 : 1 X Tdisp
10 : 2 X Tdisp
11 : 3 X Tdisp
0 : 16 timing mode
1 : 32 timing mode
Timing number control bit
Gradation display mode
selection control bit 0 : Not selecting
1 : Selecting (Note )
FLDM4
FLDM5
Note : When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0”.)
Tdisp counter
count source selection bit 0 : f(X
IN
)/32
1 : f(X
IN
)/128
FLDM6
High-breakdown voltage
port drivability select bit 0 : Drivability strong
1 : Drivability weak
FLDM7
FLD output control register
Symbol Address When reset
FLDCON 0351
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
FLDCON7
FLDCON5
FLDCON4
FLDCON2
FLDCON0
FLDCON6
P4
4
to P4
7
FLD
output reverse bit
P4
4
to P4
7
FLD
Toff is invalid bit 0 : Perform normally
1 : Toff is invalid
P9
7
dimmer output
control bit 0 : Output normally
1 : Dimmer output
CMOS ports: section of
Toff generate/not
generate bit
0 : section of Toff does NOT generate
1 : section of Toff generates
High-breakdown-voltage ports:
section of Toff
generate/not generate bit
0 : section of Toff does NOT generate
1 : section of Toff generates
Toff2
SET/RESET change bit 0 : gradation display data is reset at Toff2
(set at Toff1)
1 : gradation display data is set at Toff2
(reset at Toff1)
WR
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
0 : Output normally
1 : Reverse output
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Tdisp time set register
Symbol Address When reset
TDISP 0352
16
00
16
Values that can be set
b7 b0
Counts Tdisp time. Count source is selected by Tdisp
counter count source select bit.
WR
A
A
AA
AA
0
16
to FF
16
Function
FLD blanking
interrupt (at falling
edge of last digit)
}
b3b2
WR
A
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
AA
A
A
AA
AA
57
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 40. FLDC-related Register(2)
Toff1 time set register
Symbol Address When reset
TOFF1 0354
16
FF
16
WR
b7 b0
Function
Values that can be set
Counts Toff1 time. Count source is selected by Tdisp counter count source
select bit. 3 to FF
16
Toff2 time set register
Symbol Address When reset
TOFF2 0356
16
FF
16
WR
b7 b0
Counts Toff2 time. Count source is selected by Tdisp counter count source
select bit. 3 to FF
16
FLD data pointer
Symbol Address When reset
FLDDP 0358
16
indeterminate
WR
b7 b0
Counts FLD output timing. Set this register to “FLD output data - 1 ”. 1 to 1F
16
Note: Reading the FLD data pointer takes out the count at that moment.
0 : Normal port
1 : FLD output port
Port P2 FLD / port switch register
Symbol Address When reset
P2FPR 0359
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
P2FPR0
P2FPR2
P2FPR1
P2FPR3
P2FPR4
P2FPR6
P2FPR5
P2FPR7
Port P2
0
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
1
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
2
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
3
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
4
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
5
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
6
FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P2
7
FLD/port switch bit
Function Values that can be set
Function Values that can be set
Bit name Function
Bit symbol
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
58
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 41. FLDC-related Register(3)
0 : Normal port
1 : FLD output port
Port P3 FLD / port switch register
Symbol Address When reset
P3FPR 035A16 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
P3FPR0
P3FPR2
P3FPR1
P3FPR3
P3FPR4
P3FPR6
P3FPR5
P3FPR7
Port P30 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P31 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P32 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P33 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P34 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P35 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P36 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P37 FLD/port switch bit
Bit name Function
Bit symbol
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : Normal port
1 : FLD output port
Port P4 FLD / port switch register
Symbol Address When reset
P4FPR 035B16 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
P4FPR0
P4FPR2
P4FPR1
P4FPR3
P4FPR4
P4FPR6
P4FPR5
P4FPR7
Port P40 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P41 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P42 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P43 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P44 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P45 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P46 FLD/port switch bit
0 : Normal port
1 : FLD output port
Port P47 FLD/port switch bit
Bit name Function
Bit symbol
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : FLD output
1 : Digit output
Port P5 digit output set register
Symbol Address When reset
P5DOR 035C16 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
P5DOR0
P5DOR2
P5DOR1
P5DOR3
P5DOR4
P5DOR6
P5DOR5
P5DOR7
Port P50 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P51 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P52 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P53 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P54 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P55 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P56 FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P57 FLD/digit switch bit
Bit name Function
Bit symbol
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
59
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 42. FLDC-related Register(4)
0 : FLD output
1 : Digit output
Port P6 digit output set register
Symbol Address When reset
P6DOR 035D
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
P6DOR0
P6DOR2
P6DOR1
P6DOR3
P6DOR4
P6DOR6
P6DOR5
P6DOR7
Port P6
0
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
1
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
2
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
3
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
4
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
5
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
6
FLD/digit switch bit
0 : FLD output
1 : Digit output
Port P6
7
FLD/digit switch bit
Bit name Function
Bit symbol
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
60
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 43. Segment/Digit Setting Example
FLD automatic display pins
P0 to P6 are the pins capable of automatic display output for the FLD. The FLD start operating by setting
the automatic display control bit (bit 0 at address 035016) to “1”. There is the FLD output function that
outputs RAM contents from the port every timing or the digit output function that drives the port high with
digit timing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for
the digits. When using the FLD output for the digits, be sure to write digit display patterns to the RAM in
advance. The remaining segment and digit lines can be used as general-purpose ports. Settings of each
port are shown below.
Table 15. Pins in FLD Automatic Display Mode
Port Name Automatic Display Pins Setting Method
P5, P6 FLD0 to FLD15
P0, P1 FLD16 to FLD31
P2, P3, FLD32 to FLD51
P44 to P43
P44 to P47FLD52 to FLD55
The individual bits of the digit output set register (address 035C16,
035D16) can set each pin either FLD port (“0”) or digit port (“1”).
When the pins are set for the digit port, the digit pulse output func-
tion is enabled, so the digit pulses can always be output regardless
the value of FLD automatic display RAM.
FLD exclusive use port (automatic display control bit (bit 0 of ad-
dress 035016)=“1”)
The individual bits of the FLD/port switch register (addresses
035916 to 035B16) can set each pin to either FLD port (“1”) or gen-
eral-purpose port (“0”).
The individual bits of the FLD/port switch register (address 035B16)
can set each pin to either FLD port (“1”) or general-purpose port
(“0”). The digit pulse output function turns to available, and the digit
pulse can output by setting of the FLD output set register (address
035116). The port output format is the CMOS output. When using
the port as a display pin, a driver must be installed externally.
Port P5
Port P0
Number of segments
Number of digits
Port P6
36
16
Port P1
Setting example 1
Shown below is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
1
1
1
1
1
1
1
1
FLD
32
(SEG output)
FLD
33
(SEG output)
FLD
34
(SEG output)
FLD
35
(SEG output)
FLD
36
(SEG output)
FLD
37
(SEG output)
FLD
38
(SEG output)
FLD
39
(SEG output)
FLD
16
(SEG output)
FLD
17
(SEG output)
FLD
18
(SEG output)
FLD
19
(SEG output)
FLD
20
(SEG output)
FLD
21
(SEG output)
FLD
22
(SEG output)
FLD
23
(SEG output)
FLD
0
(DIG
output
)
FLD
1
(DIG output)
FLD
2
(DIG output)
FLD
3
(DIG output)
FLD
4
(DIG output)
FLD
5
(DIG output)
FLD
6
(DIG output)
FLD
7
(DIG output)
0
0
0
0
0
0
0
0
FLD
8
(DIG output)
FLD
9
(DIG output)
FLD
10
(DIG output)
FLD
11
(DIG output)
FLD
12
(DIG output)
FLD
13
(DIG output)
FLD
14
(DIG output)
FLD
15
(DIG output)
0
0
0
0
0
0
0
0
FLD
24
(SEG output)
FLD
25
(SEG output)
FLD
26
(SEG output)
FLD
27
(SEG output)
FLD
28
(SEG output)
FLD
29
(SEG output)
FLD
30
(SEG output)
FLD
31
(SEG output)
Port P2
1
1
1
1
1
1
1
1
FLD
40
(SEG output)
FLD
41
(SEG output)
FLD
42
(SEG output)
FLD
43
(SEG output)
FLD
44
(SEG output)
FLD
45
(SEG output)
FLD
46
(SEG output)
FLD
47
(SEG output)
Port P3
1
1
1
1
0
0
0
0
FLD
48
(SEG output)
FLD
49
(SEG output)
FLD
50
(SEG output)
FLD
51
(SEG output)
FLD
52
(port output)
FLD
53
(port output)
FLD
54
(port output)
FLD
55
(port output)
Port P4
Port P5
Port P0
Port P6
28
12
Port P1
Setting example 2
Shown below is a register setup example where both FLD output and digit waveform
output are used. In this case, because the digit display output is automatically
generated, there is no need to set the display pattern in the FLD automatic display RAM.
1
1
1
1
1
1
1
1
FLD
32
(SEG output)
FLD
33
(SEG output)
FLD
34
(SEG output)
FLD
35
(SEG output)
FLD
36
(SEG output)
FLD
37
(SEG output)
FLD
38
(SEG output)
FLD
39
(SEG output)
FLD
16
(SEG output)
FLD
17
(SEG output)
FLD
18
(SEG output)
FLD
19
(SEG output)
FLD
20
(SEG output)
FLD
21
(SEG output)
FLD
22
(SEG output)
FLD
23
(SEG output)
FLD
0
(DIG output)
FLD
1
(DIG output)
FLD
2
(DIG output)
FLD
3
(DIG output)
FLD
4
(DIG output)
FLD
5
(DIG output)
FLD
6
(DIG output)
FLD
7
(DIG output)
1
1
1
1
1
1
1
1
FLD
8
(DIG output)
FLD
9
(DIG output)
FLD
10
(DIG output)
FLD
11
(DIG output)
FLD
12
(SEG output)
FLD
13
(SEG output)
FLD
14
(SEG output)
FLD
15
(SEG output)
1
1
1
1
0
0
0
0
FLD
24
(SEG output)
FLD
25
(SEG output)
FLD
26
(SEG output)
FLD
27
(SEG output)
FLD
28
(SEG output)
FLD
29
(SEG output)
FLD
30
(SEG output)
FLD
31
(SEG output)
Port P2
1
1
1
1
0
0
0
0
FLD
40
(SEG output)
FLD
41
(SEG output)
FLD
42
(SEG output)
FLD
43
(SEG output)
FLD
44
(port output)
FLD
45
(port output)
FLD
46
(port output)
FLD
47
(port output)
Port P3
0
0
0
0
0
0
0
0
FLD
48
(port output)
FLD
49
(port output)
FLD
50
(port output)
FLD
51
(port output)
FLD
52
(port output)
FLD
53
(port output)
FLD
54
(port output)
FLD
55
(port output)
Port P4
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is
g
eneral-purpose port ( used pro
g
ram).
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port ( used program).
The contents of digit output set register
(035C
16
, 035D
16
)
FLD/port switch register
(0359
16
, 035B
16
)
Number of segments
Number of digits
The contents of digit output set register
(035C
16
, 035D
16
)
FLD/port switch register
(0359
16
, 035B
16
)
61
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
FLD automatic display RAM
The FLD automatic display RAM uses the 224 bytes of addresses 050016 to 05DF16. For FLD, the 3 modes
of 16-timing ordinary mode, 16-timing•gradation display mode and 32-timing mode are available depending
on the number of timings and the use/not use of gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
This mode is used when the display timing is 16 or less. The 112 bytes of addresses 057016 to 05DF16
are used as a FLD display data store area. Because addresses 050016 to 056F 16 are not used as the
automatic display RAM, they can be the ordinary RAM.
(2) 16-timing•Gradation Display Mode
This mode is used when the display timing is 16 or less, in which mode each segment can be set for dark
or bright display. The 224 bytes of addresses 050016 to 05DF16 are used. The 112 bytes of addresses
057016 to 05DF16 are used as an FLD display data store area, while the 112 bytes of addresses 050016
to 056F16 are used as a gradation display control data store area.
(3) 32-timing Mode
This mode is used when the display timing is 16 or greater. This mode can be used for up to 32-timing.
The 224 bytes of addresses 050016 to 05DF16 are used as an FLD display data store area.
The FLD data pointer (address 035816) is a register to count display timings. This pointer has a reload
register and when the terminal count is reached, it starts counting over again after being reloaded with the
initial count. Make sure the timing count – 1 is set to the FLD data pointer. When writing data to this address,
the data is written to the FLD data pointer reload register; when reading data from this address, the value in
the FLD data pointer is read.
Figure 44. FLD Automatic Display RAM Assignment
16-timing•ordinary mode
05DF
16
0570
16
0500
16
05DF
16
0500
16
05DF
16
0570
16
0500
16
16-timing•gradation display mode 32-timing mode
1 to 32 timing display
data stored area
Gradation display
control data stored
area
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
Not used
62
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Data setup
(1) 16-timing•Ordinary Mode
The area of addresses 057016 to 05DF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 057016, the
last data of FLD port P3 is stored at address 058016, the last data of FLD port P2 is stored at address 059016, the last
data of FLD port P1 is stored at address 05A016, the last data of FLD port P0 is stored at address 05B016,
the last data of FLD port P5 is stored at address 05C0
16
,
and the last data of FLD port P6 is stored at address 05D0
16
,
to
assign in sequence from the last data respectively.
The first data of the FLD port P4, P3, P2, P1, P0, P5, and P6 is stored at an address which adds the value of (the
timing number – 1) to the corresponding address
057016, 058016, 059016, 05A016, 05B016, 05C016 and 05DF16.
Set the FLD data pointer reload register to the value given by the number of digits – 1.
(2) 16-timing•Gradation Display Mode
Display data setting is performed in the same way as that of the 16-timing•ordinary mode. Gradation display control
data is arranged at an address resulting from subtracting 007016 from the display data store address of each timing
and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1” .
(3) 32-timing Mode
The area of addresses 050016 to 05DF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 050016, the
last data of FLD port P3 is stored at address 052016, the last data of FLD port P2 is stored at address 054016,
the last data of FLD port P1 is stored at address 056016, the last data of FLD port P0 is stored at address 0580 16, the
last data of FLD port P5 is stored at address 05A016,
and the last data of FLD port P6 is stored at address 05C0
16
,
to
assign in sequence from the last data respectively
.
The first data of the FLD port P4, P3, P2, P0, P1, P5, and P6 is stored at an address which adds the value of (the
timing number – 1) to the corresponding address
050016, 052016, 054016, 056016, 058016, 05A016 and 05C016.
Set the FLD data pointer reload register to the value given by the number of digits - 1.
Figure 45. Example of Using the FLD Automatic
Display RAM in 16-timing•Ordinary Mode
Number of timing: 8
(FLD data pointer reload register = 7)
Address
058F
16
0571
16
0572
16
0573
16
0574
16
0575
16
0576
16
0577
16
0578
16
0579
16
057A
16
057B
16
057C
16
057D
16
057E
16
057F
16
0580
16
0581
16
0582
16
0583
16
0584
16
0585
16
0586
16
0587
16
0588
16
0589
16
058A
16
058B
16
058C
16
058D
16
058E
16
0590
16
0591
16
0592
16
0593
16
0594
16
0595
16
0596
16
0597
16
0598
16
0599
16
059A
16
059B
16
059C
16
059D
16
059E
16
059F
16
05A1
16
05A2
16
05A3
16
05A4
16
05A5
16
05A6
16
05A7
16
05A8
16
05A9
16
05AA
16
05AB
16
05AC
16
05AD
16
05AE
16
05AF
16
05A0
16
0570
16
The last timing
(The last data of FLDP4)
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
76543210
Bit Address
05B1
16
05B2
16
05B3
16
05B4
16
05B5
16
05B6
16
05B7
16
05B8
16
05B9
16
05BA
16
05BB
16
05BC
16
05BD
16
05BE
16
05BF
16
05B0
16
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
76543210
Bit
05C1
16
05C2
16
05C3
16
05C4
16
05C5
16
05C6
16
05C7
16
05C8
16
05C9
16
05CA
16
05CB
16
05CC
16
05CD
16
05CE
16
05CF
16
05C0
16
05D1
16
05D2
16
05D3
16
05D4
16
05D5
16
05D6
16
05D7
16
05D8
16
05D9
16
05DA
16
05DB
16
05DC
16
05DD
16
05DE
16
05DF
16
05D0
16
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
FLDP1 data area
FLDP2 data area
FLDP4 data area
FLDP3 data area
63
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 46. Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode
Number of timing: 15
(FLD data pointer reload register = 14)
Address
058F
16
0571
16
0572
16
0573
16
0574
16
0575
16
0576
16
0577
16
0578
16
0579
16
057A
16
057B
16
057C
16
057D
16
057E
16
057F
16
0580
16
0581
16
0582
16
0583
16
0584
16
0585
16
0586
16
0587
16
0588
16
0589
16
058A
16
058B
16
058C
16
058D
16
058E
16
0590
16
0591
16
0592
16
0593
16
0594
16
0595
16
0596
16
0597
16
0598
16
0599
16
059A
16
059B
16
059C
16
059D
16
059E
16
059F
16
05A1
16
05A2
16
05A3
16
05A4
16
05A5
16
05A6
16
05A7
16
05A8
16
05A9
16
05AA
16
05AB
16
05AC
16
05AD
16
05AE
16
05AF
16
05A0
16
05B1
16
05B2
16
05B3
16
05B4
16
05B5
16
05B6
16
05B7
16
05B8
16
05B9
16
05BA
16
05BB
16
05BC
16
05BD
16
05BE
16
05BF
16
05B0
16
0570
16
The last timing
(The last data of FLDP4)
76543210
Bit
The last timing
(The last data of FLDP3)
The last timing
(The last data of FLDP2)
The last timing
(The last data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP4 data area
FLDP3 data area
FLDP2 data area
FLDP1 data area
FLDP0 data area
05C1
16
05C2
16
05C3
16
05C4
16
05C5
16
05C6
16
05C7
16
05C8
16
05C9
16
05CA
16
05CB
16
05CC
16
05CD
16
05CE
16
05CF
16
05C0
16
The last timing
(The last data of FLDP5)
FLDP5 data area
05D1
16
05D2
16
05D3
16
05D4
16
05D5
16
05D6
16
05D7
16
05D8
16
05D9
16
05DA
16
05DB
16
05DC
16
05DD
16
05DE
16
05DF
16
05D0
16
The last timing
(The last data of FLDP6)
FLDP6 data area
Address
051F
16
0501
16
0502
16
0503
16
0504
16
0505
16
0506
16
0507
16
0508
16
0509
16
050A
16
050B
16
050C
16
050D
16
050E
16
050F
16
0510
16
0511
16
0512
16
0513
16
0514
16
0515
16
0516
16
0517
16
0518
16
0519
16
051A
16
051B
16
051C
16
051D
16
051E
16
0520
16
0521
16
0522
16
0523
16
0524
16
0525
16
0526
16
0527
16
0528
16
0529
16
052A
16
052B
16
052C
16
052D
16
052E
16
052F
16
0531
16
0532
16
0533
16
0534
16
0535
16
0536
16
0537
16
0538
16
0539
16
053A
16
053B
16
053C
16
053D
16
053E
16
053F
16
0530
16
0541
16
0542
16
0543
16
0544
16
0545
16
0546
16
0547
16
0548
16
0549
16
054A
16
054B
16
054C
16
054D
16
054E
16
054F
16
0540
16
0500
16
The last timing
(The last data of FLDP4)
76543210
Bit
The last timing
(The last data of FLDP3)
The last timing
(The last data of FLDP2)
The last timing
(The last data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP4 gradation
display data area
FLDP3 gradation
display data area
FLDP2 gradation
display data area
FLDP1 gradation
display data area
FLDP0 gradation
display data area
0551
16
0552
16
0553
16
0554
16
0555
16
0556
16
0557
16
0558
16
0559
16
055A
16
055B
16
055C
16
055D
16
055E
16
055F
16
0550
16
The last timing
(The last data of FLDP5)
FLDP5 gradation
display data area
0561
16
0562
16
0563
16
0564
16
0565
16
0566
16
0567
16
0568
16
0569
16
056A
16
056B
16
056C
16
056D
16
056E
16
056F
16
0560
16
The last timing
(The last data of FLDP6)
FLDP6 gradation
display data area
Timing for start
(The first data of FLDP4)
Timing for start
(The first data of FLDP3)
Timing for start
(The first data of FLDP2)
Timing for start
(The first data of FLDP1)
Timing for start
(The first data of FLDP0)
Timing for start
(The first data of FLDP5)
Timing for start
(The first data of FLDP6)
Timing for start
(The first data of FLDP4)
Timing for start
(The first data of FLDP3)
Timing for start
(The first data of FLDP2)
Timing for start
(The first data of FLDP1)
Timing for start
(The first data of FLDP0)
Timing for start
(The first data of FLDP5)
Timing for start
(The first data of FLDP6)
64
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 47. Example of Using the FLD Automatic Display RAM in 32-timing Mode
Number of timing: 20
(FLD data pointer reload register = 19)
Address
058F
16
0571
16
0572
16
0573
16
0574
16
0575
16
0576
16
0577
16
0578
16
0579
16
057A
16
057B
16
057C
16
057D
16
057E
16
057F
16
0580
16
0581
16
0582
16
0583
16
0584
16
0585
16
0586
16
0587
16
0588
16
0589
16
058A
16
058B
16
058C
16
058D
16
058E
16
0590
16
0591
16
0592
16
0593
16
0594
16
0595
16
0596
16
0597
16
0598
16
0599
16
059A
16
059B
16
059C
16
059D
16
059E
16
059F
16
05A1
16
05A2
16
05A3
16
05A4
16
05A5
16
05A6
16
05A7
16
05A8
16
05A9
16
05AA
16
05AB
16
05AC
16
05AD
16
05AE
16
05AF
16
05A0
16
05B1
16
05B2
16
05B3
16
05B4
16
05B5
16
05B6
16
05B7
16
05B8
16
05B9
16
05BA
16
05BB
16
05BC
16
05BD
16
05BE
16
05BF
16
05B0
16
0570
16
76543210
Bit
FLDP0 data area
05C1
16
05C2
16
05C3
16
05C4
16
05C5
16
05C6
16
05C7
16
05C8
16
05C9
16
05CA
16
05CB
16
05CC
16
05CD
16
05CE
16
05CF
16
05C0
16
The last timing
(The last data of FLDP5)
FLDP5 data area
05D1
16
05D2
16
05D3
16
05D4
16
05D5
16
05D6
16
05D7
16
05D8
16
05D9
16
05DA
16
05DB
16
05DC
16
05DD
16
05DE
16
05DF
16
05D0
16
The last timing
(The last data of FLDP6)
FLDP6 data area
Address
051F
16
0501
16
0502
16
0503
16
0504
16
0505
16
0506
16
0507
16
0508
16
0509
16
050A
16
050B
16
050C
16
050D
16
050E
16
050F
16
0510
16
0511
16
0512
16
0513
16
0514
16
0515
16
0516
16
0517
16
0518
16
0519
16
051A
16
051B
16
051C
16
051D
16
051E
16
0520
16
0521
16
0522
16
0523
16
0524
16
0525
16
0526
16
0527
16
0528
16
0529
16
052A
16
052B
16
052C
16
052D
16
052E
16
052F
16
0531
16
0532
16
0533
16
0534
16
0535
16
0536
16
0537
16
0538
16
0539
16
053A
16
053B
16
053C
16
053D
16
053E
16
053F
16
0530
16
0541
16
0542
16
0543
16
0544
16
0545
16
0546
16
0547
16
0548
16
0549
16
054A
16
054B
16
054C
16
054D
16
054E
16
054F
16
0540
16
0500
16
The last timing
(The last data of FLDP4)
76543210
Bit
The last timing
(The last data of FLDP3)
The last timing
(The last data of FLDP2)
The last timing
(The last data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP4 data area
FLDP3 data area
FLDP2 data area
FLDP1 data area
0551
16
0552
16
0553
16
0554
16
0555
16
0556
16
0557
16
0558
16
0559
16
055A
16
055B
16
055C
16
055D
16
055E
16
055F
16
0550
16
0561
16
0562
16
0563
16
0564
16
0565
16
0566
16
0567
16
0568
16
0569
16
056A
16
056B
16
056C
16
056D
16
056E
16
056F
16
0560
16
Timing for start
(The first data of FLDP0)
Timing for start
(The first data of FLDP5)
Timing for start
(The first data of FLDP6)
Timing for start
(The first data of FLDP4)
Timing for start
(The first data of FLDP3)
Timing for start
(The first data of FLDP2)
Timing for start
(The first data of FLDP1)
65
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 48. FLDC Timing
Toff1
Tdisp
Toff1 Toff2
Tdisp
•Grayscale display mode is not selected
(Address 0350
16
bit 5 = “0”)
•Grayscale display mode is selected and set for bright display
(Address 0350
16
bit 5 = “1” and the corresponding grayscale
display control data = “0”)
Low output period for
blurring prevention Display output period
Display output
period
Low output period for
blurring prevention
•Grayscale display mode is selected and set for dark display
(Address 0350
16
bit 5 = “1” and the corresponding grayscale
display control data = “1”)
Low output period for
dark display
Timing setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
The Tdisp time represents the length of display timing. In non-gradation display mode, it consists of a
FLD display output period and a Toff1 time. In gradation display mode, it consists of the display output
period and Toff1 time plus a low signal output period for dark display. Set the Tdisp time by the Tdisp
counter count source select bit of the FLDC mode register and the Tdisp time set register. Supposing that
the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) x t (t: count
source). When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value
of the Tdisp time set register is 200 (C816), the Tdisp time is: Tdisp = (200+1) x 3.2 (at XIN= 10 MHz) =
643 µs. When reading the Tdisp time set register, the value in the counter is read out.
•Toff1 time setting
The Toff1 time represents a non-output (low signal output) time to prevent blurring of FLD, and to dim the
display. Use the Toff1 time set register to set this Toff1 time. Make sure the value set to Toff1 is smaller
than Tdisp and Toff2. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is
represented as Toff1 = n1 x t. When the Tdisp counter count source select bit of the FLDC mode register
is “0” and the value of the Toff1 time set register is 30 (1E16), Toff1 = 30 x 3.2 (at XIN = 10 MHz) = 96 µs.
•Toff2 time setting
The Toff2 time is provided for dark display. For bright display, the FLD display output remains effective
until the counter that is counting Tdisp reaches the terminal count. For dark display, however, “L” (or “off”)
signal is output when the counter that is counting Toff2 reaches the terminal count. This Toff2 time setting
is valid only for FLD ports which are in the gradation display mode and whose gradation display control
RAM value is “1” .
Set the Toff2 time by the Toff2 time set register. Make sure the value set to Toff2 is smaller than Tdisp but
larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is repre-
sented as Toff2 = n2 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0”
and the value of the Toff2 time set register is 180 (B416), Toff2 = 180 x 3.2 (at XIN = 10 MHz) = 576 µs.
66
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 49. Timing using digit interrupt
FLD digit output
Tdisp
Repeat synchronous
Tn Tn-1 Tn-2 T4 T3 T2 T1 Tn Tn-1 Tn-2 T4
Toff1
FLD digit interrupt generated at the rising edge of digit ( each timing)
FLD automatic display start
Automatic display starts by setting both the automatic display control bit (bit 0 of address 035016) and the
display start bit (bit 1 of address 035016) to “1”. The RAM content at a location apart from the start address
of the automatic display RAM for each port by (FLD data pointer (address 035816) – 1) is output to each
port. The FLD data pointer (address 035816) counts down in the Tdisp interval. When the count “FF16” is
reached, the pointer is reloaded and starts counting over again. Before setting the display start bit (bit 1 of
address 035016) to “1”, be sure to set the FLD/port switch register, FLD/DIG switch register, FLDC mode
register, Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer.
During FLD automatic display, bit 1 of the FLDC mode register (address 0350 16) always keeps “1”, and
FLD automatic display can be interrupted by writing “0” to bit 1.
Key-scan and interrupt
Either a FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3
of address 035016).
The FLD digit interrupt is generated when the Toff1 time in each timing expires (at rising edge of digit
output). Key scanning that makes use of FLD digits can be achieved using each FLD digit interrupt. To use
FLD digit interrupts for key scanning, follow the procedure described below.
(1) Read the port value each time the interrupt occurs.
(2) The key is fixed on the last digit interrupt.
The digit positions output can be determined by reading the FLD data pointer (address 035816).
67
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 50. Timing using FLD blanking interrupt
Tdisp Tscan
Tn Tn-1 Tn-2 T4 T3 T2 T1 Tn Tn-1 Tn-2
Segment setting by software
FLD blanking interrupt generated at the
falling of edge of the last digit
FLD digit output
Repeat synchronous
The FLD blanking interrupt is generated when the FLD data pointer (address 0358
16
) reaches “FF
16
”. The FLD automatic
display output is turned off for a duration of 1 x Tdisp, 2 x Tdisp, or 3 x Tdisp depending on post-interrupt settings. During
this time, key scanning that makes use of FLD segments can be achieved.
When a key-scan is performed with the segment during key-scan blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 035016).
2. Set the port corresponding to the segment for key-scan to the output port.
3. Perform the key-scan.
4.
After the key-scan is performed, write “1” to bit 0
of FLDC mode register (address 035016).
•Note:
When performing a key-scan according to the above steps 1 to 4, take the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 035016).
2. Do not set “1” in the ports corresponding to digits.
68
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
P44 to P47 Expansion Function
P44 to P47 are CMOS output-type ports. FLD digit outputs can be increased as many as 16 lines by con-
necting a 4-bit to 16-bit decoder to these ports. P44 to P47 have the function to allow for connection to a 4-
bit to 16-bit decoder.
(1) P44 to P47 Toff invalid Function
This function disables the Toff1 time and Toff2 time and outputs display data for the duration of Tdisp.
(See Figure 51.) This can be accomplished by setting the P44 to P47 Toff disable bit (address 0350 16 bit
2) to “1”.
Unlike the Toff section generate/not generate function, this function disables all display data.
(2) Dimmer signal output Function
This function allows a dimmer signal creation signal to be output from DIMOUT (P97). The dimmer function
can be materialized by controlling the decoder with this signal. (See Figure 51.) This function can be set
by writing P97 dimmer output control bit (bit 4 of address 035116) to “1”.
(3) P44 to P47 FLD Output Reverse Bit
P44 to P47 are provided with a function to reverse the polarity of the FLD output. This function is useful in
adjusting the polarity when using an externally installed driver.
The output polarity can be reversed by setting bit 0 of the FLD output control register (address 0351 16) to
“1” .
Figure 51. P4 to P47 FLD Output pulses
Tdisp
Toff2
Toff1
For dimmer signal
DIMOUT(P97)
FLD output
•Grayscale display mode is not selected
•Grayscale display mode is selected and
set for bright display
(grayscale display control data = “0”)
•Grayscale display mode is selected and
set for dark display
(grayscale display control data = “1”)
•Grayscale display mode is selected and
Toff2 SET/RESET bit is “1”
(grayscale display control data = “1”)
Output selecting P44 to P47
Toff invalid
69
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Toff2 SET/RESET change bit
In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the
FLD output control register (bit 7 of address 035116 ) in the initial state = “0”, RAM data is output to the FLD
output ports (SET) at the time that is set by TOFF1 and is turned to “0” (RESET) at the time that is set by
TOFF2. When bit 7 = “1”, RAM data is output (SET) at the time that is set by TOFF2 and is turned to “0”
(RESET) when the Tdisp time expires.
Toff section generate/not generate Function
The function is for reduction of useless noises which generated as every switching of ports, because of the
combined capacity of among FLD ports. In case the continuous data output to each FLD ports, the Toff1
section of the continuous parts is not generated. (See Figure 52)
If it needs Toff1 section on FLD pulses, set “CMOS ports: section of Toff generate / not generate bit” to
“1”
and set “high-breakdown-voltage ports: section of Toff generate / not generate bit” to
“1”
. High-breakdown-
voltage ports (P5, P6, P3, P2, P1, P0, P4
0
to P4
3
, total 52 pins) generate Toff1 section, by setting “high-
breakdown-voltage ports: section of Toff generate / not generate bit” to
“1”
.
The CMOS ports ( P44 to P47, total 4 pins ) generate Toff1 section, by setting
“high-breakdown-voltage
ports: section of Toff generate / not generate bit”
to “1”.
Figure 52. Toff Section Generated/not generated Function
P1X
P2X
P1X
P2X
“H” output
Output waveform when “high-
breakdown-voltage ports: section of Toff
generate/not generate bit”(bit 6 of 035116)
is “0”.
Tdisp
Toff1
Section of Toff1 is not generated because of output is same.
Output waveform when “high-
breakdown-voltage ports: section of Toff
generate/not generate bit”(bit 6 of 03511
6) is “1”.
“H” output
“H” output
“H” output “H” output
“H” output
“H” output “H” output
“H” output
“H” output
“H” output
“H” output
“L” output
“L” output
“L” output
“L” output
Section of Toff1 is not generated because of output is same.
70
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 53. Digit Pulses Output Function
Digit pulses output Function
P50 to P57 and P60 to P67 allow digit pulses to be output using the FLD/digit switch register. Set the digit
output set register by writing as many consecutive 1s as the timing count from P60. The contents of FLD
automatic display RAM for the ports that have been selected for digit output are disabled, and the pulse
shown in Figure 53 is output automatically. In gradation display mode use, Toff2 time becomes effective for
the port which selected digit output. Because the contents of FLD automatic display RAM are disabled, the
segment data can be changed easily even when segment data and digit data coexist at the same address
in the FLD automatic display RAM.
This function is effective in 16-timing normal mode and 16-timing gradation display mode. If a value is set
exceeding the timing count (FLD data pointer reload register's set value + 1) for any port, the output of such
port is “L”.
Low-order 4bits
of the data pointer
FEDCBA 0123456789
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
Tdisp
Toff1
71
Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 54 shows the block diagram of timers.
Figure 54. Timer block diagram
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
TA0
IN
/
TA3
OUT
TA1
IN
/
TA4
OUT
TA2
IN
/
TA0
OUT
TA3
IN
/
TA1
OUT
TA4
IN
/
TA2
OUT
TB0
IN
TB1
IN
TB2
IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
f
1
f
8
f
32
f
c32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32 f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
Clock prescaler reset flag
(bit 7 at address 0381
16
) set to “1”
Reset
Clock prescaler
72
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timer A
Figure 55 shows the block diagram of timer A. Figures 56 to 58 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer's over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 55. Block diagram of timer A
Figure 56. Timer A-related registers (1)
C
o
u
n
t
e
r
(
1
6
)
C
o
u
n
t
s
t
a
r
t
f
l
a
g
(
A
d
d
r
e
s
s
0
3
8
0
1
6
)
U
p
c
o
u
n
t
/
d
o
w
n
c
o
u
n
t
T
A
iA
d
d
r
e
s
s
e
sT
A
jT
A
kT
A
i
O
U
T
T
i
m
e
r
A
00
3
8
7
1
6
0
3
8
6
1
6
T
i
m
e
r
A
4T
i
m
e
r
A
1T
i
m
e
r
A
3
T
i
m
e
r
A
10
3
8
9
1
6
0
3
8
8
1
6
T
i
m
e
r
A
0T
i
m
e
r
A
2T
i
m
e
r
A
4
T
i
m
e
r
A
20
3
8
B
1
6
0
3
8
A
1
6
T
i
m
e
r
A
1T
i
m
e
r
A
3T
i
m
e
r
A
0
T
i
m
e
r
A
30
3
8
D
1
6
0
3
8
C
1
6
T
i
m
e
r
A
2T
i
m
e
r
A
4T
i
m
e
r
A
1
T
i
m
e
r
A
4
0
3
8
F
1
6
0
3
8
E
1
6
T
i
m
e
r
A
3T
i
m
e
r
A
0T
i
m
e
r
A
2
A
l
w
a
y
s
d
o
w
n
c
o
u
n
t
e
x
c
e
p
t
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
R
e
l
o
a
d
r
e
g
i
s
t
e
r
(
1
6
)
L
o
w
-
o
r
d
e
r
8
b
i
t
sH
i
g
h
-
o
r
d
e
r
8
b
i
t
s
C
l
o
c
k
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
•
T
i
m
e
r
(
g
a
t
e
f
u
n
c
t
i
o
n
)
•
T
i
m
e
r
•
O
n
e
s
h
o
t
•
P
W
M
f
1
f
8
f
3
2
E
x
t
e
r
n
a
l
t
r
i
g
g
e
r
T
A
i
I
N
(
i
=
0
t
o
4
)
T
B
2
o
v
e
r
f
l
o
w
•
E
v
e
n
t
c
o
u
n
t
e
r
f
C
3
2
C
l
o
c
k
s
e
l
e
c
t
i
o
n
T
A
j
o
v
e
r
f
l
o
w
(
j
=
i
-
1
.
N
o
t
e
,
h
o
w
e
v
e
r
,
t
h
a
t
j
=
4
w
h
e
n
i
=
0
)
P
u
l
s
e
o
u
t
p
u
t
T
o
g
g
l
e
f
l
i
p
-
f
l
o
p
T
A
i
O
U
T
(
i
=
0
t
o
4
)
D
a
t
a
b
u
s
l
o
w
-
o
r
d
e
r
b
i
t
s
D
a
t
a
b
u
s
h
i
g
h
-
o
r
d
e
r
b
i
t
s
U
p
/
d
o
w
n
f
l
a
g
D
o
w
n
c
o
u
n
t
(
A
d
d
r
e
s
s
0
3
8
4
1
6
)
T
A
k
o
v
e
r
f
l
o
w
(
k
=
i
+
1
.
N
o
t
e
,
h
o
w
e
v
e
r
,
t
h
a
t
k
=
0
w
h
e
n
i
=
4
)
P
o
l
a
r
i
t
y
s
e
l
e
c
t
i
o
n
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b
1b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select
bit
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
73
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 57. Timer A-related registers (2)
T
i
m
e
r
A
4
u
p
/
d
o
w
n
f
l
a
g
T
i
m
e
r
A
3
u
p
/
d
o
w
n
f
l
a
g
T
i
m
e
r
A
2
u
p
/
d
o
w
n
f
l
a
g
T
i
m
e
r
A
1
u
p
/
d
o
w
n
f
l
a
g
T
i
m
e
r
A
0
u
p
/
d
o
w
n
f
l
a
g
T
i
m
e
r
A
2
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
s
e
l
e
c
t
b
i
t
T
i
m
e
r
A
3
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
s
e
l
e
c
t
b
i
t
T
i
m
e
r
A
4
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
s
e
l
e
c
t
b
i
t
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
D
F0
3
8
41
60
01
6
T
A
4
P
T
A
3
P
T
A
2
P
U
p
/
d
o
w
n
f
l
a
g
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
T
A
4
U
D
T
A
3
U
D
T
A
2
U
D
T
A
1
U
D
T
A
0
U
D0
:
D
o
w
n
c
o
u
n
t
1
:
U
p
c
o
u
n
t
T
h
i
s
s
p
e
c
i
f
i
c
a
t
i
o
n
b
e
c
o
m
e
s
v
a
l
i
d
w
h
e
n
t
h
e
u
p
/
d
o
w
n
f
l
a
g
c
o
n
t
e
n
t
i
s
s
e
l
e
c
t
e
d
f
o
r
u
p
/
d
o
w
n
s
w
i
t
c
h
i
n
g
c
a
u
s
e
0
:
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
d
i
s
a
b
l
e
d
1
:
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
e
n
a
b
l
e
d
W
h
e
n
n
o
t
u
s
i
n
g
t
h
e
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
f
u
n
c
t
i
o
n
,
s
e
t
t
h
e
s
e
l
e
c
t
b
i
t
t
o
“
0
”
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
B
S
R0
3
8
01
60
01
6
C
o
u
n
t
s
t
a
r
t
f
l
a
g
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
T
i
m
e
r
B
2
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
B
1
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
B
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
4
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
3
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
2
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
1
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g0
:
S
t
o
p
s
c
o
u
n
t
i
n
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
T
B
2
S
T
B
1
S
T
B
0
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
S
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
00
3
8
71
6,
0
3
8
61
6I
n
d
e
t
e
r
m
i
n
a
t
e
T
A
10
3
8
91
6,
0
3
8
81
6I
n
d
e
t
e
r
m
i
n
a
t
e
T
A
20
3
8
B1
6,
0
3
8
A1
6I
n
d
e
t
e
r
m
i
n
a
t
e
T
A
30
3
8
D1
6,
0
3
8
C1
6I
n
d
e
t
e
r
m
i
n
a
t
e
T
A
40
3
8
F1
6,
0
3
8
E1
6I
n
d
e
t
e
r
m
i
n
a
t
e
b
7b
0b
7b
0
(
b
1
5
)
(
b
8
)
T
i
m
e
r
A
i
r
e
g
i
s
t
e
r
(
N
o
t
e
)
W
R
•
T
i
m
e
r
m
o
d
e0
0
0
01
6
t
o
F
F
F
F
C
o
u
n
t
s
a
n
i
n
t
e
r
n
a
l
c
o
u
n
t
s
o
u
r
c
e
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
•
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
C
o
u
n
t
s
p
u
l
s
e
s
f
r
o
m
a
n
e
x
t
e
r
n
a
l
s
o
u
r
c
e
o
r
t
i
m
e
r
o
v
e
r
f
l
o
w0
0
0
01
6
t
o
F
F
F
F1
6
•
O
n
e
-
s
h
o
t
t
i
m
e
r
m
o
d
e0
0
0
01
6
t
o
F
F
F
F1
6
C
o
u
n
t
s
a
o
n
e
s
h
o
t
w
i
d
t
h
•
P
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
i
o
n
m
o
d
e
(
1
6
-
b
i
t
P
W
M
)
F
u
n
c
t
i
o
n
s
a
s
a
1
6
-
b
i
t
p
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
o
r
0
01
6
t
o
F
E1
6
(
B
o
t
h
h
i
g
h
-
o
r
d
e
r
a
n
d
l
o
w
-
o
r
d
e
r
a
d
d
r
e
s
s
e
s
)
0
0
0
01
6
t
o
F
F
F
E1
6
N
o
t
e
:
R
e
a
d
a
n
d
w
r
i
t
e
d
a
t
a
i
s
i
n
1
6
-
b
i
t
u
n
i
t
s
.
•
P
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
i
o
n
m
o
d
e
(
8
-
b
i
t
P
W
M
)
T
i
m
e
r
l
o
w
-
o
r
d
e
r
a
d
d
r
e
s
s
f
u
n
c
t
i
o
n
s
a
s
a
n
8
-
b
i
t
p
r
e
s
c
a
l
e
r
a
n
d
h
i
g
h
-
o
r
d
e
r
a
d
d
r
e
s
s
f
u
n
c
t
i
o
n
s
a
s
a
n
8
-
b
i
t
p
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
o
r
74
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 58 Timer A-related registers (3)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
C
P
S
R
F0
3
8
1
1
6
0
X
X
X
X
X
X
X
2
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g0
:
N
o
e
f
f
e
c
t
1
:
P
r
e
s
c
a
l
e
r
i
s
r
e
s
e
t
(
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
i
s
“
0
”
)
C
P
S
R
W
R
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
e
s
e
b
i
t
s
c
a
n
n
e
i
t
h
e
r
b
e
s
e
t
n
o
r
r
e
s
e
t
.
W
h
e
n
r
e
a
d
,
t
h
e
i
r
c
o
n
t
e
n
t
s
a
r
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
T
A
1
T
G
L
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
R
G
S
R0
3
8
3
1
6
0
0
1
6
T
i
m
e
r
A
1
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t0
0
:
I
n
p
u
t
o
n
T
A
1
I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
0
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
T
r
i
g
g
e
r
s
e
l
e
c
t
r
e
g
i
s
t
e
r
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
0
0
:
I
n
p
u
t
o
n
T
A
2
I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
1
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
3
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
0
0
:
I
n
p
u
t
o
n
T
A
3
I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
4
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
0
0
:
I
n
p
u
t
o
n
T
A
4
I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
3
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
0
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
T
i
m
e
r
A
2
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
T
i
m
e
r
A
3
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
T
i
m
e
r
A
4
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
W
R
T
A
1
T
G
H
T
A
2
T
G
L
T
A
2
T
G
H
T
A
3
T
G
L
T
A
3
T
G
H
T
A
4
T
G
L
T
A
4
T
G
H
b
1
b
0
b
3
b
2
b
5
b
4
b
7
b
6
N
o
t
e
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
W
h
e
n
T
A
i
I
N
i
s
s
e
l
e
c
t
e
d
,
T
A
i
O
U
T
a
s
s
i
g
n
e
d
o
n
s
a
m
e
p
i
n
c
a
n
n
o
t
b
e
u
s
e
d
.
(
i
=
0
t
o
4
)
T
A
1
O
S
T
A
2
O
S
T
A
0
O
S
O
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
O
N
S
F0
3
8
2
1
6
0
0
X
0
0
0
0
0
2
T
i
m
e
r
A
0
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
1
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
2
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
3
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
4
o
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
T
A
3
O
S
T
A
4
O
S
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
i
s
b
i
t
c
a
n
n
e
i
t
h
e
r
b
e
s
e
t
n
o
r
r
e
s
e
t
.
W
h
e
n
r
e
a
d
,
t
h
e
c
o
n
t
e
n
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
.
T
A
0
T
G
L
T
A
0
T
G
H
0
0
:
I
n
p
u
t
o
n
T
A
0
I
N
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
)
0
1
:
T
B
2
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
0
:
T
A
4
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
1
1
:
T
A
1
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
T
i
m
e
r
A
0
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
b
7
b
6
N
o
t
e
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
W
h
e
n
T
A
i
I
N
i
s
s
e
l
e
c
t
e
d
,
T
A
i
O
U
T
a
s
s
i
g
n
e
d
o
n
s
a
m
e
p
i
n
c
a
n
n
o
t
b
e
u
s
e
d
.
(
i
=
0
t
o
4
)
W
R
1
:
T
i
m
e
r
s
t
a
r
t
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
i
s
“
0
”
75
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Count source f1, f8, f32, fC32
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing countin
g
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table16.) Figure 59 shows the
timer Ai mode register in timer mode.
Table 16. Specifications of timer mode
N
o
t
e
1
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
.
N
o
t
e
2
:
T
h
e
b
i
t
c
a
n
b
e
“
0
”
o
r
“
1
”
.
N
o
t
e
3
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
0
t
o
4
)0
3
9
6
1
6
t
o
0
3
9
A
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
0
:
T
i
m
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
A
i
O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
1
:
P
u
l
s
e
i
s
o
u
t
p
u
t
(
N
o
t
e
1
)
(
T
A
i
O
U
T
p
i
n
i
s
a
p
u
l
s
e
o
u
t
p
u
t
p
i
n
)
G
a
t
e
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t0
X
(
N
o
t
e
2
)
:
G
a
t
e
f
u
n
c
t
i
o
n
n
o
t
a
v
a
i
l
a
b
l
e
(
T
A
i
I
N
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
1
0
:
T
i
m
e
r
c
o
u
n
t
s
o
n
l
y
w
h
e
n
T
A
i
I
N
p
i
n
i
s
h
e
l
d
“
L
”
(
N
o
t
e
3
)
1
1
:
T
i
m
e
r
c
o
u
n
t
s
o
n
l
y
w
h
e
n
T
A
i
I
N
p
i
n
i
s
h
e
l
d
“
H
”
(
N
o
t
e
3
)
b
4
b
3
M
R
2
M
R
1
M
R
30
(
M
u
s
t
a
l
w
a
y
s
b
e
f
i
x
e
d
t
o
“
0
”
i
n
t
i
m
e
r
m
o
d
e
)
0
0
:
f
1
0
1
:
f
8
1
0
:
f
3
2
1
1
:
f
C
3
2
b
7
b
6
T
C
K
1
T
C
K
0C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
000
Figure 59. Timer Ai mode register in timer mode
76
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 17 lists timer specifications when counting a single-phase external signal. Figure
60 shows the timer Ai mode register in event counter mode.
Table 18 lists timer specifications when counting a two-phase external signal. Figure 61 shows the timer
Ai mode register in event counter mode.
Table 17. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item Specification
Count source
•External signals input to TAi
IN
pin (effective edge can be selected by software)
•TB2 overflow, TAj overflow
Count operation •Up count or down count can be selected by external signal or software
•
When the timer overflows or underflows, the reload register's content is reloaded
and the timer starts over again.
(Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer overflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading timer Ai register
Write to timer •When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function •Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
•Pulse output function
Each time the timer overflows or underflows, the TAi
OUT
pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
N
o
t
e
1
:
I
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
,
t
h
e
c
o
u
n
t
s
o
u
r
c
e
i
s
s
e
l
e
c
t
e
d
b
y
t
h
e
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
e
s
0
3
8
21
6
a
n
d
0
3
8
31
6)
.
N
o
t
e
2
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
.
N
o
t
e
3
:
V
a
l
i
d
o
n
l
y
w
h
e
n
c
o
u
n
t
i
n
g
a
n
e
x
t
e
r
n
a
l
s
i
g
n
a
l
.
N
o
t
e
4
:
W
h
e
n
a
n
“
L
”
s
i
g
n
a
l
i
s
i
n
p
u
t
t
o
t
h
e
T
A
iO
U
T
p
i
n
,
t
h
e
d
o
w
n
c
o
u
n
t
i
s
a
c
t
i
v
a
t
e
d
.
W
h
e
n
“
H
”
,
t
h
e
u
p
c
o
u
n
t
i
s
a
c
t
i
v
a
t
e
d
.
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
0
,
1
)0
3
9
61
6,
0
3
9
71
60
01
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e (
N
o
t
e
1
)
b
1
b
0
T
M
O
D
0
M
R
0
P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
Ai
O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
1
:
P
u
l
s
e
i
s
o
u
t
p
u
t
(
N
o
t
e
2
)
(
T
Ai
O
U
T
p
i
n
i
s
a
p
u
l
s
e
o
u
t
p
u
t
p
i
n
)
C
o
u
n
t
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
(
N
o
t
e
3
)
M
R
2
M
R
1
M
R
30
(
M
u
s
t
a
l
w
a
y
s
b
e
f
i
x
e
d
t
o
“
0
”
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
)
T
C
K
0C
o
u
n
t
o
p
e
r
a
t
i
o
n
t
y
p
e
s
e
l
e
c
t
b
i
t
010
0
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
f
a
l
l
i
n
g
e
d
g
e
1
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
r
i
s
i
n
g
e
d
g
e
U
p
/
d
o
w
n
s
w
i
t
c
h
i
n
g
c
a
u
s
e
s
e
l
e
c
t
b
i
t0
:
U
p
/
d
o
w
n
f
l
a
g
'
s
c
o
n
t
e
n
t
1
:
T
Ai
O
U
T
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
4
)
0
:
R
e
l
o
a
d
t
y
p
e
1
:
F
r
e
e
-
r
u
n
t
y
p
e
B
i
t
s
y
m
b
o
l
T
C
K
1I
n
v
a
l
i
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
C
a
n
b
e
“
0
”
o
r
“
1
”
T
M
O
D
1
Figure 60. Timer Ai mode register in event counter mode
77
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Count source •Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation •Up count or down count can be selected by two-phase pulse signal
•When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
Timer overflows or underflows
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Write to timer •When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
•When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
Select function •Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
•Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
Note: This does not apply when the free-run function is selected.
Table 18. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2,A3 and A4
TAi
OUT
Up
count Up
count Up
count Down
count Down
count Down
count
TAi
IN
(i=2,3)
TAi
OUT
TAi
IN
(i=3,4)
Count up all edges
Count up all ed
g
es
Count down all edges
Count down all ed
g
es
78
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
B
i
t
s
y
m
b
o
lB
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
N
o
t
e
1
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
N
o
t
e
2
:
T
h
i
s
b
i
t
i
s
v
a
l
i
d
w
h
e
n
o
n
l
y
c
o
u
n
t
i
n
g
a
n
e
x
t
e
r
n
a
l
s
i
g
n
a
l
.
N
o
t
e
3
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
N
o
t
e
4
:
T
h
i
s
b
i
t
i
s
v
a
l
i
d
f
o
r
t
i
m
e
r
A
3
m
o
d
e
r
e
g
i
s
t
e
r
.
F
o
r
t
i
m
e
r
A
2
a
n
d
A
4
m
o
d
e
r
e
g
i
s
t
e
r
s
,
t
h
i
s
b
i
t
c
a
n
b
e
“
0
”
o
r
“
1
”
.
N
o
t
e
5
:
W
h
e
n
p
e
r
f
o
r
m
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
,
m
a
k
e
s
u
r
e
t
h
e
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
0
3
8
4
1
6
)
i
s
s
e
t
t
o
“
1
”
.
A
l
s
o
,
a
l
w
a
y
s
b
e
s
u
r
e
t
o
s
e
t
t
h
e
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
e
s
0
3
8
2
1
6
a
n
d
0
3
8
3
1
6
)
t
o
“
0
0
”
.
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
(
W
h
e
n
n
o
t
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
2
t
o
4
)0
3
9
8
1
6
t
o
0
3
9
A
1
6
0
0
1
6
B
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0
P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
A
i
O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
1
:
P
u
l
s
e
i
s
o
u
t
p
u
t
(
N
o
t
e
1
)
(
T
A
i
O
U
T
p
i
n
i
s
a
p
u
l
s
e
o
u
t
p
u
t
p
i
n
)
C
o
u
n
t
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
(
N
o
t
e
2
)
M
R
2
M
R
1
M
R
30
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
)
T
C
K
1
T
C
K
0
010
0
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
f
a
l
l
i
n
g
e
d
g
e
s
1
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
r
i
s
i
n
g
e
d
g
e
s
U
p
/
d
o
w
n
s
w
i
t
c
h
i
n
g
c
a
u
s
e
s
e
l
e
c
t
b
i
t0
:
U
p
/
d
o
w
n
f
l
a
g
'
s
c
o
n
t
e
n
t
1
:
T
A
i
O
U
T
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
3
)
W
R
C
o
u
n
t
o
p
e
r
a
t
i
o
n
t
y
p
e
s
e
l
e
c
t
b
i
t
T
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
s
e
l
e
c
t
b
i
t
(
N
o
t
e
4
)
(
N
o
t
e
5
)
0
:
R
e
l
o
a
d
t
y
p
e
1
:
F
r
e
e
-
r
u
n
t
y
p
e
0
:
N
o
r
m
a
l
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
1
:
M
u
l
t
i
p
l
y
-
b
y
-
4
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
N
o
t
e
1
:
T
h
i
s
b
i
t
i
s
v
a
l
i
d
f
o
r
t
i
m
e
r
A
3
m
o
d
e
r
e
g
i
s
t
e
r
.
F
o
r
t
i
m
e
r
A
2
a
n
d
A
4
m
o
d
e
r
e
g
i
s
t
e
r
s
,
t
h
i
s
b
i
t
c
a
n
b
e
“
0
”
o
r
“
1
”
.
N
o
t
e
2
:
W
h
e
n
p
e
r
f
o
r
m
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
,
m
a
k
e
s
u
r
e
t
h
e
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
0
3
8
4
1
6
)
i
s
s
e
t
t
o
“
1
”
.
A
l
s
o
,
a
l
w
a
y
s
b
e
s
u
r
e
t
o
s
e
t
t
h
e
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
e
s
0
3
8
2
1
6
a
n
d
0
3
8
3
1
6
)
t
o
“
0
0
”
.
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
(
W
h
e
n
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
2
t
o
4
)0
3
9
8
1
6
t
o
0
3
9
A
1
6
0
0
1
6
b
7b
6
b
5b
4b
3
b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
00
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
w
h
e
n
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
0
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
w
h
e
n
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
M
R
2
M
R
1
M
R
30
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
w
h
e
n
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
T
C
K
1
T
C
K
0
010
1
(
M
u
s
t
a
l
w
a
y
s
b
e
“
1
”
w
h
e
n
u
s
i
n
g
t
w
o
-
p
h
a
s
e
p
u
l
s
e
s
i
g
n
a
l
p
r
o
c
e
s
s
i
n
g
)
W
R
C
o
u
n
t
o
p
e
r
a
t
i
o
n
t
y
p
e
s
e
l
e
c
t
b
i
t
T
w
o
-
p
h
a
s
e
p
u
l
s
e
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
s
e
l
e
c
t
b
i
t
(
N
o
t
e
1
)
(
N
o
t
e
2
)
0
:
R
e
l
o
a
d
t
y
p
e
1
:
F
r
e
e
-
r
u
n
t
y
p
e
0
:
N
o
r
m
a
l
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
1
:
M
u
l
t
i
p
l
y
-
b
y
-
4
p
r
o
c
e
s
s
i
n
g
o
p
e
r
a
t
i
o
n
001
Figure 61. Timer Ai mode register in event counter m
79
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 0000
16
, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer •When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 19.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 62 shows the timer Ai mode register in one-shot timer mode.
Table 19. Timer specifications in one-shot timer mode
Figure 62. Timer Ai mode register in one-shot timer mode
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
0
t
o
4
)0
3
9
6
1
6
t
o
0
3
9
A
1
6
0
0
1
6
b
7b
6b
5
b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t1
0
:
O
n
e
-
s
h
o
t
t
i
m
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0
P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
A
i
O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
1
:
P
u
l
s
e
i
s
o
u
t
p
u
t
(
N
o
t
e
1
)
(
T
A
i
O
U
T
p
i
n
i
s
a
p
u
l
s
e
o
u
t
p
u
t
p
i
n
)
M
R
2
M
R
1
W
R
M
R
3
0
0
:
f
1
0
1
:
f
8
1
0
:
f
3
2
1
1
:
f
C
3
2
b
7
b
6
T
C
K
1
T
C
K
0
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
100
0
:
O
n
e
-
s
h
o
t
s
t
a
r
t
f
l
a
g
i
s
v
a
l
i
d
1
:
S
e
l
e
c
t
e
d
b
y
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
r
e
g
i
s
t
e
r
T
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
E
x
t
e
r
n
a
l
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
N
o
t
e
2
)
0
:
F
a
l
l
i
n
g
e
d
g
e
o
f
T
A
i
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
3
)
1
:
R
i
s
i
n
g
e
d
g
e
o
f
T
A
i
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
3
)
N
o
t
e
1
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
N
o
t
e
2
:
V
a
l
i
d
o
n
l
y
w
h
e
n
t
h
e
T
A
i
I
N
p
i
n
i
s
s
e
l
e
c
t
e
d
b
y
t
h
e
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
e
s
0
3
8
2
1
6
a
n
d
0
3
8
3
1
6
)
.
I
f
t
i
m
e
r
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
,
t
h
i
s
b
i
t
c
a
n
b
e
“
1
”
o
r
“
0
”
.
N
o
t
e
3
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
0
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
i
n
o
n
e
-
s
h
o
t
t
i
m
e
r
m
o
d
e
)
80
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 20.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 63 shows the timer
Ai mode register in pulse width modulation mode. Figure 64 shows the example of how a 16-bit pulse width
modulator operates. Figure 65 shows the example of how an 8-bit pulse width modulator operates.
Table 20. Timer specifications in pulse width modulation mode
Figure 63. Timer Ai mode register in pulse width modulation mode
Item Specification
Count source f1, f8, f32, fC32
Count operation •
The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
•The timer is not affected by a trigger that occurs when counting
16-bit PWM •High level width n / fi n : Set value
•Cycle time (216-1) / fi fixed
8-bit PWM •High level width n X (m+1) / fi
n : values set to timer Ai register’s high-order address
•Cycle time (28-1) X (m+1) / fi
m : values set to timer Ai register’s low-order address
Count start condition •External trigger is input
•The timer overflows
•The count start flag is set (= 1)
Count stop condition •The count start flag is reset (= 0)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer •When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
T
i
m
e
r
A
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
i
M
R
(
i
=
0
t
o
4
)0
3
9
6
1
6
t
o
0
3
9
A
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7
b
6b
5b
4b
3
b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t1
1
:
P
W
M
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0
M
R
2
M
R
1
M
R
3
0
0
:
f
1
0
1
:
f
8
1
0
:
f
3
2
1
1
:
f
C
3
2
b
7
b
6
T
C
K
1
T
C
K
0
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
W
R
111
1
(
M
u
s
t
a
l
w
a
y
s
b
e
f
i
x
e
d
t
o
“
1
”
i
n
P
W
M
m
o
d
e
)
1
6
/
8
-
b
i
t
P
W
M
m
o
d
e
s
e
l
e
c
t
b
i
t
0
:
F
u
n
c
t
i
o
n
s
a
s
a
1
6
-
b
i
t
p
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
o
r
1
:
F
u
n
c
t
i
o
n
s
a
s
a
n
8
-
b
i
t
p
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
o
r
T
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
E
x
t
e
r
n
a
l
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
N
o
t
e
1
)
0
:
F
a
l
l
i
n
g
e
d
g
e
o
f
T
A
i
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
2
)
1
:
R
i
s
i
n
g
e
d
g
e
o
f
T
A
i
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
(
N
o
t
e
2
)
0
:
C
o
u
n
t
s
t
a
r
t
f
l
a
g
i
s
v
a
l
i
d
1
:
S
e
l
e
c
t
e
d
b
y
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
r
e
g
i
s
t
e
r
N
o
t
e
1
:
V
a
l
i
d
o
n
l
y
w
h
e
n
t
h
e
T
A
i
I
N
p
i
n
i
s
s
e
l
e
c
t
e
d
b
y
t
h
e
e
v
e
n
t
/
t
r
i
g
g
e
r
s
e
l
e
c
t
b
i
t
(
a
d
d
r
e
s
s
e
s
0
3
8
2
1
6
a
n
d
0
3
8
3
1
6
)
.
I
f
t
i
m
e
r
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
,
t
h
i
s
b
i
t
c
a
n
b
e
“
1
”
o
r
“
0
N
o
t
e
2
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
81
TimerA
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 64. Example of how a 16-bit pulse width modulator operates
Figure 65. Example of how an 8-bit pulse width modulator operates
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Trigger is not generated by this signal
Count source
Condition : Reload register = 0003
16
, when external trigger
(falling edge of TA0
IN
pin's input signal) is selected.
1 / f
i
X
(2 –1)
16
TA0
IN
pin's
input signal
PWM pulse output
from TA0
OUT
pin
“H”
“H”
“L”
“L”
Timer A0 interrupt
request bit
“1”
“0”
Cleared to “0” by software, or when interrupt request is accepted.
Note: n = 0000
16
to FFFE
16
.
1 / f
i
X
n
C
o
u
n
t
s
o
u
r
c
e
(
N
o
t
e
1
)
T
A
0
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
U
n
d
e
r
f
l
o
w
s
i
g
n
a
l
o
f
8
-
b
i
t
p
r
e
s
c
a
l
e
r
(
N
o
t
e
2
)
P
W
M
p
u
l
s
e
o
u
t
p
u
t
f
r
o
m
T
A
0
O
U
T
p
i
n
“
H
”
“
H
”
“
L
”
“
L
”
T
i
m
e
r
A
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
f
i
:
F
r
e
q
u
e
n
c
y
o
f
c
o
u
n
t
s
o
u
r
c
e
(
f
1
,
f
8
,
f
3
2
,
f
C
3
2
)
N
o
t
e
1
:
T
h
e
8
-
b
i
t
p
r
e
s
c
a
l
e
r
c
o
u
n
t
s
t
h
e
c
o
u
n
t
s
o
u
r
c
e
.
N
o
t
e
2
:
T
h
e
8
-
b
i
t
p
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
o
r
c
o
u
n
t
s
t
h
e
8
-
b
i
t
p
r
e
s
c
a
l
e
r
'
s
u
n
d
e
r
f
l
o
w
s
i
g
n
a
l
.
N
o
t
e
3
:
m
=
0
0
1
6
t
o
F
E
1
6
;
n
=
0
0
1
6
t
o
F
E
1
6
.
C
o
n
d
i
t
i
o
n
:
R
e
l
o
a
d
r
e
g
i
s
t
e
r
'
s
h
i
g
h
-
o
r
d
e
r
8
b
i
t
s
=
0
2
1
6
R
e
l
o
a
d
r
e
g
i
s
t
e
r
'
s
l
o
w
-
o
r
d
e
r
b
i
t
s
8
=
0
2
1
6
W
h
e
n
e
x
t
e
r
n
a
l
t
r
i
g
g
e
r
(
f
a
l
l
i
n
g
e
d
g
e
o
f
T
A
0
I
N
p
i
n
'
s
i
n
p
u
t
s
i
g
n
a
l
)
i
s
s
e
l
e
c
t
e
d
.
1
/
f
i
X
(
m
+
1
)
X
(
2
–
1
)
8
1
/
f
i
X
(
m
+
1
)
X
n
1
/
f
i
X
(
m
+
1
)
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
“
H
”
“
L
”
“
1
”
“
0
”
82
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timer B
Figure 66 shows the block diagram of timer B. Figures 67 and 68 show the timer B-related registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
•
Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Figure 66. Block diagram of timer B
Clock source selection
(address 0380
16
)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16)
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
1
f
8
f
32
TBj overflow
(j = i - 1. Note, however,
j = 2 when i = 0)
Can be selected in only
event counter mode
Count start flag
fc
32
Polarity switching
and edge pulse
(i = 0 to 2)
Counter reset circuit
Counter (16)
TBi Address TBj
Timer B0 0391
16
0390
16
Timer B2
Timer B1 0393
16
0392
16
Timer B0
Timer B2 0395
16
0394
16
Timer B1
TBi
IN
T
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
i
M
R
(
i
=
0
t
o
2
)0
3
9
B
1
6
t
o
0
3
9
D
1
6
0
0
X
X
0
0
0
0
2
B
i
t
s
y
m
b
o
lB
i
t
n
a
m
eF
u
n
c
t
i
o
n
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
0
0
:
T
i
m
e
r
m
o
d
e
0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
0
:
P
u
l
s
e
p
e
r
i
o
d
/
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
T
C
K
1
M
R
3
M
R
2
M
R
1
T
M
O
D
1
M
R
0
T
M
O
D
0
T
C
K
0
F
u
n
c
t
i
o
n
v
a
r
i
e
s
w
i
t
h
e
a
c
h
o
p
e
r
a
t
i
o
n
m
o
d
e
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
(
F
u
n
c
t
i
o
n
v
a
r
i
e
s
w
i
t
h
e
a
c
h
o
p
e
r
a
t
i
o
n
m
o
d
e
)
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t
(
N
o
t
e
1
)
(
N
o
t
e
2
)
N
o
t
e
1
:
T
i
m
e
r
B
0
.
N
o
t
e
2
:
T
i
m
e
r
B
1
,
t
i
m
e
r
B
2
.
Figure 67. Timer B-related registers (1)
83
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 68. Timer B-related registers (2)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
A
B
S
R0
3
8
0
1
6
0
0
1
6
C
o
u
n
t
s
t
a
r
t
f
l
a
g
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
lWR
b
7b
6b
5b
4b
3b
2b
1b
0
T
i
m
e
r
B
2
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
B
1
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
B
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
4
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
3
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
2
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
1
c
o
u
n
t
s
t
a
r
t
f
l
a
g
T
i
m
e
r
A
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g0
:
S
t
o
p
s
c
o
u
n
t
i
n
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
T
B
2
S
T
B
1
S
T
B
0
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
S
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
C
P
S
R
F0
3
8
1
1
6
0
X
X
X
X
X
X
X
2
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
lWR
b
7b
6b
5b
4b
3b
2b
1b
0
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g0
:
N
o
e
f
f
e
c
t
1
:
P
r
e
s
c
a
l
e
r
i
s
r
e
s
e
t
(
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
i
s
“
0
”
)
C
P
S
R
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
00
3
9
1
1
6
,
0
3
9
0
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
T
B
10
3
9
3
1
6
,
0
3
9
2
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
T
B
20
3
9
5
1
6
,
0
3
9
4
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
b
7b
0b
7b
0
(
b
1
5
)(
b
8
)
T
i
m
e
r
B
i
r
e
g
i
s
t
e
r
(
N
o
t
e
)
W
R
•
P
u
l
s
e
p
e
r
i
o
d
/
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
M
e
a
s
u
r
e
s
a
p
u
l
s
e
p
e
r
i
o
d
o
r
w
i
d
t
h
•
T
i
m
e
r
m
o
d
e0
0
0
0
1
6
t
o
F
F
F
F
1
6
C
o
u
n
t
s
t
h
e
t
i
m
e
r
'
s
p
e
r
i
o
d
F
u
n
c
t
i
o
n
V
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
•
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e0
0
0
0
1
6
t
o
F
F
F
F
1
6
C
o
u
n
t
s
e
x
t
e
r
n
a
l
p
u
l
s
e
s
i
n
p
u
t
o
r
a
t
i
m
e
r
o
v
e
r
f
l
o
w
N
o
t
e
:
R
e
a
d
a
n
d
w
r
i
t
e
d
a
t
a
i
n
1
6
-
b
i
t
u
n
i
t
s
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
84
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Count source f1, f8, f32, fC32
Count operation •Counts down
•When the timer underflows, the reload register's content is reloaded and the
timer starts over again.
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer •When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 21.) Figure 69 shows the
timer Bi mode register in timer mode.
Table 21. Timer specifications in timer mode
Figure 69. Timer Bi mode register in timer mode
N
o
t
e
1
:
T
i
m
e
r
B
0
.
N
o
t
e
2
:
T
i
m
e
r
B
1
,
t
i
m
e
r
B
2
.
T
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
i
M
R
(
i
=
0
t
o
2
)0
3
9
B1
6
t
o
0
3
9
D1
60
0
X
X
0
0
0
02
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
0
:
T
i
m
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0
I
n
v
a
l
i
d
i
n
t
i
m
e
r
m
o
d
e
C
a
n
b
e
“
0
”
o
r
“
1
”
M
R
2
M
R
1
M
R
3
0
0
:
f1
0
1
:
f8
1
0
:
f3
2
1
1
:
fC
3
2
T
C
K
1
T
C
K
0C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
0
I
n
v
a
l
i
d
i
n
t
i
m
e
r
m
o
d
e
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
i
n
t
i
m
e
r
m
o
d
e
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
0
0
(
F
i
x
e
d
t
o
“
0
”
i
n
t
i
m
e
r
m
o
d
e
;
i
=
0
)
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
(
i
=
1
,
2
)
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
(
N
o
t
e
1
)
(
N
o
t
e
2
)
b
7
b
6
85
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 70. Timer Bi mode register in event counter mode
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 22.) Figure 70
shows the timer Bi mode register in event counter mode.
Table 22. Timer specifications in event counter mode
Item Specification
Count source •External signals input to TBiIN pin
•Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation •Counts down
•When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
I
nterrupt request generation timing
The timer underflows
TBiIN pin function Count source input
Read from timer Count value can be read out by reading timer Bi register
Write to timer •When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
•When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
T
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
i
M
R
(
i
=
0
t
o
2
)0
3
9
B1
6
t
o
0
3
9
D1
60
0
X
X
0
0
0
02
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
lWR
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0C
o
u
n
t
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
(
N
o
t
e
1
)
M
R
2
M
R
1
M
R
3I
n
v
a
l
i
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
T
C
K
1
T
C
K
0
01
0
0
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
f
a
l
l
i
n
g
e
d
g
e
s
0
1
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
r
i
s
i
n
g
e
d
g
e
s
1
0
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
'
s
f
a
l
l
i
n
g
a
n
d
r
i
s
i
n
g
e
d
g
e
s
1
1
:
I
n
h
i
b
i
t
e
d
b
3
b
2
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
(
i
=
1
,
2
)
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
N
o
t
e
1
:
V
a
l
i
d
o
n
l
y
w
h
e
n
i
n
p
u
t
f
r
o
m
t
h
e
T
B
iI
N
p
i
n
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
e
v
e
n
t
c
l
o
c
k
.
I
f
t
i
m
e
r
'
s
o
v
e
r
f
l
o
w
i
s
s
e
l
e
c
t
e
d
,
t
h
i
s
b
i
t
c
a
n
b
e
“
0
”
o
r
“
1
”
.
N
o
t
e
2
:
T
i
m
e
r
B
0
.
N
o
t
e
3
:
T
i
m
e
r
B
1
,
t
i
m
e
r
B
2
.
N
o
t
e
4
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
I
n
v
a
l
i
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
.
C
a
n
b
e
“
0
”
o
r
“
1
”
.
E
v
e
n
t
c
l
o
c
k
s
e
l
e
c
t0
:
I
n
p
u
t
f
r
o
m
T
B
iI
N
p
i
n
(
N
o
t
e
4
)
1
:
T
B
j
o
v
e
r
f
l
o
w
(
j
=
i
-
1
;
h
o
w
e
v
e
r
,
j
=
2
w
h
e
n
i
=
0
)
0
(
F
i
x
e
d
t
o
“
0
”
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
;
i
=
0
)
(
N
o
t
e
2
)
(
N
o
t
e
3
)
86
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Count source f1, f8, f32, fC32
Count operation •Up count
•Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
•When measurement pulse's effective edge is input (Note 1)
•When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count start
flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function Measurement pulse input
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2:
The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 23.)
Figure 71 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 72
shows the operation timing when measuring a pulse period. Figure 73 shows the operation timing when
measuring a pulse width.
Table 23. Timer specifications in pulse period/pulse width measurement mode
Figure 71. Timer Bi mode register in pulse period/pulse width measurement mode
T
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
i
M
R
(
i
=
0
t
o
2
)0
3
9
B
1
6
t
o
0
3
9
D
1
6
0
0
X
X
0
0
0
0
2
B
i
t
n
a
m
eB
i
t
s
y
m
b
o
l
WR
b
7b
6b
5b
4b
3b
2b
1b
0
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t1
0
:
P
u
l
s
e
p
e
r
i
o
d
/
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
b
1
b
0
T
M
O
D
1
T
M
O
D
0
M
R
0M
e
a
s
u
r
e
m
e
n
t
m
o
d
e
s
e
l
e
c
t
b
i
t
M
R
2
M
R
1
M
R
3
T
C
K
1
T
C
K
0
01
0
0
:
P
u
l
s
e
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
(
I
n
t
e
r
v
a
l
b
e
t
w
e
e
n
m
e
a
s
u
r
e
m
e
n
t
p
u
l
s
e
'
s
f
a
l
l
i
n
g
e
d
g
e
t
o
f
a
l
l
i
n
g
e
d
g
e
)
0
1
:
P
u
l
s
e
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
(
I
n
t
e
r
v
a
l
b
e
t
w
e
e
n
m
e
a
s
u
r
e
m
e
n
t
p
u
l
s
e
'
s
r
i
s
i
n
g
e
d
g
e
t
o
r
i
s
i
n
g
e
d
g
e
)
1
0
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
(
I
n
t
e
r
v
a
l
b
e
t
w
e
e
n
m
e
a
s
u
r
e
m
e
n
t
p
u
l
s
e
'
s
f
a
l
l
i
n
g
e
d
g
e
t
o
r
i
s
i
n
g
e
d
g
e
,
a
n
d
b
e
t
w
e
e
n
r
i
s
i
n
g
e
d
g
e
t
o
f
a
l
l
i
n
g
e
d
g
e
)
1
1
:
I
n
h
i
b
i
t
e
d
F
u
n
c
t
i
o
n
b
3
b
2
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
(
i
=
1
,
2
)
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
T
i
m
e
r
B
i
o
v
e
r
f
l
o
w
f
l
a
g
(
N
o
t
e
1
)0
:
T
i
m
e
r
d
i
d
n
o
t
o
v
e
r
f
l
o
w
1
:
T
i
m
e
r
h
a
s
o
v
e
r
f
l
o
w
e
d
0
0
:
f
1
0
1
:
f
8
1
0
:
f
3
2
1
1
:
f
C
3
2
b
7
b
6
N
o
t
e
1
:
T
h
e
t
i
m
e
r
B
i
o
v
e
r
f
l
o
w
f
l
a
g
c
h
a
n
g
e
s
t
o
“
0
”
w
h
e
n
t
h
e
c
o
u
n
t
s
t
a
r
t
f
l
a
g
i
s
“
1
”
a
n
d
a
v
a
l
u
e
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
.
T
h
i
s
f
l
a
g
c
a
n
n
o
t
b
e
s
e
t
t
o
“
1
”
b
y
s
o
f
t
w
a
r
e
.
N
o
t
e
2
:
T
i
m
e
r
B
0
.
N
o
t
e
3
:
T
i
m
e
r
B
1
,
t
i
m
e
r
B
2
.
0
(
F
i
x
e
d
t
o
“
0
”
i
n
p
u
l
s
e
p
e
r
i
o
d
/
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
;
i
=
0
)
(
N
o
t
e
2
)
(
N
o
t
e
3
)
87
TimerB
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 73. Operation timing when measuring a pulse width
Figure 72. Operation timing when measuring a pulse period
Count source
Measurement pulse
Count start
flag
Timer Bi interrupt
request bit
Timing when counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
Reload register counter
transfer timing
“L”
“0”
“0”
Timer Bi overflow
flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
Measurement of puls time interval from falling edge to falling edge
(Note 2)
Cleared to “0” by software, or when interrupt request is accepted.
Transfer
(measured value)
“1”
Measurement pulse
“H”
Count source
Reload register counter
transfer timing
Count start
flag
Timer Bi interrupt
request bit
Timing when counter
reaches
“
0000
16
”
“1”
“1”
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1) (Note 1)
Cleared to “0” by software, or when interrupt request is accepted.
(Note 2)
Transfer (measured value)Transfer (indeterminate value)
88
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 74. Block diagram of UARTi (i = 0, 1)
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1.
UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 74 shows the block diagram of UART0 and UART1. Figure 75 shows the block diagram of the transmit/receive unit.
UARTi (i=0, 1) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016 and 03A816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART.
Although a few function are different, UART0 and UART1 have almost same functions.
Figures 76 through 78 show the registers related to UARTi.
m: Values set to UART0 bit rate generator (U0BRG)
n : Values set to
U
ART1 bit rate
g
enerator
(U
1BR
G)
RxD
0
1 / (m+1)
1/16
1/16
1/2
Bit rate generator
(address 03A1
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive clock
Transmit
clock
CLK
0
Clock source selection
CTS
0
/ RTS
0
f
1
f
8
f
32
Internal
External
Vcc
RTS0
CTS0
TxD
0
Transmit/
receive
unit
RxD
1
1 / (n+1)
1/16
1/16
1/2
Bit rate generator
(address 03A9
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Receive
clock
Transmit
clock
CLK
1
Clock source selection
f
1
f
8
f
32
Internal
External
RTS
1
CTS
1
TxD
1
(UART1)
(UART0)
Polarity
reversing
circuit
Polarity
reversing
circuit
CTS/RTS disabled
Clock output pin
select switch
CTS
1
/ RTS
1
CLKS
1
CTS/RTS disabled
CTS/RTS selected
CTS/RTS disabled
V
CC
CTS/RTS disabled
Reception control
circuit
Transmission
control circuit
Reception control
circuit
Transmission
control circuit
Transmit/
receive
unit
89
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 75. Block diagram of transmit/receive unit
SP SP PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock
synchronouss
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7
bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
Data bus low-order bits
MSB/LSB conversion circuit
0000000
SP SP PAR
"0"
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
90
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 76. Serial I/O-related registers (1)
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register
Function
Transmission data
Symbol Address When reset
U0TB 03A316, 03A216 Indeterminate
U1TB 03AB16, 03AA16 Indeterminate
UARTi bit rate generator
b7 b0 Symbol Address When reset
U0BRG 03A116 Indeterminate
U1BRG 03A916 Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1) 0016 to FF16
Values that can be set
Symbol Address When reset
U0RB 03A716, 03A616 Indeterminate
U1RB 03AF16, 03AE16 Indeterminate
b7 b0
(b15) (b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A616 and 03AE16) is read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note)
Framing error flag (Note)
Parity error flag (Note)
Error sum flag (Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Reception data
WR
WR
WR
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
91
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 77. Serial I/O-related registers (2)
W
R
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
M
R
(
i
=
0
,
1
)0
3
A
0
1
6
,
0
3
A
8
1
6
0
0
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
b
e
f
i
x
e
d
t
o
0
0
1
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
C
K
D
I
R
S
M
D
1
S
M
D
0S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
b
i
t
S
M
D
2
I
n
t
e
r
n
a
l
/
e
x
t
e
r
n
a
l
c
l
o
c
k
s
e
l
e
c
t
b
i
t
S
T
P
S
P
R
Y
P
R
Y
E
S
L
E
P
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
S
t
o
p
b
i
t
l
e
n
g
t
h
s
e
l
e
c
t
b
i
t
O
d
d
/
e
v
e
n
p
a
r
i
t
y
s
e
l
e
c
t
b
i
t
S
l
e
e
p
s
e
l
e
c
t
b
i
t
0
:
O
n
e
s
t
o
p
b
i
t
1
:
T
w
o
s
t
o
p
b
i
t
s
0
:
P
a
r
i
t
y
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
e
n
a
b
l
e
d
0
:
S
l
e
e
p
m
o
d
e
d
e
s
e
l
e
c
t
e
d
1
:
S
l
e
e
p
m
o
d
e
s
e
l
e
c
t
e
d
1
0
0
:
T
r
a
n
s
f
e
r
d
a
t
a
7
b
i
t
s
l
o
n
g
1
0
1
:
T
r
a
n
s
f
e
r
d
a
t
a
8
b
i
t
s
l
o
n
g
1
1
0
:
T
r
a
n
s
f
e
r
d
a
t
a
9
b
i
t
s
l
o
n
g
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
I
n
v
a
l
i
d
V
a
l
i
d
w
h
e
n
b
i
t
6
=
“
1
”
0
:
O
d
d
p
a
r
i
t
y
1
:
E
v
e
n
p
a
r
i
t
y
I
n
v
a
l
i
d
I
n
v
a
l
i
d
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
C
0
(
i
=
0
,
1
)0
3
A
4
1
6
,
0
3
A
C
1
6
0
8
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
T
X
E
P
T
C
L
K
1
C
L
K
0
C
R
S
C
R
D
N
C
H
C
K
P
O
L
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
0
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
1
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
L
K
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
d
i
s
a
b
l
e
b
i
t
D
a
t
a
o
u
t
p
u
t
s
e
l
e
c
t
b
i
t
0
0
:
f
1
i
s
s
e
l
e
c
t
e
d
0
1
:
f
8
i
s
s
e
l
e
c
t
e
d
1
0
:
f
3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
4
7
a
n
d
P
7
4
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
U
F
O
R
MT
r
a
n
s
f
e
r
f
o
r
m
a
t
s
e
l
e
c
t
b
i
t
0
0
:
f
1
i
s
s
e
l
e
c
t
e
d
0
1
:
f
8
i
s
s
e
l
e
c
t
e
d
1
0
:
f
3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
N
o
t
e
1
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
N
o
t
e
2
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
.
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
4
7
a
n
d
P
7
7
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
WR
92
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 78. Serial I/O-related registers (3)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A516, 03AD16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B016 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous receive
mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous receive
mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
Invalid
Invalid
CLK/CLKS select bit 1
(Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Reserved bit Must always be “0” Must always be “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0
93
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 24 lists
the specifications of the clock synchronous serial I/O mode. Figure 79 shows the UARTi transmit/receive
mode register.
Table 24. Specifications of clock synchronous serial I/O mode
Specification
• Transfer data length: 8 bits
•
When internal clock is selected (bit 3 at address 03A016, 03A816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
•
When external clock is selected (bit 3 at address 03A0
16
, 03A8
16
=“1”) : Input from CLKi pin
(Note 2)
_______ ________ _______ ________
• CTS function/ RTS function/ CTS,RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______ _______
_ When CTS function is selected, CTS input level = "L"
•
Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at address 03A4
16
, 03AC
16
) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at address 03A4
16
, 03AC
16
) = “1”: CLKi input level = “L”
• To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03A516, 03AD16) = “1”
_ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 03A516, 03AD16) = “0”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at address 03A4
16
, 03AC
16
) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at address 03A4
16
, 03AC
16
) = “1”: CLKi input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi re-
ceive buffer register are read out
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be set 2 pins, and can be selected to output from
which pin.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condi-
tion
Reception start condition
Interrupt request
generation timing
Error detection
Select function
94
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 79. UARTi transmit/receive mode register in clock synchronous serial I/O mode (i=0,1)
Table 25 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 25. Input/output pin functions in clock synchronous serial I/O mode (i=0,1)
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit/receive mode register
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 (Must always be "0" in clock synchronous serial I/O mode)
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
Pin name Function Method of selection
TxDi
(P4
4
, P7
4
)Serial data output
Serial data input
Transfer clock output
Transfer clock input
Programmable I/O port
(Outputs dummy data when performing reception only)
RxDi
(P4
5
, P7
5
)
CLKi
(P4
6
, P7
6
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “1”
Port P4
6
, P7
6
direction register (bits 6 at address 03EA
16
and 03EF
16
) = “0”
Port P4
5
, P7
5
direction register (bits 5 at address 03EA
16
and 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
) = “0”
Port P4
7
, P7
7
direction register (bits 7 address 03EA
16
and 03EF16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P4
7
, P7
7
)
95
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 80. Typical transmit/receive timings in clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
c
T
C
L
K
S
t
o
p
p
e
d
p
u
l
s
i
n
g
b
e
c
a
u
s
e
t
r
a
n
s
f
e
r
e
n
a
b
l
e
b
i
t
=
“
0
”
D
a
t
a
i
s
s
e
t
i
n
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
T
c
=
T
C
L
K
=
2
(
n
+
1
)
/
f
i
f
i
:
f
r
e
q
u
e
n
c
y
o
f
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
(
f
1
,
f
8
,
f
3
2
)
n
:
v
a
l
u
e
s
e
t
t
o
B
R
G
i
T
r
a
n
s
f
e
r
c
l
o
c
k
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
l
)
C
L
K
i
T
x
D
i
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
(
T
X
E
P
T
)
“
H
”
“
L
”
“
0
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
C
T
S
i
S
h
o
w
n
i
n
(
)
a
r
e
b
i
t
s
y
m
b
o
l
s
.
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
I
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
.
•
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
.
•
C
L
K
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
=
“
0
”
.
•
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
c
a
u
s
e
s
e
l
e
c
t
b
i
t
=
“
0
”
.
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
I
R
)“
0
”
“
1
”
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
S
t
o
p
p
e
d
p
u
l
s
i
n
g
b
e
c
a
u
s
e
C
T
S
=
“
H
”
1
/
f
E
X
T
D
u
m
m
y
d
a
t
a
i
s
s
e
t
i
n
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
l
)
C
L
K
i
R
x
D
i
R
e
c
e
i
v
e
c
o
m
p
l
e
t
e
f
l
a
g
(
R
l
)
R
T
S
i“
H
”
“
L
”
“
0
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(
R
E
)“
0
”
“
1
”
R
e
c
e
i
v
e
d
a
t
a
i
s
t
a
k
e
n
i
n
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
R
e
a
d
o
u
t
f
r
o
m
U
A
R
T
i
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
S
h
o
w
n
i
n
(
)
a
r
e
b
i
t
s
y
m
b
o
l
s
.
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
.
•
E
x
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
.
•
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
.
•
C
L
K
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
=
“
0
”
.
f
E
X
T
:
f
r
e
q
u
e
n
c
y
o
f
e
x
t
e
r
n
a
l
c
l
o
c
k
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
r
e
c
e
i
v
e
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
I
R
)“
0
”
“
1
”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
M
e
e
t
t
h
e
f
o
l
l
o
w
i
n
g
c
o
n
d
i
t
i
o
n
s
w
h
e
n
t
h
e
C
L
K
i
n
p
u
t
b
e
f
o
r
e
d
a
t
a
r
e
c
e
p
t
i
o
n
=
“
H
”
•
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t“
1
”
•
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t“
1
”
•
D
u
m
m
y
d
a
t
a
w
r
i
t
e
t
o
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
96
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(a) Polarity select function
As shown in Figure 81, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows selection
of the polarity of the transfer clock.
Figure 81. Polarity of transfer clock
(b) LSB first/MSB first sel82GA-9, when the transfer format select bit (bit 7 at addresses 03A416,
03AC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB
first”.
Figure 82. Transfer format
• When CLK polarity select bit = “1”
Note 2: The CLKi pin level when not
transferring data is “L”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
i
R
X
D
i
CLK
i
• When CLK polarity select bit = “0”
Note 1: The CLKi pin level when not
transferring data is “H”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
LSB first
• When transfer format select bit = “0”
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
• When transfer format select bit = “1”
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
T
X
D
i
R
X
D
i
CLK
i
MSB first
Note: This applies when the CLK polarit
y
select bit = “0”.
97
Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 83.) The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
_______ _______
function is selected, CTS/RTS function of UART1 cannot be used.
Figure 83. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
Microcomputer
T
X
D
1
(P7
4
)
CLKS
1
(P7
7
)
CLK
1
(P7
6
)IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission is
p
erformed only in clock synchronous serial I/O mode.
98
Clock asynchronous serial I/O (UART) mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Clock asynchronous serial I/O (UART) mode
The UART allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Table 26 lists the specifications of the UART mode. Figure 84 shows the UARTi transmit/receive
mode register.
Table 26. Specifications of clock synchronous serial I/O mode
Item Specification
Transfer data format •Character bit (transfer data): 7 bits, 8 bits or 9 bits as selected
•Start bit: 1 bit
•Parity bit: Odd, even or nothing as selected
•Stop bit: 1 bit or 2 bits as selected
Transfer clock •When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
Transmission/reception control
_______ _______ _______ _______
•CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
•To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______ _______
- When CTS function is selected, CTS input level = “L”
Reception start condition •To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
Interrupt request •When transmitting
generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
•When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection •Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
•Framing error
This error occurs when the number of stop bits set is not detected
•Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
•Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
select function •Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
99
Clock asynchronous serial I/O (UART) mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 27 lists the functions of the input/output pins during UART mode. Note that for a period from when
the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 27. Input/output pin functions in UART mode (i=0,1)
Figure 84. UARTi transmit/receive mode register in UART mode
Pin name Function Method of selection
TxDi
(P4
4
, P7
4
)Serial data output
Serial data input
Programmable I/O port
Transfer clock input
Programmable I/O port
RxDi
(P4
5
, P7
5
)
CLKi
(P4
6
, P7
6
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “1”
Port P4
5
, P7
5
direction register (bits 5 at address 03EA
16
and 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
) = “0”
Port P4
7
, P7
7
direction register (bits 7 at address 03EA
16
and 03EF
16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P4
7
, P7
7
)
(Outputs dummy data when performing reception only)
Symbol Address When reset
UiMR (i=0,1) 03A016, 03A816 0016
CKDIR
UARTi transmit/receive mode register
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
Sleep select bit
100
Clock asynchronous serial I/O (UART) mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 85. Typical transmit timings in UART mode
T
r
a
n
s
m
i
t
e
n
a
b
l
e
e
b
i
t
(
T
E
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
I
)
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
(
T
X
E
P
T
)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
TP
S
t
a
r
t
b
i
tP
a
r
i
t
y
b
i
t
T
x
D
i
C
T
S
i
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
P
a
r
i
t
y
i
s
e
n
a
b
l
e
d
.
•
O
n
e
s
t
o
p
b
i
t
.
•
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
.
•
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
c
a
u
s
e
s
e
l
e
c
t
b
i
t
=
“
1
”
.
“
1
”
“
0
”
“
1
”
“
L
”
“
H
”
“
0
”
“
1
”
T
c
=
1
6
(
n
+
1
)
/
f
i
o
r
1
6
(
n
+
1
)
/
f
E
X
T
f
i
:
f
r
e
q
u
e
n
c
y
o
f
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
(
f
1
,
f
8
,
f
3
2
)
f
E
X
T
:
f
r
e
q
u
e
n
c
y
o
f
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
(
e
x
t
e
r
n
a
l
c
l
o
c
k
)
n
:
v
a
l
u
e
s
e
t
t
o
B
R
G
i
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
I
R
)
“
0
”
“
1
”
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
TPS
PD
0
D
1
S
T
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
I
)
T
x
D
i
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
(
T
X
E
P
T
)
“
0
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
P
a
r
i
t
y
i
s
d
i
s
a
b
l
e
d
.
•
T
w
o
s
t
o
p
b
i
t
s
.
•
C
T
S
f
u
n
c
t
i
o
n
i
s
d
i
s
a
b
l
e
d
.
•
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
c
a
u
s
e
s
s
e
l
e
c
t
b
i
t
=
“
0
”
.
T
r
a
n
s
f
e
r
c
l
o
c
k
T
c
T
c
=
1
6
(
n
+
1
)
/
f
i
o
r
1
6
(
n
+
1
)
/
f
E
X
T
f
i
:
f
r
e
q
u
e
n
c
y
o
f
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
(
f
1
,
f
8
,
f
3
2
)
f
E
X
T
:
f
r
e
q
u
e
n
c
y
o
f
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
(
e
x
t
e
r
n
a
l
c
l
o
c
k
)
n
:
v
a
l
u
e
s
e
t
t
o
B
R
G
i
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
I
R
)
“
0
”
“
1
”
S
h
o
w
n
i
n
(
)
a
r
e
b
i
t
s
y
m
b
o
l
s
.
S
h
o
w
n
i
n
(
)
a
r
e
b
i
t
s
y
m
b
o
l
s
.
T
c
T
r
a
n
s
f
e
r
c
l
o
c
k
S
P
S
t
o
p
p
e
d
p
u
l
s
i
n
g
b
e
c
a
u
s
e
t
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
=
“
0
”
S
t
o
p
b
i
t
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
S
t
a
r
t
b
i
t
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
TD
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
TD
8
D
0
D
1
S
T
S
PS
P
S
t
o
p
b
i
t
S
P
T
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
s
t
o
p
s
m
o
m
e
n
t
a
r
i
l
y
a
s
C
T
S
i
s
“
H
”
w
h
e
n
t
h
e
s
t
o
p
b
i
t
i
s
c
h
e
c
k
e
d
.
T
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
s
t
a
r
t
s
a
s
t
h
e
t
r
a
n
s
f
e
r
s
t
a
r
t
s
i
m
m
e
d
i
a
t
e
l
y
C
T
S
c
h
a
n
g
e
s
t
o
“
L
”
.
D
a
t
a
i
s
s
e
t
i
n
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
S
P
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
S
t
o
p
b
i
t
D
a
t
a
i
s
s
e
t
i
n
U
A
R
T
i
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
.
“
0
”
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
101
Clock asynchronous serial I/O (UART) mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 86. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
D
0
D
1
S
t
a
r
t
b
i
t
S
a
m
p
l
e
d
“
L
”R
e
c
e
i
v
e
d
a
t
a
t
a
k
e
n
i
n
B
R
G
i
'
s
c
o
u
n
t
s
o
u
r
c
e
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
R
x
D
i
T
r
a
n
s
f
e
r
c
l
o
c
k
R
e
c
e
i
v
e
c
o
m
p
l
e
t
e
f
l
a
g
R
T
S
i
S
t
o
p
b
i
t
“
1
”
“
0
”
“
0
”
“
1
”
“
H
”
“
L
”
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
P
a
r
i
t
y
i
s
d
i
s
a
b
l
e
d
.
•
O
n
e
s
t
o
p
b
i
t
.
•
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
.
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t“
0
”
“
1
”
C
l
e
a
r
e
d
t
o
“
0
”
b
y
s
o
f
t
w
a
r
e
,
o
r
w
h
e
n
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
.
T
r
a
n
s
f
e
r
r
e
d
f
r
o
m
U
A
R
T
i
r
e
c
e
i
v
e
r
e
g
i
s
t
e
r
t
o
U
A
R
T
i
r
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
R
e
c
e
p
t
i
o
n
t
r
i
g
g
e
r
e
d
w
h
e
n
t
r
a
n
s
f
e
r
c
l
o
c
k
i
s
g
e
n
e
l
a
t
e
d
b
y
f
a
l
l
i
n
g
e
d
g
e
o
f
s
t
a
r
t
b
i
t
D
7
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
102
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Serial I/O2
Serial I/O2 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer
mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer
RAM which has up to 256 bytes (addresses 0040016 to 004FF16).
The SRDY2, SBUSY2 and SSTB2 pins each have a handshake I/O signal function and can select either “H”
active or “L” active for active logic.
Specification
• 8-bit serial I/O mode (non-automatic transfer)
• Automatic transfer serial I/O mode
• Transfer data length: 8 bits
• Full duplex mode / transmit-only mode selected by bit 5 at address 034216
•
When internal clock is selected (bit 2 at address 034216 = “0”) : selected by bits 5 to 7 at address 034816
•
When external clock is selected (bit 2 at address 034216 = “1”) : Input from SCLK21 pin, SCLK22 pin(Note 2)
• When internal clock is selected : f(XIN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32, f(XIN)/64, f(XIN)/128, f(XIN)/256
• When external clock is selected : input cycle 0.95 µs or less
• SSTB2 output / SBUSY2 input or output / SRDY2 input or output chosen
• To start transmission / reception, the following requirements must be met:
_ Serial I/O initialization bit (bit 4 at address 034216) = “1”
_ When SBUSY2 input, or SRDY2 input is selected : selected input level = “H”
____________ _________
_ When SBUSY2 input, or SRDY2 input is selected : selected input level = “L”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ Input level of SCLK21 or SCLK22 = “H”
• To stop transmission and reception, set serial I/O initialization bit (bit 4 at
address 034216) to “0” regardless internal clock and external clock.
• 8-bit serial I/O mode : Interrupts requested when 8-bit data transfer is com-
pleted
• Automatic transfer serial I/O mode :Interrupts requested when last receive
data transfer to Automatic transfer RAM
• SOUT2 P-channel output disable function
CMOS output or N-channel open-drain output can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Serial I/O2 clock pin select bit
Serial clock input/output can be selected; SCLK21 or SCLK22
• SBUSY output, SSTB2 output select function (only automatic transfer serial
mode)
SBUSY output, SSTB2 output can be selected; 1-byte data transfer unit or all
data transfer unit
• SOUT2 pin control bit
Either output active or high-impedance can be selected as a S
OUT2
pin state at
serial non-transfer .
Note 1: It is necessary to set the serial I/O clock pin select bit ( bit 7 at address 034216)
Item
Serial mode
Transfer data format
Transfer clock
Transfer rate
Transmission/reception control
Transmission /
reception start condition
Transmission and
reception stop condition
Interrupt request
generation timing
Select function
Table 28. Specifications of clock synchronous serial I/O2
103
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 87. Block Diagram of Serial I/O2
Main
data bus
Serial I/O2
automatic transfer
controller
Local
data bus
Serial I/O automatic
transfer RAM
(0040016—004FF16)
Serial I/O2
control register 3
XIN
Serial I/O2
automatic transfer
data pointer
Address decoder
Main address
bus Local address
bus
1/8
1/16
1/32
1/64
1/128
Serial I/O2
interrupt request
Port latch
Serial I/O2 counter
Synchronous
circuit
Serial I/O2
synchronous clock
selection bit
“1”
Port latch
SCLK21
“0”
“1”
S
CLK2
“0
”
Internal synchronous
clock selection bits
1/256
Port latch
SBUSY2
SSTB2
(SSTB2 pin control bit)
Serial transfer
status flag
“0”
“1”
“0”
“1”
“0”
“1”
Port latch
SOUT2
SIN2
Port latch
Serial I/O2 register (8)
“0”
“1” Serial transfer selection bits
Divider
1/4
Serial I/O2 clock
pin selection bit
SCLK22 “1”
“0”
Port latch
“0”
“1”
“0” “1”
Serial I/O2 clock
pin selection bits
SRDY2
SRDY2•SBUSY2 pin
control bit
SRDY2•SBUSY2 pin
control bit
104
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 88. Serial I/O2 Control Registers 1, 2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
S
I
O
2
C
O
N
20
3
4
4
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nR
B
i
t
s
y
m
b
o
l
W
b
7b
6b
5b
4
b
3b
2b
1b
0
S
R
D
Y
2
•
S
B
U
S
Y
2
p
i
n
c
o
n
t
r
o
l
b
i
t
s
S
C
O
N
2
0
S
C
O
N
2
1
S
C
O
N
2
2
S
C
O
N
2
3
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
S
I
O
2
C
O
N
10
3
4
2
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l R
W
b
7b
6b
5b
4b
3b
2b
1b
0
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
S
C
O
N
1
0
S
C
O
N
1
1
S
C
O
N
1
2
S
C
O
N
1
3
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
(
S
S
T
B
2
p
i
n
c
o
n
t
r
o
l
b
i
t
)0
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0
1
:
E
x
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
1
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
S
S
T
B
2
o
u
t
p
u
t
.
)
1
1
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
S
S
T
B
2
o
u
t
p
u
t
.
)
0
:
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
T
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t0
:
F
u
l
l
d
u
p
l
e
x
(
t
r
a
n
s
m
i
t
a
n
d
r
e
c
e
i
v
e
)
m
o
d
e
(
S
I
N
2
p
i
n
i
s
a
S
I
N
2
i
n
p
u
t
.
)
1
:
T
r
a
n
s
m
i
t
-
o
n
l
y
m
o
d
e
(
S
I
N
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
S
C
O
N
1
4
S
C
O
N
1
5
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
p
i
n
s
e
l
e
c
t
b
i
t
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
S
C
O
N
1
6
S
C
O
N
1
7
0
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
s
e
r
i
a
l
I
/
O
p
i
n
s
a
r
e
I
/
O
p
o
r
t
s
)
0
1
:
8
-
b
i
t
s
s
e
r
i
a
l
I
/
O
1
0
:
I
n
h
i
b
i
t
1
1
:
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
(
8
-
b
i
t
s
)
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
0
:
S
C
L
K
2
1
(
S
C
L
K
2
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
1
:
S
C
L
K
2
2
(
S
C
L
K
2
1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0
:
F
u
n
c
t
i
o
n
s
a
s
e
a
c
h
1
-
b
y
t
e
s
i
g
n
a
l
1
:
F
u
n
c
t
i
o
n
s
a
s
s
i
g
n
a
l
f
o
r
a
l
l
t
r
a
n
s
f
e
r
d
a
t
a
S
B
U
S
Y
2
o
u
t
p
u
t
•
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
(
V
a
l
i
d
i
n
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
m
o
d
e
)
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
S
C
O
N
2
4
S
C
O
N
2
5
S
O
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
S
O
U
T
2
p
i
n
c
o
n
t
r
o
l
b
i
t
(
a
t
n
o
-
t
r
a
n
s
f
e
r
s
e
r
i
a
l
d
a
t
a
)
S
C
O
N
2
6
S
C
O
N
2
7
0
:
O
u
t
p
u
t
a
c
t
i
v
e
1
:
O
u
t
p
u
t
h
i
g
h
-
i
m
p
e
d
a
n
c
e
0
:
C
M
O
S
3
-
s
t
a
t
e
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
v
a
l
i
d
.
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
i
n
v
a
l
i
d
.
)
b
3
b
2
b
1
b
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
S
R
D
Y
2
p
i
nS
B
U
S
Y
2
p
i
n
I
/
O
p
o
r
tI
/
O
p
o
r
t
N
o
t
u
s
e
d
S
R
D
Y
2
o
u
t
p
u
tI
/
O
p
o
r
t
S
R
D
Y
2
o
u
t
p
u
tI
/
O
p
o
r
t
I
/
O
p
o
r
tS
B
U
S
Y
2
i
n
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
i
n
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
o
u
t
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
o
u
t
p
u
t
S
R
D
Y
2
i
n
p
u
tS
B
U
S
Y
2
o
u
t
p
u
t
S
R
D
Y
2
i
n
p
u
tS
B
U
S
Y
2
o
u
t
p
u
t
S
R
D
Y
2
i
n
p
u
tS
B
U
S
Y
2
o
u
t
p
u
t
S
R
D
Y
2
i
n
p
u
tS
B
U
S
Y
2
o
u
t
p
u
t
S
R
D
Y
2
o
u
t
p
u
tS
B
U
S
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
tS
B
U
S
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
tS
B
U
S
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
tS
B
U
S
Y
2
i
n
p
u
t
b
1
b
0
b
3
b
2
105
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 89. Serial I/O2 automatic transfer data pointer
Serial I/O2 control register 3
Symbol Address When reset
SIO2CON3 0348
16
00000000
2
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Automatic transfer
interval set bits
TTRAN0
TTRAN1
TTRAN2
TTRAN3
Internal synchronous
clock selection bits 000:f(X
IN
)/4
001:f(X
IN
)/8
010:f(X
IN
)/16
011:f(X
IN
)/32
100:f(X
IN
)/64
101:f(X
IN
)/128
110:f(X
IN
)/256
TTRAN4
TCLK0
TCLK1
TCLK2
00000 :2 cycles of transfer clocks
00001 :3 cycles of transfer clocks
:
11110 :32 cycles of transfer clocks
11111 :33 cycles of transfer clocks
Data is written to a latch and read from
a decrement counter.
b4b3b2b1b0
b7b6b5
Serial I/O2 automatic transfer data pointer
Symbol Address When reset
SIO2DP 0340
16
00
16
Function R W
b7 b6 b5 b4 b3 b2 b1 b0
• Automatic transfer data pointer set
Specify the low-order 8 bits of the first data store address on the serial I/O
automatic transfer RAM.
Data is written into the latch and read from the decrement counter.
Serial I/O2 register/transfer counter
Symbol Address When reset
SIO2 0346
16
00
16
Function R W
b7 b6 b5 b4 b3 b2 b1 b0
• Number of automatic transfer data set
Set the number of automatic transfer data.
Set a value one less than number of transfer data.
Data is written into the latch and read from the decrement counter.
106
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 29. Functions of the serial I/O2 input/output pins
Table 29 lists the functions of the serial I/O2 input/output pins
Pin name Function Method of selection
S
OUT2
(P9
4
)Serial data output
Serial data input
Transfer clock output
Transfer clock input
Port P9
4
direction register (bit 4 at address 03F3
16
)= “1”
S
OUT2
P-channel output disable bit (bit 7 at address 0344
16
)= “0” , “1”
S
OUT2
pin control bit (bit 6 at address 0344
16
)= “0” , “1”
(Outputs dummy data when performing reception only)
S
IN2
(P9
3
)
S
CLK21
(P9
5
)Serial I/O2 synchronous clock select bits (bits 2, 3 at address 0342
16
) = “00” , “01”
Serial I/O2 clock pin select bit (bit 7 at address 0342
16
) = “0”
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 0342
16
) = “01” , “11”
Serial I/O2 clock pin select bit (bit 7 at address 0342
16
) = “0”
Port P9
5
direction register (bit 5 at address 03F3
16
)= “0”
Port P9
3
direction register (bit 4 at address 03F3
16
)= “0”
Transfer mode select bit (bit 5 at address 0342
16
)= “0”
(Input/output port when transfer mode select bit (bit 5 at address 0342
16
)= “1”)
Transfer clock output
Transfer clock input
S
CLK22
(P9
6
)Serial I/O2 synchronous clock select bits (bits 2, 3 at address 0342
16
) = “00” , “01”
Serial I/O2 clock pin select bit (bit 7 at address 0342
16
) = “1”
Serial I/O2 synchronous clock select bits (bits 2, 3 at address 0342
16
) = “01” , “11”
Serial I/O2 clock pin select bit (bit 7 at address 0342
16
) = “1”
Port P9
6
direction register (bit 6 at address 03F3
16
)= “0”
S
RDY
input / output
S
RDY2
(P9
0
)Set by S
RDY2
• S
BUSY2
pin control bits (bits 0 to 3 at address 0344
16
)
S
BUSY
input / output
S
BUSY2
(P9
1
)Set by S
RDY2
• S
BUSY2
pin control bits (bits 0 to 3 at address 0344
16
)
S
BUSY2
output • S
STB2
output function select bit (bit 4 at address 0344
16
)= “0” , “1”
S
STB
input / output
S
STB2
(P9
2
)Serial I/O2 synchronous clock select bits (bits 2, 3 at address 0342
16
) = “10” , “11”
S
BUSY2
output • S
STB2
output function select bit (bit 4 at address 0344
16
)= “0” , “1”
SOUT2 Output
Either output active or high-impedance can be selected as a SOUT2 pin state at serial non-transfer by the
SOUT2 pin control bit (bit 6 of address 034416).
However, when the external synchronous clock is selected, perform the following setup to put the SOUT2
pin into a high-impedance state.
When the SCLK2i ( i = 1, 2) input is “H” after completion of transfer, set the SOUT2 pin control bit to “1”. When
the SCLK2i ( i = 1, 2) input goes to “L” after the start of the next serial transfer, the S OUT2 pin control bit is
automatically reset to “0” and put into an output active state.
107
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Serial I/O2 Mode
There are two types of serial I/O2 modes: 8-bit serial I/O mode where automatic transfer RAM is not
used, and an automatic transfer serial I/O mode.
(1) 8-bit Serial I/O Mode
Address 034616 is assigned to the serial I/O2 register. When the internal synchronous clock is
selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O2 register
(address 034616).
The serial transfer status flag (bit 5 of address 034416) is set to “1” by writing into the serial I/O2
register and reset to “0” after completion of 8-bit transfer. At the same time, a serial I/O2 interrupt
request occurs. If the transfer is completed, the receive data is read out from serial I/O2 register.
When the external synchronous clock is selected, the contents of the serial I/O2 register are con-
tinuously shifted while transfer clocks are input to SCLK21 or SCLK22. Therefore, the clock needs to
be controlled externally.
(2) Automatic Transfer Serial I/O Mode
Address 034616 is assigned to the transfer counter (1-byte units). The serial I/O2 automatic trans-
fer controller controls the write and read operations of the serial I/O2 register. The serial I/O auto-
matic transfer RAM is mapped to addresses 0040016 to 004FF16. Before starting transfer, make
sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is
set to the automatic transfer data pointer (address 034016).
When the internal synchronous clock is selected, the transfer interval is inserted between one data
and another in the following cases:
1. When using no handshake signal
2. When using the SRDY2 output, SBUSY2 output, and SSTB2 output of the handshake signal inde
pendently
3. When using a combination of SRDY2 output and SSTB2 output or a combination of SBUSY2 output
and SSTB2 output of the handshake signal
The transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval
set bit (bits 0–4 of address 034816 ).
Also, when using SBUSY2 output as a signal for each occurrence of the all transfer data, a transfer
interval is inserted before the system starts sending or receiving the first data and after the system
finished sending or receiving the last data, not just between one data and another.
Furthermore, when using SSTB2 output, the transfer interval between each 1-byte data is extended
by 2 cycles from the set value no matter how the SBUSY2 output. S STB2 output function select bit (bit
4 of address 034416) is set.
When using SBUSY2 output and SSTB2 output in combination as a signal for each occurrence of the
all transfer data, the transfer interval after the system finished sending or receiving the last data is
extended by 2 cycles from the set value.
When an external synchronous clock is selected, the automatic transfer interval is disabled.
108
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 90. Automatic Transfer Serial I/O Operation
004FF
16
Automatic transfer RAM
Transfer counter
Automatic transfer
data pointer
Serial I/O2 re
g
ister
00452
16
00451
16
00450
16
0044F
16
0044E
16
00400
16
04
16
52
16
S
IN2
S
OUT2
When the internal synchronous clock is selected, automatic serial transfer starts by writing 1 less than
the number of transfer bytes to the transfer counter (address 034616). When an external sync clock is
selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the
transfer counter and the transfer clock is input. In this case, allow for at least 5 cycles of internal
system clock before the transfer clock is input after writing to the transfer counter.
Also, for data to data transfer intervals, allow at least 5 cycles of internal system clock reckoning from
a rise of clock at the last bit of one-byte data.
Regardless of whether the internal or external synchronous clock is selected, the automatic transfer
data pointer and the transfer counter are decreased after each 1-byte data is received and then written
into the automatic transfer RAM. The serial transfer status flag (bit5 of address 034416) is set to “1” by
writing data into the transfer counter. The serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial I/O2 interrupt request occurs.
The values written in the automatic transfer data pointer (address 034016) and the automatic transfer
interval set bits (bit 0 to bit 4 of address 034816) are held in the latch.
When data is written into the transfer counter, the values latched in the automatic transfer data pointer
(address 034016) and the automatic transfer interval set bits (bit 0 to bit 4) are transferred to the
decrement counter.
109
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Handshake Signal
There are five types of handshake signal : SSTB2 output,
SBUSY2 input/
output
,
and SRDY2 input/output.
(1) SSTB2 output signal
The SSTB2 output is a signal to inform an end of transmission/reception to the serial transfer destina-
tion. The SSTB2 output signal can be used only when the internal synchronous clock is selected. In the
initial status [ serial I/O initialization bit (bit 4 of address 034216) = “0” ], the SSTB2 output goes to “L”
__________
(bits 2, 3 of address 034216=11), or the SSTB2 output goes to “H” (bits 2, 3 of address 034216=10).
At the end of transmit/receive operation, after the all data of the serial I/O2 register (
address 034616)
is
_________
output from S
OUT2
,
SSTB2 output is “H” (or S
STB2
output is “L”)
in the period of 1 cycle of the transfer clock.
Furthermore, after 1 cycle, the serial transfer status flag (bit 5
of address 034416
) is reset to “0”.
In the automatic transfer serial I/O mode, whether the S
STB2
output is to be output at an end of each 1-byte
data or after completion of transfer of all data can be selected by the S
BUSY2
output • S
STB2
output function
select bit (bit 4 of address 0344
16
).
Figure 91. SSTB2 Output Operation
"1"
"0"
S
STB2
(output)
"H"
"L"
D
0
Tc
D
1
D
2
D
3
D
4
D
5
D
6
D
7
"1"
"0"
"H"
"L"
D
0
Tc
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Automatic
transfer interval
•Serial operation used S
STB2
output
Operation mode
: 8-bit serial I/O mode
Transfer clock : Internal synchronous clock
S
STB2
output timing : Each 1-byte data
Internal clock
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i=1, 2)(output)
S
OUT2
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
•Serial operation used S
STB2
output
Operation mode
: Automatic transfer serial I/O mode
Transfer clock : Internal synchronous clock
S
STB2
output timing : Each transfer of all data
Internal clock
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i=1, 2)(output)
S
STB2
(output)
S
OUT2
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
110
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 93. SBUSY2 Input Operation (2)
Figure 92. SBUSY2 Input Operation (1)
(2) SBUSY2 input signal
The SBUSY2 input is a signal requested to stop of transmission/reception from the serial transfer des-
tination.
When the internal synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status [serial I/O initialization bit (bit 4 of address
____________
034216) = “0”]. When a “L” level signal into the SBUSY2 ( or “H” on SBUSY2 ) input for 1.5 cycles or more
of transfer clock, transfer clocks are output from SCLK2i (i = 1, 2), and transmit/receive operation is
____________
started. When SBUSY2 input is driven “H” (or SBUSY2 input is driven “L”) during transmit/receive
operation, the transfer clock being output from SCLK2i (i = 1, 2) remains active until after the system
finishes sending or receiving the designated number of bits, without stopping the transmit/receive
operation immediately. The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic
transfer serial I/O is 8 bits.
Internal clock
"1"
"0"
"H"
"L"
Tc
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
1.5 cycle or more
•Serial operation used S
BUSY2
input
Operation mode
: 8-bit serial I/O mode
Transfer clock : Internal synchronous clock
S
BUSY2
input timing : Each 1-byte data
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i = 1, 2)(output)
S
OUT2
S
BUSY2
(input
)
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
"1"
"0"
"H"
"L"
Note: The last output data
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Invalid
Note
•Serial operation used S
BUSY2
input
Operation mode
: 8-bit serial I/O mode
Transfer clock : External synchronous clock
S
BUSY2
input timing : Each 1-byte data
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i = 1, 2)(input
)
S
OUT2
S
BUSY2
(input
)
High-impedance High-impedance
When the external synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L”
___________
level signal into the SBUSY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
= “0”]. At this time, the transfer clock become invalid. The transfer clock become valid while a “L” level
___________
signal is input into the SBUSY2 input (or a “H” level signal into the S BUSY2 input) and transmit/receive
operation work. ___________
When changing the input values into the SBUSY2 (or SBUSY2) input at these operations, change them
when the transfer clock input is in a “H” state. When the high-impedance of the SOUT2 output is
selected by the SOUT2 pin control bit (bit 6 of address 034416), the SOUT2 becomes high-impedance,
___________
while a “H” level signal is input into the SBUSY2 input (or a “L” level signal into the SBUSY2 input.)
111
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 94. SBUSY2 Output Operation (1)
Figure 95. SBUSY2 Output Operation (2)
Internal clock
"1"
"0"
"H"
"L"
D
0
Tc
TC : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
D
1
D
2
D
3
D
4
D
5
D
6
D
7
•Serial operation used S
BUSY2
output
Operation mode
: 8-bit serial I/O mode
Transfer clock : Internal synchronous clock
S
BUSY2
output timing : Each 1-byte data
Serial transfer status flag
(bit 5 at address 0344
16
)
S
OUT2
S
CLK2i
(i = 1, 2)(output)
S
BUSY2
(output
)
"1"
"0"
"H"
"L"
D
0
SOUT2
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Write to serial I/O register
(Address 034616)
•Serial operation used S
BUSY2
output
Operation mode
: 8-bit serial I/O mode
Transfer clock : External synchronous clock
SBUSY2 output timing : Each 1-byte data
Serial transfer status flag
(bit 5 at address 034416)
SCLK2i
(i = 1, 2)(Input)
SBUSY2(output)
(3) SBUSY2 output signal
The SBUSY2 output is a signal which requests to stop of transmission/reception to the serial transfer
destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchro-
nous clock, whether the SBUSY2 output is to be output at transfer of each 1-byte data or during transfer
of all data can be selected by the SBUSY2 output • SSTB2 output function select bit (bit 4 of address
034416). In the initial status[ serial I/O initialization bit (bit 4 of address 034216) = “0” ], the status in
____________
which the SBUSY2 outputs “H” (or the SBUSY2 outputs “L”).
When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic trans-
fer serial I/O mode (SBUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to
____________
“L” (or the SBUSY2 output goes to “H”) before 0.5 cycle of the timing at which the transfer clock goes to
“L” . In the automatic transfer serial I/O mode (the SBUSY2 output function: all transfer data is selected),
____________
the SBUSY2 output goes to “L” (or the SBUSY2 output goes to “H”) when the first transmit data is written
into the serial I/O2 register (address 034616).
____________
When the external synchronous clock is selected, the SBUSY2 output goes to “L” (or the SBUSY2 output
goes to “H”) when transmit data is written into the serial I/O2 register(address 034616), regardless of
the serial I/O transfer mode.
At termination of transmit/receive operation, in the 8-bit serial I/O mode, the S BUSY2 output goes to “H”
____________
(or the SBUSY2 output returns to “L”), when the serial transfer status flag is set to “0”, regardless of
whether the internal or external synchronous clock is selected. Furthermore, in the automatic transfer
serial I/O mode (SBUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to “H”
____________
(or the SBUSY2 output goes to “L”) each time 1-byte of receive data is written into the automatic trans-
fer RAM.
112
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 96. SBUSY2 Output Operation (3)
Internal clock
"1"
"0"
"H"
"L"
D
0
Tc
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Automatic
transfer interval
Automatic transfer RAM
Serial I/O2 register
Serial I/O2 register
Automatic transfer RAM
•Serial operation used S
BUSY2
output
Operation mode
: Automatic transfer serial I/O mode
Transfer clock : Internal synchronous clock
S
BUSY2
output timing : Each 1-byte data
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i = 1, 2)(output)
S
OUT2
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
S
BUSY2
(output)
Internal clock
"1"
"0"
"H"
"L"
D
0
Tc
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Automatic
transfer interval
Automatic transfer RAM
Serial I/O2 register
Serial I/O2 register
Automatic transfer RAM
•Serial operation used S
BUSY2
output
Operation mode
: Automatic transfer serial I/O mode
Transfer clock : Internal synchronous clock
S
BUSY2
output timing : Each transfer of all data
Serial transfer status flag
(bit 5 at address 0344
16
)
S
CLK2i
(i = 1, 2)(output)
S
OUT2
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
S
BUSY2
(output)
113
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 97. SRDY2 Output Operation
Figure 98. SRDY2 Input Operation
•Serial operation used S
RDY2
output
Internal clock
S
RDY2
(output)
"H"
"L"
Tc
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
CLK2i
(i = 1, 2) (output)
S
OUT2
Operation mode
: 8-bit serial I/O mode
Transfer clock : Internal synchronous clock
"1"
"0"
Serial transfer status flag
(bit 5 at address 0344
16
)
•Serial operation used S
RDY2
input
Internal clock
"1"
"0"
S
RDY2
(input
)
"H"
"L"
Tc
Tc : Internal synchronous clock is selected by bits 5 to 7 of address 0348
16
D0D1D2D3D4D5D6D7
1.5 cycle or more
S
CLK2i
(i = 1, 2) (output)
S
OUT2
Operation mode
: 8-bit serial I/O mode
Transfer clock : Internal synchronous clock
Serial transfer status flag
(bit 5 at address 0344
16
)
(4) SRDY2 output signal
The SRDY2 output is a transmit/receive enable signal which informs the serial transfer destination that
transmit/receive is ready. In the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0” ],
__________
the SRDY2 output goes to “L” (or the SRDY2 output goes to “H”). When the transmitted data is written to
__________
the serial I/O2 register (address 034616), the SRDY2 output goes to “H” (or the SRDY2 output goes to
“L”). When a transmit/receive operation is started and the transfer clock goes to “L”, the SRDY2 output
__________
goes to “L” (or the SRDY2 output goes to “H”).
(5) SRDY2 input signal
The SRDY2 input is a signal for receiving a transmit/receive ready completion signal from the serial
transfer destination. The SRDY2 input signal becomes valid only when the SRDY2 input and the SBUSY2
output are used.
When the internal synchronous clock is selected, input a “L” level signal into the SRDY2 input (or a “H”
__________
level signal into the SRDY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216)
__________
= “0” ]. When a “H” level signal is input into the SRDY2 input (or a “L” level signal is input into the SRDY2
input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK2i (i =
__________
1, 2) output and a transmit/receive operation is started. When SRDY2 input is driven “L” (or SRDY2 input
is driven “H”) during transmit/receive operation, the transfer clock being output from S CLK2i (i = 1, 2)
remains active until after the system finishes sending or receiving the designated number of bits,
without stopping the transmit/receive operation immediately.
The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, the SRDY2 input becomes one of the triggers to
____________
output the SBUSY2 signal. To start a transmit/receive operation (SBUSY2 output: “L”, (or SBUSY2 output:
__________
“H”)), input a “H” level signal into the SRDY2 input (or a “L” level signal into the SRDY2 input,) and also
write transmit data into the serial I/O2 register (address 034616).
114
Serial I/O2
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 99. Handshake Operation at Serial I/O2 Mutual Connecting (1)
Figure 100. Handshake Operation at Serial I/O2 Mutual Connecting (2)
A: B:
SCLK2i
(i = 1, 2)
SRDY2
SBUSY2 SBUSY2
SRDY2
SCLK2i
(i = 1, 2)
A:
B: Write to serial
I/O2 re
g
ister
SCLK2i
(i = 1, 2)
SRDY2
SBUSY2
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O2 register
A: B:
S
CLK2i
(i= 1, 2)
S
RDY2
S
BUSY2
S
BUSY2
S
RDY2
S
CLK2i
(i= 1, 2)
A:
B:
Write to serial
I/O2 re
g
ister
S
CLK2i
(i= 1, 2)
S
RDY2
S
BUSY2
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O2 register
115
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Absolute precision VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• Without sample and hold function (10-bit resolution)
±3LSB
VCC = 3V • Without sample and hold function (8-bit resolution)(Note 3)
±2LSB
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 8pins (AN0 to AN7)
A-D conversion start condition
•Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin •Without sample and hold function
8-bit resolution: 49
φ
AD cycles, 10-bit resolution: 59
φ
AD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33
φ
AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the
φ
AD frequency to 250kHz min.
With the sample and hold function, set the
φ
AD frequency to 1MHz min.
Note 3: Only mask ROM version.
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107 also function as the analog signal input pins. The direction registers of
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716)
can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF)
when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from
VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting
bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 30 shows the performance of the A-D converter. Figure 101 shows the block diagram of the A-D
converter, and Figures 102 and 103 show the A-D converter-related registers.
Table 30. Performance of A-D converter
116
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 101. Block diagram of A-D converter
1
/
2
A
D
1
/
2
f
A
D
A
-
D
c
o
n
v
e
r
s
i
o
n
r
a
t
e
s
e
l
e
c
t
i
o
n
(
0
3
C
1
1
6
,
0
3
C
0
1
6
)
(
0
3
C
3
1
6
,
0
3
C
2
1
6
)
(
0
3
C
5
1
6
,
0
3
C
4
1
6
)
(
0
3
C
7
1
6
,
0
3
C
6
1
6
)
(
0
3
C
9
1
6
,
0
3
C
8
1
6
)
(
0
3
C
B
1
6
,
0
3
C
A
1
6
)
(
0
3
C
D
1
6
,
0
3
C
C
1
6
)
(
0
3
C
F
1
6
,
0
3
C
E
1
6
)
C
K
S
1
=
1
C
K
S
0
=
0
A
-
D
r
e
g
i
s
t
e
r
0
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
1
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
2
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
3
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
4
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
5
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
6
(
1
6
)
A
-
D
r
e
g
i
s
t
e
r
7
(
1
6
)
R
e
s
i
s
t
o
r
l
a
d
d
e
r
S
u
c
c
e
s
s
i
v
e
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
A
N
0
A
N
1
A
N
2
A
N
3
A
N
5
A
N
6
A
N
7
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
a
d
d
r
e
s
s
0
3
D
6
1
6
)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
a
d
d
r
e
s
s
0
3
D
7
1
6
)
V
r
e
f
V
I
N
V
C
U
T
=
0
D
a
t
a
b
u
s
h
i
g
h
-
o
r
d
e
r
D
a
t
a
b
u
s
l
o
w
-
o
r
d
e
r
V
R
E
F
A
V
S
S
A
N
4
V
C
U
T
=
1
C
K
S
0
=
1
C
K
S
1
=
0
C
H
2
,
C
H
1
,
C
H
0
=
0
0
0
C
H
2
,
C
H
1
,
C
H
0
=
0
0
1
C
H
2
,
C
H
1
,
C
H
0
=
0
1
0
C
H
2
,
C
H
1
,
C
H
0
=
0
1
1
C
H
2
,
C
H
1
,
C
H
0
=
1
0
0
C
H
2
,
C
H
1
,
C
H
0
=
1
0
1
C
H
2
,
C
H
1
,
C
H
0
=
1
1
0
C
H
2
,
C
H
1
,
C
H
0
=
1
1
1
D
e
c
o
d
e
r
C
o
m
p
a
r
a
t
o
r
A
d
d
r
e
s
s
e
s
117
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 102. A-D converter-related registers (1)
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected
CH0
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
MD0
MD1
Must always be “0”.
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select
bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1 0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
0 : Vref not connected
1 : Vref connected
Must always be “0”.
WR
b2 b1 b0
b4 b3
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pin)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
0
00
118
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 103. A-D converter-related registers (2)
Eight low-order bits of A-D conversion result
A-D control register 2 (Note)
Symbol Address When reset
ADCON2 03D4
16
XXXXXXX0
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion method
select bit 0 Without sample and hold
1 With sample and hold
SMP
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
A-D register i
Symbol Address When reset
ADi (i=0 to 7)
03C0
16
to 03CF
16
Indeterminate
Function WR
(b15) b7b7 b0 b0
(b8)
• During 10-bit mode
Two high-order bits of A-D conversion result
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
• During 8-bit mode
When read, the content is indeterminate
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
119
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table
31 shows the specifications of one-shot mode. Figure 104 shows the A-D control register in one-shot mode.
Table 31. One-shot mode specifications
Item Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”)
•Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Figure 104. A-D conversion register in one-shot mode
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
R
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0: f
AD
/4 is selected
1: f
AD
/2 is selected
CKS0
W
00
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1 0 : Any mode other than repeat sweep
mode 1
1 : Vref connected
WR
Invalid in one-shot mode
0
0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected
b2 b1 b0
0 0 : One-shot mode
b4 b3
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Frequency select bit1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Must always be “0”.
Must always be “0”.
0
0
0
120
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table
32 shows the specifications of repeat mode. Figure 105 shows the A-D control register in repeat mode.
Table 32. Repeat mode specifications
Item Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Star condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Figure 105. A-D conversion register in repeat mode
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D616 00000XXX2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
01
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
b2 b1 b0
0 1 : Repeat mode
b4 b3
Note: If the A-D control register is rewritten during A-D conversion, the conversin
result is indeterminate.
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1
1 : Vref connected
WR
Invalid in repeat mode
01
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Any mode other than repeat sweep mode 1
Note: If the A-D control register is rewritten during A-D conversion, the conversn
result is indeterminate.
0
00
Must always be “0”.
Must always be “0”.
121
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 33 shows the specifications of single sweep mode. Figure 106 shows the A-D control
register in single sweep mode.
Table 33. Single sweep mode specifications
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition Writing “1” to A-D converter start flag
Stop condition •End of A-D conversion
(A-D conversion start flag changes to “0”, except when external trigger is selected)
•Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin
AN
0
and AN
1
(2 pins), AN
0
to AN
3
(4 pins), AN
0
to AN
5
(6 pins), or AN
0
to AN
7
(8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Figure 106. A-D conversion register in single sweep mode
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D616 00000XXX2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
A-D operation mode
select bit 0 1 0 : Single sweep mode
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
0 : Any mode other than repeat sweep mode 1A-D operation mode
select bit 1
1 : Vref connected
WR
10
Invalid in single sweep mode
0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When single sweep and repeat sweep mode 0
are selected
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Must always be “0”.
Must always be “0”.
0
00
122
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 34 shows the specifications of repeat sweep mode 0. Figure 107 shows the A-D
control register in repeat sweep mode 0.
Table 34. Repeat sweep mode 0 specifications
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin
AN
0
and AN
1
(2 pins), AN0 to AN
3
(4 pins), AN
0
to AN
5
(6 pins), or AN
0
to AN
7
(8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
Figure 107. A-D conversion register in repeat sweep mode 0
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 0
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
1 : Any mode other than repeat sweep mode 1A-D operation mode
select bit 1
1 : Vref connected
WR
11
Invalid in repeat sweep mode 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When repeat sweep mode 1 is selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
0
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Must always be “0”.
Must always be “0”.
0
00
123
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected -> AN0 -> AN1 -> AN0 -> AN2 -> AN0 -> AN3, etc
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin
Emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 35 shows the specifications of repeat sweep mode 1. Figure
108 shows the A-D control register in repeat sweep mode 1.
Table 35. Repeat sweep mode 1 specifications
Figure 108. A-D conversion register in repeat sweep mode 1
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 1
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
1 : Repeat sweep mode 1A-D operation mode
select bit 1
1 : Vref connected
WR
11
Invalid in repeat sweep mode 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pins)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
1
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Must always be “0”.
Must always be “0”.
0
00
124
A-D converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”.
When sample and hold is selected, the rate of conversion of each pin increases. As a result, 28 φ AD
cycles are achieved with 8-bit resolution and 33 φ AD cycles with 10-bit resolution. Sample and hold
can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion
whether sample and hold is to be used.
125
D-A converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 36 lists the performance of the D-A converter. Figure 109 shows the block diagram of the D-A
converter. Figure 110 shows the D-A control register. Figure 111 shows the D-A converter equivalent
circuit.
Table 36. Performance of D-A converter
Item Performance
Conversion method R-2R method
Resolution 8 bits
Analog output pin 2 channels
AAAAAAA
AAAAAAA
P9
7
/DA
0
/CLK
OUT
/DIM
OUT
AAAAAA
P9
6
/DA
1
/SCLK
22
Data bus low-order bits
D-A register0 (8)
R-2R resistor ladder
D-A0 output enable bit
D-A register1 (8)
R-2R resistor ladder
D-A1 output enable bit
(Address 03D8
16
)
(Address 03DA
16
)
Figure 109. Block diagram of D-A converter
126
D-A converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 110. D-A control register
D-A control register
Symbol Address When reset
DACON 03DC
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
D-A0 output enable bit
DA0E
Bit symbol Bit name Function R W
0 : Output disabled
1 : Output enabled
D-A1 output enable bit 0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
Symbol Address When reset
DAi (i = 0,1) 03D8
16
,
03DA
16
Indeterminate
WR
b7 b0
Function R W
Output value of D-A conversion
Figure 111. D-A converter equivalent circuit
V
REF
AV
SS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
DA0
MSB LSB
D-A0 output enable bit
"0"
"1"
D-A0 register0
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A
16
.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 00
16
so that no current flows in the resistors Rs and 2Rs.
127
CRC Calculation Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 112 shows the block diagram of the CRC circuit. Figure 113 shows the CRC-related registers.
Figure 114 shows the calculation example using the CRC calculation circuit
Figure 113. CRC-related registers
Figure 112. Block diagram of CRC circuit
AAAAAAAAAA
AAAAAAAAAA
CRC code generating circt
x
16
+ x
12
+ x
5
+ 1
Eight low-order bits
AAAAA
Eight high-order bits
Data bus high-order bits
Data bus low-order bits
AAAAAAAAAA
AAAAAAAAAA
AAAAAA
AAAAAA
CRC data register (16)
CRC input register (8)
(Addresses 03BD
16
, 03BC
16
)
(Address 03BE
16
)
Symbol Address When reset
CRCD 03BD
16
, 03BC
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
CRC data register
WR
CRC calculation result output register
Function Values that
can be set
0000
16
to FFFF
16
Symbo Address When reset
CRCIN 03BE
16
Indeterminate
b7 b0
CRC input register
WR
Data input register
Function Values that
can be set
00
16
to FF
16
128
CRC Calculation Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 114. Calculation example using the CRC calculation circuit
b15 b0
(1) Setting 0000
16
CRC data register CRCD
[03BD
16
, 03BC
16
]
b0b7
b15 b0
(2) Setting 01
16
CRC input register CRCIN
[03BE
16
]
2 cycles
After CRC calculation is complete
CRC data register CRCD
[03BD
16
, 03BC
16
]
1189
16
Stores CRC code
b0b7
b15 b0
(3) Setting 23
16
CRC input register CRCIN
[03BE
16
]
After CRC calculation is complete
CRC data register CRCD
[03BD
16
, 03BC
16
]
0A41
16
Stores CRC code
The code resulting from sending 01
16
in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X
16
+ X
12
+ X
5
+ 1), becomes the remainder resulting from dividing (1000 0000) X
16
by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189
16
in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000
LSB MSB
LSB MSB
98 1 1
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
129
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Programmable I/O Ports
There are 48 programmable I/O ports: P3, P4 and P7 to P10. Each port can be set independently for input
or output using the direction register. A pull-up resistance for each block of 4 ports can be set.
P3 and P40 to P43 are high-breakdown-voltage, P-channel open drain outputs, and have no built-in pull-
down resistance (note).
Figures 115, 116 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
Note: These ports can be selected whether pull-down resistors are built-in or not by the option specify.
(1) Direction registers
Figure 117 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
(2) Port registers
Figure 118 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 119 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
Note: P3, P40 to P43 have no built-in pull-up resistance, because of these pin's are high-breakdown-
voltage, P-channel open drain outputs.
Exclusive High-breakdown-voltage Output Ports
There are 40 exclusive output Ports: P0 to P2, P5 and P6.
All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output ports
except P2 have built-in pull-down resistance.
Figure UA-1 shows the configuration of the exclusive high-breakdown-voltage output ports.
130
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 115. Programmable I/O ports (1)
P7
0
to P7
2
, P8
0
to P8
5
, P8
7
, P9
3
(inside dotted-line included)
P8
6
(inside dotted-line not included)
P3
0
to P3
7
, P4
0
to P4
3
P4
4
, P9
2
,P9
4
Data bus
Pull-up selection
Data bus
Data bus
Data bus
Pull-up selection
output
“1”
output
“1”
Input to respective peripheral functions
Direction register
Port latch
Port latch
Port latch
Direction register
Port latch
Direction register
P0
0
to P0
7
, P1
0
to P1
7
,
P5
0
to P5
7
, P6
0
to P6
7
,
(inside dotted-line included)
P2
0
to P2
7
(inside dotted-line not included)
Output
V
EE
131
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 116. Programmable I/O ports (2)
P4
5
to P4
7
, P7
3
to P7
7
P9
0
, P9
1
, P9
5
P9
6
(inside dotted-line included)
P9
7
(inside dotted-line not included)
Data bus
Pull-up selection
Data
bus
Direction register
Port latch
Pull-up selection
Analog output D-A output enabled
Direction register
Port latch
output
“1”
output
“1”
P10
0
to P10
7
Data bus
Pull-up selection
Direction register
Port latch
Analog input
Input to respective peripheral functions
Input to respective peripheral functions
132
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 117. Direction register
P
o
r
t
P
i
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
s W
h
e
n
r
e
s
e
t
P
D
i
(
i
=
3
t
o
1
0
,
e
x
c
e
p
t
5
,
6
)0
3
E
7
1
6
,
0
3
E
A
1
6
,
0
3
E
F
1
6
00
1
6
0
3
F
2
1
6
,
0
3
F
3
1
6
,
0
3
F
6
1
6
00
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
lW
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
D
i
_
0P
o
r
t
P
i0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
1P
o
r
t
P
i1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
2P
o
r
t
P
i2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
3P
o
r
t
P
i3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
4P
o
r
t
P
i4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
5P
o
r
t
P
i5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
6P
o
r
t
P
i6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
7P
o
r
t
P
i7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
0
:
I
n
p
u
t
m
o
d
e
(
F
u
n
c
t
i
o
n
s
a
s
a
n
i
n
p
u
t
p
o
r
t
)
1
:
O
u
t
p
u
t
m
o
d
e
(
F
u
n
c
t
i
o
n
s
a
s
a
n
o
u
t
p
u
t
p
o
r
t
)
(
i
=
3
t
o
1
0
e
x
c
e
p
t
5
,
6
)
Port Pi register
Symbol Addres When reset
Pi (i = 0 to 10) 03E0
16
, 03E1
16
, 03E4
16
, 03E5
16
, 03E8
16
Indeterminate
03E9
16
, 03EC
16
, 03ED
16
, 03F0
16
, 03F1
16
, 03F4
16
Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 10)
Figure 118. Port register
133
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 119. Pull-up control register
Pull-up control register 0
Symbol
Address
When rese
t
PUR0
03FD
16
00
16
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU01 P4
4
to P4
7
pull-up
PU06 P7
0
to P7
3
pull-up
PU07 P7
4
to P7
7
pull-up
Pull-up control register 1
Symbol
Address
When rese
t
PUR1
03FE
16
00
16
Bit name Function Bit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PU10 P8
0
to P8
3
pull-up
PU11 P8
4
to P8
7
pull-up
PU12 P9
0
to P9
3
pull-up
PU13 P9
4
to P9
7
pull-up
PU14 P10
0
to P10
3
pull-up
PU15 P10
4
to P10
7
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if
read, turns out to be indeterminate.
134
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 37. Example connection of unused pins
Figure 120. Example connection of unused pins
Pin name Connection
Ports P3, P4(Note 2), P7 to P10 Specify output mode, and leave these pins open;
or specify input mode, and connect to V
SS
via resistor (pull-down)
Note 1: With external clock input to X
IN
pin.
Note 2: In case of pull-down option is specified, leave the specified ports open.
(Pull-down resistors are built-in the specified port)
Note 3: Connect a bypass capacitor.
X
OUT
(Note 1), V
EE
AV
SS
, V
REF
AV
CC
Open
Connect to V
CC
(Note 3)
Connect to V
SS
(Note 3)
Ports P0 to P2, P5, P6 Leave these pins open
CNV
SS
Connect to V
SS
via resistor
Port P3, P4(Note 1), P7 to P10
(Input mode)
(Output mode)
Port P0 to P2, P5, P6
(Output mode)
X
OUT
AV
CC
(Note 2)
CNV
SS
AV
SS
(Note 2)
V
REF
(Note 2)
Microcomputer
V
CC
V
SS
Open
Open
Open
V
EE
Open
Note 1: In case of pull-down option is specified, leave the specified ports (port P3, P4) open.
(Pull-down resistors are built-in the specified port)
Note 2: Connect a bypass capacitor.
135
Pull-down
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
1
2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
MASK OPTION OF PULL-DOWN RESISTOR (object product: mask ROM version)
Whether built-in pull-down resistors are connected or not to high-breakdown voltage ports P20 to P27, P30
to P37,and P40 to P43 can be specified in ordering mask ROM. The option type can be specified from
among 7 types; A to G.
A
B
C
D
E
F
G
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
P4
0
P4
1
P4
2
0000000000000000000
P4
3
0
11110000000000000000
11111111000000000000
11111111111100000000
11111111111111110000
11111111111111111100
11111111111111111111
Note 1: The electrical characteristics of high-breakdown voltage ports P20 to P27, P30 to P37, and P40 to
P43’s built-in pull-down resistors are the same as that of high-breakdown voltage ports P00 to P07.
Note 2: The absolute maximum ratings of power dissipation may be exceed owing to the number of built-in
pull-down resistor. After calculating the power dissipation, specify the option type.
Note 3: The option types B to G cannot be specified because these types are currently under development.
Power Dissipation Calculating Method
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value = 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a X c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
(1) Digit pin power dissipation
{h X b X (1–Toff / Tdisp) X voltage} / a
(2) Segment pin power dissipation
{i X d X (1–Toff / Tdisp) X voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit X (b X f / b) X (1–Toff / Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment X (d X g / c) X (1–Toff / Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190 mW
(1) + (2)+ (3) + (4) + (5) = X mW
136
Pull-down
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Power Dissipation Calculating example 1
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 X 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 X 16 X (1–1/16) X 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 X 31 X (1–1/16) X 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
(50 – 2)2 /68 X (16 X 16/16) X (1 – 1/16) / 17 = 29.90 mW
(4) Pull-down resistor power dissipation (segment)
(50 – 2)2 /68 X (31 X 20/20) X (1 – 1/16) / 17 = 57.93 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 319.86 mW
DIG0
DIG1
DIG2
DIG3
DIG13
DIG14
DIG15
Timing
number 12 3 16171514
Tscan
Repeat cycle
Figure 121. Digit timing waveform (1)
137
Pull-down
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Power Dissipation Calculating example 2(when 2 or more digit is turned ON at same time)
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 X 12 X (1–1 / 16) X 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 X 114 X (1–1 / 16) X 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
(50– 2)2 / 68 X (12 X 10 / 12) X (1 – 1 / 16) / 11 = 28.88 mW
(4) Pull-down resistor power dissipation (segment)
(50 – 2)2 / 68 X (114 X 22 / 24) X (1 – 1 / 16) / 11 = 301.77 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 615.77 mW (There is a limit of use temperature)
DIG0
DIG1
DIG2
DIG3
DIG7
DIG8
DIG9
Timing
number 12 34567891011
DIG4
DIG5
DIG6
Tscan
Repeat cycle
Figure 122. Digit timing waveform (2)
138
Pull-down
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Power Dissipation Calculating example 3
(when 2 or more digit is turned ON at same time, and used Toff invalid function)
Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW
Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114 ( for Toff invalid waveform;50)
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
[{18 X 10 X (1–1/16) X 2} + {18 X 2 X 2}] / 11 = 37.23 mW
(2) Segment pin power dissipation
[{3 X 64 X (1–1/16) X 2} + {3 X 50 X 2}] / 11 = 60.00 mW
(3) Pull-down resistor power dissipation (digit)
[{(50– 2)2 / 68 X (10 X 10 / 12) X (1 – 1 / 16)} + {(50– 2)2 / 68 X (2 X 10 / 12) } ] /11 = 29.20 mW
(4) Pull-down resistor power dissipation (segment)
[{(50– 2)2 / 68 X (64 X 22 / 24) X (1 – 1 / 16)} + {(50– 2)2 / 68 X (50 X 22 / 24) } ] / 11 = 310.59 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW
(1) + (2)+ (3) + (4) + (5) = 627.02 mW (There is a limit of use temperature)
Figure 123. Digit timing waveform (3)
DIG0
DIG1
DIG2
DIG3
DIG7
DIG8
DIG9
Timing
number 12 34567891011
DIG4
DIG5
DIG6
Tscan
Repeat cycle
139
Electrical characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 38. Absolute maximum ratings
Operating ambient temperature
Parameter Unit
V
REF,
X
IN
Input voltage RESET
,
CNVss
,
Analog supply voltage
Supply voltage
Output voltage
V
O
- 0.3 to Vcc+0.3
(Note)
P
d
Storage temperature
- 0.3 to 6.5
Standard
- 0.3 to 6.5 V
V
V
Condition
V
I
AVcc
Vcc
T
stg
T
opr
Symbol
V
-40 to 150
-20 to 85
P4
4
to P4
7,
P7
0
to P7
7,
P8
0
to P8
7,
P9
0
to P9
7,
P10
0
to P10
7,
2.7(Note1) 5.5
Typ. Max. Unit
Parameter
Vcc 5.0
Supply voltage
Symbol Min Standard
Analog supply voltage Vcc
AVcc V
V0
0
Analog supply voltage
Supply voltage
Vss
AVss
0.8Vcc
V
V
V
V
0.52Vcc
Vcc
Vcc
0.16Vcc0
HIGH input voltage
LOW input voltage
HIGH input voltage
P3
0
to P3
7,
P4
0
to P4
3
V
P3
0
to P3
7,
P4
0
to P4
3
P7
0
to P7
7,
P8
0
to P8
7,
P9
0
to P9
7,
P10
0
to P10
7,
X
IN,
RESET
,
CNV
SS
V
IH
V
IH
V
IL
Pull-down supply voltage Vcc - 50 to Vcc+0.3V VV
EE
V
I
P3
0
to P3
7,
P4
0
to P4
3
Input voltage Vcc - 50 to Vcc+0.3 V
P0
0
to P0
7,
P1
0
to P1
7,
P2
0
to P2
7,
P3
0
to P3
7,
P4
0
to P4
3,
P5
0
to P5
7,
Output voltage
V
O
P6
0
to P6
7
Vcc - 50 to Vcc+0.3
V
V
EE
Pull-down supply voltage Vcc-48 Vcc V
V
IL
LOW input voltage P7
0
to P7
7,
P8
0
to P8
7,
P9
0
to P9
7,
P10
0
to P10
7,
X
IN,
RESET
,
CNV
SS
0V
0.2Vcc
X
OUT
P4
4
to P4
7,
P7
0
to P7
7,
P8
0
to P8
7,
P9
0
to P9
7,
P10
0
to P10
7,
-0.3 to Vcc+0.3
Power
dissipation Ta=-20 to 60 750
750-12 X (Ta-60)
Ta=60 to 85 mW
mW
V
IH
P4
4
to P4
7
0.50Vcc Vcc V
HIGH input voltage
V
0.16Vcc0
LOW input voltage P4
4
to P4
7
V
IL
C
C C
C
Note 1: When writing to flash ,only CNVss is –0.3 to 13 (V) .
Note: VCC = 4.0V to 5.5V in flash memory version.
Table 39. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to
85oC unless otherwise specified) (Note)
140
Electrical characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 40. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to
85oC unless otherwise specified) (Note 6)
Note 1: The total output current is the sum of all the currents through the applicable ports. The total
average value measured over 100ms. The total peak current is the peak of all the currents.
Note 2: The peak output current is the peak current flowing in each port.
Note 3: The average output current in an average value measured over 100ms.
Note 4: When the oscillating frequency has a duty cycle of 50 %.
Note 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency
on condition that f(XCIN) < f(XIN) / 3.
Note 6: VCC=4.0V to 5.5V in flash memory version.
Note 7: Relationship between main clock oscillation frequency and supply voltage.
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAA
A
AA
A
A
AA
A
A
AA
A
A
AA
A
A
AA
A
AAAA
10.0
3.5
0.0 2.7 4.0 5.5
Main clock input oscillation frequency
(No wait)
5 X V
CC
-10.000MH
Z
Flash memory version
Operating maximum
frequency
[MH
Z
]
Supply voltage
[V] (BCLK: no division)
I
OH (avg)
mA
mA
I
OH (peak)
-18
-40
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
3
, P5
0
to P5
7
,
P6
0
to P6
7
f
(X
IN
)MHz
10
f
(Xc
IN
)kHz50
32.768
Vcc=4.0V to 5.5V
Vcc=2.7V to 4.0V MHz
0
05 X Vcc-10
Symbol Parameter Unit
Standard
Min Typ. Max.
HIGH peak output
current (Note 2)
HIGH average output
current (Note 3)
Main clock input oscillation frequency (Note 4, 7)
Sub clock oscillation frequency (Note 4, 5)
P0
0
to P0
7
, P5
0
to P5
7
,
P6
0
to P6
7
HIGH total peak output
current (Note 1)
I
OH (peak)
-240 mA
P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
,
P4
0
to P4
3
HIGH total peak output
current (Note 1)
I
OH (peak)
-240 mA
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
5
HIGH total peak output
current (Note 1)
I
OH (peak)
-80 mA
P8
6
, P8
7
,
P9
0
to P9
7
,
P10
0
to P10
7
HIGH total peak output
current (Note 1)
I
OH (peak)
-80 mA
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
5
LOW total peak output
current (Note 1)
I
OL (peak)
80 mA
P8
6
, P8
7
,
P9
0
to P9
7
,
P10
0
to P10
7
LOW total peak output
current (Note 1)
I
OL (peak)
80 mA
P0
0
to P0
7
, P5
0
to P5
7
,
P6
0
to P6
7
HIGH total average
output current (Note 1)
I
OH (avg)
-120 mA
P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
,
P4
0
to P4
3
HIGH total average
output current (Note 1)
I
OH (avg)
-120 mA
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
5
HIGH total average
output current (Note 1)
I
OH (avg)
-40 mA
P8
6
, P8
7
,
P9
0
to P9
7
,
P10
0
to P10
7
HIGH total average
output current (Note 1)
I
OH (avg)
-40 mA
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
5
LOW total average
output current (Note 1)
I
OL (avg)
40 mA
P8
6
, P8
7
,
P9
0
to P9
7
,
P10
0
to P10
7
LOW total average
output current (Note 1)
I
OL (avg)
40 mA
mAI
OH (peak)
-10
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
7
HIGH peak output
current (Note 2) P9
0
to P9
7
,
P10
0
to P10
7
mAI
OL (peak)
10
P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
7
LOW peak output
current (Note 2) P9
0
to P9
7
,
P10
0
to P10
7
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
,P3
0
to P3
7
,
P4
0
to P4
3
, P5
0
to P5
7
,
P6
0
to P6
7
I
OH (avg)
mA-5
HIGH average output
current (Note 3) P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
7
P9
0
to P9
7
,
P10
0
to P10
7
I
OL (avg)
mA5
LOW average output
current (Note 3) P4
4
to P4
7
, P7
0
to P7
7
,
P8
0
to P8
7
P9
0
to P9
7
,
P10
0
to P10
7
141
Electrical characteristics (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 41.
Electrical characteristics (referenced to V
CC
= 5V, V
SS
= 0V at Ta = 25
o
C,
f(X
IN
) =10MH
Z
unless otherwise specified)
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
S
y
m
b
o
l
V
O
H
V
O
H
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
H
V
O
L
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
i
n
p
u
t
c
u
r
r
e
n
t
I
I
L
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
S
t
a
n
d
a
r
d
T
y
p
.U
n
i
t
M
e
a
s
u
r
i
n
g
c
o
n
d
i
t
i
o
n
V
V
V
X
O
U
T
3
.
0
3
.
0
V2
.
0
µ
A
M
i
n
.M
a
x
.
3
.
5
P
a
r
a
m
e
t
e
r
I
O
H
=
-
1
8
m
A
I
O
H
=
-
1
m
A
I
O
H
=
-
5
m
A
I
O
H
=
-
0
.
5
m
A
I
O
L
=
5
m
A
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
I
=
0
V
-
5
.
0
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
L
H
y
s
t
e
r
e
s
i
s
H
y
s
t
e
r
e
s
i
s
H
I
G
H
i
n
p
u
t
c
u
r
r
e
n
t
I
I
H
V
T
+
-
V
T
-
V
T
+
-
V
T
-
V
X
O
U
T
2
.
0
2
.
0
0
.
20
.
8V
0
.
21
.
8V
5
.
0µ
A
I
O
L
=
1
m
A
I
O
L
=
0
.
5
m
A
R
E
S
E
T
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,V
I
=
5
V
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
T
A
0
I
N
t
o
T
A
4
I
N
,
T
B
0
I
N
t
o
T
B
2
I
N
,
C
L
K
0
,
C
L
K
1
,
S
R
D
Y
2
I
N
,
S
B
S
Y
2
I
N
,
I
N
T
0
t
o
I
N
T
5
,
C
T
S
0
,
C
T
S
1
,
S
I
N
2
,
S
C
L
K
2
1
,
S
C
L
K
2
2
,
R
x
D
0
,
I
I
H
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
(
N
o
t
e
1
)V
I
=
5
V5
.
0µ
A
I
I
L
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
(
N
o
t
e
1
)V
I
=
0
V
-
5
.
0µ
A
R
P
U
L
L
U
P
P
u
l
l
-
u
p
r
e
s
i
s
t
a
n
c
eP
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
I
O
H
=
-
5
m
A4
.
5
3
0
.
05
0
.
01
6
7
.
0k
Ω
3
.
0
R
x
D
1
R
f
X
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
e
X
I
N
1
.
0
R
P
U
L
L
D
P
u
l
l
-
d
o
w
n
r
e
s
i
s
t
a
n
c
eP
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
E
E
=
V
C
C
-
4
8
V
,
V
O
L
=
V
C
C
O
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
s
“
o
f
f
”
I
L
E
A
K
O
u
t
p
u
t
l
e
a
k
c
u
r
r
e
n
tP
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
4
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
E
E
=
V
C
C
-
4
8
V
,
V
O
L
=
V
C
C
-
4
8
V
O
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
s
“
o
f
f
”
6
88
01
2
0k
Ω
(P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
i
n
o
p
t
i
o
n
s
p
e
c
i
f
y
)
-
1
0µ
A
V
I
=
0
V
V
R
A
M
R
A
M
r
e
t
e
n
t
i
o
n
v
o
l
t
a
g
e
I
c
cP
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
(
N
o
t
e
3
)
W
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d2
.
0V
S
q
u
a
r
e
w
a
v
e
,
n
o
d
i
v
i
s
i
o
n
1
.
0µ
A
m
A
2
0
.
0
1
9
.
03
8
.
0
f
(
X
I
N
)
=
1
0
M
H
z
f
(
X
C
I
N
)
=
3
2
k
H
z4
.
0µ
A
S
q
u
a
r
e
w
a
v
e
,
8
d
i
v
i
s
i
o
n
f
(
X
I
N
)
=
1
0
M
H
z4
.
2m
A
S
q
u
a
r
e
w
a
v
e
(
N
o
t
e
2
)
f
(
X
C
I
N
)
=
3
2
k
H
z9
0
.
0µ
A
M
Ω
R
f
X
C
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
e
X
C
I
N
6
.
0M
Ω
Th
e
o
u
t
p
u
t
p
i
n
s
a
r
e
o
p
e
n
a
n
d
o
t
h
e
r
p
i
n
s
a
r
e
V
S
S
W
h
e
n
a
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
(
N
o
t
e
2
)
T
a
=
8
5
w
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
T
a
=
2
5
w
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
C
C
Note 1: Except when reading ports P3, P40 to P43.
Note 2: Fixed XCIN-XCOUT drive capacity select bit to “HIGH” and XIN pin to “H” level.
Note 3: This contains an electric current to flow into AVCC pin.
142
Electrical characteristics (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 42. A-D conversion characteristics (referenced to V
CC
= AV
CC
= V
REF
= 5V, Vss = AV
SS
= 0V
at Ta = 25
o
C, f(X
IN
) = 10MH
Z
unless otherwise specified)
Table 43. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
µs
Standard
Min. Typ. Max.
Resolution
Absolute
accuracy
Bits
LSB
V
REF
=
V
CC
±3
10
Symbol Parameter Measuring condition Unit
V
REF
= V
CC
= 5V
R
LADDER
t
CONV
Ladder resistance
Conversion time
(10bit)
Reference voltage
Analog input voltage
kΩ
V
V
IA
V
REF
V0
2
10
V
CC
V
REF
40
3.3
Conversion time
(8bit) 2.8
t
CONV
t
SAMP
Sampling time
0.3
V
REF
=
V
CC
Sample & hold function not available
Sample & hold function available(10bit)
AN
0
to AN
7
input
V
REF
=V
CC
= 5V
LSB
Sample & hold function available(8bit)
V
REF
= V
CC
= 5V
±2LSB
µs
µs
±3
Min. Typ. Max.
t
su
R
O
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
kΩ
mA
I
VREF
1.0
1.5
8
3
Symbol Parameter Measuring condition Unit
20104 µs
(
Note
)
Standard
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
143
Timing (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 44. External clock input
Max.
External clock rise time
ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
15
100
40
40 15
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise
specified)
Table 45. High-breakdown voltage p-channel open-drain output port
Symbol
Standard
Measuring condition Max.Typ.
Parameter Unit
Min.
t
r(Pch-strg)
P-channel high-breakdown
voltage output rising time
(Note 1) 55
µs
ns
t
r(Pch-weak)
P-channel high-breakdown
voltage output rising time
(Note 2) 1.8
C
L=100pF
V
EE=VCC - 43V
C
L=100pF
V
EE=VCC - 43V
Note 1: When bit 7 of the FLDC mode register (address 035016) is at “0”.
Note 2: When bit 7 of the FLDC mode re
g
ister
(
address 035016
)
is at “1”.
V
EE
P0, P1, P2, P3,
P4
0
to P4
3
, P5, P6
P-channel high-
breakdown
voltage output
port (Note)
Note: Ports P2, P3, and P4
0
to P4
3
need external resistors in mask ROM version.
(in case of not mask option specified)
Ports P2, P3, and P4
0
to P4
3
need external resistors in flash memory version.
C
L
Figure 124. Circuit for measuring output switching characteristics
144
Timing (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 46. Timer A input (counter input in event counter mode)
Table 47. Timer A input (gating input in timer mode)
Table 48. Timer A input (external trigger input in one-shot timer mode)
Table 49. Timer A input (external trigger input in pulse width modulation mode)
Table 50. Timer A input (up/down input in event counter mode)
Standard
Max.
ns
TAi
IN
input LOW pulse width
t
w(TAL)
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
ns
ns
TAi
IN
input HIGH pulse width
t
w(TAH)
ParameterSymbol
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
Symbol Parameter
t
c(TA)
TAi
IN
input cycle time
TAi
OUT
input cycle time
TAi
OUT
input HIGH pulse width
TAi
OUT
input LOW pulse width
TAi
OUT
input setup time
TAi
OUT
input hold time
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
40
100
40
400
200
200
200
100
100
100
100
2000
1000
1000
400
400
145
Timing (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 52. Timer B input (pulse period measurement mode)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 51. Timer B input (counter input in event counter mode)
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBi
IN
input cycle time (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input LOW pulse width (counted on one edge)
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ParameterSymbol Unit
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
t
c(TB)
t
w(TBH)
Symbol Parameter Unit
t
w(TBL)
ns
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(TB)
Symbol Parameter Unit
t
w(TBL)
ns
t
w(TBH)
TBi
IN
input cycle time
TBi
IN
input HIGH pulse width
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
w(INH)
t
w(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
t
c(CK)
t
w(CKH)
t
w(CKL)
ParameterSymbol Unit
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
TxDi hold time
RxDi input setup time
TxDi output delay time
t
h(C-D)
RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
250
250
200
100
100
0
30
90
80
µs
ns
ns
ns
Standard
Max.Min.
Serial I/O clock input cycle time
Serial I/O clock input HIGH pulse width
Serial I/O clock input LOW pulse width
t
c(SCLK)
t
wH(SCLK)
t
wL(SCLK)
ParameterSymbol Unit
t
su(SCLK-SIN)
Serial I/O input setup time
t
h(SCLK-SIN)
Serial I/O input hold time
0.95
400
200
200
ns
400
Table 53. Timer B input (pulse width measurement mode)
Table 54. Serial I/O
_______
Table 55. External interrupt INTi inputs
Table 56. Automatic transfer serial I/O
146
Timing (VCC=5V)
VCC=5V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
t
su(D-C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLK
i
TxD
i
RxD
i
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
INT
i
input
t
d(C-Q)
t
h(C-D)
t
h(C-Q)
t
h(TIN-UP)
t
su(UP-TIN)
TAi
IN
input
(When count on falling edge is selected)
TAi
IN
input
(When count on rising edge is selected)
TAi
OUT
input
(Up/down input)
S
OUT
S
IN
S
CLK
0.2V
CC
t
d(SCLK-SOUT)
0.2V
CC
0.8V
CC
0.8V
CC
t
SU(SiN-SCLK)
t
h(SCLK-SiN)
t
V(SCLK-SOUT)
t
WL(SCLK)
t
WH(SCLK)
tf
(SCLK)
t
C(SCLK)
t
r
147
Electrical characteristics(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 57.
Electrical characteristics (referenced to V
CC
= 3V, V
SS
= 0V at Ta = 25
o
C,
f(X
IN
) =5MH
Z
unless otherwise specified)
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
S
y
m
b
o
l
V
O
H
V
O
H
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
H
V
O
L
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
i
n
p
u
t
c
u
r
r
e
n
t
I
I
L
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
S
t
a
n
d
a
r
d
T
y
p
.U
n
i
t
M
e
a
s
u
r
i
n
g
c
o
n
d
i
t
i
o
n
V
V
V
X
O
U
T
2
.
5
2
.
5
V0
.
5
µ
A
M
i
n
.M
a
x
.
1
.
5
P
a
r
a
m
e
t
e
r
I
O
H
=
-
1
8
m
A
I
O
H
=
-
0
.
1
m
A
I
O
H
=
-
1
m
A
I
O
H
=
-
5
0
µ
A
I
O
L
=
1
m
A
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
I
=
0
V
-
4
.
0
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
L
H
y
s
t
e
r
e
s
i
s
H
y
s
t
e
r
e
s
i
s
H
I
G
H
i
n
p
u
t
c
u
r
r
e
n
t
I
I
H
V
T
+
-
V
T
-
V
T
+
-
V
T
-
V
X
O
U
T
0
.
5
0
.
5
0
.
20
.
8V
0
.
21
.
8V
4
.
0µ
A
I
O
L
=
0
.
1
m
A
I
O
L
=
5
0
µ
A
R
E
S
E
T
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,V
I
=
3
V
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
T
A
0
I
N
t
o
T
A
4
I
N
,
T
B
0
I
N
t
o
T
B
2
I
N
,
C
L
K
0
,
C
L
K
1
,
S
R
D
Y
2
I
N
,
S
B
S
Y
2
I
N
,
I
N
T
0
t
o
I
N
T
5
,
C
T
S
0
,
C
T
S
1
,
S
I
N
2
,
S
C
L
K
2
1
,
S
C
L
K
2
2
I
I
H
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
(
N
o
t
e
1
)V
I
=
3
V4
.
0µ
A
I
I
L
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
(
N
o
t
e
1
)V
I
=
0
V
-
4
.
0µ
A
R
P
U
L
L
U
P
P
u
l
l
-
u
p
r
e
s
i
s
t
a
n
c
eP
4
4
t
o
P
4
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
I
O
H
=
-
5
m
A2
.
5
6
6
.
01
2
0
.
05
0
0
.
0k
Ω
2
.
5
R
T
S
0
,
R
T
S
1
R
f
X
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
e
X
I
N
3
.
0
R
P
U
L
L
D
P
u
l
l
-
d
o
w
n
r
e
s
i
s
t
a
n
c
eP
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
E
E
=
V
C
C
-
4
8
V
,
V
O
L
=
V
C
C
O
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
s
“
o
f
f
”
I
L
E
A
K
O
u
t
p
u
t
l
e
a
k
c
u
r
r
e
n
tP
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
4
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
V
E
E
=
V
C
C
-
4
8
V
,
V
O
L
=
V
C
C
-
4
8
V
O
u
t
p
u
t
t
r
a
n
s
i
s
t
o
r
s
“
o
f
f
”
6
88
01
2
0k
Ω
(
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
3
i
n
o
p
t
i
o
n
s
p
e
c
i
f
y
)
-
1
0µ
A
V
I
=
0
V
V
R
A
M
R
A
M
r
e
t
e
n
t
i
o
n
v
o
l
t
a
g
e
I
c
cP
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
(
N
o
t
e
3
)
W
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d2
.
0V
S
q
u
a
r
e
w
a
v
e
,
n
o
d
i
v
i
s
i
o
n
1
.
0µ
A
m
A
2
0
.
0
T
h
e
o
u
t
p
u
t
p
i
n
s
a
r
e
o
p
e
n
a
n
d
o
t
h
e
r
p
i
n
s
a
r
e
V
S
S
6
.
01
5
.
0
f
(
X
I
N
)
=
5
M
H
z
f
(
X
C
I
N
)
=
3
2
k
H
z
2
.
8
µ
A
S
q
u
a
r
e
w
a
v
e
,
8
d
i
v
i
s
i
o
n
f
(
X
I
N
)
=
5
M
H
z1
.
6m
A
f
(
X
C
I
N
)
=
3
2
k
H
z
0
.
9
µ
A
M
Ω
R
f
X
C
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
e
X
C
I
N
1
0
.
0M
Ω
S
q
u
a
r
e
w
a
v
e
f
(
X
C
I
N
)
=
3
2
k
H
z5
0
.
0µ
A
T
a
=
8
5
w
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
T
a
=
2
5
w
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
C
C
W
h
e
n
a
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
.
O
s
c
i
l
l
a
t
i
o
n
c
a
p
a
c
i
t
y
H
i
g
h
(
N
o
t
e
2
)
W
h
e
n
a
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
.
O
s
c
i
l
l
a
t
i
o
n
c
a
p
a
c
i
t
y
L
o
w
(
N
o
t
e
2
)
Note 1: Except when reading ports P3, P40 to P43.
Note 2: With one timer operated using fC32.
Note 3: This contains an electric current to flow into AVCC pin.
148
Electrical characteristics(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 58. A-D conversion characteristics (referenced to V
CC
= AV
CC
= V
REF
= 3V, Vss = AV
SS
= 0V
at Ta = 25
o
C, f(X
IN
) = 5MH
Z
unless otherwise specified)
Table 59. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
at Ta = 25oC, f(XIN) = 5MHZ unless otherwise specified)
R
LADDER
Ladder resistance
Reference voltage
Analog input voltage
V
V
IA
V
REF
V0
2.7
10
V
CC
V
REF
40
Conversion time
(8bit) 14.0t
CONV
V
REF
= V
CC
Standard
Min. Typ. Max
Resolution
Absolute accuracy
Bits
LSB
V
REF
= V
CC
±2
10
Symbol Parameter Measuring condition Unit
V
REF
= V
CC
= 3V, φ
AD
= f(X
IN
)/2
Sample & hold function not available (8 bit)
kΩ
µs
Standard
Min. Typ. Max
t
su
R
O
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
mAI
VREF
1.0
1.0
8
3
Symbol Parameter Measuring condition Unit
20104
(Note) kΩ
µs
Note:
This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “00
16
”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
149
Timing(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 60. External clock input
ns
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
r
t
f
Max.Min.
ParameterSymbol Unit
Standard
External clock rise time
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
200
85
85 18
18
150
Timing(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 61. Timer A input (counter input in event counter mode)
Table 62. Timer A input (gating input in timer mode)
Table 63. Timer A input (external trigger input in one-shot timer mode)
Table 64. Timer A input (external trigger input in pulse width modulation mode)
Table 65. Timer A input (up/down input in event counter mode)
Standard
Max.Min. UnitParameterSymbol
nst
w(TAL)
TAi
IN
input LOW pulse width 60
nst
c(TA)
TAi
IN
input cycle time 150 nst
w(TAH)
TAi
IN
input HIGH pulse width 60
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 600 nst
w(TAH)
TAi
IN
input HIGH pulse width 300 nst
w(TAL)
TAi
IN
input LOW pulse width 300
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 300 nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
c(UP)
TAi
OUT
input cycle time 3000 nst
w(UPH)
TAi
OUT
input HIGH pulse width 1500 nst
w(UPL)
TAi
OUT
input LOW pulse width 1500 nst
su(UP-TIN)
TAi
OUT
input setup time 600 nst
h(TIN-UP)
TAi
OUT
input hold time 600
151
Timing(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 67. Timer B input (pulse period measurement mode)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 66. Timer B input (counter input in event counter mode)
Table 68. Timer B input (pulse width measurement mode)
Table 69. Serial I/O
_______
Table 70. External interrupt INTi inputs
Table 71. Automatic transfer serial I/O
Standard
Max.Min.
ParameterSymbol Unit
nstc(TB) TBiIN input cycle time (counted on one edge) 150 nstw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 nstw(TBL) TBiIN input LOW pulse width (counted on one edge) 60
tw(TBH) nsTBiIN input HIGH pulse width (counted on both edges) 160
tw(TBL) nsTBiIN input LOW pulse width (counted on both edges) 160
tc(TB) nsTBiIN input cycle time (counted on both edges) 300
Standard
Max.Min.
ParameterSymbol Unit
nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300
tw(TBL) nsTBiIN input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300
tw(TBL) nsTBiIN input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nstw(INH) INTi input HIGH pulse width 380 nstw(INL) INTi input LOW pulse width 380
Standard
Max.Min.
ParameterSymbol Unit
nstc(CK) CLKi input cycle time 300 nstw(CKH) CLKi input HIGH pulse width 150 nstw(CKL) CLKi input LOW pulse width 150
th(C-Q) nsTxDi hold time 0
tsu(D-C) nsRxDi input setup time 50
th(C-D) nsRxDi input hold time 90
td(C-Q) nsTxDi output delay time 160
µs
ns
ns
ns
Standard
Max.Min.
Serial I/O clock input cycle time
Serial I/O clock input HIGH pulse width
Serial I/O clock input LOW pulse width
tc(SCLK)
twH(SCLK)
twL(SCLK)
ParameterSymbol Unit
tsu(SCLK-SIN) Serial I/O input setup time
th(SCLK-SIN) Serial I/O input hold time
TBD
ns
TBD
TBD
TBD
TBD
152
Timing(VCC=3V, only mask ROM version)
VCC=3V
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
t
su(D-C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLK
i
TxD
i
RxD
i
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
INT
i
input
t
d(C-Q)
t
h(C-D)
t
h(C-Q)
t
h(T
IN
-UP)
t
su(UP-T
IN
)
TAi
IN
input
(When count on falling edge is selected)
TAi
IN
input
(When count on rising edge is selected)
TAi
OUT
input
(Up/down input)
S
OUT
S
IN
S
CLK
0.2V
CC
t
d(SCLK-SOUT)
0.2V
CC
0.8V
CC
0.8V
CC
t
SU(SiN-SCLK)
t
h(SCLK-SiN)
t
V(SCLK-SOUT)
t
WL(SCLK)
t
WH(SCLK)
tf
(SCLK)
t
C(SCLK)
t
r
153
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Item
Power supply voltage
Program/erase voltage
Flash memory operation mode
Erase block
division
Program method
Erase method
Program/erase control method
Number of commands
Program/erase count
ROM code protect
Performance
4.0V to 5.5 V (f(X
IN
)=10MHz)
V
PP
=12V ± 5% (f(X
IN
)=10MHz)
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
See Figure 1.AA.3.
One division (3.5 K bytes) (Note)
In units of byte
Collective erase / block erase
Program/erase control by software command
6 commands
100 times
Standard serial I/O mode is supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
User ROM area
Boot ROM area
V
CC
=5V ± 10% (f(X
IN
)=10MHz)
Table 72. Outline Performance of the M30218 group (flash memory version)
Outline Performance
Table 72 shows the outline performance of the M30218 group (flash memory version).
154
Description
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Flash Memory
The M30218 group (flash memory version) contains the NOR type of flash memory that requires a high-
voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device
operation. For this flash memory, three flash memory modes are available in which to read, program, and
erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro-
cessing Unit (CPU). Each mode is detailed in the pages to follow.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Figure 125. Block diagram of flash memory version
SFR
RAM
SFR
RAM
SFR
RAM
User ROM
area
00000
16
00400
16
YYYYY
16
DF000
16
XXXXX
16
FFFFF
16
Microcomputer mode Parallel I/O mode CPU rewrite mode
Standard serial I/O mode
Boot ROM
area
(3.5K bytes)
User ROM
area User ROM
area
Boot ROM
area
(3.5K bytes)
DFDFF
16
E0000
16
E8000
16
F0000
16
F8000
16
FFFFF
16
Block 3
Block 2
Block 1
Block 0
Type No.
XXXXX
16
YYYYY
16
M30218FC E0000
16
033FF
16
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
155
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by
reading or writing to the flash memory control register and flash command register. Figure 126, Figure 127
show the flash memory control register, and flash command register respectively.
Also, in CPU rewrite mode, the CNVSS pin is used as the V PP power supply pin. Apply the power supply
voltage, VPPH, from an external source to this pin.
In CPU rewrite mode, only the user ROM area shown in Figure 128 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to internal RAM before it can be executed.
Flash memory control register 0
Symbol Address When reset
FCON0 03B4
16
00100000
2
WR
b7 b6 b5 b4 b3 b2 b1 b0
CPU rewrite mode
select bit
FCON00
Bit symbol
Bit name Function
RW
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
This bit can not write. The value, if
read, turns out to be indeterminate.
Reserved bit
CPU rewrite mode
monitor flag 0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Must always be set to "0".
FCON02
AA
AA
AA
A
AA
A
Reserved bit
0
000: Block 0 program/erase
001: Block 1 program/erase
010: Block 2 program/erase
011: Block 3 program/erase
110: Block 0 to 3 erase
111: Inhibit
0
AA
AA
A
A
Must always be set to "0".
Reserved bit
Flash memory control register 1
Symbol Address When reset
FCON1 03B5
16
XXXXXX00
2
WR
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name Function
RW
0
AA
0
Reserved bit
A
Nothing is assigned. In an attempt to write these bits, write "0". The
value, if read, turns out to be indeterminate.
Must always be set to "0".
A
AA
A
AA
A
FCON04
FCON05
FCON06
b6b5b4
Erase / program
area select bit
Flash command register
Symbol Address When reset
FCMD 03B616 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
Writing of software command
<Software command name> <Command code>
•Read command "0016"
•Program command "4016"
•Program verify command "C016"
•Erase command "2016"+"2016"
•Erase verify command "A016"
•Reset command "FF16"+"FF6"
Function RW
A
Figure 126. Flash memory control register
Figure 127. Flash command register
156
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 125 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low
(VSS). In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU
starts operating using the control program in the boot ROM area. This mode is called the “boot” mode.
The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed on-
board by writing commands from the CPU to the flash memory control register (addresses 03B4 16,
03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot
ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom-
plished, a CPU write control program must be written into the boot ROM area in parallel input/output
mode. The following shows a CPU rewrite mode operation procedure.
<Start procedure (Note 1)>
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P46 pin for reset release. Or the user can
jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU
write control program. In this case, set the CPU write mode select bit of the flash memory control
register to “1” before applying VPPH to the CNVSS/VPP pin.
(2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump
to this control program in RAM. (The operations described below are controlled by this program.)
(3) Set the CPU rewrite mode select bit to “1”.
(4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled.
(5) Execute operation on the flash memory by writing software commands to the flash command regis-
ter.
Note 1: In addition to the above, various other operations need to be performed, such as for entering the
data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and
writing to the watchdog timer.
<Clearing procedure>
(1) Apply VSS to the CNVSS/VPP pin.
(2) Set the CPU rewrite mode select bit to “0”.
157
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During erase/program mode, set BCLK to one of the following frequencies by changing the divide
ratio:
5 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)(Note 1)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
Note 1: Internal access wait state can be set in CPU rewrite mode. In this time, the following function is
only used.
• CPU, ROM, RAM, timer, UART, SI/O2(non-automatic transfer), port
In case of setting internal access wait state, refer to the following explain (software wait).
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note 2).
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus
cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit.
Table 73 shows the software wait and bus cycles. Figure 128 shows example bus timing when using
software waits.
Note 2: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area Wait bit Bus cycle
1 2 BCLK cycles
SFR
Internal
ROM/RAM 0 1 BCLK cycle
Invalid 2 BCLK cycles
Table 73. Software waits and bus cycles
158
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 128. Typical bus timings using software wait
Output Input
Address Address
Bus cycle
< Internal bus (with wait) >
BCLK
Read signal
Write signal
Data bus
Address bus
BCLK
Read signal
Write signal
Address bus Address Address
Bus cycle
< Internal bus (no wait) >
Output
Data bus
Input
159
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Command
Program verify
Read
Program
03B616
First bus cycle Second bus cycle
0016
4016
C016
Write
Write
Write
Program
address
Write
Read
Erase verify A016
Write Verify
address Verify
data
Read
Erase 2016
Write 03B616 2016
Write
Verify
address
Reset FF16
Write
Mode Address Mode Address Data
(D0 to D7)
Data
(D0 to D7)
03B616
03B616
03B616
03B616
03B616
Program
data
Verify
data
FF16
Write 03B616
Software Commands
Table 74 lists the software commands available with the M30218 group (flash memory version).
When CPU rewrite mode is enabled, write software commands to the flash command register to specify
the operation to erase or program.
The content of each software command is explained below.
Table 74. List of Software Commands (CPU Rewrite Mode)
Read Command (0016)
The read mode is entered by writing the command code “0016” to the flash command register in the
first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of
the specified address is read out at the data bus (D0–D7), 8 bits at a time.
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” to the flash command register in
the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g.,
STE instruction) in the second bus cycle, the flash memory control circuit executes the program op-
eration. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user
go to the next processing.
During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 129 for an example of a programming flowchart.
160
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” to the flash command
register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte
data from the address to be verified (the previously programmed address) in the second bus cycle,
the content that has actually been written to the address is read out from the memory.
The CPU compares this read data with the data that it previously wrote to the address using the
program command. If the compared data do not match, the user need to execute the program and
program-verify operations one more time.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” to the
flash command register in the first bus cycle and the same command code to the flash command
register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20
ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands. During erase operation, the
watchdog timer remains idle, with the value “7FFF16 set in it.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure 129 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” to the flash command register
in the first bus cycle. When the user execute an instruction to read byte data from the address to be
verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out.
The CPU must sequentially erase-verify memory contents one address at a time, over the entire area
erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop
erase-verify at that point and execute erase and erase-verify operations one more time.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
161
CPU Rewrite Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Start
Address = first location
Loop counter : X=0
Write program command Write : 40
16
Duration = 20 µs
Duration = 6 µs
X=25 ?
Verify
OK ?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Write program data/
address
Loop counter : X=X+1
Write program verify
command
Last
address ?
Next address ?
Write read command Write read command
Verify
OK ?
Write : Program data
Write : C0
16
Write : 00
16
Write:20
16
Duration = 6µs
X=1000 ?
Verify
OK?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Duration = 20ms
YES
NO
Start
All bytes =
"00
16
"?
Program all bytes =
"00
16
"
Address = First address
Loop counter X=0
Write erase command
Write erase command
Loop counter X=X+1
Write erase verify
command/address
Verify
OK?
Last
address?
Next address
Write read command Write read command
Write:20
16
Write:A0
16
Write:00
16
Read:
expect value=FF
16
Figure 129. Program and erase execution flowchart in the CPU rewrite mode
Program Erase
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice to the flash command register, write
command code “FF16” to the flash command register in the first bus cycle and the same command
code to the flash command register again in the second bus cycle. The program command or erase
command is disabled, with the flash memory placed in read mode.
162
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Pin Description
V
CC
,V
SS
Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin.
CNV
SS
Apply 12V ± 5 % to this pin.
RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
X
IN
Connect a ceramic resonator or crystal oscillator between X
IN
and
X
OUT
pins. To input an externally generated clock, input it to X
IN
pin
and open X
OUT
pin.
X
OUT
AV
CC
, AV
SS
V
REF
Connect AV
SS
to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
P0
0
to P0
7
Output exclusive use pin.
P1
0
to P1
7
Output exclusive use pin.
P2
0
to P2
7
Output exclusive use pin.
P3
0
to P3
7
Input "H" or "L" level signal or open.
P4
0
to P4
3
Input "H" or "L" level signal or open.
P4
4
Serial data output pin.
P4
5
P4
6
Serial clock input pin.
P4
7
P5
0
to P5
7
Output exclusive use pin.
Name
Power input
CNV
SS
Reset input
Clock input
Clock output
Analog power supply input
Reference voltage input
Output port P0
Output port P1
Output port P2
Input port P3
Input port P4
TxD output
SCLK input
BUSY output
Output port P5
I/O
I
I
I
O
I
O
O
O
I
I
I
I
O
O
RxD input Serial data input pin.
OBUSY signal output pin.
P6
0
to P6
7
Output exclusive use pin.
P7
0
to P7
7
Input "H" or "L" level signal or open.
Output port P6
Input port P7
O
I
P8
0
to P8
7
Input "H" or "L" level signal or open.
Input port P8 I
P9
0
to P9
7
Input "H" or "L" level signal or open.
Input port P9 I
P10
0
to P10
7
Input "H" or "L" level signal or open.
Input port P10 I
Pin functions (Flash memory standard serial I/O mode)
163
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 130. Pin connections for serial I/O mode (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M30218FCFP
P6
0
/FLD0
P6
1
/FLD1
P6
2
/FLD2
P6
3
/FLD3
P6
4
/FLD4
P6
5
/FLD5
P6
6
/FLD6
P6
7
/FLD7
P5
0
/FLD8
V
CC
X
IN
RESET
X
OUT
V
SS
CNV
SS
P8
6
/X
COUT
P8
7
/X
CIN
P9
0
/SRDY2
P7
6
/TA3
IN
/TA1
OUT
/CLK1
P7
7
/TA4
IN
/TA2
OUT
/CTS1/RTS1/CLKS1
P9
4
/S
OUT
2
P9
5
/SCLK21
P9
6
/DA1/SCLK22
P9
7
/DA0/CLK
OUT
/DIM
OUT
P9
2
/SSTB2
P9
3
/S
IN2
P7
3
/TA0
IN
/TA3
OUT
P7
2
/TB2
IN
P9
1
/SBUSY2
V
EE
P10
7
/AN7
P10
6
/AN6
P10
5
/AN5
P10
3
/AN3
P10
2
/AN2
P10
4
/AN4
P10
1
/AN1
AV
SS
P10
0
/AN0
V
REF
AV
CC
P5
1
/FLD9
P5
2
/FLD10
P5
3
/FLD11
P5
4
/FLD12
P5
5
/FLD13
P5
6
/FLD14
P5
7
/FLD15
P0
0
/FLD16
P0
1
/FLD17
P0
2
/FLD18
P0
3
/FLD19
P0
4
/FLD20
P0
5
/FLD21
P0
6
/FLD22
V
SS
P0
7
/FLD23
V
CC
P1
0
/FLD24
P1
1
/FLD25
P1
2
/FLD26
P1
3
/FLD27
P1
4
/FLD28
P1
5
/FLD29
P1
6
/FLD30
P1
7
/FLD31
P2
0
/FLD32
P2
1
/FLD33
P2
2
/FLD34
P2
3
/FLD35
P2
4
/FLD36
P2
5
/FLD37
P2
6
/FLD38
P2
7
/FLD39
P3
0
/FLD40
P3
1
/FLD41
P3
2
/FLD42
P3
3
/FLD43
P3
4
/FLD44
P3
5
/FLD45
P3
6
/FLD46
P3
7
/FLD47
P4
0
/FLD48
P4
1
/FLD49
P4
2
/FLD50
P4
3
/FLD51
P4
4
/T
X
D0/FLD52
P4
5
/R
X
D0/FLD53
P4
6
/CLK0/FLD54
P47/CTS0/RTS0/FLD55
P7
5
/TA2
IN
/TA0
OUT
/R
X
D1
P7
4
/TA1
IN
/TA4
OUT
/T
X
D1
P7
1
/TB1
IN
P7
0
/TB0
IN
P8
5
/INT5
P8
4
/INT4
P8
3
/INT3
P8
2
/INT2
P8
1
/INT1
P8
0
/INT0
Vss
Vcc
CNVss
Vss
Vcc
CNVss VppH
RESET
TxD
SCLK RxD
BUSY
RESET
Vss
Vcc
Mode setup method
Signal Value
V
SS
V
CC
Connect oscillator
circuit.
164
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
serial programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with VPPH at the CNVss pin. (For the normal microprocessor
mode, set CNVss to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figure 130 shows the pin connections for the standard serial I/O mode. Serial data I/O uses three UART0
pins: CLK0, RxD0, TxD0, and RTS0 (BUSY).
The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs
the CMOS signal. The RTS0 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure 125 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O
(UART0) . In reception, the software commands, addresses and program data are synchronized with the
rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD0 pin.
The TxD0 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the RTS0 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS0 (BUSY)
pin is “L” level.
Also, data in memory and the status register can be read after inputting a software command. It is pos-
sible to check flash memory operating status or whether a program or erase operation ended success-
fully or in error by reading the status register.
Software commands and the status register are explained here following.
165
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Software Commands
Table 75 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table 75. Software commands (Standard serial I/O mode)
Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte
1 Page read
2 Page program
3 Bclock ease
4 Erase all unlocked blocks
5 Read status register
6 Clear status register
7 Read lockbit status
8 ID check function
9 Download function
10 Version data output function
11 Boot area output function
Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is
transferred from the serial programmer to the flash memory microcomputer.
Note2: SRD refers to status register data. SRD1 refers to status register 1 data.
Note3: All commands can be accepted when the flash memory is totally blank.
When ID is
not verificate
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Acceptable
Not
acceptable
Version
data output
to 9th byte
Data
output to
259th byte
Data
output to
259th
byte
Data input
to 259th
byte
To ID7
Data
output
Data
input
ID1
To
required
number
of times
Version
data
output
Data
output
Data
output
Data
input
ID size
Data
input
Version
data
output
Data
output
Data
output
Data
input
D016
Lock bit
data
output
Address
(high)
Check-
sum
Version
data
output
Data
output
Address
(high)
Address
(high)
Address
(high)
SRD1
output
Address
(high)
Address
(middle)
Size
(high)
Version
data
output
Address
(high)
Address
(middle)
Address
(middle)
Address
(middle)
D016
SRD
output
Address
(middle)
Address
(low)
Size
(low)
Version
data
output
Address
(middle)
FF16
4116
2016
A716
7016
5016
7116
F516
FA16
FB16
FC16
1st byte
transfer
166
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
data0 data255
CLK0
RxD0
TxD0
RTS0(BUSY)
A
8
to
A
15
A
16
to
A
23
FF
16
SRD
output SRD1
output
CLK0
RxD0
TxD0
RTS0(BUSY)
70
16
Figure 131. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
Figure 132. Timing for reading the status register
167
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 133. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A
8
to A
15
and A
16
to A
23
in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, as write data (D
0
–D
7
) for the page (256 bytes) specified with addresses
A
8
to A
23
is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
CLK0
RxD0
TxD0
RTS0(BUSY)
5016
Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the RTS0 (BUSY) signal changes
from the “H” to the “L” level.
CLK0
RxD0
TxD0
RTS0(BUSY)
A
8
to
A
15
A
16
to
A
23
41
16
data0 data255
Figure 134. Timing for the page program
168
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Send the “2016” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify com-
mand code, the erase operation will start for the specified block in the flash memory. Write the
highest address of the specified block for addresses A16 to A23.
When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
Figure 135.Timing for block erasing
A
8
to
A
15
A
16
to
A
23
20
16
D0
16
CLK0
RxD0
TxD0
RTS0(BUSY)
169
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Send the “7116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the
highest address of the specified block for addresses A8 to A23.
The M30218 group (flash memory version) does not have the lock bit, so the read value is always
“1” (block unlock).
CLK0
RxD0
TxD0
RTS0(BUSY)
A8 to
A15 A16 to
A23
7116
DQ6
Figure 137. Timing for reading lock bit status
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify com-
mand code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the
RTS0
(BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
CLK0
RxD0
TxD0
RTS0(BUSY)
A7
16
D0
16
Figure 136. Timing for erasing all unlocked blocks
170
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
FA
16 Program
data Program
data
Data size (high)
Data size (low)
Check
sum
CLK0
RxD0
TxD0
RTS0(BUSY)
Figure 138. Timing for download
171
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
Figure 139. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
FB
16
'X'
'V' 'E' 'R'
CLK0
RxD0
TxD0
RTS0(BUSY)
data0 data255
CLK0
RxD0
TxD0
RTS0(BUSY)
A8 to
A15 A16 to
A23
FC16
Figure 140. Timing for boot area output
172
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A 15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
ID size ID1 ID7
CLK0
RxD0
TxD0
RTS0(BUSY)
F516 DF16 FF16 0F16
Figure 141. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code
written in the flash memory are compared to see if they match. If the codes do not match, the com-
mand sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is,
from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, and
0FFFF716 . Write a program into the flash memory, which already has the ID code set for these
addresses.
Reset vector
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
0FFFFF
16
to 0FFFFC
16
0FFFFB
16
to 0FFFF8
16
0FFFF7
16
to 0FFFF4
16
0FFFF3
16
to 0FFFF0
16
0FFFEF
16
to 0FFFEC
16
0FFFEB
16
to 0FFFE8
16
0FFFE7
16
to 0FFFE4
16
0FFFE3
16
to 0FFFE0
16
0FFFDF
16
to 0FFFDC
16
4 bytes
Address
Figure 142. ID code storage addresses
173
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 76 gives the definition of each status register bit. After clearing the reset, the status register outputs
“8016”.
Table 76. Status register (SRD)
Status Bit (SR7)
The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready)
is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to
“1” when the operation ends.
Erase Bit (SR5)
The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set
to “1”. When the erase status is cleared, it is set to “0”.
Program Bit (SR4)
The program bit reports the operating status of the auto write operation. If a write error occurs, it is set
to “1”. When the program status is cleared, it is set to “0”.
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status name
Status bit
Reserved
Erase bit
Program bit
Reserved
Reserved
Reserved
Reserved
Definition
"1" "0"
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Busy
-
Terminated normally
Terminated normally
-
-
-
-
174
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 77 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table 77. Status register 1 (SRD1)
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
SRD1 bits
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
SR9 (bit1)
SR8 (bit0)
Status name
Boot update completed bit
Reserved
Reserved
Checksum match bit
ID check completed bits
Data receive time out
Reserved
Definition
"1" "0"
Update completed
-
-
Match
00
01
10
11
Not update
-
-
Mismatch
Normal operation
-
Not verified
Verification mismatch
Reserved
Verified
Time out
-
175
Appendix Standard Serial I/O Mode
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example Circuit Application for The Standard Serial I/O Mode
The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary ac-
cording to programmer, therefore see the programmer manual for more information.
RTS0(BUSY)
CLK0
R
X
D0
T
X
D0
CNVss
Clock input
RTS output
Data input
Data output
M30218 Flash
memory version
(1) Control pins and external circuitry will vary according to programmer. For
more information, see the programmer manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are
switched via a switch.
V
PP
Figure 143. Example circuit application for the standard serial I/O mode
176
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
x – – 0.13
b
x
M
Chapter 2
Peripheral Functions Usage
178
Protect
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.1.2 Protect Operation
The following explains the protect operation. Figure 2.1.2 shows the set-up procedure.
(1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system
clock control register 0 and system clock control register 1 to be in write-enabled state.
(2) The contents of system clock control register 0 and that of system clock control register 1 are changed.
(3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock
control register 0 and system control register 1 to be in write-inhibited state.
(4) To change the contents of processor mode register 0 and that of processor mode register 1,
follow the same steps as in dealing with system clock control registers.
Operation
2.1.1 Overview
'Protect' is a function that causes a value held in a register to be unchanged even when a program runs
away. The following is an overview of the protect function:
(1) Registers affected by the protect function
The registers affected by the protect function are:
(a) System clock control registers 0, 1 (addresses 000616 and 000716)
(b) Processor mode registers 0, 1 (addresses 000416 and 000516)
The values in registers (1) through (2) cannot be changed in write-protect state. To change values in
the registers, put the individual registers in write-enabled state.
(2) Protect register
Figure 2.1.1 shows protect register.
2.1 Protect
Figure 2.1.1. Protect register
P
r
o
t
e
c
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
R
C
R0
0
0
A1
6X
X
X
X
X
0
0
02
B
i
t
n
a
m
eB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
0
:
W
r
i
t
e
-
i
n
h
i
b
i
t
e
d
1
:
W
r
i
t
e
-
e
n
a
b
l
e
d
P
R
C
1
P
R
C
0
E
n
a
b
l
e
s
w
r
i
t
i
n
g
t
o
p
r
o
c
e
s
s
o
r
m
o
d
e
r
e
g
i
s
t
e
r
s
0
a
n
d
1
(
a
d
d
r
e
s
s
e
s
0
0
0
41
6
a
n
d
0
0
0
51
6)
F
u
n
c
t
i
o
n
0
:
W
r
i
t
e
-
i
n
h
i
b
i
t
e
d
1
:
W
r
i
t
e
-
e
n
a
b
l
e
d
E
n
a
b
l
e
s
w
r
i
t
i
n
g
t
o
s
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
0
a
n
d
1
(
a
d
d
r
e
s
s
e
s
0
0
0
61
6
a
n
d
0
0
0
71
6)
WR
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
179
Protect
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.1.2. Set-up procedure for protect function
(1) Clearing the protect (set to write-enabled state)
Protect register [Address 000A
16
]
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
16
and 0007
16
)
1 : Write-enabled
b7 b0
1
(3) Setting the protect (set to write-inhibited state)
Protect register [Address 000A
16
]
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
16
and 0007
16
)
0 : Write-inhibited
b7 b0
0
Setting system clock control register i (i = 0, 1)(2)
180
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.2.1 Overview
The following is an overview for timer A, a 16-bit timer.
(1) Mode
Timer A operates in one of the four modes:
(a) Timer mode
In this mode, the internal count source is counted. Two functions can be selected: the pulse output
function that reverses output from a port every time an overflow occurs, or the gate function which
controls the count start/stop according to the input signal from a port.
• Timer mode operation .............................................................................................................. P186
• Timer mode, gate function operation........................................................................................ P188
• Timer mode, pulse output function operation ........................................................................... P190
(b) Event counter mode
This mode counts the pulses from the outside and the number of underflows in other timers. The
free-run type, in which nothing is reloaded from the reload register, can be selected when an under-
flow occurs. The pulse output function can also be selected. Please refer to the timer mode expla-
nation for details, as the operation is identical.
• Event counter mode operation ................................................................................................. P192
• Event counter mode, free run type operation ........................................................................... P194
Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count
or down count in the event counter mode, depending on the phase of the two input signals.
• Operation of the 2-phase pulse signal processing function in normal event counter mode ..... P196
• Operation of the 2-phase pulse signal processing function in 4-multiplication mode............... P198
(c) One-shot timer mode
In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can
be selected from the following 3 types: an external input signal, an overflow of the timer, or a software
trigger. The pulse output function can also be selected. Please refer to the timer mode explanation
for details, as the operation is identical.
• Operation in one-shot timer mode effected by software........................................................... P200
• Operation in one-shot timer mode effected by an external trigger ........................................... P202
(d) Pulse width modulation (PWM) mode
In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or
8-bit variable-period mode can be selected. The trigger for initiating output can also be selected.
Please refer to the one-shot timer mode explanation for details, as the operation is identical.
• 16-bit PWM mode operation..................................................................................................... P204
• 8-bit PWM mode operation....................................................................................................... P206
2.2 Timer A
181
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Count source
The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived
by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the
CPU's secondary clock by 32.
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be-
comes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate.
(5) Writing to the timer
To write to the timer register when a count is in progress, the value is written only to the reload register.
When writing to the timer register when a count is stopped, the value is written both to the reload
register and to the counter. Write a value in 16-bit units.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, pulses are output regardless of the direction register of the
relevant port. To input an external signal to the timer, set the direction register of the relevant port to
input.
(7) Pins related to timer A
(a) TA0IN, TA1IN, TA2IN, TA3IN, TA4IN Input pins to timer A.
(b)
TA0OUT, TA1OUT, TA2OUT, TA3OUT, TA4OUT
Output pins from timer A. They become input pins to
timer A when event counter mode is active.
(8) Registers related to timer A
Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show
timer A-related registers.
182
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.2. Timer A-related registers (1)
Figure 2.2.1. Memory map of timer A-related registers
0055
16
0056
16
0057
16
0058
16
0059
16
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0396
16
0397
16
0398
16
0399
16
039A
16
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Up-down flag (UDF)
Timer A3 (TA3)
Timer A4 (TA4)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
Timer A1 interrupt control register (TA1IC)
Timer A3 interrupt control register (TA3IC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
Timer A4 interrupt control register (TA4IC)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
183
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.3. Timer A-related registers (2)
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Symbol Address When reset
TA0 0387
16
,0386
16
Indeterminate
TA1 0389
16
,0388
16
Indeterminate
TA2 038B
16
,038A
16
Indeterminate
TA3 038D
16
,038C
16
Indeterminate
TA4 038F
16
,038E
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (Note)
WR
• Timer mode 0000
16
to FFFF
16
Counts an internal count source
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts pulses from an external source or timer overflow
• One-shot timer mode 0000
16
to FFFF
16
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
00
16
to FE
16
(Both high-order
and low-order
addresses)
0000
16
to FFFE
16
Note: Read and write data in 16-bit units.
184
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.4. Timer A-related registers (3)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address When reset
UDF 0384
16
00
16
TA4P
TA3P
TA2P
Up/down flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0382
16
00X00000
2
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TA0TGL
TA0TGH
0 0 : Input on TA0
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
When selecting the TAi
IN
(i = 0–4) pin, TAi
OUT
(i = 0–4) pin which is
assigned to the same pin cannot be used.
WR
1 : Timer start
When read, the value is “0”
185
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.5. Timer A-related registers (4)
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
TA1TGL
Symbol Address When reset
TRGSR 0383
16
00
16
Timer A1 event/trigger
select bit 0 0 :
Input on TA1
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 :
Input on TA2
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 :
Input on TA3
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 :
Input on TA4
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
WR
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note: Set the corresponding port direction register to “0”.
When selecting the TAi
IN
(i = 0–4) pin, TAi
OUT
(i = 0–4) pin which is
assigned to the same pin cannot be used.
186
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are
described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure.
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
2.2.2 Operation of Timer A (timer mode)
Table 2.2.1. Choosed functions
Figure 2.2.6. Operation timing of timer mode
FFFF
16
n
0000
16
Time
Start count again
Count start flag
Timer Ai interrupt
request bit
“1”
“1”
Counter content (hex)
n = reload register content
Set to “1” by software
“0”
“0”
Set to “1” by software
Cleared to “0” by
software
Cleared to “0” when interrupt request is accepted, or cleared by software
(1) Start count (2) Underflow (3) Stop count
Item
Count source
Pulse output function
Gate function
Set-up
O
O
O
Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
No pulses output
Pulses output
No gate function
Performs count only for the period in which the TAi
IN
pin is at “L” level
Performs count only for the period in which the TAi
IN
pin is at “H” level
187
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.7. Set-up procedure of timer mode
Setting divide ratio
Can be set to 000016 to FFFF16
b7 b0
(b15) (b8)b7 b0 Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16]TA3
Timer A4 register [Address 038F16, 038E16] TA4
Start count
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Setting count start flag
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Selecting timer mode and functions
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
Selection of timer mode
b7 b0
00000
0 (Must always be “0” in timer mode)
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6 Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6 Count
source 100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
Gate function select bit
0 0 :
0 1 :
b4 b3 Gate function not available (TAiIN pin is a normal port pin)
188
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.2.3 Operation of Timer A (timer mode, gate function selected)
Figure 2.2.8. Operation timing of timer mode, gate function selected
In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are
described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure.
Table 2.2.2. Choosed functions
(1) When the count start flag is set to “1” and the TAiIN pin inputs at “H” level, the counter per-
forms a down count on the count source.
(2) When the TAiIN pin inputs at “L” level, the counter holds its value and stops.
(3) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
• Make the pulse width of the signal input to the TAiIN pin not less than two cycles of the count
source.
Operation
Note
FFFF
16
n
0000
16
Time
Count start flag
Timer Ai interrupt
request bit
“1”
“1”
Counter content (hex)
n = reload register content
TAi
IN
pin
input signal
(2) Stop count
“0”
“0”
Set to “1” by software
“H”
“L”
(4) Stop count
(1) Start count
Cleared to “0” when interrupt request is accepted, or cleared by software
(3) Underflow
Set to “1” by software
Cleared to “0” by
software
Start count again.
Item
Count source
Pulse output function
Gate function
Set-up
O
O
O
Internal count source(f
1
/ f
8
/ f
32
/ fc
32
)
No pulses output
Pulses output
No gate function
Performs count only for the period in which the TAi
IN
pin is at “L” level
Performs count only for the period in which the TAi
IN
pin is at “H” level
189
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.9. Set-up procedure of timer mode, gate function selected
Setting divide ratio
Can be set to 0000
16
to FFFF
16
b7 b0
(b15) (b8)b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
]TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Pulse output function select bit
0 : Pulse is not output (TA
iOUT
pin is a normal port pin)
Selecting timer mode and functions
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
Gate function select bit
1 1 : Timer counts only when TA
iIN
pin is held “H” (Note)
b4 b3
Selection of timer mode
b7 b0
0000
0 (Must always be “0” in timer mode)
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note: Set the corresponding port direction register to “0”.
11
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by
dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Start count
190
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.10. Operation timing of timer mode, pulse output function selected
2.2.4 Operation of Timer A (timer mode, pulse output function selected)
In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are
described below. Figure 2.2.10 shows the operation timing, and Figure 2.2.11 shows the set-up proce-
dure.
Table 2.2.3. Choosed functions
(1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”. Also, the output polarity of the
TAiOUT pin reverses.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
Operation
FFFF
16
n
0000
16
Time
Count start flag
Timer Ai interrupt
request bit
“1”
“1”
Counter content (hex)
n = reload register content
Pulse output from
TAi
OUT
pin “H”
“0”
“L”
“0”
Set to “1” by software Set to “1” by software
Cleared to “0” by
software
(3) Stop count
Cleared to “0” when interrupt request is accepted, or cleared by software
(1) Start count (2) Underflow
Start count again
Item
Count source
Pulse output function
Gate function
Set-up
O
O
O
Internal count source(f
1
/ f
8
/ f
32
/ fc
32
)
No pulses output
Pulses output
No gate function
Performs count only for the period in which the TAi
IN
pin is at “L” level
Performs count only for the period in which the TAi
IN
pin is at “H” level
191
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected
Setting divide ratio
Can be set to 0000
16
to FFFF
16
b7 b0
(b15) (b8) b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
] TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Start count
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by
dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Pulse output function select bit
1 : Pulse is output (Note) (TA
iOUT
pin is a pulse output pin)
Selecting timer mode and functions
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
Selection of timer mode
b7 b0
00010
0 (Must always be “0” in timer mode)
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note: The settings of the corresponding port register and port direction register are invalid.
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Gate function select bit
0 0 :
0 1 :
b4 b3
Gate function not available (TAi
IN
pin is a normal port pin)
192
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.12. Operation timing of event counter mode, reload type selected
2.2.5 Operation of Timer A (event counter mode, reload type selected)
In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items
are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up
procedure.
Note: j = i – 1, but j = 4 when i = 0.
(1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
(5) If an overflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
Operation
Table 2.2.4. Choosed functions
FFFF
16
n
0000
16
Time
Counter content (hex)
n = reload register content
(1) Start count
Count start flag “1”
Set to “1” by software
“0”
Timer Ai interrupt
request bit “1”
“0”
Up/down flag “1”
“0”
Set to “1” by software
Set to “1” by software
(5) Overflow
Cleared to “0” when interrupt request is accepted, or cleared by software
Start count again
AAAA
(2) Underflow
AAAA
AAAA
(3) Switch count
Cleared to “0” by
software
(4) Stop count
Item ItemSet-up Set-up
Count source Input signal to TAi
IN
(counting falling edges)
Input signal to TAi
IN
(counting rising edges)
Timer overflow
(TB2/TAj overflow)
Count operation type Reload type
Free-run type
Factor for switching
between up and
down
Content of up/down flag
Input signal to TAi
OUT
Pulse output function No pulses output
Pulses output
O
O
O
O
193
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.13. Set-up procedure of event counter mode, reload type selected
Selecting event counter mode and functions
b7 b0
Pulse output function select bit
0 : Pulse is not output (TA
iOUT
pin is a normal port pin)
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
Up/down switching cause select bit
0 : Up/down flag's content
Selection of event counter mode
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Count operation type select bit
0 : Reload type
0 (Must always be “0” in event counter mode)
Count polarity select bit
0 : Counts external signal's falling edge
0100000
b7 b0
000
Up/down flag [Address 0384
16
]
UDF
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the 2-phase pulse signal processing function, set the select bit to “0”.
Setting one-shot start flag and trigger select register
Trigger select register [Address 0383
16
]
TRGSR
One-shot start flag [Address 0382
16
]
ONSF
Timer A0 event/trigger select bit
0 0 :
Input on TA0
IN
is selected (Note)
b7 b6
b7 b0 b7 b0
Timer A1 event/trigger select bit
0 0 :
Input on TA1
IN
is selected (Note)
b1 b0
Timer A2 event/trigger select bit
0 0 :
Input on TA2
IN
is selected (Note)
b3 b2
Timer A3 event/trigger select bit
0 0 :
Input on TA3
IN
is selected (Note)
b5 b4
Timer A4 event/trigger select bit
0 0 :
Input on TA4
IN
is selected (Note)
b7 b6
Note: Set the corresponding port direction register to “0”.
Setting divide ratio
Can be set to 0000
16
to FFFF
16
b7 b0
(b15) (b8) b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
]TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Setting up/down flag
194
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.14. Operation timing of event counter mode, free run type selected
2.2.6 Operation of Timer A (event counter mode, free run type selected)
In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items
are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up
procedure.
Note: j = i – 1, but j = 4 when i = 0
(1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
Table 2.2.5. Choosed functions
Operation
FFFF
16
n
0000
16
Time
Counter content (hex)
n = reload register content
(1) Start count
Count start flag “1”
“0”
Timer Ai interrupt
request bit “1”
Cleared to “0” when interrupt request is accepted, or cleared by software
“0”
Up/down flag “1”
“0”
Set to “1” by software
(2) Underflow (3) Switch count (4) Overflow
Set to “1” by software
Item ItemSet-up Set-up
Count source Input signal to TAi
IN
(counting falling edges)
Input signal to TAi
IN
(counting rising edges)
Timer overflow
(TB2/TAj overflow)
Count operation type Reload type
Free-run type
Factor for switching
between up and
down
Content of up/down flag
Input signal to TAi
OUT
Pulse output function No pulses output
Pulses output
O
O
O
O
195
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.15. Set-up procedure of event counter mode, free run type selected
Setting divide ratio
Can be set to 000016 to FFFF16
b7 b0
(b15) (b8)b7 b0 Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16]TA3
Timer A4 register [Address 038F16, 038E16] TA4
Start count
Pulse output function select bit
0 : Pulse is not output (TAiOUT pin is a normal port pin)
Selecting event counter mode and functions
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
Up/down switching cause select bit
0 : Up/down flag's content
Selection of event counter mode
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Count operation type select bit
1 : Free-run type
0 (Must always be “0” in event counter mode)
Count polarity select bit
0 : Counts external signal's falling edge
b7 b0
0100001
b7 b0
000
Setting up/down flag
Up/down flag [Address 038416]
UDF
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the 2-phase pulse signal processing function, be sure to set the select bit to “0”.
Setting count start flag
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Setting one-shot start flag and trigger select register
b7 b0 One-shot start flag [Address 038216]
ONSF
Timer A0 event/trigger select bit
0 0 : Input on TA0IN is selected (Note)
b7 b6
b7 b0 Trigger select register [Address 038316]
TRGSR
Timer A1 event/trigger select bit
0 0 : Input on TA1IN is selected (Note)
b1 b0
Timer A2 event/trigger select bit
0 0 : Input on TA2IN is selected (Note)
b3 b2
Timer A3 event/trigger select bit
0 0 : Input on TA3IN is selected (Note)
b5 b4
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note)
b7 b6
Note: Set the corresponding port direction register to “0”.
196
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected
2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode,
normal mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and
Figure 2.2.17 shows the set-up procedure.
Table 2.2.6. Choosed functions
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4
multiplication processes.
(1) Setting the count start flag to “1” causes the counter to count effective edges of the count
source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
• The up count or down count conditions are as follows:
If a rising edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
an up count is performed.
If a falling edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
a down count is performed.
Operation
Note
0000
16
Count start flag
Timer Ai interrupt
request bit
“1”
“0”
“1”
“0”
FFFF
16
Counter content (hex) Input pulse
TAi
OUT
“H”
“L”
“H”
“L”
TAi
IN
Set to “1” by software
Cleared to “0” when interrupt request is accepted, or cleared by software
(1) Start count
(2) Underflow (3) Overflow
Time
Item
Count operation type
2-phase pulses
process (Note)
Set-up
O
O
Reload type
Free run type
Normal processing
4-multiplication processing
197
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected
Setting divide ratio
Can be set to 0000
16
to FFFF
16
b7 b0
(b15) (b8)b7 b0
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
]TA3
Start count
Selecting event counter mode and functions
0 (Must always be “0” when using two-phase pulse signal processing)
Timer Ai mode register (i= 2, 3) [Address 0398
16
, 0399
16
]
TAiMR (i= 2, 3)
1 (Must always be “1” when using two-phase pulse signal processing)
Selection of event counter mode
Two-phase pulse signal processing operation select bit
0 : Normal processing operation
Count operation type select bit
1 : Free-run type
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
b7 b0
01001001
Two-phase pulse signal processing select bit
b7 b0
Up/down flag [Address 0384
16
]
UDF
Timer A2 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A2 count start flag
Timer A3 count start flag
b7 b0
198
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,
multiply-by-4 mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and
Figure 2.2.19 shows the set-up procedure.
Table 2.2.7. Choosed functions
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4-
multiplication processes.
(1)
Setting the count start flag to “1” causes the counter to count effective edges of the count source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
• The up count or down count conditions are as follows:
Operation
Note
Table 2.2.8. The up count or down count conditions
Time
Set to “1” by software
000016
Count start flag
Timer Ai interrupt
request bit
“1”
“0”
“1”
“0”
FFFF16
Counter content (hex) Input pulse
TAiOUT “H”
“L”
“H”
“L”
TAiIN
(1) Start count
(2) Underflow (3) Overflow
Cleared to “0” when interrupt request is accepted, or cleared by software
Item ItemSet-up Set-up
Count operation type Reload type
Free run typeOProcessing 2 phase
pulses (Note) O
Normal processing
4-multiplication processing
Up count
Input signal to the
TAi
OUT
pin Input signal to the
TAi
IN
pin
Down
count
Input signal to the
TAi
OUT
pin Input signal to the
TAi
IN
pin
“H” level
“L” level
Rising
Falling
Rising
Falling
“L” level
“H” level
“H” level
“L” level
Rising
Falling
Falling
Rising
“H” level
“L” level
199
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.19. Set-up procedure of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
Setting divide ratio
Can be set to 000016 to FFFF16
b7 b0
(b15) (b8)b7 b0 Timer A3 register [Address 038D16, 038C16]TA3
Timer A4 register [Address 038F16, 038E16] TA4
Start count
Selecting event counter mode and functions
0 (Must always be “0” when using two-phase pulse signal processing)
Timer Ai mode register (i= 3, 4) [Address 039916, 039A16]
TAiMR (i= 3, 4)
1 (Must always be “1” when using two-phase pulse signal processing)
Selection of event counter mode
Two-phase pulse signal processing operation select bit
1 : Multiply-by-4 processing operation
Count operation type select bit
1 : Free-run type
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
b7 b0
01001011
Two-phase pulse signal processing select bit
b7 b0 Up/down flag [address 038416]
UDF
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A4 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting count start flag
Count start flag [Address 038016]
TABSR
Timer A3 count start flag
Timer A4 count start flag
b7 b0
200
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.2.9 Operation of Timer A (one-shot timer mode)
Figure 2.2.20. Operation timing of one-shot mode
In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items
are described below. Figure 2.2.20 shows the operation timing, and Figure 2.2.21 shows the set-up
procedure.
Operation
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
(1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to
perform a down count on the count source. At this time, the TAiOUT pin outputs an “H” level.
(2) The instant the value of the counter becomes “0000 16”, the TAiOUT pin outputs an “L” level,
and the counter reloads the content of the reload register and stops counting. At this time, the
timer Ai interrupt request bit goes to “1”.
(3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload
register again and continues counting. The reload timing is in step with the next count source
input after the trigger.
(4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the
reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt
request bit goes to “1”.
Table 2.2.9. Choosed functions
Item
Count source
Pulse output function
Count start condition
Set-up
O
O
O
Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
No pulses output
Pulses output
External trigger input (falling edge of input signal to the TAi
IN
pin)
External trigger input (rising edge of input signal to the TAi
IN
pin)
Timer overflow (TB2/TAj/TAk overflow)
Writing “1” to the one-shot start flag
FFFF
16
n
0001
16
Timer Ai interrupt
request bit
Counter content (hex)
n = reload register content
Reload
One-shot pulse output
from TAi
OUT
pin “H” 1 / f
i
X (n)
“L”
Time
Reload
1 / f
i
X (n+1)
Write signal to
one-shot start flag
“1”
“0”
Count start flag “1”
“0”
(1) Start count
Cleared to “0” when interrupt request is accepted, or cleared by software
(2) Stop count
(3) Start count (4) Stop count
Start count
Reload
Set to “1” by software Cleared to “0” by software
201
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.21. Set-up procedure of one-shot mode
Pulse output function select bit
1 : Pulse is output
Selecting one-shot timer mode and functions
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
External trigger select bit
When internal is selected, this bit can be “1” or “0”
Selection of one-shot timer mode
b7 b0
10010
0 (Must always be “0” in one-shot timer mode)
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Trigger select bit
0 : When the one-shot start flag is set “1”
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6 Count
source 100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
Setting one-shot timer's time
Can be set to 0001
16
to FFFF
16
b7 b0
(b15) (b8)b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
] TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Setting one-shot start flag
One-shot start flag [Address 0382
16
]
ONSF
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
b7 b0
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Clearing timer Ai interrupt request bit
Timer Ai interrupt control register [Address 0055
16
to 0059
16
]
TAiIC (i=0 to 4)
Interrupt request bit
b7 b0
0
Refer to 'Precaution for Timer A (one-shot timer mode)'
202
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled
items are described below. Figure 2.2.22 shows the operation timing, and Figure 2.2.23 shows the set-up
procedure.
2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected)
Figure 2.2.22. Operation timing of one-shot mode, external trigger selected
Operation
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
(1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the
counter performs a down count on the count source. At this time, the TAiOUT pin output level
goes to “H” level.
(2) If the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the
counter reloads the content of the reload register and stops counting. At this time, the timer Ai
interrupt request bit goes to “1”.
(3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload
register again and continues counting. The reload timing is in step with the next count source
input after the trigger.
(4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the
reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt
request bit goes to “1”.
Table 2.2.10. Choosed functions
Item
Count source
Pulse output function
Count start condition
Set-up
O
O
O
Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
No pulses output
Pulses output
External trigger input (falling edge of input signal to the TAi
IN
pin)
External trigger input (rising edge of input signal to the TAi
IN
pin)
Timer overflow (TB2/TAj/TAk overflow)
Writing “1” to the one-shot start flag
FFFF
16
n
0001
16
Timer Ai interrupt
request bit
Counter content (hex)
n = reload register content
Reload
Reload
(4) Stop count
One-shot pulse output
from TAi
OUT
pin “H” 1 / fi X (n)
“L”
1 / fi X (n+1)
TAi
IN
pin
input signal “H”
“L”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
“0”
Count start flag “1”
“0”
(2) Stop count
(1) Start count (3) Start count
Time
Reload
Start count
Set to “1” by software
Trigger during count
Cleared to “0” by software
203
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected
Setting one-shot timer's time
Can be set to 0001
16
to FFFF
16
b7 b0
(b15) (b8)b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
] TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Pulse output function select bit
1 : Pulse is output
Selecting one-shot timer mode and functions
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
External trigger select bit
1 : Rising edge of TAi
IN
pin's input signal
Selection of one-shot timer mode
b7 b0
10111
0 (Must always be “0” in one-shot timer mode)
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Trigger select bit
1 : Selected by event/trigger select bit
0
Setting event/trigger select bit
Trigger select register [Address 0383
16
]
TRGSR
One-shot start flag [Address 0382
16
]
ONSF
Timer A0 event/trigger select bit
0 0 : Input on TA0
IN
is selected (Note)
b7 b6
b7 b0 b7 b0
Timer A1 event/trigger select bit
0 0 :
Input on TA1
IN
is selected (Note)
b1 b0
Timer A2 event/trigger select bit
0 0 :
Input on TA2
IN
is selected (Note)
b3 b2
Timer A3 event/trigger select bit
0 0 :
Input on TA3
IN
is selected (Note)
b5 b4
Timer A4 event/trigger select bit
0 0 :
Input on TA4
IN
is selected (Note)
b7 b6
Note: Set the corresponding port direction register to “0”.
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Clearing timer Ai interrupt request bit
Timer Ai interrupt control register [Address 0055
16
to 0059
16
]
TAiIC (i=0 to 4)
Interrupt request bit
b7 b0
0
Refer to 'Precaution for Timer A (one-shot timer mode)'
204
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the
circled items are described below. Figure 2.2.24 shows the operation timing, and Figure 2.2.25 shows the
set-up procedure.
2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)
Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Table 2.2.11. Choosed functions
(1)
If the TAi
IN
pin input level changes from “L” to “H” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAi
OUT
pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT outputs an “L” level.
• The period of PWM pulses becomes (216 – 1)/fi, and the “H” level pulse width becomes n/fi. If
the timer Ai register is set to “000016”, the pulse width modulator does not work, and the
TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fC32; n : value of the timer)
Operation
Note
Item
Count source
PWM mode
Count start condition
Set-up
O
O
O
Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
16-bit PWM
8-bit PWM
External trigger input (falling edge of input signal to the TAi
IN
pin)
External trigger input (rising edge of input signal to the TAi
IN
pin)
Timer overflow (TB2/TAj/TAk overflow)
Count source
TA
iIN
pin
input signal
PWM pulse output
from TA
iOUT
pin
Timer Ai interrupt
request bit
Count start flag
1 / f
i
X
(2 –1)
16
Conditions: Reload register = 0003
16
, external trigger (rising edge of TAi
IN
pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
“1”
“0”
Cleared to “0” when interrupt request is
accepted, or cleared by software
1 / f
i
X n
“1”
“0”
Set to “1” by software
(1) Start count
(2) Output level “H” to “L”
Note: n = 0000
16
to FFFE
16
(3) One period is complete
(4) Stop count
Cleared to “0”
by software
205
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected
Setting PWM pulse's “H” level width
Can be set to 0000
16
to FFFE
16
b7 b0
(b15) (b8)b7 b0
Timer A0 register [Address 0387
16
, 0386
16
] TA0
Timer A1 register [Address 0389
16
, 0388
16
] TA1
Timer A2 register [Address 038B
16
, 038A
16
] TA2
Timer A3 register [Address 038D
16
, 038C
16
] TA3
Timer A4 register [Address 038F
16
, 038E
16
] TA4
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Setting event/trigger select bit
One-shot start flag [Address 0382
16
]
ONSF
Timer A0 event/trigger select bit
0 0 :
Input on TA0
IN
is selected (Note 2)
b7 b6
b7 b0 b7 b0
Timer A1 event/trigger select bit
0 0 :
Input on TA1
IN
is selected (Note 2)
b1 b0
Timer A2 event/trigger select bit
0 0 :
Input on TA2
IN
is selected (Note 2)
b3 b2
Timer A3 event/trigger select bit
0 0 :
Input on TA3
IN
is selected (Note 2)
b5 b4
Timer A4 event/trigger select bit
0 0 :
Input on TA4
IN
is selected (Note 2)
b7 b6
Note 2: Set the corresponding port direction register to “0”.
Trigger select register [Address 0383
16
]
TRGSR
1 (Must always be “1” in PWM mode)
Selecting PWM mode and functions
Timer Ai mode register (i=0 to 4) [Address 0396
16
to 039A
16
]
TAiMR (i=0 to 4)
External trigger select bit
1 : Rising edge of TAi
IN
pin's input signal (Note 1)
Selection of PWM mode
b7 b0
11111
16/8-bit PWM mode select bit
0 : Functions as a 16-bit pulse width modulator
b7 b6
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
Trigger select bit
1 : Selected by event/trigger select register
0
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Note 1: Set the corresponding port direction
register to “0”.
Clearing timer Ai interrupt request bit
Timer Ai interrupt control register [Address 0055
16
to 0059
16
]
TAiIC (i=0 to 4)
Interrupt request bit
b7 b0
0
Refer to 'Precaution for Timer A (pulse width modulation mode)'
206
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)
Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected
In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the
circled items are described below. Figure 2.2.26 shows the operation timing, and Figure 2.2.27 shows the
set-up procedure.
Table 2.2.12. Choosed functions
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
(1)
If the TAi
IN
pin input level changes from “H” to “L” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAi
OUT
pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
• The period of PWM pulses becomes (m + 1) X (28 – 1) / fi, and the “H” level pulse width
becomes n X (m + 1) / fi. If “0016” is set in the eight higher-order bits of the timer Ai register, the
pulse width modulator does not work, and the TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fc32; n : value of the timer)
• When a trigger is generated, the TAiOUT pin outputs “L” level of same amplitude as “H” level of
the set PWM pulse, after which it starts PWM pulse output.
Operation
Note
Item
Count source
PWM mode
Count start condition
Set-up
O
O
O
Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
16-bit PWM
8-bit PWM
External trigger input (falling edge of input signal to the TAi
IN
pin)
External trigger input (rising edge of input signal to the TAi
IN
pin)
Timer overflow (TB2/TAj/TAk overflow)
Count source (Note 1)
Reload register high-order 8 bits = 02
16
Reload register low-order 8 bits = 02
16
External trigger (falling edge of TAi
IN
pin input signal) is selected
1 / f
i
X (m
+ 1) X (2 – 1)
8
TA
iIN
pin input
Underflow signal of 8-bit
prescaler (Note 2)
PWM pulse output from
TA
iOUT
pin
“H”
“H”
“L”
“L”
Timer Ai interrupt
request bit
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
“H”
“L”
“1”
“0”
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FE
16
; n = 00
16
to FE
16
.
1 / f
i
X (m + 1) X n
Count start flag
“1”
“0”
(1) Start count (2) Output level “H” to “L”
Cleared to “0” when interrupt request
is accepted, or cleared by software
(3)
(4) Stop count
1 / f
i
X (m+1)
Conditions:
One period is
complete
207
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected
Start count
Setting count start flag
Count start flag [Address 038016]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
b7 b0
Setting PWM pulse's period and “H” level width
Can be set to 0016 to FE16
b7 b0
(b15) (b8)b7 b0 Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Can be set to 0016 to FE16
1 (Must always be “1” in PWM mode)
Selecting PWM mode and function
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16]
TAiMR (i=0 to 4)
External trigger select bit
0 : Falling edge of TAiIN pin's input signal (Note1)
Selection of PWM mode
b7 b0
11011
16/8-bit PWM mode select bit
1: Functions as an 8-bit pulse width modulator
b7 b6
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Trigger select bit
1 : Selected by event/trigger select register
1
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6 Count
source 100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
Setting event/trigger select bit
One-shot start flag [Address 038216]
ONSF
Timer A0 event/trigger select bit
0 0 : Input on TA0IN is selected (Note 2)
b7 b6
b7 b0 Trigger select register [Address 038316]
TRGSR
b7 b0
Timer A1 event/trigger select bit
0 0 : Input on TA1IN is selected (Note 2)
b1 b0
Timer A2 event/trigger select bit
0 0 : Input on TA2IN is selected (Note 2)
b3 b2
Timer A3 event/trigger select bit
0 0 : Input on TA3IN is selected (Note 2)
b5 b4
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note 2)
b7 b6
Note 2: Set the corresponding port direction register to “0”.
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Note 1: Set the corresponding port direction
register to “0”.
Clearing timer Ai interrupt request bit
Timer Ai interrupt control register [Address 005516 to 005916]
TAiIC (i=0 to 4)
Interrupt request bit
b
7b0
0
Refer to 'Precaution for Timer A (pulse width modulation mode)'
208
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.2.13 Precautions for Timer A (timer mode)
Figure 2.2.28. Reading timer Ai register
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.28 gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai regis-
ter with a count halted but before the counter starts counting gets a proper value.
2 1 0 n n – 1
Counter value (Hex.)
2 1 0 FFFF n – 1
Read value (Hex.)
Reload
Time
n = reload register content
209
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.29 gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after
setting a value in the timer Ai register with a count halted but before the counter starts count-
ing gets a proper value.
(3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse
signals input signals to the TAiIN pin and TAiOUT pin (i = 2, 3, 4), as shown in Figure 2.2.30.
(4) When free run type is selected, if count is stopped, set a value in the timer Ai register again.
2.2.14 Precautions for Timer A (event counter mode)
Figure 2.2.30. Standard of 2-phase pulses
Figure 2.2.29. Reading timer Ai register
210nn – 1
Counter value
(Hex.)
210
FFFF
Read value
(Hex.)
Reload
Time
n = reload register content
(1) Down count
FFFD FFFE FFFF nn + 1
Counter value
(Hex.)
FFFD FFFE FFFF 0000 n + 1
Read value
(Hex.)
AA
AA
Reload
Time
n = reload register content
(2) Up count
n – 1
T1
T2 T3
TA2
OUT
TA3
OUT
TA4
OUT
TA2
IN
TA3
IN
TA4
IN
T1
(Min.) T2, T3
(Min.)
Vcc = 5V, f(X
IN
) = 10MHz
800ns 200ns
T1
(Min.) T2, T3
(Min.)
Vcc = 3V, f(X
IN
) = 7MHz, one-wait
2µs 500ns
210
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request is generated and the timer Ai interrupt request bit goes to “1”.
(3) The output from the one-shot timer synchronizes with the count source generated internally.
Therefore, when an external trigger has been selected, a delay of one cycle of the maximum
count source occurs between the trigger input to the TAiIN pin and the one-shot timer output.
(4) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of
the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(5) If a trigger occurs while a count is in progress, after the counter performs one down count
following the reoccurrence of a trigger, the reload register contents are reloaded, and the
count continues. To generate a trigger while a count is in progress, generate the second
trigger after an elapse longer than one cycle of the timer's count source after the previous
trigger occurred.
2.2.15 Precautions for Timer A (one-shot timer mode)
Figure 2.2.31. One-shot timer delay
Note: The above applies when an external trigger (falling edge of TAi
IN
pin input signal) is selected.
TAi
IN
pin input signal “H”
“L”
Count source
Trigger input
Start one-shot pulse output
One-shot pulse
output from TAi
OUT
pin
211
Timer A
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compli-
ance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to
stop counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level
goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAi OUT pin is outputting an
“L” level in this instance, the level does not change, and the timer Ai interrupt request bit does
not becomes “1”.
2.2.16 Precautions for Timer A (pulse width modulation mode)
212
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.3 Timer B
2.3.1 Overview
The following is an overview for timer B, a 16-bit timer.
(1) Mode
Timer B operates in one of three modes:
(a) Timer mode
The internal count source is counted.
• Operation in timer mode ........................................................................................................... P216
(b) Event counter mode
The number of pulses coming from outside and the number of the timer overflows are counted.
• Operation in event counter mode ............................................................................................. P218
(c) Pulse period measurement/pulse width measurement mode
External pulse period or external pulse widths are measured. If pulse period measurement mode is
selected, the periods of input pulses are continuously measured. If pulse width measurement mode
is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured.
• Operation in pulse period measurement mode ........................................................................ P220
• Operation in pulse width measurement mode .......................................................................... P222
(2) Count source
An internal count source can be selected from f1, f8, f32, and fC32. f1, f8, and f32 are clocks obtained by
dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the
CPU secondary clock by 32.
(3) Frequency division ratio
The frequency division ratio equals [the value set in the timer register + 1]. The counter underflows
when a count source equal to a frequency division ratio is input, and an interrupt request occurs.
(4) Reading the timer
In timer mode or event counter mode, the count value at the time of reading the timer register will be
read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse
width measurement mode, an indeterminate value is read until the second effective edge is input after
a count is started, otherwise, the measurement results are read.
(5) Writing to the timer
When writing to the timer register while a count is in progress, the value is written only to the reload
register. When writing to the timer register while a count has stopped, the value is written both to the
reload register and the count. Write the value in 16-bit increments. The timer register cannot be
written to in either the pulse period measurement mode or the pulse width measurement mode.
213
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(6) Input to the timer and the direction register
To input an external signal to the timer, set the direction register of the relevant port to input.
(7) Pins related to timer B
(a) TB0IN, TB1IN, TB2IN Input pins to timer B.
(8) Registers related to timer B
Figure 2.3.1 shows the memory map of timer B-related registers. Figures 2.3.2 and 2.3.3 show timer
B-related registers.
Figure 2.3.1. Memory map of timer B-related registers
005A
16
005B
16
005C
16
0380
16
0381
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
039B
16
039C
16
039D
16
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
Timer B1 interrupt control register (TB1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
214
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.2. Timer B-related registers (1)
T
i
m
e
r
B
i
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
B
i
M
R
(
i
=
0
t
o
2
)0
3
9
B
1
6
t
o
0
3
9
D
1
6
0
0
X
X
0
0
0
0
2
B
i
t
s
y
m
b
o
lB
i
t
n
a
m
eF
u
n
c
t
i
o
n
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
0
0
:
T
i
m
e
r
m
o
d
e
0
1
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
1
0
:
P
u
l
s
e
p
e
r
i
o
d
/
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
T
C
K
1
M
R
3
M
R
2
M
R
1
T
M
O
D
1
M
R
0
T
M
O
D
0
T
C
K
0
F
u
n
c
t
i
o
n
v
a
r
i
e
s
w
i
t
h
e
a
c
h
o
p
e
r
a
t
i
o
n
m
o
d
e
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
(
F
u
n
c
t
i
o
n
v
a
r
i
e
s
w
i
t
h
e
a
c
h
o
p
e
r
a
t
i
o
n
m
o
d
e
)
O
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t
(
N
o
t
e
1
)
(
N
o
t
e
2
)
N
o
t
e
1
:
T
i
m
e
r
B
0
.
N
o
t
e
2
:
T
i
m
e
r
B
1
,
t
i
m
e
r
B
2
.
215
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.3. Timer B-related registers (2)
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Symbol Address When reset
TB0 0391
16
, 0390
16
Indeterminate
TB1 0393
16
, 0392
16
Indeterminate
TB2 0395
16
, 0394
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (Note)
WR
• Pulse period / pulse width measurement mode
Measures a pulse period or width
• Timer mode 0000
16
to FFFF
16
Counts the timer's period
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts external pulses input or a timer overflow
Note: Read and write data in 16-bit units.
Function
216
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are
described below. Figure 2.3.4 shows the operation timing, and Figure 2.3.5 shows the set-up procedure.
2.3.2 Operation of Timer B (timer mode)
Operation
Table 2.3.1. Choosed functions
(1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the counter contin-
ues counting. At this time, the timer Bi interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Figure 2.3.4. Operation timing of timer mode
Item
Count source
Set-up
OInternal count source (f
1
/ f
8
/ f
32
/ fc
32
)
FFFF
16
n
0000
16
Time
Count start flag
Timer Bi interrupt
request bit
“1”
“1”
Counter content (hex)
n = reload register content
Set to “1” by software
“0”
“0”
Set to “1” by software
Cleared to “0” by
software
(2) Underflow (3) Stop count(1) Start count
Cleared to “0” when interrupt request is accepted, or cleared by software
Start count
again
217
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.5. Set-up procedure of timer mode
Setting divide ratio
Can be set to 0000
16
to FFFF
16
b7 b0
(b15) (b8)b7 b0
Timer B0 register [Address 0391
16
, 0390
16
] TB0
Timer B1 register [Address 0393
16
, 0392
16
] TB1
Timer B2 register [Address 0395
16
, 0394
16
] TB2
Start count
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by
dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
b7 b0
Selecting timer mode and functions
Invalid in timer mode
Can be “0” or “1”
Timer Bi mode register (i=0 to 2) [Address 039B
16
to 039D
16
]
TBiMR (i=0 to 2)
Fixed to “0” in timer mode ( i = 0)
This bit can neither be set nor reset (i = 1, 2)
Selection of timer mode
b7 b0
00
Invalid in timer mode
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
218
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are
described below. Figure 2.3.6 shows the operation timing, and Figure 2.3.7 shows the set-up procedure.
2.3.3 Operation of Timer B (event counter mode)
Operation
Table 2.3.2. Choosed functions
Note: j = i – 1, but j = 2 when i = 0
Figure 2.3.6. Operation timing of event counter mode
(1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Bi interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Item Set-up
Count source Input signal to the TBi
IN
pin (counting falling edges)
Timer overflow(TBj overflow)
O
Input signal to the TBi
IN
pin (counting rising edges)
Input signal to the TBi
IN
pin (counting rising edges and falling edges)
FFFF
16
n
0000
16
Time
Count start flag
Timer Bi interrupt
request bit
“1”
“1”
Counter content (hex)
n = reload register content
Set to “1” by software
“0”
“0”
Set to “1” by software
Cleared to “0” by
software
(1) Start count (2) Underflow (3) Stop count
Cleared to “0” when interrupt request is accepted, or cleared by software
Start count again
219
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.7. Set-up procedure of event counter mode
Setting divide ratio
Can be set to 0000
16
to FFFF
16
(n)
b7 b0
(b15) (b8)b7 b0
Timer B0 register [Address 0391
16
, 0390
16
] TB0
Timer B1 register [Address 0393
16
, 0392
16
] TB1
Timer B2 register [Address 0395
16
, 0394
16
] TB2
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
b7 b0
Selecting event counter mode and functions
Timer Bi mode register (i=0 to 2) [Address 039B
16
to 039D
16
]
TBiMR (i=0 to 2)
Fixed to “0” in event counter mode ( i = 0)
This bit can neither be set nor reset (i = 1, 2)
Selection of event counter mode
b7 b0
01
Invalid in event counter mode
Event clock select
0 : Input from TBi
IN
pin (Note)
000
Count polarity select bit
0 0 : Counts external signal falling edges
b3 b2
Note: Set the corresponding port direction register to “0”.
220
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Op-
erations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure
2.3.9 shows the set-up procedure.
2.3.4 Operation of Timer B (pulse period measurement mode)
Figure 2.3.8. Operation timing of pulse period measurement mode
Table 2.3.3. Choosed functions
Operation
Note
(1) Setting the count start flag to “1” causes the counter to start counting the count source.
(2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”,
and measurement is started. In this instance, an indeterminate value is transferred to the
reload register. The timer Bi interrupt request is not generated.
(3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred
to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the
counter becomes “000016”, and the measurement is started again.
• The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is
input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the
timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be in-
stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start
flag is “1”. This flag cannot be set to “1” by software.
Item Set-up
Count source Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
Pulse width measurement (interval between measurement pulse falling edge to rising edge,
and between rising edge to falling edge)
O
Pulse period measurement (interval between measurement pulse falling edge to falling edge)
Pulse period measurement (interval between measurement pulse rising edge to rising edge)
O
Measurement
mode
Count source
Measurement pulse
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “000016”“1”
“H”
“1”
Transfer
(indeterminate value)
Reload register ← counter
transfer timing
“L”
“0”
“0”
Timer Bi overflow flag “1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Measurement of pulse time interval from falling edge to falling edge
Transfer
(measured value)
Cleared to “0” when interrupt request is accepted, or cleared by software
(1) Start count (2) Start measurement (3) Start measurement again
(Note 1) (Note 1) (Note 2)
221
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.9. Set-up procedure of pulse period measurement mode
Setting count start flag
Count start flag [Address 038016]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
b7 b0
Selecting pulse period / pulse width measurement mode and functions
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
Fixed to “0” in pulse period/pulse width measurement mode (i = 0)
This bit can neither be set nor reset (i = 1,2)
Selection of pulse period / pulse width measurement mode
b7 b0
10
Timer Bi overflow flag
0 : Timer did not overflow
1 : Timer has overflowed
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
Measurement mode select bit
0 0 : Pulse period measurement
(Interval between measurement pulse falling edge to falling edge)
b3 b2
00
Clearing overflow flag
Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16]
TBiMR (i=0 to 2)
b7 b0
Timer Bi overflow flag
0 : Timer did not overflow
0
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6 Count
source 100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
Start count
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
Clock prescaler reset flag [Address 038116]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
222
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Op-
erations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure
2.3.11 shows the set-up procedure.
2.3.5 Operation of Timer B (pulse width measurement mode)
Figure 2.3.10. Operation timing of pulse width measurement mode
Operation
Note
Table 2.3.4. Choosed functions
(1) Setting the count start flag to “1” causes the counter to start counting the count source.
(2) If an effective edge of a pulse to be measured is input, the value of the counter goes to
“000016”, and measurement is started. In this instance, an indeterminate value is transferred
to the reload register. The timer Bi interrupt request is not generated.
(3) If an effective edge of a pulse to be measured is input again, the value of the counter is
transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the
value of the counter becomes “000016”, and measurement is started again.
• The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured
is input or timer Bi overflows. The factor of interrupt request can be determined by use of the
timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be in-
stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start
flag is “1”. This flag cannot be set to “1” by software.
Item Set-up
Count source Internal count source (f
1
/ f
8
/ f
32
/ fc
32
)
Pulse width measurement (interval between measurement pulse falling edge to rising edge,
and between rising edge to falling edge)
O
Pulse period measurement (interval between measurement pulse falling edge to falling edge)
Pulse period measurement (interval between measurement pulse rising edge to rising edge)
O
Measurement
mode
Measurement pulse “H”
Count source
Reload register ← counter
transfer timing
Count start flag
Timer Bi interrupt request bit
Timing at which counter
reaches “0000
16”
“1”
“1”
“L”
“0”
“0”
Timer Bi overflow flag “1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1) (Note 2)
(1) Start count
(2) Start measurement
(3) Start measurement again
Cleared to “0” when interrupt request is accepted, or cleared by software
Transfer
(indeterminate
value)
Transfer(measured value)
(Note 1)
223
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.3.11. Set-up procedure of pulse width measurement mode
Start count
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
b7 b0
Selecting pulse period / pulse width measurement mode and functions
Timer Bi mode register (i=0 to 2) [Address 039B
16
to 039D
16
]
TBiMR (i=0 to 2)
Fixed to “0” in pulse period/pulse width measurement mode (i = 0)
This bit can neither be set nor reset (i = 1, 2)
Selection of pulse period / pulse width measurement mode
b7 b0
10
Timer Bi overflow flag
0 : Timer did not overflow
1 : Timer has overflowed
Count source select bit
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Measurement mode select bit
1 0 : Pulse width measurement (Interval between measurement pulse falling edge to
rising edge, and between rising edge to falling edge)
b3 b2
01
Clearing overflow flag
Timer Bi mode register (i=0 to 2) [Address 039B
16
to 039D
16
]
TBiMR (i=0 to 2)
b7 b0
Timer Bi overflow flag
0 : Timer did not overflow
0
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Setting clock prescaler reset flag
(This function is effective when f
C32
is selected as the count source. Reset the prescaler for generating f
C32
by
dividing the X
CIN
by 32.)
Clock prescaler reset flag [Address 0381
16
]
CPSRF
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
b7 b0
224
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the
flag to “1”.
(2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Bi register with the reload timing shown in Figure
2.3.12 gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi regis-
ter with a count halted but before the counter starts counting gets a proper value.
2.3.6 Precautions for Timer B (timer mode, event counter mode)
Figure 2.3.12. Reading timer Bi register
210n n – 1
Counter value (Hex.)
210FFFF n – 1
Read value (Hex.)
Reload
Time
n = reload register content
225
Timer B
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse
is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of
the timer Bi overflow flag within the interrupt routine.
(2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the
interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and
count the number of overflows.
(3) When reset, the timer Bi overflow flag goes to “1”. This flag cannot be set to “0” by writing to
the timer Bi mode register when the count start flag is “1”.
(4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag
only to determine the interrupt factor within the interrupt routine.
(5) When the first effective edge is input after a count is started, an indeterminate value is trans-
ferred to the reload register. At this time, timer Bi interrupt request is not generated.
(6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi
overflow flag may go to “1” immediately after a count is started.
(7) If changing the measurement mode select bit is set after a count is started, the timer Bi
interrupt request bit goes to “1”.
(8) If the input signal to the TBiIN pin is affected by noise, precise measurement may not be
performed in some cases. It is recommended to see that measurements fall within a specific
range by use of software.
(9) For pulse width measurement, pulse widths are successively measured. Use software to
check whether the measurement result is an “H” level width or an “L” level width.
2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)
226
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.4.1 Overview
Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The
following is an overview of the clock-synchronous serial I/O.
(1) Transmission/reception format
8-bit data
(2) Transfer rate
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be se-
lected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
(3) Error detection
Only overrun error can be detected. Overrun error is an error that occurs when the next data is made
ready before the reception buffer register is read.
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the serial I/O mode select bit to “0002” (invalid serial I/O).
3. Set the serial I/O mode select bit.
4. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Function selection
For clock-synchronous serial I/O, the following functions can be selected:
_______ _______
(a) CTS/RTS function
_______
In the CTS function, an external IC can start transmission/reception by inputting an “L” level to the
_______ _______
CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the
level is set to “H” during transmission/reception, it will stop from the next data.
_______ _______ _______
The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS
goes to “H” at the falling edge of the transfer clock. _______ _______
The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from:
_______ _______
• CTS/RTS functions disabled _______ _______
CTS/RTS pin is a programmable I/O port.
_______
• CTS function only enabled _______ _______ _______
CTS/RTS pin performs the CTS function.
_______
• RTS function only enabled _______ _______ _______
CTS/RTS pin performs the RTS function.
2.4 Clock-Synchronous Serial I/O
227
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(b) Function for choosing polarity
This function switches the polarity of the transfer clock. The following operations are available:
• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge.
(c) Function for choosing which bit to transmit first
This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the
following:
• LSB first Data is transmitted from bit 0.
• MSB first Data is transmitted from bit 7.
(d) Function for choosing successive reception mode
Successive reception mode is a mode in which reading the receive buffer register makes the recep-
tion-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer
register so as to make the reception-enabled status ready. But at the time of starting reception, read
the receive buffer register into a dummy manner.
• Normal mode Writing dummy data to the transmit buffer register makes the
reception enabled status ready.
• Successive reception mode
Reading the reception buffer register makes the reception-enabled
status ready.
(e) Function for outputting transfer clock to multiple pins
This function is to switch among pins to output the transfer clock. This function is effective only when
selecting the internal clock. Switching among pins for outputting the transfer clock allows data trans-
mission to two external ICs in a time-sharing manner.
(f) Function for choosing a transmission interrupt factor
The timing to generate a transmission interrupt can be selected from the following: the instant the
transmission buffer is emptied or the instant the transmission register is emptied. When transmis-
sion buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the
transmission buffer to the transmission register. Therefore, data can be transmitted in succession.
When transmission register empty timing is selected, an interrupt occurs when data transmission is
complete.
Following are some examples in which various functions (a) through (f) are selected:
_______
• Transmission Operation WITH: CTS function, transmission at falling edge of transfer clock, LSB
First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple
pins function ............................................................................................................................ P232
_______ _______
• Transmission Operation WITH: CTS/RTS function disabled, transmission at falling edge of transfer
clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to mul-
tiple pins function (UART0 selection available)....................................................................... P236
_______
• Reception WITH: RTS function, reception at falling edge of transfer clock, LSB First, successive
reception mode disabled; WITHOUT transfer clock output to multiple pins function .............. P240
228
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, set the direction register of the relevant port to input.
(7) Pins related to the serial I/O
_______
• CTS0, CTS1 pins _______
Input pins for the CTS function
________
• RTS0, RTS1 pins _______
Output pins for the RTS function
• CLK0, CLK1 pins Input/output pins for the transfer clock
• RxD0, RxD1 pins Input pins for data
• TxD0, TxD1 pins Output pins for data.
• CLKS1 pin Output pin for transfer clock. Can be used as transfer clock output pin in
the transfer clock output to multiple pins function.
(8) Registers related to the serial I/O
Figure 2.4.1 shows the memory map of serial I/O-related registers, and Figures 2.4.2 to 2.4.4 show
serial I/O-related registers.
Figure 2.4.1. Memory map of serial I/O-related registers
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
005116
005216
005316
005416
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control regster(S1TIC)
UART1 receive interrupt control register(S1RIC)
229
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.2. Serial I/O-related registers (1)
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register
Function
Transmission data
Symbol Address When reset
U0TB 03A3
16
, 03A2
16
Indeterminate
U1TB 03AB
16
, 03AA
16
Indeterminate
UARTi bit rate generator
b7 b0
Symbol Address When reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1) 00
16
to FF
16
Values that can be set
Symbol Address When reset
U0RB 03A7
16
, 03A6
16
Indeterminate
U1RB 03AF
16
, 03AE
16
Indeterminate
b7 b0
(b15) (b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A0
16
and 03A8
16
) are set to “000
2
” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A6
16
and 03AE
16
) is read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note)
Framing error flag (Note)
Parity error flag (Note)
Error sum flag (Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Reception data
WR
WR
WR
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
230
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.3. Serial I/O-related registers (2)
W
R
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
M
R
(
i
=
0
,
1
)0
3
A
01
6,
0
3
A
81
60
01
6
b
7b
6b
5b
4b
3b
2b
1b
0
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
b
e
f
i
x
e
d
t
o
0
0
1
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
C
K
D
I
R
S
M
D
1
S
M
D
0S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
b
i
t
S
M
D
2
I
n
t
e
r
n
a
l
/
e
x
t
e
r
n
a
l
c
l
o
c
k
s
e
l
e
c
t
b
i
t
S
T
P
S
P
R
Y
P
R
Y
E
S
L
E
P
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
S
t
o
p
b
i
t
l
e
n
g
t
h
s
e
l
e
c
t
b
i
t
O
d
d
/
e
v
e
n
p
a
r
i
t
y
s
e
l
e
c
t
b
i
t
S
l
e
e
p
s
e
l
e
c
t
b
i
t
0
:
O
n
e
s
t
o
p
b
i
t
1
:
T
w
o
s
t
o
p
b
i
t
s
0
:
P
a
r
i
t
y
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
e
n
a
b
l
e
d
0
:
S
l
e
e
p
m
o
d
e
d
e
s
e
l
e
c
t
e
d
1
:
S
l
e
e
p
m
o
d
e
s
e
l
e
c
t
e
d
1
0
0
:
T
r
a
n
s
f
e
r
d
a
t
a
7
b
i
t
s
l
o
n
g
1
0
1
:
T
r
a
n
s
f
e
r
d
a
t
a
8
b
i
t
s
l
o
n
g
1
1
0
:
T
r
a
n
s
f
e
r
d
a
t
a
9
b
i
t
s
l
o
n
g
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
I
n
v
a
l
i
d
V
a
l
i
d
w
h
e
n
b
i
t
6
=
“
1
”
0
:
O
d
d
p
a
r
i
t
y
1
:
E
v
e
n
p
a
r
i
t
y
I
n
v
a
l
i
d
I
n
v
a
l
i
d
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
C
0
(
i
=
0
,
1
)0
3
A
41
6,
0
3
A
C1
60
81
6
b
7b
6b
5b
4b
3b
2b
1b
0
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
T
X
E
P
T
C
L
K
1
C
L
K
0
C
R
S
C
R
D
N
C
H
C
K
P
O
L
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
0
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
1
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
L
K
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
d
i
s
a
b
l
e
b
i
t
D
a
t
a
o
u
t
p
u
t
s
e
l
e
c
t
b
i
t
0
0
:
f1
i
s
s
e
l
e
c
t
e
d
0
1
:
f8
i
s
s
e
l
e
c
t
e
d
1
0
:
f3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
47
a
n
d
P
77
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
U
F
O
R
MT
r
a
n
s
f
e
r
f
o
r
m
a
t
s
e
l
e
c
t
b
i
t
0
0
:
f1
i
s
s
e
l
e
c
t
e
d
0
1
:
f8
i
s
s
e
l
e
c
t
e
d
1
0
:
f3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
N
o
t
e
1
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
N
o
t
e
2
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
.
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
47
a
n
d
P
77
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
WR
231
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.4. Serial I/O-related registers (3)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A516, 03AD16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B016 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous receive
mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous receive
mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
Invalid
Invalid
CLK/CLKS select bit 1
(Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Reserved bit Must always be “0” Must always be “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0
232
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.1. Operations of the circled items are described below. Figure 2.4.5 shows the operation timing, and
Figures 2.4.6 and 2.4.7 show the set-up procedures.
2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
Note: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______ _______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
________ _______
(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be
controlled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “H” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Operation
Table 2.4.1. Choosed functions
Item ItemSet-up Set-up
Transfer clock
source
CLK polarity
Internal clock (f
1
/ f
8
/ f
32
)
External clock (CLKi pin)
CTS function CTS function enabled
CTS function disabled
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
O
O
O
Transmission
interrupt factor Transmission buffer empty
Transmission complete
Output transfer clock
to multiple pins
(Note)
Not selected
Selected
O
O
Transfer clock LSB first
MSB first
O
233
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example of wiring
Figure 2.4.5. Operation timing of transmission in clock-synchronous serial I/O mode
Example of operation
CLKi
T
X
Di
CTSi
CLK
R
X
D
Port
Microcomputer Receiver side IC
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
CLK
Stopped pulsing because
transfer enable bit = “0”
Tc = T
CLK
= 2(n + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
32
)
n: value set to BRGi
Transfer clock
Transmit
enable bit (TE)
Transmit
buffer empty
flag (Tl)
CLKi
TxDi
Transmit register
empty flag
(TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
Transmit
interrupt request
bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
AAAAAAAAA
(1) Transmission enabled
AAAAAAA
(2) Confirming CTS
AAAAAAA
AAAAAAA
(3) Start transmission Tc
AAAAAAAAAA
(4) Transmission is complete
AAAAAAAAA
(5) Transmit next data
Data is set to UARTi transmit buffer register
Stopped pulsing because CTSi = “H”
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transferred from UARTi transmit buffer register to UARTi transmit register
234
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
Continued to the next page
Internal/external clock select bit
0 : Internal clock
Setting UARTi transmit/receive mode register (i=0, 1)
UART0 transmit/receive mode register
U0MR
[Address
03A0
16
]
UART1 transmit/receive mode register
U1MR
[Address
03A8
16
]
Invalid in clock synchronous I/O mode
Must be fixed to “001”
b7 b0
01000
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UARTi transmit/receive control register 0 (i=0, 1)
UART0 transmit/receive control register 0
U0C0 [Address 03A4
16
]
UART1 transmit/receive control register 0
U1C0 [Address 03AC
16
]
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
b7 b0
0000
BRG count source select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Inhibited
b1 b0
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Transfer format select bit
0 : LSB first
Note: Set the corresponding port direction register to “0” .
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
UART transmit/receive control register 2
UCON [Address 03B0
16
]
UART0 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
UART1 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Valid when bit 5 = “1”
Fix “0” to this bit.
b7 b0
00
Setting UART transmit/receive control register 2
00
235
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2)
Start transmission
When CTSi input level = “L”
Setting UARTi bit rate generator
(i = 0, 1)
UARTi bit rate generator (i = 0, 1) [Address 03A1
16
, 03A9
16
]
UiBRG (i = 0, 1)
Can be set to 00
16
to FF
16
(Note)
b7 b0
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission is complete
Continued from the previous page
UART0 transmit/receive control register 1
U0C1 [Address 03A5
16
]
UART1 transmit/receive control register 1
U1C1 [Address 03AD
16
]
Transmit enable bit
1 : Transmission enabled
b7 b0
1
Transmission enabled
Writing transmit data
UART0 receive buffer register [Address 03A3
16
, 03A2
16
] U0TB
UART1 receive buffer register [Address 03AB
16
, 03AA
16
] U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
UART0 transmit/receive control register 1
U0C1 [Address 03A5
16
]
UART1 transmit/receive control register 1
U1C1 [Address 03AD
16
]
b7 b0
Transmit buffer empty flag
0 : Data present in transmit
buffer register
1 : No data present in transmit
buffer register
(Writing next transmit data enabled)
Checking the status of UARTi transmit /receive control register (i = 0, 1)
Writing next transmit data
UART0 transmit buffer register [Address 03A3
16
, 03A2
16
] U0TB
UART1 transmit buffer register [Address 03AB
16
, 03AA
16
] U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
236
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O
mode, transfer clock output from multiple pins function selected)
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______ _______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
(1) Setting the transmit enable bit to “1” makes data transmissible status ready.
(2) When transmission data is written to the UART1 transmit buffer register, transmission data
held in the UART1 transmit buffer register is transmitted to the UART1 transmit register in
synchronization with the first falling edge of the transfer clock. At this time, the first bit of the
transmission data is transmitted from the TxD1 pin. Then the data is transmitted bit by bit
from the lower order in synchronization with the falling edges of the transfer clock.
(3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that the transmission is completed. The transfer clock stops at “H” level. At
this time, the UART1 transmit interrupt request bit goes to “1”.
(4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the
CLKS1 pin to go to the transfer clock output pin. Change the transfer clock output pin when
transmission is halted.
Operation
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.2. Operations of the circled items are described below. Figure 2.4.8 shows the operation timing, and
Figures 2.4.9 and 2.4.10 show the set-up procedures.
Table 2.4.2. Choosed functions
Item ItemSet-up Set-up
Transfer clock
source
CLK polarity
Internal clock (f
1
/ f
8
/ f
32
)
External clock (CLKi pin)
CTS function CTS function enabled
CTS function disabled
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
O
O
O
Transmission
interrupt factor Transmission buffer empty
Transmission complete
Output transfer clock
to multiple pins
(Note 1)
Not selected
Selected
O
O
Transfer clock LSB first
MSB first
O
237
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example of wiring
Example of operation
Figure 2.4.8. Operation timing of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)IN
CLK
IN
CLK
Note: This applies when performing only transmission with an internal
clock selected in the clock synchronous serial I/O mode.
Transmit interrupt
request bit “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit buffer
empty flag
CLK1
TxD1
“0”
“1”
Transmit enable bit “0”
“1”
Transfer clock
CLKS1
D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7
CLK, CLKS
select bit 1 “0”
“1”
“0”
“1”
CLK, CLKS
select bit 0
(1) Transmission enabled
(2) Start transmission (3) Transmission is complete
(4) Clock switched
238
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.9. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected (1)
Internal/external clock select bit
0 : Internal clock
Setting UART1 transmit/receive mode register
UART1 transmit/receive mode register [Address 03A8 16]
U1MR
Invalid in clock synchronous I/O mode
Must be fixed to “001”
b7 b0
01000
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UART1 transmit/receive control register 0
UART1 transmit/receive control register 0 [Address 03AC 16]
U1C0
CLK polarity select bit
0 : Transmission data is output at falling edge of transfer clock and
reception data is input at rising edge
b7 b0
100
BRG count source select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
Data output select bit
0 : TXDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CTS/RTS disable bit
1 : CTS/RTS function disabled
Transmit register empty flag
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register (transmission completed)
Transfer format select bit
0 : LSB first
Continued to the next page
Setting UART transmit/receive control register 2
UART transmit/receive control register 2 [Address 03B0 16]
UCON
CLK/CLKS select bit 1
1 : Transfer clock output from multiple pins function selected
UART0 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
CLK/CLKS select bit 0
0 : Clock output to CLK1
1 : Clock output to CLKS1
Fix “0” to this bit.
b7 b0
1 10
239
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.10. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer
clock output from multiple pins function selected (2)
Setting UART1 bit rate generator
UART1 bit rate generator [Address 03A9 16]
U1BRG
Can be set to 0016 to FF16 (Note)
b7 b0
Writing transmit data
UART1 transmit buffer register [Address 03AB 16, 03AA16]
U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
Transmission enabled
UART1 transmit/receive control register 1 [Address 03AD 16]
U1C1
Transmit enable bit
1 : Transmission enabled
b7 b0
1
Checking the status of UART1 transmit buffer register
UART1 transmit/receive control register 1 [Address 03AD 16]
U1C1
b7 b0
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register (Writing next transmit data enabled)
Start transmission
Writing next transmit data
UART1 transmit buffer register [Address 03AB 16, 03AA16]
U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
Transmission is complete
Continued from the previous page
Note: Write to UARTi bit rate generator when transmission/reception is halted.
240
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3.
Operations of the circled items are described below. Figure 2.4.11 shows the operation timing, and Fig-
ures 2.4.12 and 2.4.13 show the set-up procedures.
2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
Table 2.4.3. Choosed functions
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______ _______ _______
selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”.
(1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
________
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
_______
checking that the RTS output has gone to “L” level).
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer
register is read.
Operation
Item ItemSet-up Set-up
Transfer clock
source
CLK polarity
Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
RTS function RTS function enabled
RTS function disabled
Input reception data at
the rising edge of the
transfer clock
Input reception data at
the falling edge of the
transfer clock
O
O
O
Continuous receive
mode Disabled
Enabled
O
Output transfer clock
to multiple pins
(Note 1)
Not selected
Selected
O
Transfer clock LSB first
MSB first
O
241
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example of wiring
Figure 2.4.11. Operation timing of reception in clock-synchronous serial I/O mode
Example of operation
CLKi
R
X
Di
RTSi
CLK
T
X
D
Port
Microcomputer Transmitter side IC
1 / fEXT
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi “H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE) “0”
“1”
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Make sure that the following conditions are met when
the CLKi pin input =“H” before data reception
• Transmit enable bit → “1”
• Receive enable bit → “1”
• Dummy data write to UARTi transmit buffer register
Receive interrupt
request bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Shown in ( ) are bit symbols.
Reception data is taken in
Transferred from UARTi receive register
to UARTi receive buffer register
(1) Reception enabled
(2) Start reception
(3) Reception is complete
Read out from UARTi receive buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
(4) Read of reception data
Dummy data is set in UARTi transmit buffer register
242
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.12. Set-up procedure of reception in clock-synchronous serial I/O mode (1)
Continued to the next page
Internal/external clock select bit
1 : External clock
Setting UARTi transmit/receive mode register (i=0, 1)
UART0 transmit/receive mode register
U0MR
[Address
03A0
16]
UART1 transmit/receive mode register
U1MR
[Address
03A8
16]
Invalid in clock synchronous I/O mode
Must be fixed to “001”
b7 b0
01001
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must be “0” in clock synchronous I/O mode
Setting UARTi transmit/receive control register 0 (i=0, 1)
UART0 transmit/receive control register 0
U0C0 [Address 03A416]
UART1 transmit/receive control register 0
U1C0 [Address 03AC16]
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
b7 b0
0100
BRG count source select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
CTS/RTS disable bit
0 : CTS/RTS function enabled
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Transfer format select bit
0 : LSB first
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
UART transmit/receive control register 2
UCON [Address 03B016]
UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
UART1 continuous receive mode enable bit
0 : Continuous receive mode disabled
Valid when bit 5 = “1”
Fix “0” to this bit.
b7 b0
00
Setting UART transmit/receive control register 2
00
243
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.4.13. Set-up procedure of reception in clock-synchronous serial I/O mode (2)
Writing dummy data
UART0 transmit buffer register [Address 03A3
16
, 03A2
16
] U0TB
UART1 transmit buffer register [Address 03AB
16
, 03AA
16
] U1TB
Setting dummy data
b7 b0 b7 b0
(b15) (b8)
Checking completion of reception
b7 b0
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Start reception
Processing after reading out reception data
Continued from the previous page
Checking error
UART0 receive buffer register [Address 03A7
16
, 03A6
16
]U0RB
UART1 receive buffer register [Address 03AF
16
, 03AE
16
]U1RB
Overrun error flag
0 : No overrun error
1 : Overrun error found
b7 b0 b7 b0
(b15) (b8)
Receive data
Reception enabled
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
Transmit enable bit
1 : Transmission enabled
b7 b0
Receive enable bit
1 : Reception enabled
11
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
244
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O)
Transmission/reception _______ ________
(1) With an external clock selected, and choosing the RTS function, the output level of the RTSi
pin goes to “L” when the data-receivable status becomes ready, which informs the transmis-
________
sion side that the reception has become ready. The output level of the RTSi pin goes to “H”
________ ________
when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission
side, the circuit can transmission and reception data with consistent timing. With the internal
_______
clock, the RTS function has no effect. Figure 2.4.14 shows an example of wiring.
Figure 2.4.14. Example of wiring
TxD
i
RxD
i
CLK
i
CTS
i
TxD
i
RxD
i
CLK
i
RTS
i
Transmitter side IC Receiver side IC
245
Clock-Synchronous Serial I/O
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Transmission
Reception
(1) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set the transmit enable bit (to “1”)
2. Write transmission data to the UARTi transmit buffer register
________ _______
3. “L” level input to the CTSi pin (when the CTS function is selected)
(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is
output to the outside from the TxDi pin (transmission pin) when receiving data.
(2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled
status) and setting dummy data in the UARTi transmission buffer register generates a shift
clock.
With the external clock selected, a shift clock is generated when the transmit enable bit is set
to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input
to the CLKi pin.
(3) In receiving data in succession, an overrun error occurs when the next reception data is made
ready in the UARTi receive register with the receive complete flag set to “1” (before the
content of the UARTi receive buffer register is read), and overrun error flag is set to “1”. In this
instance, the next data is written to the UARTi receive buffer register, so handle with this
problem by writing programs on transmission side and reception side so that the previous
data is transmitted again.
If an overrun error occurs, the UARTi receive interrupt request bit does not go to “1”.
(4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit
buffer register every time reception is made.
(5) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set receive enable bit (to “1”)
2. Set transmit enable bit (to “1”)
3. Write dummy data to the UARTi transmit buffer register
_______
(6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This
is not related to the content of the transmit buffer empty flag or the content of the transmit
enable bit. _______
Output from the RTS pin goes to “H” level when reception starts, and goes to “L” level when
reception is completed. This is not related to the content of the transmit buffer empty flag or
the content of the receive complete flag.
246
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.5 Clock-Asynchronous Serial I/O (UART)
2.5.1 Overview
UART handles communications by means of character-by-character synchronization. The transmission
side and the reception side are independent of each other, so full-duplex communication is possible. The
following is an overview of the clock-asynchronous serial I/O.
(1) Transmission/reception format
Figure 2.5.1 shows the transmission/reception format, and Table 2.5.1 shows the names and func-
tions of transmission data.
Figure 2.5.1. Transmission/reception format
Table 2.5.1. Transmission data names and functions
Transfer data length : 7 bits 1ST – 7DATA 1SP
1ST – 7DATA 2SP
1ST – 7DATA – 1PAR – 1SP
1ST – 7DATA – 1PAR – 2SP
Transfer data length : 8 bits 1ST – 8DATA 1SP
1ST – 8DATA 2SP
1ST – 8DATA – 1PAR – 1SP
1ST – 8DATA – 1PAR – 2SP
Transfer data length : 9 bits 1ST – 9DATA 1SP
1ST – 9DATA 2SP
1ST – 9DATA – 1PAR – 1SP
1ST – 9DATA – 1PAR – 2SP
ST : Start bit
DATA : Character bit (Transfer data)
PAR : Parity bit
SP : Stop bit
Name Function
ST (start bit)
DATA (character bits)
SP (stop bit)
A 1-bit “L” signal to be added immediately before character bits.
This bit signals the start of data transmission.
Transmission data set in the UARTi transmit buffer register.
A signal to be added immediately after character bits so as to increase data
reliability. The level of this signal so varies that the total number of 1's in
character bits and this bit always becomes even or odd depending on which
parity is chosen, even or odd.
PAR (parity bit)
Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after
the parity bit if parity is checked). This / they signals the end of data
transmission.
247
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the bit rate generator can be selected from f1, f8, f32, and the input from
the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respec-
tively.
Table 2.5.2. Example of baud rate setting
Table 2.5.3. Error detection
(3) An error detection
In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.
Baud rate
(bps) BRG's
count source System clock : 10MHz System clock : 7.3728MHz
BRG's set value : n Actual time (bps) BRG's set value : n
600
1200
2400
4800
9600
14400
19200
28800
31250
f
8
f
8
f
8
f
1
f
1
f
1
f
1
f
1
f
1
129 (81
16
)
64 (40
16
)
32 (20
16
)
129 (81
16
)
64 (40
16
)
42 (2A
16
)
32 (20
16
)
21 (15
16
)
19 (13
16
)
600
1201
2367
4807
9615
14534
18939
28409
31250
95 (5F
16
)
47 (2F
16
)
23 (17
16
)
95 (5F
16
)
47 (2F
16
)
31 (1F
16
)
23 (17
16
)
15 (F
16
)
600
1200
2400
4800
9600
14400
19200
28800
Actual time (bps)
Type of error When the flag turns onDescription How to clear the flag
• This error occurs when the
next data lines up before the
content of the UARTi receive
buffer register is read.
• The next data is written to the
UARTi receive buffer register.
• The UARTi receive interrupt
request bit does not go to “1”.
• This error occurs when the
stop bit falls short of the set
number of stop bits.
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
The error is detected
when data is
transferred from the
UARTi receive register
to the UARTi receive
buffer register.
• Set the serial I/O mode select
bits to “000
2
”.
• Set the receive enable bit to
“0”.
• When all error (overrun,
framing, and parity) are
removed, the flag is cleared.
• Set the serial I/O mode select
bits to ”000
2
”.
• Set the receive enable bit to
“0”.
• Read the lower-order byte of
the UARTi receive buffer
register.
Overrun error
Framing error
Parity error
Error-sum flag
248
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Functions selection
In operating UART, the following functions can be used:
_______ _______
(a) CTS/RTS function
_______
CTS function is a function in which an external IC can start transmission/reception by means of
_______ _______
inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception
starts, so if the level is gone to“ H” while transmission/reception is in progress, transmission/recep-
tion stops at the next data.
_______ _______
RTS function is a function to inform an external IC that RTS pin output level has changed to “L” when
_______
reception is ready. RTS regoes to “H” at the falling edge of the transfer clock.
_______ _______
When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions.
_______ _______
• CTS/RTS functions disabled _______ _______
CTS/RTS pin is a programmable I/O port.
_______
• CTS function only enabled _______ _______ _______
CTS/RTS pin performs the CTS function.
_______
• RTS function only enabled _______ _______ _______
CTS/RTS pin performs the RTS function.
(b) Sleep mode
Sleep mode is a mode in which data is transferred to a particular microcomputer among those con-
nected by use of clock-asynchronous serial I/O devices.
(c) Data logic select function
This function is to reserve data when writing to transmit buffer register or reading from receive buffer
register.
The following are examples in which functions (a) to (c) are chosen:
_______
• Transmission WITH: CTS function, WITHOUT: other functions............................................... P254
_______
• Reception WITH: RTS function, WITHOUT: other functions .................................................... P258
249
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, set the direction register of the relevant port to input.
(7) Pins related to the serial I/O
_________ _________
• CTS0, CTS1 pins _______
:Input pins for the CTS function
_________ _________
• RTS0, RTS1 pins _______
:Output pins for the RTS function
• CLK0, CLK1 pins :Input pins for the transfer clock
• RxD0, RxD1 pins :Input pins for data
• TxD0, TxD1 pins :Output pins for data/
250
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.2. Memory map of UARTi-related registers
(8) Registers related to the serial I/O
Figure 2.5.2 shows the memory map of serial I/O-related registers, and Figures 2.5.3 to 2.5.5 show
UARTi-related registers.
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
0051
16
0052
16
0053
16
0054
16
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control regster(S1TIC)
UART1 receive interrupt control register(S1RIC)
251
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.3. UARTi-related registers (1)
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register
Function
Transmission data
Symbol Address When reset
U0TB 03A3
16
, 03A2
16
Indeterminate
U1TB 03AB
16
, 03AA
16
Indeterminate
UARTi bit rate generator
b7 b0
Symbol Address When reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
Function
Assuming that set value = n, BRGi divides the count
source by (n + 1) 00
16
to FF
16
Values that can be set
Symbol Address When reset
U0RB 03A7
16
, 03A6
16
Indeterminate
U1RB 03AF
16
, 03AE
16
Indeterminate
b7 b0
(b15) (b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A0
16
and 03A8
16
) are set to “000
2
” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A6
16
and 03AE
16
) is read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note)
Framing error flag (Note)
Parity error flag (Note)
Error sum flag (Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Reception data
WR
WR
WR
Reception data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
252
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.4. UARTi-related registers (2)
W
R
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
M
R
(
i
=
0
,
1
)0
3
A
0
1
6
,
0
3
A
8
1
6
0
0
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
b
e
f
i
x
e
d
t
o
0
0
1
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
C
K
D
I
R
S
M
D
1
S
M
D
0S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
b
i
t
S
M
D
2
I
n
t
e
r
n
a
l
/
e
x
t
e
r
n
a
l
c
l
o
c
k
s
e
l
e
c
t
b
i
t
S
T
P
S
P
R
Y
P
R
Y
E
S
L
E
P
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
S
t
o
p
b
i
t
l
e
n
g
t
h
s
e
l
e
c
t
b
i
t
O
d
d
/
e
v
e
n
p
a
r
i
t
y
s
e
l
e
c
t
b
i
t
S
l
e
e
p
s
e
l
e
c
t
b
i
t
0
:
O
n
e
s
t
o
p
b
i
t
1
:
T
w
o
s
t
o
p
b
i
t
s
0
:
P
a
r
i
t
y
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
e
n
a
b
l
e
d
0
:
S
l
e
e
p
m
o
d
e
d
e
s
e
l
e
c
t
e
d
1
:
S
l
e
e
p
m
o
d
e
s
e
l
e
c
t
e
d
1
0
0
:
T
r
a
n
s
f
e
r
d
a
t
a
7
b
i
t
s
l
o
n
g
1
0
1
:
T
r
a
n
s
f
e
r
d
a
t
a
8
b
i
t
s
l
o
n
g
1
1
0
:
T
r
a
n
s
f
e
r
d
a
t
a
9
b
i
t
s
l
o
n
g
0
0
0
:
S
e
r
i
a
l
I
/
O
i
n
v
a
l
i
d
0
1
0
:
I
n
h
i
b
i
t
e
d
0
1
1
:
I
n
h
i
b
i
t
e
d
1
1
1
:
I
n
h
i
b
i
t
e
d
b
2
b
1
b
0
0
:
I
n
t
e
r
n
a
l
c
l
o
c
k
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
I
n
v
a
l
i
d
V
a
l
i
d
w
h
e
n
b
i
t
6
=
“
1
”
0
:
O
d
d
p
a
r
i
t
y
1
:
E
v
e
n
p
a
r
i
t
y
I
n
v
a
l
i
d
I
n
v
a
l
i
d
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
U
A
R
T
i
t
r
a
n
s
m
i
t
/
r
e
c
e
i
v
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
U
i
C
0
(
i
=
0
,
1
)0
3
A
4
1
6
,
0
3
A
C
1
6
0
8
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
U
A
R
T
m
o
d
e
)
F
u
n
c
t
i
o
n
(
D
u
r
i
n
g
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
m
o
d
e
)
T
X
E
P
T
C
L
K
1
C
L
K
0
C
R
S
C
R
D
N
C
H
C
K
P
O
L
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
T
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
e
m
p
t
y
f
l
a
g
0
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
1
:
T
r
a
n
s
m
i
t
d
a
t
a
i
s
o
u
t
p
u
t
a
t
r
i
s
i
n
g
e
d
g
e
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
a
n
d
r
e
c
e
i
v
e
d
a
t
a
i
s
i
n
p
u
t
a
t
f
a
l
l
i
n
g
e
d
g
e
C
L
K
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
C
T
S
/
R
T
S
d
i
s
a
b
l
e
b
i
t
D
a
t
a
o
u
t
p
u
t
s
e
l
e
c
t
b
i
t
0
0
:
f
1
i
s
s
e
l
e
c
t
e
d
0
1
:
f
8
i
s
s
e
l
e
c
t
e
d
1
0
:
f
3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
4
7
a
n
d
P
7
7
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
U
F
O
R
MT
r
a
n
s
f
e
r
f
o
r
m
a
t
s
e
l
e
c
t
b
i
t
0
0
:
f
1
i
s
s
e
l
e
c
t
e
d
0
1
:
f
8
i
s
s
e
l
e
c
t
e
d
1
0
:
f
3
2
i
s
s
e
l
e
c
t
e
d
1
1
:
I
n
h
i
b
i
t
e
d
b
1
b
0
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
V
a
l
i
d
w
h
e
n
b
i
t
4
=
“
0
”
0
:
C
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
1
)
1
:
R
T
S
f
u
n
c
t
i
o
n
i
s
s
e
l
e
c
t
e
d
(
N
o
t
e
2
)
0
:
D
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
d
u
r
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
)
1
:
N
o
d
a
t
a
p
r
e
s
e
n
t
i
n
t
r
a
n
s
m
i
t
r
e
g
i
s
t
e
r
(
t
r
a
n
s
m
i
s
s
i
o
n
c
o
m
p
l
e
t
e
d
)
0
:
T
X
D
i
p
i
n
i
s
C
M
O
S
o
u
t
p
u
t
1
:
T
X
D
i
p
i
n
i
s
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
B
i
t
n
a
m
e
B
i
t
s
y
m
b
o
l
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
N
o
t
e
1
:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
N
o
t
e
2
:
T
h
e
s
e
t
t
i
n
g
s
o
f
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
r
e
g
i
s
t
e
r
a
n
d
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
a
r
e
i
n
v
a
l
i
d
.
0
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
e
n
a
b
l
e
d
1
:
C
T
S
/
R
T
S
f
u
n
c
t
i
o
n
d
i
s
a
b
l
e
d
(
P
4
7
a
n
d
P
7
7
f
u
n
c
t
i
o
n
a
s
p
r
o
g
r
a
m
m
a
b
l
e
I
/
O
p
o
r
t
)
WR
253
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.5. UARTi-related registers (3)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A516, 03AD16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B016 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous receive
mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous receive
mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
Invalid
Invalid
CLK/CLKS select bit 1
(Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Reserved bit Must always be “0” Must always be “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0
254
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the
circled items are described below. Figure 2.5.6 shows the operation timing, and Figures 2.5.7 and 2.5.8
show the set-up procedures.
2.5.2 Operation of Serial I/O (transmission in UART mode)
Table 2.5.4. Choosed functions
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register readies the data transmissible status.
________ ________
(2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be con-
trolled on the reception side).
(3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi
transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted
from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit,
and stop bit(s).
(4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit
goes to “1”. The transfer clock stops at “H” level.
(5) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
Operation
Item Set-up
Transfer clock
source Internal clock (f
1
/ f
8
/ f
32
)
External clock (CLKi pin)
CTS function CTS function enabled
CTS function disabled
O
O
Transmission
interrupt factor Transmission buffer empty
Transmission completeO
Sleep mode Sleep mode off
Sleep mode selected
O
255
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example of wiring
Example of operation
Figure 2.5.6. Operation timing of transmission in UART mode
T
X
Di
CTSi
R
X
D
Port
Microcomputer Receiver side IC
Transmit
enable bit (TE)
Transmit buffer
empty flag (Tl)
Transmit
register empty
flag (TXEPT)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
TxDi
CTSi
“0”
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Transmit
interrupt request
bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP D
0
D
1
ST
Shown in ( ) are bit symbols.
SP
Stopped pulsing because transfer enable bit = “0”
Stop
bit
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
Tc
Transfer clock
When confirming stop bit, stopped transfer clock once because CTS = “H”
Started transfer clock again to start transmitting immediately after confirming CTS = “L”
(1) Transmission enabled
(2) Confirme CTS
(3) Start transmission
(4) Confirme stop bit
(5) Start transmission
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
256
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.7. Set-up procedure of transmission in UART mode (1)
Continued to the next page
Setting UARTi transmit/receive mode register (i=0, 1)
Internal/external clock select bit
0 : Internal clock
Stop bit length select bit
0 : One stop bit
b7 b0
01010
Odd/even parity select bit (Valid when bit 6 = “1”)
0 : Odd parity
Parity enable bit
1 : Parity enabled
Sleep select bit
0 : Invalid
Serial I/O mode select bit
1 0 1 : Transfer data 8 bits long
b2 b1 b0
010 UART0 transmit/receive mode register
U0MR [Address 03A016]
UART1 transmit/receive mode register
U1MR [Address 03A816]
Setting UARTi transmit/receive control register 0 (i = 0, 1)
UART0 transmit/receive control register 0
U0C0 [Address 03A416]
UART1 transmit/receive control register 0
U1C0 [Address 03AC16]
Must be “0” in UART mode
b7 b0
0000
BRG count source select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
CTS/RTS function select bit (Valid when bit 4 = “0”)
0 : CTS function is selected
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CTS/RTS disable bit
0 : CTS/RTS function enabled
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Must be “0” in UART mode
Setting UART transmit/receive control register 2
UART transmit/receive control register 2
UCON [Address 03B016]
UART0 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Must be “0” in UART mode
UART1 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Invalid in UART mode
Invalid in UART mode
Invalid in UART mode
Reserved bit
Fix “0” to this bit.
00
b7 b0
257
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.8. Set-up procedure of transmission in UART mode (2)
Start transmission
When CTSi input level = “L”
Setting UARTi bit rate generator
(i = 0, 1)
UARTi bit rate generator (i = 0, 1) [Address 03A1
16
, 03A9
16
]
UiBRG (i = 0, 1)
Can be set to 00
16
to FF
16
(Note)
b7 b0
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission is complete
Continued from the previous page
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
Transmit enable bit
1 : Transmission enabled
b7 b0
1
Transmission enabled
Writing transmit data
UART0 transmit buffer register [Address 03A3
16
, 03A2
16
] U0TB
UART1 transmit buffer register [Address 03AB
16
, 03AA
16
] U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
b7 b0
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
(Writing next transmit data enabled)
Checking the status of UARTi transmit/receive control (i = 0, 1)
Writing next transmit data
UART0 transmit buffer register [Address 03A3
16
, 03A2
16
] U0TB
UART1 transmit buffer register [Address 03AB
16
, 03AA
16
] U1TB
Setting transmission data
b7 b0 b7 b0
(b15) (b8)
258
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In receiving data in UART mode, choose functions from those listed in Table 2.5.5. Operations of the
circled items are described below. Figure 2.5.9 shows the operation timing, and Figures 2.5.10 and
2.5.11 show the set-up procedures.
2.5.3 Operation of Serial I/O (reception in UART mode)
Table 2.5.5. Choosed functions
(1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from
________
the RTSi pin goes to “L” level to inform the transmission side that the receivable status is
ready.
(2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the
_______
RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop
bit(s).
(3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted
to the UARTi receive buffer register.
At this time, the receive complete flag goes to “1” to indicate that the reception is completed,
_______
the UARTi receive interrupt request bit goes to “1”, and output from the RTS pin goes to “L”
level.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer
register is read.
Operation
Item Set-up
Transfer clock
source Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
RTS function RTS function enabled
RTS function disabled
O
O
Sleep mode Sleep mode off
Sleep mode selected
O
259
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Example of wiring
Example of operation
Figure 2.5.9. Operation timing of reception in UART mode
RXDi
RTSi
TXD
Port
Microcomputer Transmitter side IC
CLKi CLK
D
0
D
1
D
7
Start bit
Reception started when transfer
clock is generated by falling edge
of start bit
Sampled “L” Receive data taken in
BRGi's count
source
Receive enable
bit
RxD
i
Transfer clock
Receive
complete flag
RTS
i
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
Timing of transfer data 8 bits long applies to the following settings :
•Transfer data length is 8 bits.
•Parity is disabled.
•One stop bit
•RTS function is selected.
Receive interrupt
request bit
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transferred from UARTi receive register
to UARTi receive buffer register
(1) Reception enabled
(2) Start reception
(4) Data is
read
(3) Receiving is
completed
260
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.10. Set-up procedure of reception in UART mode (1)
Continued to the next page
UART transmit/receive control register 2 [Address 03B0 16] UCON
Invalid in UART mode
Must be fixed to “0” in UART mode
Invalid in UART mode
Invalid in UART mode
Reserved bit
Fix “0” to this bit.
b7 b0
00
Setting UART transmit/receive control register 2
Setting UARTi transmit/receive mode register (i=0, 1)
Internal/external clock select bit
1 : External clock
UART0 transmit/receive mode register [Address 03A016] U0MR
UART1 transmit/receive mode register [Address 03A816] U1MR
Valid when bit 6 = “1”
Parity enable bit
0 : Parity diabled
b7 b0
01011
Sleep select bit
0 : Sleep mode deselected
Serial I/O mode select bit
1 0 1 : Transfer data 8 bits long
b2 b1 b0
00
Stop bit length select bit
0 : One stop bit
Setting UARTi transmit/receive control register 0 (i=0, 1)
Must be fixed to “0” in UART mode
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Must be fixed to “0” in UART mode
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
UART0 transmit/receive control register 0 [Address 03A4 16] U0C0
UART1 transmit/receive control register 0 [Address 03AC 16] U1C0
b7 b0
0100
BRG count source select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
b1 b0
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
CTS/RTS disable bit
0 : CTS/RTS function enabled
0
261
UART
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.5.11. Set-up procedure of reception in UART mode (2)
Start reception
Processing after reading out reception data
Continued from the previous page
Checking error
UART0 receive buffer register [Address 03A7
16
, 03A6
16
]U0RB
UART1 receive buffer register [Address 03AF
16
, 03AE
16
]U1RB
Overrun error flag
0 : No overrun error
1 : Overrun error found
b7 b0 b7 b0
(b15) (b8)
Receive data
Framing error flag
0 : No framing error
1 : Framing error found
Parity error flag
0 : No parity error
1 : Parity error found
Error sum flag
0 : No error
1 : Error found
Setting UARTi bit rate generator (i = 0, 1)
UARTi bit rate generator (i = 0, 1) [Address 03A1
16
, 03A9
16
]
UiBRG (i = 0, 1)
Can be set to 00
16
to FF
16
b7 b0
Reception enabled
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
b7 b0
Receive enable bit
1 : Reception enabled
1
Checking completion of reception
UART0 transmit/receive control register 1 [Address 03A5
16
] U0C1
UART1 transmit/receive control register 1 [Address 03AD
16
] U1C1
b7 b0
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Note: Write to UARTi bit rate generator when transmission/reception is halted.
262
Serial I/O2
2.6 Serial I/O2
2.6.1 Overview
Serial I/O2 performs 8-bit data serial communication, synchronized with the clocks. In the automatic
transfer serial I/O mode, serial communication of up to 256 bytes can be continuously performed without
use of the CPU. The following is the Serial I/O2 overview.
(1) Transfer format
Transfer format is 8-bit data.
(2) Transfer rate
When selecting an internal clock as the transfer clock, the transfer rate is the division ratio selected by
the internal synchronous clock selection bits. Any one of f(XIN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32,
f(XIN)/64, f(XIN)/128 or f(XIN)/256 can be selected by the internal synchronous clock selection bits.
When selecting an external clock as the transfer clock, the transfer rate is the frequency of the clock
input to the CLK pin.
(3) Automatic transfer serial I/O mode
Clock synchronous communication, which does not depend on the CPU, can be continuously per-
formed up to 256 bytes.
(4) Selection function
The following selection functions can be applied to Serial I/O2.
(a) SSTB2 output (for selecting internal synchronous clock)
•STB function invalid: SSTB2 output pin is used as a programmable I/O pin.
•STB function valid: SSTB2 output pin functions as SSTB2 or SSTB2 output.
(b) SBUSY2 input/output
•SBUSY2 input/output function invalid: SBUSY2 pin is used as a programmable I/O pin.
•SBUSY2 input/output function valid: SBUSY2 pin functions as input/output of SBUSY2 or SBUSY2.
(c) SRDY2 input/output
•SRDY2 input/output function invalid: SRDY2 pin is used as a programmable I/O pin.
•SRDY2 input/output function valid: SRDY2 pin functions as input/output of SRDY2 or SRDY2.
(d) SOUT2 P-channel output disable (invalid for P94 as I/O port)
The SOUT2 output pin can be switched between C-MOS 3 state and N-channel open-drain when in
the 8-bit or the automatic transfer serial I/O mode. The mode is selected by the serial transfer select
bits.
(e) LSB first/MSB first
This function switches the starting bit for the transmission/reception; either bit 0 or bit 7. The following
two types can be selected with the transfer direction select bit:
•LSB first: transmission/reception begins with from bit 0.
•MSB first: transmission/reception begins with from bit 7.
263
Serial I/O2
(f) Transfer mode
Either the full duplex mode or the transmit-only mode can be selected. The SIN2 pin can be used as
a programmable input/output port in the transmit-only mode.
(g) Plural transfer clock input/output pin
This function switches the pins for transfer clock input/output. By switching the transfer clock pins,
data can be transmitted/received to two external ICs in a time-sharing manner.
(h) SOUT2 pin control
This pin selects either output active (value of last transmitted data or undefined value) or high-imped-
ance as the SOUT2 pin state for non-transfer periods (i.e. before and after serial transfers).
(5) Input to serial I/O2 and direction register
When inputting external signals to Serial I/O2, set the corresponding port direction register to input.
(6) Serial I/O2-related pins
(a) SSTB2 pin: Output pin for STB and STB functions.
(b) SBUSY2 pin: Input/output pin for BUSY and BUSY functions.
(c) SRDY2 pin: Input/output pin for RDY and RDY functions.
(d) SCLK21, SCLK22 pins: Input/output pins for transfer clocks. Pin is selectable by user.
(e) SIN2 pin: Data input pin.
(f) SOUT2 pin: Data output pin.
264
Serial I/O2
(7) Registers related to Serial I/O2
Figure 2.6.1 shows the memory map of Serial I/O2 related-registers.
Figures 2.6.2 and 2.6.3 show the Serial I/O2 related-registers.
0
3
4
4
1
6
0
3
4
5
1
6
0
3
4
6
1
6
0
3
4
7
1
6
0
3
4
8
1
6
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
S
I
O
2
C
O
N
2
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
/
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
S
I
O
2
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
(
S
I
O
2
C
O
N
3
)
0
3
4
3
1
6
0
3
4
2
1
6
0
0
4
F
1
6
0
3
4
0
1
6
S
I
/
O
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
S
I
O
I
C
)
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
(
S
I
O
2
D
P
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
S
I
O
2
C
O
N
1
)
0
3
4
1
1
6
0
4
0
0
1
6
0
4
F
F
1
6
:
:
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
:
:
Figure 2.6.1. Memory map of Serial I/O2 related-registers
265
Serial I/O2
Figure 2.6.2. Serial I/O2 related-registers (1)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
S
I
O
2
C
O
N
20
3
4
41
60
01
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nR
B
i
t
s
y
m
b
o
l
W
b
7b
6b
5b
4
b
3b
2b
1b
0
SR
D
Y
2
•
SB
U
S
Y
2
p
i
n
c
o
n
t
r
o
l
b
i
t
s
S
C
O
N
2
0
S
C
O
N
2
1
S
C
O
N
2
2
S
C
O
N
2
3
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
S
I
O
2
C
O
N
10
3
4
21
60
01
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l R
W
b
7b
6b
5b
4b
3b
2b
1b
0
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
S
C
O
N
1
0
S
C
O
N
1
1
S
C
O
N
1
2
S
C
O
N
1
3
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
(
SS
T
B
2
p
i
n
c
o
n
t
r
o
l
b
i
t
)0
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
SS
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0
1
:
E
x
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
SS
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
1
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
SS
T
B
2
p
i
n
i
s
a
n
SS
T
B
2
o
u
t
p
u
t
.
)
1
1
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
SS
T
B
2
p
i
n
i
s
a
n
SS
T
B
2
o
u
t
p
u
t
.
)
0
:
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
T
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t0
:
F
u
l
l
d
u
p
l
e
x
(
t
r
a
n
s
m
i
t
a
n
d
r
e
c
e
i
v
e
)
m
o
d
e
(
SI
N
2
p
i
n
i
s
a
SI
N
2
i
n
p
u
t
.
)
1
:
T
r
a
n
s
m
i
t
-
o
n
l
y
m
o
d
e
(
SI
N
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
S
C
O
N
1
4
S
C
O
N
1
5
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
p
i
n
s
e
l
e
c
t
b
i
t
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
S
C
O
N
1
6
S
C
O
N
1
7
0
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
s
e
r
i
a
l
I
/
O
p
i
n
s
a
r
e
I
/
O
p
o
r
t
s
)
0
1
:
8
-
b
i
t
s
s
e
r
i
a
l
I
/
O
1
0
:
I
n
h
i
b
i
t
1
1
:
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
(
8
-
b
i
t
s
)
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
0
:
SC
L
K
2
1 (
SC
L
K
2
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
1
:
SC
L
K
2
2 (
SC
L
K
2
1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0
:
F
u
n
c
t
i
o
n
s
a
s
e
a
c
h
1
-
b
y
t
e
s
i
g
n
a
l
1
:
F
u
n
c
t
i
o
n
s
a
s
s
i
g
n
a
l
f
o
r
a
l
l
t
r
a
n
s
f
e
r
d
a
t
a
SB
U
S
Y
2
o
u
t
p
u
t
•
SS
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
(
V
a
l
i
d
i
n
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
m
o
d
e
)
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
S
C
O
N
2
4
S
C
O
N
2
5
SO
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
SO
U
T
2
p
i
n
c
o
n
t
r
o
l
b
i
t
(
a
t
n
o
-
t
r
a
n
s
f
e
r
s
e
r
i
a
l
d
a
t
a
)
S
C
O
N
2
6
S
C
O
N
2
7
0
:
O
u
t
p
u
t
a
c
t
i
v
e
1
:
O
u
t
p
u
t
h
i
g
h
-
i
m
p
e
d
a
n
c
e
0
:
C
M
O
S
3
-
s
t
a
t
e
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
v
a
l
i
d
.
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
i
n
v
a
l
i
d
.
)
b
3
b
2
b
1
b
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
SR
D
Y
2
p
i
nSB
U
S
Y
2
p
i
n
I
/
O
p
o
r
tI
/
O
p
o
r
t
N
o
t
u
s
e
d
SR
D
Y
2
o
u
t
p
u
tI
/
O
p
o
r
t
SR
D
Y
2
o
u
t
p
u
tI
/
O
p
o
r
t
I
/
O
p
o
r
tS
B
U
S
Y
2
i
n
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
i
n
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
o
u
t
p
u
t
I
/
O
p
o
r
tS
B
U
S
Y
2
o
u
t
p
u
t
SR
D
Y
2
i
n
p
u
tSB
U
S
Y
2
o
u
t
p
u
t
SR
D
Y
2
i
n
p
u
tSB
U
S
Y
2
o
u
t
p
u
t
SR
D
Y
2
i
n
p
u
tSB
U
S
Y
2
o
u
t
p
u
t
SR
D
Y
2
i
n
p
u
tSB
U
S
Y
2
o
u
t
p
u
t
SR
D
Y
2
o
u
t
p
u
tSB
U
S
Y
2
i
n
p
u
t
SR
D
Y
2
o
u
t
p
u
tSB
U
S
Y
2
i
n
p
u
t
SR
D
Y
2
o
u
t
p
u
tSB
U
S
Y
2
i
n
p
u
t
SR
D
Y
2
o
u
t
p
u
tSB
U
S
Y
2
i
n
p
u
t
b
1
b
0
b
3
b
2
266
Serial I/O2
Serial I/O2 control register 3
Symbol Address When reset
SIO2CON3 034816 000000002
Bit name FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
Automatic transfer
interval set bits
TTRAN0
TTRAN1
TTRAN2
TTRAN3
Internal synchronous
clock selection bits 000:f(XIN)/4
001:f(XIN)/8
010:f(XIN)/16
011:f(XIN)/32
100:f(XIN)/64
101:f(XIN)/128
110:f(XIN)/256
TTRAN4
TCLK0
TCLK1
TCLK2
00000 :2 cycles of transfer clocks
00001 :3 cycles of transfer clocks
:
11110 :32 cycles of transfer clocks
11111 :33 cycles of transfer clocks
Data is written to a latch and read from
a decrement counter.
b4b3b2b1b0
b7b6b5
Serial I/O2 automatic transfer data pointer
Symbol Address When reset
SIO2DP 034016 0016
Function R W
b7 b6 b5 b4 b3 b2 b1 b0
• Automatic transfer data pointer set
Specify the low-order 8 bits of the first data store address on the serial I/O
automatic transfer RAM.
Data is written into the latch and read from the decrement counter.
Serial I/O2 register/transfer counter
Symbol Address When reset
SIO2 034616 0016
Function R W
b7 b6 b5 b4 b3 b2 b1 b0
• Number of automatic transfer data set
Set the number of automatic transfer data.
Set a value one less than number of transfer data.
Data is written into the latch and read from the decrement counter.
Figure 2.6.3. Serial I/O2 related-registers (2)
267
Serial I/O2
2.6.2 Serial I/O2 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.6.4 shows connection examples with peripheral ICs which have the CS pin. The automatic
transfer function can be used in all examples.
S
B
U
S
Y
2
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
S
C
L
K
I
N
O
U
T
S
B
U
S
Y
2
S
C
L
K
2
1
S
O
U
T
2
C
S
C
L
K
D
A
T
A
(
1
)
O
n
l
y
t
r
a
n
s
m
i
s
s
i
o
n
(
U
s
i
n
g
S
I
N
2
p
i
n
a
s
I
/
O
p
o
r
t
)
S
B
U
S
Y
2
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
S
C
L
K
I
N
O
U
T
P
o
r
t
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
P
o
r
t
C
S
C
L
K
I
N
O
U
T
C
S
C
L
K
I
N
O
U
T
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
(
O
S
D
c
o
n
t
r
o
l
l
e
r
,
e
t
c
.
)
(
2
)
T
r
a
n
s
m
i
s
s
i
o
n
a
n
d
r
e
c
e
p
t
i
o
n
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
(
E
E
P
R
O
M
,
e
t
c
.
)
(
3
)
T
r
a
n
s
m
i
s
s
i
o
n
a
n
d
r
e
c
e
p
t
i
o
n
(
W
h
e
n
c
o
n
n
e
c
t
i
n
g
S
I
N
2
w
i
t
h
S
O
U
T
2
)
(
W
h
e
n
c
o
n
n
e
c
t
i
n
g
I
N
w
i
t
h
O
U
T
i
n
p
e
r
i
p
h
e
r
a
l
I
C
)
M
3
0
2
1
8
g
r
o
u
p✽1P
e
r
i
p
h
e
r
a
l
I
C
✽2
(
E
E
P
R
O
M
,
e
t
c
.
)
(
4
)
C
o
n
n
e
c
t
i
o
n
o
f
p
l
u
r
a
l
I
C
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
1
P
e
r
i
p
h
e
r
a
l
I
C
2
✽1
:
S
e
l
e
c
t
a
n
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
f
o
r
S
O
U
T
2
p
i
n
o
u
t
p
u
t
c
o
n
t
r
o
l
.
✽2
:
U
s
e
t
h
e
O
U
T
p
i
n
o
f
p
e
r
i
p
h
e
r
a
l
I
C
w
h
i
c
h
i
s
a
n
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
a
n
d
b
e
c
o
m
e
s
h
i
g
h
i
m
p
e
-
d
a
n
c
e
d
u
r
i
n
g
r
e
c
e
i
v
i
n
g
d
a
t
a
.
N
o
t
e
:
“
P
o
r
t
”
m
e
a
n
s
a
n
o
u
t
p
u
t
p
o
r
t
c
o
n
t
r
o
l
l
e
d
b
y
s
o
f
t
w
a
r
e
.
Figure 2.6.4. Serial I/O2 onnection examples (1)
268
Serial I/O2
(2) MCU connections
Figure 2.6.5 shows connection examples with other MCUs.
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
S
C
L
K
2
2
P
o
r
t
C
L
K
I
N
O
U
T
(
4
)
U
s
i
n
g
s
w
i
t
c
h
f
u
n
c
t
i
o
n
o
f
C
L
K
s
i
g
n
a
l
o
u
t
p
u
t
p
i
n
s
,
S
C
L
K
2
2
(
S
e
l
e
c
t
i
n
g
i
n
t
e
r
n
a
l
c
l
o
c
k
)
C
L
K
I
N
O
U
T
C
S
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
L
K
I
N
O
U
T
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
L
K
I
N
O
U
T
S
R
D
Y
2
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
R
D
Y
C
L
K
I
N
O
U
T
(
1
)
S
e
l
e
c
t
i
n
g
i
n
t
e
r
n
a
l
c
l
o
c
k
M
3
0
2
1
8
g
r
o
u
pM
i
c
r
o
c
o
m
p
u
t
e
r
(
2
)
S
e
l
e
c
t
i
n
g
e
x
t
e
r
n
a
l
c
l
o
c
k
(
3
)
U
s
i
n
g
S
R
D
Y
2
s
i
g
n
a
l
o
u
t
p
u
t
f
u
n
c
t
i
o
n
(
S
e
l
e
c
t
i
n
g
e
x
t
e
r
n
a
l
c
l
o
c
k
)
P
e
r
i
p
h
e
r
a
l
I
C
M
3
0
2
1
8
g
r
o
u
pM
i
c
r
o
c
o
m
p
u
t
e
r
M
3
0
2
1
8
g
r
o
u
pM
i
c
r
o
c
o
m
p
u
t
e
rM
i
c
r
o
c
o
m
p
u
t
e
r
M
3
0
2
1
8
g
r
o
u
p
Figure 2.6.5. Serial I/O2 onnection examples (2)
269
Serial I/O2
2.6.3 Serial I/O2 modes
Figure 2.6.6 shows Serial I/O2 modes.
S
e
r
i
a
l
I
/
O
2
8
-
b
i
t
s
e
r
i
a
l
I
/
O
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
I
n
t
e
r
n
a
l
c
l
o
c
k
U
s
i
n
g
h
a
n
d
s
h
a
k
e
s
i
g
n
a
l
E
x
t
e
r
n
a
l
c
l
o
c
k
O
u
t
p
u
t
S
R
D
Y
2
✽
s
i
g
n
a
l
F
u
l
l
d
u
p
l
e
x
m
o
d
e
T
r
a
n
s
m
i
t
-
o
n
l
y
m
o
d
e
N
o
t
u
s
i
n
g
h
a
n
d
s
h
a
k
e
s
i
g
n
a
l
U
s
i
n
g
h
a
n
d
s
h
a
k
e
s
i
g
n
a
l
N
o
t
u
s
i
n
g
h
a
n
d
s
h
a
k
e
s
i
g
n
a
l
I
np
u
t
S
R
D
Y
2
✽
s
i
g
n
a
l
(N
o
t
e)
O
u
t
p
u
t
S
B
U
S
Y2
✽
s
i
g
n
a
l
I
np
u
t
S
B
U
S
Y2
✽
s
i
g
n
a
l
O
u
t
p
u
t
S
S
T
B2
✽
s
i
g
n
a
l
O
u
t
p
u
t
S
R
D
Y
2
✽
s
i
g
n
a
l
I
np
u
t
S
R
D
Y
2
✽
s
i
g
n
a
l
(N
o
t
e)
O
u
t
p
u
t
S
B
U
S
Y2
✽
s
i
g
n
a
l
I
np
u
t
S
B
U
S
Y2
✽
s
i
g
n
a
l
N
o
t
e
:
T
h
i
s
i
s
o
n
l
y
v
a
l
i
d
w
h
e
n
o
u
t
p
u
t
t
i
n
g
t
h
e
S
B
U
S
Y
2
s
i
g
n
a
l
.
✽
A
c
t
i
v
e
l
o
g
i
c
c
a
n
a
p
p
l
y
t
o
e
a
c
h
s
i
g
n
a
l
o
f
S
R
D
Y
2
,
S
B
U
S
Y
2
,
S
S
T
B
2
.
Figure 2.6.6. Serial I/O2 modes
270
Serial I/O2
2.6.4 Serial I/O2 Operations (transmission in 8-bit serial I/O mode)
The functions listed in Table 2.6.1 can be selected in the 8-bit serial I/O mode for Serial I/O2 transmission/
reception. Operations of the circled items are described below. Figure 2.6.7 shows the operation timing,
and Figures 2.6.8 and 2.6.9 show the set-up procedure.
Operation (1) Serial I/O2 becomes transmission-enabled with the following settings: serial transfer select
bits SCON10 to “1” and SCON11 to “0”; transfer mode select bit (SCON15) to “1”; serial I/O
initialization bit (SCON14) to “1”.
(2) When transmission data is written to the serial I/O2 register, transmission starts and the serial
transfer status flag is set to “1”.
(3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge.
(4) When one-byte data transmission is completed, the serial transfer status flag is set to “0” to
indicate the transmission completion. The transfer clock stops at “H” level.
(5) Continuous transmission can be performed by setting the next transmission data in the serial
I/O2 register during transmission, before output of the 8th bit.
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
r
a
n
s
f
e
r
c
l
o
c
k
s
o
u
r
c
eI
n
t
e
r
n
a
l
c
l
o
c
k
(
f
1
/
f
8
/
f
3
2
)
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
OS
e
l
e
c
t
e
d
O
O
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
nO
O
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
E
xt
e
r
n
a
l
c
l
o
c
k
(
C
L
K
i
p
i
n
)
N
o
t
s
e
l
e
c
t
e
d
N
o
t
s
e
l
e
c
t
e
d
S
S
T
B
2
(
“
H
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
S
S
T
B
2
(
“
L
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
L
S
B
f
i
r
s
tO
MS
B
f
i
r
s
t
S
B
U
S
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
B
U
S
Y
2
i
n
p
u
t
S
B
U
S
Y2
o
u
t
p
u
t
(
“
H
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
B
U
S
Y2
o
u
t
p
u
t
(
“
L
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
R
D
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
R
D
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
t
S
R
D
Y2
o
u
t
p
u
t
(
“
H
”
a
t
r
e
a
d
y
)
S
R
D
Y2
o
u
t
p
u
t
(
“
L
”
a
t
r
e
a
d
y
)
Table 2.6.1. Selectable functions
271
Serial I/O2
Figure 2.6.7. Operation timing of transmission in 8-bit serial I/O mode, using plural transfer clock
output function output
S
B
U
S
Y
2
S
C
L
K
2
1
S
O
U
T
2
C
S
C
L
K
D
A
T
A
“1
”
“0
”
“H
”
“L
”
D
0
T
C
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
S
O
U
T
2
(
2
)
T
r
a
n
s
m
i
s
s
i
o
n
s
t
a
r
t(
4
)
T
r
a
n
s
m
i
s
s
i
o
n
i
s
c
o
m
p
l
e
t
e
d
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
O
p
e
r
a
t
i
o
n
e
x
a
m
p
l
e
I
n
t
e
r
n
a
l
c
l
o
c
k
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
(
b
i
t
5
o
f
a
d
d
r
e
s
s
0
3
4
4
1
6
)
S
B
U
S
Y
2
(
o
u
t
p
u
t
)
S
C
L
K
2
1
(
o
u
t
p
u
t
)
T
c
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
w
h
i
c
h
i
s
s
e
l
e
c
t
e
d
w
i
t
h
b
i
t
s
5
t
o
7
o
f
a
d
d
r
e
s
s
0
3
4
8
1
6
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
I
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
•
8
-
b
i
t
s
e
r
i
a
l
I
/
O
m
o
d
e
•
S
B
U
S
Y
2
o
u
t
p
u
t
t
i
m
i
n
g
:
E
a
c
h
1
b
y
t
e
272
Serial I/O2
Figure 2.6.8. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer
clock output function output (1)
0 0 1 0 0 0 0 0
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
21
6]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
0
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
s
e
r
i
a
l
I
/
O
p
i
n
s
a
r
e
I
/
O
p
o
r
t
s
)
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
b
3
b
2
0
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
SS
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
0
:
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
T
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t
1
:
T
r
a
n
s
m
i
t
-
o
n
l
y
m
o
d
e
(
SI
N
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
L
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
p
i
n
s
e
l
e
c
t
b
i
t
0
:
SC
L
K
2
1
(
SC
L
K
2
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0 0 0 1 1 0
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
41
6]
S
I
O
2
C
O
N
2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
s
e
t
-
u
p
SR
D
Y
2
•
SB
U
S
Y
2
p
i
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
b
1
b
0
0 1 1 0
:
SR
D
Y
2
p
i
n
a
s
I
/
O
p
o
r
t
,
SB
U
S
Y2
p
i
n
a
s
SB
U
S
Y
2
o
u
t
p
u
t
SB
U
S
Y
2
o
u
t
p
u
t
•
SS
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
F
u
n
c
t
i
o
n
s
a
s
e
a
c
h
1
-
b
y
t
e
s
i
g
n
a
l
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
SO
U
T
2
p
i
n
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
a
c
t
i
v
e
SO
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
3
-
s
t
a
t
e
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
v
a
l
i
d
.
)
0
0 1 1
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
[
A
d
d
r
e
s
s
0
3
4
81
6]
S
I
O
2
C
O
N
3
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
n
t
e
r
v
a
l
s
e
t
b
i
t
s
b
4
b
3
b
2
b
1
b
0
0
0 0 0 0
:
2
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
0
0 0 0 1
:
3
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
:
1
1 1 1 0
:
3
2
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
1
1 1 1 1
:
3
3
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
b
5
0 1 1
:
f
(
XI
N)
/
3
2
0 1 S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
21
6]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
0
1
:
8
-
b
i
t
s
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
273
Serial I/O2
Figure 2.6.9. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer
clock output function output (2)
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
E
n
a
b
l
i
n
g
tr
a
n
s
m
i
s
s
i
o
n
T
r
a
n
s
m
i
s
s
i
o
n
i
s
c
o
m
p
l
e
t
e
d
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
(
N
o
t
e
)
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
4
1
6
]
S
I
O
2
C
O
N
2
C
o
n
f
i
r
m
a
t
i
o
n
o
f
c
o
m
p
l
e
t
e
t
r
a
n
s
m
i
s
s
i
o
n
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
1
N
o
t
e
:
A
f
t
e
r
s
e
t
t
i
n
g
t
h
e
s
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
,
p
e
r
f
o
r
m
t
h
i
s
s
e
t
-
u
p
.
b
7b
0
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
4
6
1
6
]
S
I
O
2
W
r
i
t
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
S
e
t
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
F
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
274
Serial I/O2
2.6.5
Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode)
The functions listed in Table 2.6.2 can be selected in the automatic transfer serial I/O mode for Serial I/O2
transmission/reception. Operations of the circled items are described below. Figure 2.6.10 shows the
operation timing, and Figures 2.6.11 and 2.6.12 show the set-up procedure.
Operation (1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2
transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts.
(2) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge. The reception data is received bit by bit from the upper bits, synchronized with
each rising edge.
(3) When eight-byte data transmission/reception is completed, the serial transfer status flag is
set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H”
level.
Table 2.6.2. Selectable functions
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
r
a
n
s
f
e
r
c
l
o
c
k
s
o
u
r
c
eI
n
t
e
r
n
a
l
c
l
o
c
k
(
f
1
/
f
8
/
f
3
2
)
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
OS
e
l
e
c
t
e
d
O
O
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
nO
O
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
E
xt
e
r
n
a
l
c
l
o
c
k
(
C
L
K
i
p
i
n
)
N
o
t
s
e
l
e
c
t
e
d
N
o
t
s
e
l
e
c
t
e
d
S
S
T
B
2
(
“
H
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
S
S
T
B
2
(
“
L
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
L
S
B
f
i
r
s
tO
MS
B
f
i
r
s
t
S
B
U
S
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
B
U
S
Y
2
i
n
p
u
t
S
B
U
S
Y2
o
u
t
p
u
t
(
“
H
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
B
U
S
Y2
o
u
t
p
u
t
(
“
L
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
R
D
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
R
D
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
t
S
R
D
Y2
o
u
t
p
u
t
(
“
H
”
a
t
r
e
a
d
y
)
S
R
D
Y2
o
u
t
p
u
t
(
“
L
”
a
t
r
e
a
d
y
)
275
Serial I/O2
Figure 2.6.10. Operation timing of transmission/reception in automatic transfer serial I/O mode
S
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
L
K
S
I
N
S
O
U
T
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
T
C
S
C
L
K
2
1
S
I
N
2
S
O
U
T
2
“
1
”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
(
1
)
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
s
t
a
r
t(
3
)
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
(
b
i
t
5
o
f
a
d
d
r
e
s
s
0
3
4
4
1
6
)
T
c
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
w
h
i
c
h
i
s
s
e
l
e
c
t
e
d
w
i
t
h
b
i
t
s
5
t
o
7
o
f
a
d
d
r
e
s
s
0
3
4
8
1
6
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
I
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
•
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
m
o
d
e
T
r
a
n
s
f
e
r
c
l
o
c
k
“
0
”
W
r
i
t
i
n
g
t
o
s
e
r
i
a
l
I
/
O
2
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
a
d
d
r
e
s
s
0
3
4
6
1
6
)
“
1
”
“
0
”
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
r
a
n
s
f
e
r
i
n
t
e
r
v
a
lT
r
a
n
s
f
e
r
i
n
t
e
r
v
a
l
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
o
f
t
h
e
s
e
c
o
n
d
b
y
t
eT
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
o
f
t
h
e
e
i
g
h
t
h
b
y
t
e
C
l
e
a
r
e
d
t
o
“
0
”
w
h
e
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
,
o
r
c
l
e
a
r
e
d
b
y
s
o
f
t
w
a
r
e
Connection example
Operation example
276
Serial I/O2
Figure 2.6.11. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1)
0 0 0 0 0 0 0 0
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
0
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
s
e
r
i
a
l
I
/
O
p
i
n
s
a
r
e
I
/
O
p
o
r
t
s
)
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
b
3
b
2
0
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
0
:
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
T
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t
0
:
F
u
l
l
d
u
p
l
e
x
(
t
r
a
n
s
m
i
t
a
n
d
r
e
c
e
i
v
e
)
m
o
d
e
(
S
I
N
2
p
i
n
i
s
a
S
I
N
2
i
n
p
u
t
.
)
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
L
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
p
i
n
s
e
l
e
c
t
b
i
t
0
:
S
C
L
K
2
1
(
S
C
L
K
2
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0 0 0 0 0 0
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
4
1
6
]
S
I
O
2
C
O
N
2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
s
e
t
-
u
p
S
R
D
Y
2
•
S
B
U
S
Y
2
p
i
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
b
1
b
0
0
0
0
0
:
S
R
D
Y
2
p
i
n
a
n
d
S
B
U
S
Y2
p
i
n
a
s
I
/
O
p
o
r
t
S
B
U
S
Y
2
o
u
t
p
u
t
•
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
F
u
n
c
t
i
o
n
s
a
s
e
a
c
h
1
-
b
y
t
e
s
i
g
n
a
l
1
:
F
u
n
c
t
i
o
n
s
a
s
s
i
g
n
a
l
f
o
r
a
l
l
t
r
a
n
s
f
e
r
d
a
t
a
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
S
O
U
T
2
p
i
n
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
a
c
t
i
v
e
S
O
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
3
-
s
t
a
t
e
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
v
a
l
i
d
.
)
0 1 1
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
[
A
d
d
r
e
s
s
0
3
4
8
1
6
]
S
I
O
2
C
O
N
3
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
n
t
e
r
v
a
l
s
e
t
b
i
t
s
b
4
b
3
b
2
b
1
b
0
0
0
0
0
0
:
2
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
b
5
0
1
1
:
f
(
X
I
N
)
/
3
2
1 1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
1
1
:
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
(
8
-
b
i
t
)
00000
277
Serial I/O2
Figure 2.6.12. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2)
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
E
n
a
b
l
i
n
g
tr
a
n
s
m
i
s
s
i
o
n
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
4
1
6
]
S
I
O
2
C
O
N
2
C
o
n
f
i
r
m
a
t
i
o
n
o
f
c
o
m
p
l
e
t
e
a
u
t
o
m
a
t
i
c
t
r
a
n
s
m
i
s
s
i
o
n
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
1
b
7b
0
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
[
A
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
F
F
1
6
]
W
r
i
t
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
S
e
t
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
f
o
r
t
r
a
n
s
m
i
s
s
i
o
n
b
y
t
e
n
u
m
b
e
r
(
8
b
y
t
e
s
)
t
o
a
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
0
7
1
6
.
T
h
e
a
r
e
a
f
r
o
m
a
d
d
r
e
s
s
e
s
0
4
0
8
1
6
t
o
0
4
F
F
1
6
,
w
h
i
c
h
i
s
n
o
t
u
s
e
d
i
n
t
h
i
s
e
x
a
m
p
l
e
,
c
a
n
b
e
u
s
e
d
a
s
g
e
n
e
r
a
l
-
p
u
r
p
o
s
e
R
A
M
.
b
7b
0
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
4
0
1
6
]
S
I
O
2
D
P
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
S
e
t
t
h
e
l
o
w
e
r
8
b
i
t
s
(
0
7
1
6
)
o
f
a
d
d
r
e
s
s
0
4
0
7
1
6
(
N
o
t
e
)
N
o
t
e
:
S
p
e
c
i
f
y
t
h
e
l
o
w
e
r
8
b
i
t
s
o
f
t
h
e
f
i
r
s
t
d
a
t
a
s
t
o
r
e
a
d
d
r
e
s
s
o
n
t
h
e
s
e
r
i
a
l
I
/
O
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
.
W
h
e
n
s
e
t
t
i
n
g
a
v
a
l
u
e
,
w
r
i
t
e
a
t
n
o
n
-
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
.
F
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
11100000
b
7b
0
S
e
r
i
a
l
I
/
O
2
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
[
A
d
d
r
e
s
s
0
3
4
6
1
6
]
S
I
O
2
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
t
a
r
t
S
e
t
7
=
(
T
r
a
n
s
f
e
r
b
y
t
e
n
u
m
b
e
r
–
1
)
W
r
i
t
i
n
g
t
o
t
h
i
s
r
e
g
i
s
t
e
r
s
t
a
r
t
s
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
.
O
t
h
e
r
p
r
o
c
e
s
s
e
s
c
a
n
b
e
p
e
r
f
o
r
m
e
d
w
h
i
l
e
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
s
b
e
i
n
g
p
e
r
f
o
r
m
e
d
.
b
7b
0
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
[
A
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
F
F
1
6
]
T
a
k
i
n
g
i
n
r
e
c
e
p
t
i
o
n
d
a
t
a
T
a
k
e
i
n
r
e
c
e
p
t
i
o
n
d
a
t
a
a
t
a
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
0
7
1
6
i
n
t
o
t
h
e
R
A
M
f
o
r
p
r
o
c
e
s
s
.
278
Serial I/O2
2.6.6
Serial I/O2 Operations
(transmission/reception in automatic transfer serial I/O
mode, using handshake signal)
The functions listed in Table 2.6.3 can be selected in the automatic transfer serial I/O mode for Serial I/O2
transmission/reception. Operations of the circled items are described below. Figure 2.6.13 shows the
operation timing, and Figures 2.6.14 and 2.6.15 show the set-up procedure.
Operation (1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2
transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts.
SRDY2 output simultaneously goes to “H” level.
(2) When “L” level is input to the SBUSY2 pin, the SRDY2 output goes to “L” level, synchronized
with the falling edge of the transfer clock, and the serial transfer starts.
(3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each
falling edge. The reception data is received bit by bit from the upper bits, synchronized with
each rising edge.
(4) When sixteen-byte data transmission/reception is completed, the serial transfer status flag is
set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H”
level.
Table 2.6.3. Selectable functions
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
r
a
n
s
f
e
r
c
l
o
c
k
s
o
u
r
c
eI
n
t
e
r
n
a
l
c
l
o
c
k
(
f
1
/
f
8
/
f
3
2
)
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
OS
e
l
e
c
t
e
d
O
O
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
nO
O
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
E
xt
e
r
n
a
l
c
l
o
c
k
(
C
L
K
i
p
i
n
)
N
o
t
s
e
l
e
c
t
e
d
N
o
t
s
e
l
e
c
t
e
d
S
S
T
B
2
(
“
H
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
S
S
T
B
2
(
“
L
”
a
t
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
c
o
m
p
l
e
t
e
d
)
L
S
B
f
i
r
s
tO
MS
B
f
i
r
s
t
S
B
U
S
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
B
U
S
Y
2
i
n
p
u
t
S
B
U
S
Y2
o
u
t
p
u
t
(
“
H
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
B
U
S
Y2
o
u
t
p
u
t
(
“
L
”
a
t
s
t
o
p
r
e
q
u
i
r
e
d
)
S
R
D
Y2
f
u
n
c
t
i
o
nN
o
t
s
e
l
e
c
t
e
d
S
R
D
Y
2
i
n
p
u
t
S
R
D
Y
2
o
u
t
p
u
t
S
R
D
Y2
o
u
t
p
u
t
(
“
H
”
a
t
r
e
a
d
y
)
S
R
D
Y2
o
u
t
p
u
t
(
“
L
”
a
t
r
e
a
d
y
)
279
Serial I/O2
Figure 2.6.13. Operation timing of transmission/reception in automatic transfer serial I/O mode
Connection example
Operation example
C
L
K
2
1
S
O
U
T
2
S
I
N
2
C
L
K
I
N
O
U
T
S
R
D
Y
2
R
D
Y
S
B
U
S
Y
2
B
U
S
Y
M
3
0
2
1
8
g
r
o
u
pP
e
r
i
p
h
e
r
a
l
I
C
SC
L
K
2
1
SI
N
2
SO
U
T
2
SR
D
Y
2
SB
U
S
Y
2
D0D1D2D3D4D5D6D7D0D1D4D5D6D7D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7D0D1D4D5D6D7D0D1D2D3D4D5D6D7
TC
(
2
)
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
s
t
a
r
t
(
4
)
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
(
b
i
t
5
o
f
a
d
d
r
e
s
s
0
3
4
41
6)
T
c
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
w
h
i
c
h
i
s
s
e
l
e
c
t
e
d
w
i
t
h
b
i
t
s
5
t
o
7
o
f
a
d
d
r
e
s
s
0
3
4
81
6
T
h
e
a
b
o
v
e
t
i
m
i
n
g
a
p
p
l
i
e
s
t
o
t
h
e
f
o
l
l
o
w
i
n
g
s
e
t
t
i
n
g
s
:
•
I
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
•
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
m
o
d
e
T
r
a
n
s
f
e
r
c
l
o
c
k
W
r
i
t
i
n
g
t
o
s
e
r
i
a
l
I
/
O
2
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
(
a
d
d
r
e
s
s
0
3
4
61
6)
S
e
r
i
a
l
I
/
O
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
r
a
n
s
f
e
r
i
n
t
e
r
v
a
lT
r
a
n
s
f
e
r
i
n
t
e
r
v
a
l
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
o
f
t
h
e
s
e
c
o
n
d
b
y
t
eT
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
o
f
t
h
e
s
i
x
t
e
e
n
t
h
b
y
t
e
C
l
e
a
r
e
d
t
o
“
0
”
w
h
e
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
a
c
c
e
p
t
e
d
,
o
r
c
l
e
a
r
e
d
b
y
s
o
f
t
w
a
r
e
(
1
)
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
t
a
r
t
“
1
”
“
0
”
“
1
”
“
0
”
280
Serial I/O2
Figure 2.6.14. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1)
0 0 0 0 0 0 0 0
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
0
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
s
e
r
i
a
l
I
/
O
p
i
n
s
a
r
e
I
/
O
p
o
r
t
s
)
S
e
r
i
a
l
I
/
O
2
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
b
i
t
s
b
3
b
2
0
0
:
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
S
S
T
B
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
0
:
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
T
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t
0
:
F
u
l
l
d
u
p
l
e
x
(
t
r
a
n
s
m
i
t
a
n
d
r
e
c
e
i
v
e
)
m
o
d
e
(
S
I
N
2
p
i
n
i
s
a
S
I
N
2
i
n
p
u
t
.
)
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
L
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
2
c
l
o
c
k
p
i
n
s
e
l
e
c
t
b
i
t
0
:
S
C
L
K
2
1
(
S
C
L
K
2
2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
)
0 0 1 1 1 1
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
4
1
6
]
S
I
O
2
C
O
N
2
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
s
e
t
-
u
p
S
R
D
Y
2
•
S
B
U
S
Y
2
p
i
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
b
1
b
0
1 1 1 1
:
S
R
D
Y
2
p
i
n
a
s
S
R
D
Y
2
o
u
t
p
u
t
,
S
B
U
S
Y2
p
i
n
a
s
S
B
U
S
Y
2
i
n
p
u
t
S
B
U
S
Y
2
o
u
t
p
u
t
•
S
S
T
B
2
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
1
:
F
u
n
c
t
i
o
n
s
a
s
s
i
g
n
a
l
f
o
r
a
l
l
t
r
a
n
s
f
e
r
d
a
t
a
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
S
O
U
T
2
p
i
n
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
a
c
t
i
v
e
S
O
U
T
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
0
:
C
M
O
S
3
-
s
t
a
t
e
(
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
i
s
v
a
l
i
d
.
)
0 1 1
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
[
A
d
d
r
e
s
s
0
3
4
8
1
6
]
S
I
O
2
C
O
N
3
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
n
t
e
r
v
a
l
s
e
t
b
i
t
s
b
4
b
3
b
2
b
1
b
0
0
0 0 0 0
:
2
c
y
c
l
e
s
o
f
t
r
a
n
s
f
e
r
c
l
o
c
k
s
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
b
5
0 1 1
:
f
(
X
I
N
)
/
3
2
1 1 S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
s
e
t
-
u
p
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
b
i
t
s
b
1
b
0
1
1
:
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
e
r
i
a
l
I
/
O
(
8
-
b
i
t
)
00000
1
281
Serial I/O2
Figure 2.6.15. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2)
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
[
A
d
d
r
e
s
s
0
3
4
2
1
6
]
S
I
O
2
C
O
N
1
E
n
a
b
l
i
n
g
tr
a
n
s
m
i
s
s
i
o
n
T
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
S
e
r
i
a
l
I
/
O
i
n
i
t
i
a
l
i
z
a
t
i
o
n
b
i
t
1
:
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
d
b
7b
0
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
[
A
d
d
r
e
s
s
0
3
4
4
1
6
]
S
I
O
2
C
O
N
2
C
o
n
f
i
r
m
a
t
i
o
n
o
f
c
o
m
p
l
e
t
e
a
u
t
o
m
a
t
i
c
t
r
a
n
s
m
i
s
s
i
o
n
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
0
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
1
:
S
e
r
i
a
l
t
r
a
n
s
f
e
r
r
i
n
g
1
b
7b
0
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
[
A
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
F
F
1
6
]
W
r
i
t
i
n
g
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
S
e
t
t
r
a
n
s
m
i
s
s
i
o
n
d
a
t
a
f
o
r
t
r
a
n
s
m
i
s
s
i
o
n
b
y
t
e
n
u
m
b
e
r
(
1
6
b
y
t
e
s
)
t
o
a
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
0
F
1
6
.
T
h
e
a
r
e
a
f
r
o
m
a
d
d
r
e
s
s
e
s
0
4
1
0
1
6
t
o
0
4
F
F
1
6
,
w
h
i
c
h
i
s
n
o
t
u
s
e
d
i
n
t
h
i
s
e
x
a
m
p
l
e
,
c
a
n
b
e
u
s
e
d
a
s
g
e
n
e
r
a
l
-
p
u
r
p
o
s
e
R
A
M
.
b
7b
0
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
4
0
1
6
]
S
I
O
2
D
P
S
e
r
i
a
l
I
/
O
2
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
d
a
t
a
p
o
i
n
t
e
r
S
e
t
0
F
1
6
(
N
o
t
e
)
N
o
t
e
:
S
p
e
c
i
f
y
t
h
e
l
o
w
e
r
8
b
i
t
s
o
f
t
h
e
f
i
r
s
t
d
a
t
a
s
t
o
r
e
a
d
d
r
e
s
s
o
n
t
h
e
s
e
r
i
a
l
I
/
O
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
.
W
h
e
n
s
e
t
t
i
n
g
a
v
a
l
u
e
,
w
r
i
t
e
a
t
n
o
n
-
t
r
a
n
s
m
i
s
s
i
o
n
/
r
e
c
e
p
t
i
o
n
.
F
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
11110000
b
7b
0
S
e
r
i
a
l
I
/
O
2
t
r
a
n
s
f
e
r
c
o
u
n
t
e
r
[
A
d
d
r
e
s
s
0
3
4
6
1
6
]
S
I
O
2
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
s
t
a
r
t
S
e
t
1
5
=
(
T
r
a
n
s
f
e
r
b
y
t
e
n
u
m
b
e
r
–
1
)
W
r
i
t
i
n
g
t
o
t
h
i
s
r
e
g
i
s
t
e
r
s
t
a
r
t
s
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
.
O
t
h
e
r
p
r
o
c
e
s
s
e
s
c
a
n
b
e
p
e
r
f
o
r
m
e
d
w
h
i
l
e
a
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
i
s
b
e
i
n
g
p
e
r
f
o
r
m
e
d
.
b
7b
0
A
u
t
o
m
a
t
i
c
t
r
a
n
s
f
e
r
R
A
M
[
A
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
F
F
1
6
]
T
a
k
i
n
g
i
n
r
e
c
e
p
t
i
o
n
d
a
t
a
T
a
k
e
i
n
r
e
c
e
p
t
i
o
n
d
a
t
a
a
t
a
d
d
r
e
s
s
e
s
0
4
0
0
1
6
t
o
0
4
0
F
1
6
i
n
t
o
t
h
e
R
A
M
f
o
r
p
r
o
c
e
s
s
.
282
Serial I/O2
2.6.7 Precautions for Serial I/O2
(1) Clock
(a) Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before performing a normal serial I/O transfer or a serial I/O automatic transfer.
(b) Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit before
performing a normal serial I/O transfer or a serial I/O automatic transfer.
(2) Using Serial I/O2 interrupt
Clear bit 3 of the interrupt control register to “0” by software before enabling interrupts.
(3) State of SOUT2 pin
The SOUT2 pin control bit of the serial I/O2 control register 2 can be used to select the S OUT2 pin state
for non-transfer periods. Either output active or high-impedance can be selected. However, when
using an external synchronous clock, set the SOUT2 pin control bit to “1” while the serial I/O2 clock
input is in “H” level (after transfer completion) in order to put the SOUT2 pin in the high-impedance state.
(4) Serial I/O initialization bit
•To terminate a serial transfer while transferring, set “0” to the serial I/O initialization bit of the serial
I/O2 control register 1.
•When “1” is written to the serial I/O initialization bit, Serial I/O2 is enabled, however, each register is
not initialized. The value of each register needs to be set by software.
(5) Handshake signal
(a) SBUSY2 input signal
Input “H” level to the SBUSY2 input and “L” level to the SBUSY2 input in the initial state. When using the
external synchronous clock, switch the input level to the SBUSY2 input and the SBUSY2 input while the
serial I/O2 clock input is in “H” level.
(b) SRDY2 input/output signal
When using the internal synchronous clock, input “L” level to the SRDY2 input and “H” level to the
SRDY2 input in the initial state.
(6) In 8-bit serial I/O mode
When the external synchronous clock is used, the contents of the serial I/O2 register are being shifted
continually while the transfer clock is input to the serial I/O2 clock pin. At this time, the clock must be
controlled externally.
283
Serial I/O2
(7) In automatic transfer serial I/O mode
<How to set automatic transfer interval>
(a)
When using
•SBUSY2 output and,
•SBUSY2 output•SSTB2 output function as signals for each transfer data, which is set by SBUSY2
output•SSTB2 output function select bit of the serial I/O2 control register 2,
then the transfer interval is inserted before the first data is transmitted/received and after the last data
is transmitted/received.
Accordingly, regardless of the contents of the SBUSY2 output•SSTB2 output function select bit, the
transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic
transfer interval set bits of the serial I/O2 control register 3.
(b)
When using SSTB2 output, regardless of the contents of the SBUSY2 output•SSTB2 output function
select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the
automatic transfer interval set bits of the serial I/O2 control register 3.
(c)
When using the combined output of SBUSY2 and SSTB2 as the signal for each transfer data set, the
transfer interval after completion of transmission/reception of the last data becomes 2 cycles longer
than the value set by the automatic transfer interval set bits.
284
Serial I/O2
(d)
Set the automatic transfer interval for each 1-byte data transfer as explained below to avoid incorrect
transmit/receive of the serial data.
•Not using FLD controller
Keep the interval open for 5 cycles or more of the internal system clock from the rising edge of the
last bit of 1-byte data.
•Using FLD controller
a. Gradation display OFF
Keep the interval open for 17 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
b. Gradation Display ON
Keep the interval open for 27 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
Tables 2.6.4 and 2.6.5 show the serial I/O2 control register 3 (address 034816) setting example.
(e)
When using an external clock, the automatic transfer interval setting becomes invalid.
Serial I/O2 control register 3, SIO2CON3 (address 034816)
Internal synchronous
clock selection bits
b7 b6 b5
0 0 0 : f(XIN) / 4
0 0 1 : f(XIN) / 8
0 1 0 : f(XIN) / 16
Automatic transfer interval set bits
(b4 to b0)
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 1 1 : 5 cycles of transfer clocks
0 0 1 0 0 : 6 cycles of transfer clocks
0 0 1 0 1 : 7 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
Not using
FLDC
Usable
Usable
Usable
Usable
Usable
Usable
Usable
Usable
Usable
Usable
Gradation
display mode
OFF
Prohibited
Prohibited
Prohibited
Usable
Usable
Usable
Prohibited
Usable
Usable
Usable
Gradation
display mode
ON
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
Usable
Prohibited
Prohibited
Usable
Usable
Note: Do not perform the following in the automatic transfer serial I/O mode:
•Transfer within the RAM area (addresses 0040016 to 005FF16) using the DMAC
•Transfer within the RAM area (addresses 0040016 to 005FF16) using assembler instructions SMOVF and SMOVB.
Table 2.6.4 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with internal
synchronous clock)
Serial I/O2 control register 3,
SIO2CON3 (address 034816);
Automatic transfer interval set bits
Not using FLDC
Gradation display mode OFF
Gradation display mode ON
“n” cycles of transfer clocks
Transfer clock ✕ n cycles ≥ 5 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 17 cycles of internal system clock
Transfer clock ✕ n cycles ≥ 27 cycles of internal system clock
Table 2.6.5 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with external
synchronous clock)
285
Serial I/O2
<How to set serial I/O2 transfer counter>
(a)
Write the value of the number of transfer-data decreased by 1 to the serial I/O2 transfer counter.
(b)
When using an external clock, after writing a value to the serial I/O2 register/transfer counter, wait for
5 or more cycles of the internal system clock before inputting the transfer clock to the serial I/O2
clock pin.
<Serial I/O initialization bit>
The serial I/O automatic transfer interrupt request occurs when “0” is written to the serial I/O initializa-
tion bit during an operation. Use software to set this interrupt priority level to level 0 (interrupt dis-
abled), or any other methods which will disable it.
<Interrupt request bit>
The occurrence timing of serial I/O automatic transfer interrupt request may be delayed:
•Normally, the maximum delay is 17 cycles. In the FLD gradation display mode ON, the maximum
delay increases to 27 cycles.
•If the occurrence timing of the serial I/O2 interrupt request is delayed, the flags and the signals
which change simultaneously with the timing of the interrupt request, such as the serial transfer
status flag and the handshake signals, will also change in accordance to the delay.
286
FLD controller
2.7 FLD (VFD) Controller
2.7.1 Overview
The FLD controller drives and controls FLDs (fluorescent display). The following is the FLD controller
overview.
(1) FLDC port
There are a total of 56 ports, consisting of 52 high-breakdown-voltage (HBV) ports and 4 CMOS ports.
20 of the 52 HBV ports can be switched to normal ports, and all of the 4 CMOS ports can be switched
to general purpose ports. However, when using CMOS ports as display pins, external drivers must be
installed.
Ports P0, P1, P5 and P6, totaling 32 ports, have built-in pull-down resistors.
Additionally, by selecting the pull-down resistor option in the mask options when ordering the mask
ROM version, users can chose to have the built-in pull-down resistors connected to ports P2, P3 and
P40 to P43.
(2) Display pixel number
(a) Using all ports for FLD output
28 segments ✕ 28 digits (segment number + digit number ≤ 56)
(b) Using digit pulse output function
40 segments ✕ 16 digits (segment number + digit number ≤ 56, however, digit number ≤ 16)
(c) Using P44 to P47 expansion function
52 segments ✕ 16 digits (segment number ≤ 52, digit number ≤ 16)
(3) Selection function
The following selection functions can be applied to the FLD controller.
(a) Tscan control
Two types of interrupt sources can be selected, using the Tscan control bits (bits 2, 3 of address
035016):
•FLD digit interrupt
This is generated when the Toff1 time for each timing ends (at rising edge of digit output). Key
scanning, which makes use of FLD digits, can be applied by using each FLD digit interrupt.
•FLD blanking interrupt
This is generated when the FLD data pointer (address 035816) reaches FF16.
The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp,
depending on post-interrupt settings. Key scanning, which makes use of FLD segments, can be
applied during this time.
287
FLD controller
(b) Timing number
The following two types of timing can be selected:
•16-timing
This timing is used when the display timing is 16 sets or less.
•32-timing
This timing is used when the display timing is more than 16 sets. This can be used for up to 32 sets.
(c) Gradation display mode
The gradation display mode can apply bright/dark display for each segment when the display timing
is 16 or less.
Selection of gradation mode is as follows:
•Gradation display mode ON
Make sure to fix the timing number control bit (bit 4 of address 035016) to “0” as the maximum timing
is 16. Additionally, set the value to the Toff2 time set register (address 0356 16) so that Toff2 time
can be less than Tdisp time and more than Toff1 time.
•Gradation display mode OFF
(d) HBV port drivability
Two types of drivability, strong or weak, can be selected for HBV ports. This setting is also valid when
using HBV ports as general purpose ports.
(e) P44 to P47 FLD output reverse
Selecting this function enables the polarity reversal of the FLD output from P44 to P47. This function
is useful for adjusting the polarity when using an externally installed driver.
(f) P44 to P47 Toff invalid
Selecting this function disables Toff1 time and Toff2 time and outputs display data for the duration of
Tdisp.
(g) P97 dimmer signal output
Selecting this function outputs a signal from DIMOUT (P97) to the decoder which, in turn, sends out
the dimmer signal. The decoder controls this signal to enable the dimmer function.
(h) Toff section generate/not generate
This function can be applied to all of the HBV ports (P0, P1, P2, P3, P40 to P43, P5, P6) and CMOS
ports (P44 to P47). Two types can be selected:
•Generate Toff section
The Toff section is generated.
•No Toff section
This function reduces unwanted noises generated whenever a port switches due to the combined
capacity of the FLD ports. When continuous data is output to each FLD port, the Toff1 section of the
continuous parts is not generated.
288
FLD controller
(i) Toff2 SET/RESET change
In gradation display mode, this function specifies either output (SET) or “0” (RESET) depending on
Toff2 time for FLD output of dark display data (when gradation display control data is “1”). Two types
can be selected:
•Toff2SET
RAM data is output to the FLD output ports (SET) at the time set by Toff2 and is returned to “0”
(RESET) when the Tdisp time ends.
•Toff2RESET
RAM data is output to the FLD output ports (SET) at the time set by Toff1 and is returned to “0”
(RESET) at the time set by Toff2.
(4) Expansion function
The FLD controller is equipped with an expansion function.
(a) Digit pulses output function
Digit pulses can be output automatically from ports P5 and P6. When the same number of “1s” as the
timing number are consecutively written from P60 to the digit output set registers (addresses 035C16,
035D16), the contents of the FLD automatic display RAM for the ports that have been selected for
digit output are disabled. The digit pulses are then automatically output.
If a value exceeding the timing number for any port is set, the output of such port becomes “L” level.
(b) P44 to P47 expansion function
These ports have CMOS output structure. This function provides 16 lines of FLD digit outputs to
these four ports by connecting the decoder which converts 4-bit data to 16-bit data.
(5) Registers related to FLD controller
Figure 2.7.1 shows the memory map of FLDC related-registers. Figures 2.7.2 to 2.7.6 show FLDC
related-registers.
289
FLD controller
Figure 2.7.1. Memory map of FLDC related-registers
0
3
5
4
1
6
0
3
5
5
1
6
0
3
5
6
1
6
0
3
5
7
1
6
0
3
5
8
1
6
0
3
5
C
1
6
T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
O
F
F
1
)
T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
O
F
F
2
)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
(
F
L
D
D
P
)
P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
(
P
5
D
O
R
)
0
3
5
3
1
6
0
3
5
2
1
6
0
3
5
9
1
6
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
2
F
P
R
)
0
3
5
A
1
6
P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
3
F
P
R
)
0
3
5
B
1
6
P
o
r
t
P
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
4
F
P
R
)
0
0
5
0
1
6
0
3
5
0
1
6
F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
F
L
D
I
C
)
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
(
F
L
D
M
)
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
(
T
D
I
S
P
)
P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
(
P
6
D
O
R
)
0
3
5
D
1
6
0
3
5
1
1
6
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
F
L
D
C
O
N
)
290
FLD controller
Figure 2.7.2. FLDC related-registers (1)
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
F
L
D
M0
3
5
0
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t0
:
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e
m
o
d
e
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
F
L
D
M
0
F
L
D
M
1
F
L
D
M
2
F
L
D
M
3
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t0
:
S
t
o
p
d
i
s
p
l
a
y
1
:
D
i
s
p
l
a
y
(
s
t
a
r
t
t
o
d
i
s
p
l
a
y
b
y
s
w
i
t
c
h
i
n
g
“
0
”
t
o
“
1
”
)
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s0
0
:
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
(
a
t
r
i
s
i
n
g
e
d
g
e
o
f
e
a
c
h
d
i
g
i
t
)
0
1
:
1
X
T
d
i
s
p
1
0
:
2
X
T
d
i
s
p
1
1
:
3
X
T
d
i
s
p
0
:
1
6
t
i
m
i
n
g
m
o
d
e
1
:
3
2
t
i
m
i
n
g
m
o
d
e
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t0
:
N
o
t
s
e
l
e
c
t
i
n
g
1
:
S
e
l
e
c
t
i
n
g
(
N
o
t
e
)
F
L
D
M
4
F
L
D
M
5
N
o
t
e
:
W
h
e
n
a
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
i
s
s
e
l
e
c
t
e
d
,
a
n
u
m
b
e
r
o
f
t
i
m
i
n
g
i
s
m
a
x
.
1
6
t
i
m
i
n
g
.
(
S
e
t
t
h
e
t
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
t
o
“
0
”
.
)
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t0
:
f
(
XI
N)
/
3
2
1
:
f
(
XI
N)
/
1
2
8
F
L
D
M
6
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t0
:
D
r
i
v
a
b
i
l
i
t
y
s
t
r
o
n
g
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
F
L
D
M
7
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
F
L
D
C
O
N0
3
5
1
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
F
L
D
C
O
N
7
F
L
D
C
O
N
5
F
L
D
C
O
N
4
F
L
D
C
O
N
2
F
L
D
C
O
N0
F
L
D
C
O
N
6
P
44
t
o
P
47
F
L
D
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
P
44
t
o
P
47
F
L
D
T
o
f
f
i
s
i
n
v
a
l
i
d
b
i
t0
:
P
e
r
f
o
r
m
n
o
r
m
a
l
l
y
1
:
T
o
f
f
i
s
i
n
v
a
l
i
d
P
97
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
1
:
D
i
m
m
e
r
o
u
t
p
u
t
C
M
O
S
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
s
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
1
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
H
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
s
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
1
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
T
o
f
f
2
S
E
T
/
R
E
S
E
T
c
h
a
n
g
e
b
i
t0
:
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
r
e
s
e
t
a
t
T
o
f
f
2
(
s
e
t
a
t
T
o
f
f
1
)
1
:
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
s
e
t
a
t
T
o
f
f
2
(
r
e
s
e
t
a
t
T
o
f
f
1
)
WR
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
1
:
R
e
v
e
r
s
e
o
u
t
p
u
t
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
(
a
t
f
a
l
l
i
n
g
e
d
g
e
o
f
l
a
s
t
d
i
g
i
t
)
}
b
3
b
2
WR
291
FLD controller
Figure 2.7.3. FLDC related-registers (2)
T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
O
F
F
10
3
5
41
6F
F1
6
W
R
b
7b
0
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
C
o
u
n
t
s
T
o
f
f
1
t
i
m
e
.
C
o
u
n
t
s
o
u
r
c
e
i
s
s
e
l
e
c
t
e
d
b
y
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
.
S
u
p
p
o
s
i
n
g
t
h
a
t
t
h
e
s
e
t
v
a
l
u
e
i
s
“
n
1
”
,
t
h
e
T
o
f
f
1
t
i
m
e
i
s
e
x
p
r
e
s
s
e
d
a
s
T
o
f
f
1
=
n
1
✕
c
o
u
n
t
s
o
u
r
c
e
.
(
E
x
a
m
p
l
e
)
T
o
f
f
1
=
3
0
✕
3
.
2
µs
=
9
6
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
F
L
D
M
6
=
0
(
f
(
X
I
N
)
/
3
2
s
e
l
e
c
t
e
d
a
s
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
)
•
T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
=
3
0
(
1
E
1
6
)
3
t
o
F
F
1
6
T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
rS
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
O
F
F
20
3
5
61
6F
F1
6
W
R
b
7b
0
C
o
u
n
t
s
T
o
f
f
2
t
i
m
e
.
C
o
u
n
t
s
o
u
r
c
e
i
s
s
e
l
e
c
t
e
d
b
y
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
.
S
u
p
p
o
s
i
n
g
t
h
a
t
t
h
e
s
e
t
v
a
l
u
e
i
s
“
n
2
”
,
t
h
e
T
o
f
f
2
t
i
m
e
i
s
e
x
p
r
e
s
s
e
d
a
s
T
o
f
f
2
=
n
2
✕
c
o
u
n
t
s
o
u
r
c
e
.
T
h
i
s
s
e
t
t
i
n
g
o
f
T
o
f
f
2
t
i
m
e
a
p
p
l
i
e
s
o
n
l
y
t
o
t
h
e
F
L
D
p
o
r
t
s
a
s
t
h
e
f
o
l
l
o
w
i
n
g
:
•
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
a
n
d
•
T
h
e
R
A
M
v
a
l
u
e
o
f
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
c
o
n
t
r
o
l
i
s
“
1
”
(
=
d
a
r
k
d
i
s
p
l
a
y
)
.
(
E
x
a
m
p
l
e
)
T
o
f
f
2
=
1
8
0
✕
3
.
2
µs
=
5
7
6
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
F
L
D
M
6
=
0
(
f
(
X
I
N
)
/
3
2
s
e
l
e
c
t
e
d
a
s
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
)
•
T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
=
1
8
0
(
B
4
1
6
)
3
t
o
F
F
1
6
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
D
I
S
P0
3
5
21
60
01
6
W
R
b
7b
0
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
0
1
6
t
o
F
F
1
6
C
o
u
n
t
s
T
d
i
s
p
t
i
m
e
.
C
o
u
n
t
s
o
u
r
c
e
i
s
s
e
l
e
c
t
e
d
b
y
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
.
S
u
p
p
o
s
i
n
g
t
h
a
t
t
h
e
s
e
t
v
a
l
u
e
i
s
“
n
”
,
t
h
e
T
d
i
s
p
t
i
m
e
i
s
e
x
p
r
e
s
s
e
d
a
s
T
d
i
s
p
=
(
n
+
1
)
✕
c
o
u
n
t
s
o
u
r
c
e
.
W
h
e
n
r
e
a
d
i
n
g
t
h
i
s
r
e
g
i
s
t
e
r
,
t
h
e
v
a
l
u
e
i
n
t
h
e
c
o
u
n
t
e
r
o
f
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
i
s
r
e
a
d
o
u
t
.
(
E
x
a
m
p
l
e
)
T
d
i
s
p
=
(
2
0
0
+
1
)
✕
3
.
2
µs
=
6
4
3
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
F
L
D
M
6
=
0
(
f
(
X
I
N
)
/
3
2
s
e
l
e
c
t
e
d
a
s
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
)
•
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
=
2
0
0
(
C
8
1
6
)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
T
O
F
F
10
3
5
41
6F
F1
6
292
FLD controller
F
L
D
d
a
t
a
p
o
i
n
t
e
rS
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
F
L
D
D
P0
3
5
81
6
i
n
d
e
t
e
r
m
i
n
a
t
e
W
R
b
7b
0
C
o
u
n
t
s
F
L
D
o
u
t
p
u
t
t
i
m
i
n
g
.
S
e
t
t
h
i
s
r
e
g
i
s
t
e
r
t
o
“
F
L
D
o
u
t
p
u
t
d
a
t
a
-
1
”
.
T
h
e
s
e
t
v
a
l
u
e
i
s
w
r
i
t
t
e
n
i
n
t
o
t
h
e
F
L
D
d
a
t
a
p
o
i
n
t
e
r
r
e
l
o
a
d
r
e
g
i
s
t
e
r
.
W
h
e
n
r
e
a
d
i
n
g
t
h
i
s
r
e
g
i
s
t
e
r
,
t
h
e
v
a
l
u
e
o
f
t
h
e
F
L
D
d
a
t
a
p
o
i
n
t
e
r
i
s
r
e
a
d
o
u
t
.
1
t
o
1
F1
6
N
o
t
e
:
R
e
a
d
i
n
g
t
h
e
F
L
D
d
a
t
a
p
o
i
n
t
e
r
t
a
k
e
s
o
u
t
t
h
e
c
o
u
n
t
a
t
t
h
a
t
m
o
m
e
n
t
.
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
2
F
P
R0
3
5
91
60
01
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
2
F
P
R
0
P
2
F
P
R
2
P
2
F
P
R
1
P
2
F
P
R
3
P
2
F
P
R
4
P
2
F
P
R
6
P
2
F
P
R
5
P
2
F
P
R
7
P
o
r
t
P
20
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
21
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
22
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
23
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
24
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
25
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
26
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
27
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
3
F
P
R0
3
5
A1
60
01
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
3
F
P
R
0
P
3
F
P
R
2
P
3
F
P
R
1
P
3
F
P
R
3
P
3
F
P
R
4
P
3
F
P
R
6
P
3
F
P
R
5
P
3
F
P
R
7
P
o
r
t
P
30
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
31
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
32
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
33
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
34
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
35
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
36
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
37
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
Figure 2.7.4. FLDC related-registers (3)
293
FLD controller
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
4
F
P
R0
3
5
B
1
6
0
0
1
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
4
F
P
R
0
P
4
F
P
R
2
P
4
F
P
R
1
P
4
F
P
R
3
P
4
F
P
R
4
P
4
F
P
R
6
P
4
F
P
R
5
P
4
F
P
R
7
P
o
r
t
P
4
0
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
1
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
5
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
6
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
4
7
F
L
D
/
p
o
r
t
s
w
i
t
c
h
b
i
t
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
5
D
O
R0
3
5
C
1
6
0
0
1
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
5
D
O
R0
P
5
D
O
R
2
P
5
D
O
R
1
P
5
D
O
R
3
P
5
D
O
R
4
P
5
D
O
R
6
P
5
D
O
R
5
P
5
D
O
R
7
P
o
r
t
P
5
0
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
1
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
2
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
3
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
4
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
5
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
6
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
5
7
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
Figure 2.7.5. FLDC related-registers (4)
294
FLD controller
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
P
6
D
O
R0
3
5
D
1
6
0
0
1
6
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
6D
O
R0
P
6D
O
R
2
P
6D
O
R
1
P
6D
O
R
3
P
6D
O
R
4
P
6D
O
R
6
P
6D
O
R
5
P
6D
O
R
7
P
o
r
t
P
6
0
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
1
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
2
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
3
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
4
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
5
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
6
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
0
:
F
L
D
o
u
t
p
u
t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
6
7
F
L
D
/
d
i
g
i
t
s
w
i
t
c
h
b
i
t
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
Figure 2.7.6. FLDC related-registers (5)
295
FLD controller
This page kept blank for layout purposes.
296
FLD controller
2.7.2 FLD operation (FLD automatic display and key-scan using segments)
The FLD controller can choose functions from those listed in Table 2.7.1. The circled items are described
in detail below. Figure 2.7.7 shows the operation timing, and Figures 2.7.8 to 2.7.10 show the set-up
procedures.
Table 2.7.1. Selectable functions
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
s
c
a
n
c
o
n
t
r
o
l
(
N
o
t
e
1
)F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
yS
t
r
o
n
g
W
e
a
k
O
T
i
m
i
n
g
n
u
m
b
e
r1
6
-
t
i
m
i
n
g
3
2-
t
i
m
i
n
g
OP
9
7
d
i
m
m
e
r
o
u
t
p
u
tN
o
r
m
a
l
p
o
r
t
D
i
m
m
e
r
o
u
t
p
u
t
O
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
f
(
X
I
N
)
/
3
2
f
(
X
I
N
)
/
1
2
8
OH
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
-
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
O
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
(
N
o
t
e
2
)N
o
t
s
e
l
e
c
t
i
n
g
Se
l
e
c
t
i
n
g
O
T
o
f
f
2
S
E
T
/
R
E
S
E
TR
e
s
e
t
a
t
T
o
f
f
2
Se
t
a
t
T
o
f
f
2
O
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The grada-
tion display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
However, the contents of the FLD automatic display RAM for ports P50, P51, and P60 to P6 7
are disabled by selection of the digit pulse output function, and the digit pulses are automati-
cally output.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF16”, the
pointer is reloaded and starts counting over again.
(4) The FLD interrupt request bit is set to “1” simultaneously with the falling edge of the last
timing. The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp,
or 3 ✕ Tdisp, depending on post-interrupt settings. During this time, key scanning, which
makes use of FLD segments, can be applied.
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
297
FLD controller
Figure 2.7.7. Operation timing of FLD automatic display
F
L
D
3
2
(
P
2
0
)
F
L
D
3
3
(
P
2
1
)
F
L
D
3
4
(
P
2
2
)
F
L
D
3
9
(
P
2
7
)
•
•
•
•
•
•
P
5
0
,
P
5
1
P
6
0
–P
6
7
P
3
0
,
P
3
1
P
2
0
–
P
2
7
P
3
4
–
P
3
7
S
e
g
m
e
n
t
D
i
g
i
t
R
E
C
■
L
E
V
E
L
A
M
P
MC
H
S
U
N
M
O
N
T
U
E
W
E
D
T
H
U
F
R
I
S
A
T
●
L
R
M
3
0
2
1
8
G
r
o
u
p
K
e
y
-
m
a
t
r
i
x
P
a
n
e
l
w
i
t
h
f
l
u
o
r
e
s
c
e
n
t
d
i
s
p
l
a
y
(
F
L
D
)
●
●
●
S
e
g
m
e
n
t
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
T
d
i
s
p T
s
c
a
n
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
F
L
D
9
(
P
5
1
)
F
L
D
8
(
P
5
0
)
F
L
D
7
(
P
6
7
)
F
L
D
0
(
P
6
0
)
F
L
D
3
2
–
F
L
D
4
1
(
P
2
0
–
P
2
7
,
P
3
0
,
P
3
1
)K
e
y
-
s
c
a
n
•
•
•
T
o
f
f
1
T
o
f
f
2
•
•
•
•
•
•
O
p
e
r
a
t
i
o
n
e
x
a
m
p
l
e
E
n
l
a
r
g
e
d
v
i
e
w
o
f
T
s
c
a
n
S
P
E
P
298
FLD controller
Figure 2.7.8. Set-up procedure for FLD automatic display (1)
0 0 0 0
b
7b
0
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
E
7
1
6
]
P
D
3
S
e
t
P
3
4
–
P
3
7
t
o
i
n
p
u
t
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
i
n
p
u
t
1 1 1 1 1 1 1 1
b
7b
0
D
i
s
p
l
a
y
p
i
n/
p
o
r
t
s
w
i
t
c
h
o
f
P
2
,
P
3
,
P
5
a
n
d
P
6
s
e
t
-
u
p
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
9
1
6
]
P
2
F
P
R
0 0 0 0 0 0 1 1
b
7b
0P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
A
1
6
]
P
3
F
P
R
S
e
t
P
3
0
a
n
d
P
3
1
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
0
,
F
L
D
4
1
)
S
e
t
P
3
2
–
P
3
7
t
o
n
o
r
m
a
l
I
/
O
o
u
t
p
u
t
p
o
r
t
s
0 0 0 0 0 0 1 1
b
7b
0P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
C
1
6
]
P
5
D
O
R
S
e
t
P
5
0
a
n
d
P
5
1
t
o
d
i
g
i
t
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
8
,
F
L
D
9
)
S
e
t
P
5
2
–
P
5
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
1 1 1 1 1 1 1 1
S
e
t
P
2
0
–
P
2
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
3
2
t
o
F
L
D
3
9
)
1 1 1 1 1 1 1 1
b
7b
0P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
D
1
6
]
P
6
D
O
R
S
e
t
P
6
0
–
P
6
7
t
o
d
i
g
i
t
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
0
t
o
F
L
D
7
)
1 0 1 0 1 1 0 1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
1
1
:
3
X
T
d
i
s
p
;
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
0
:
1
6
t
i
m
i
n
g
m
o
d
e
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t
1
:
S
e
l
e
c
t
i
n
g
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
3
2
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
0 1 0 0 0 0
b
7b
0F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
1
1
6
]
F
L
D
C
O
N
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
4
4
t
o
P
4
7
F
L
D
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
P
4
4
t
o
P
4
7
F
L
D
T
o
f
f
i
s
i
n
v
a
l
i
d
b
i
t
0
:
P
e
r
f
o
r
m
n
o
r
m
a
l
l
y
P
9
7
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
C
M
O
S
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
S
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
H
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
1
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
T
o
f
f
2
S
E
T
/
R
E
S
E
T
c
h
a
n
g
e
b
i
t
0
:
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
r
e
s
e
t
a
t
T
o
f
f
2
(
s
e
t
a
t
T
o
f
f
1
)
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
299
FLD controller
F
L
D
d
a
t
a
p
o
i
n
t
e
r
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
T
d
i
s
p
,
T
o
f
f
1
a
n
d
T
o
f
f
2
t
i
m
e
s
e
t
-
u
p
1 1 0 0 1 0 0 0
b
7b
0T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
2
1
6
]
T
D
I
S
P
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
1
:
D
i
s
p
l
a
y
0
b
7b
0F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
0
5
0
1
6
]
F
L
D
I
C
F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
I
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
s
e
l
e
c
t
b
i
t
b
2
b
1
b
0
0
0
0
:
L
e
v
e
l
0
(
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
)
0
0
1
:
L
e
v
e
l
1
0
1
0
:
L
e
v
e
l
2
0
1
1
:
L
e
v
e
l
3
1
0
0
:
L
e
v
e
l
4
1
0
1
:
L
e
v
e
l
5
1
1
0
:
L
e
v
e
l
6
1
1
1
:
L
e
v
e
l
7
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
S
e
t
C
8
1
6
;
T
d
i
s
p
=
(
2
0
0
+
1
)
✕
c
o
u
n
t
s
o
u
r
c
e
=
6
4
3
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 1 1 1 1 0
b
7b
0T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
4
1
6
]
T
O
F
F
1
S
e
t
1
E
1
6
;
T
o
f
f
1
=
3
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
9
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
1 0 1 1 0 1 0 0
b
7b
0T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
6
1
6
]
T
O
F
F
2
S
e
t
B
4
1
6
;
T
o
f
f
2
=
1
8
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
5
7
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 0 1 0 0 1
b
7b
0F
L
D
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
5
8
1
6
]
F
L
D
D
P
S
e
t
9
=
“
d
i
g
i
t
n
u
m
b
e
r
–
1
”
.
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
N
o
t
e
)
0
:
I
n
t
e
r
r
u
p
t
n
o
t
r
e
q
u
e
s
t
e
d
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
N
o
t
e
:
O
n
l
y
“
0
”
c
a
n
b
e
w
r
i
t
t
e
n
t
o
t
h
i
s
b
i
t
.
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
Figure 2.7.9. Set-up procedure for FLD automatic display (2)
300
FLD controller
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
r
o
u
t
i
n
e
P
u
s
h
re
g
i
s
t
e
r
s
a
n
d
a
n
y
o
t
h
e
r
s
e
t
-
u
p
0
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
0
:
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e
m
o
d
e
1 1 1 1 1 1 1 1
b
7b
0
P
2
,
P
5
a
n
d
P
6
s
e
t
-
u
p
0 0 0 0 0 0 0 0
b
7b
0
0 0 0 0 0 0 0 0
b
7b
0
S
e
t
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
t
o
n
o
r
m
a
l
p
o
r
t
s
0 0
b
7b
0P
o
r
t
P
5
[
A
d
d
r
e
s
s
0
3
E
9
1
6
]
P
5
S
e
t
“
L
”
l
e
v
e
l
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
d
i
g
i
t
s
P
o
r
t
P
6
[
A
d
d
r
e
s
s
0
3
E
C
1
6
]
P
6
S
e
t
“
L
”
l
e
v
e
l
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
d
i
g
i
t
s
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
9
1
6
]
P
2
F
P
R
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
2
[
A
d
d
r
e
s
s
0
3
E
4
1
6
]
P
2
O
u
t
p
u
t
“
L
”
l
e
v
e
l
f
r
o
m
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
K
e
y
-
s
c
a
n
p
r
o
c
e
s
s
i
n
g
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
2
[
A
d
d
r
e
s
s
0
3
E
4
1
6
]
P
2
O
u
t
p
u
t
“
L
”
l
e
v
e
l
f
r
o
m
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
P
2
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
S
e
t
n
o
r
m
a
l
p
o
r
t
s
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
9
1
6
]
P
2
F
P
R
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
R
T
I
Figure 2.7.10. Set-up procedure for key-scan processing
301
FLD controller
This page kept blank for layout purposes.
302
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.7.3 FLD operation (FLD automatic display and key-scan using digits)
The FLD controller can choose functions from those listed in Table 2.7.2. The circled items are described
in detail below. Figure 2.7.11 shows the operation timing, and Figures 2.7.12 and 2.7.13 show the set-up
procedures.
Table 2.7.2. Selectable functions
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The grada-
tion display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
However, the contents of the FLD automatic display RAM for ports P50, P51, and P60 to P6 7
are disabled by selection of the digit pulse output function, and the digit pulses are automati-
cally output.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF16”, the
pointer is reloaded and starts counting over again.
(4) The FLD interrupt request bit is set to “1” simultaneously with the end of Toff1 time (at the
rising edge of a digit) for each timing. Key scanning, which makes use of FLD digits, can be
applied by using each FLD digit interrupt.
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
s
c
a
n
c
o
n
t
r
o
l
(
N
o
t
e
1
)F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
yS
t
r
o
n
g
W
e
a
k
O
T
i
m
i
n
g
n
u
m
b
e
r1
6
-
t
i
m
i
n
g
3
2-
t
i
m
i
n
g
OP
9
7
d
i
m
m
e
r
o
u
t
p
u
tN
o
r
m
a
l
p
o
r
t
D
i
m
m
e
r
o
u
t
p
u
t
O
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
f
(
X
I
N
)
/
3
2
f
(
X
I
N
)
/
1
2
8
OH
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
-
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
O
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
(
N
o
t
e
2
)N
o
t
s
e
l
e
c
t
i
n
g
Se
l
e
c
t
i
n
g
O
T
o
f
f
2
S
E
T
/
R
E
S
E
TR
e
s
e
t
a
t
T
o
f
f
2
Se
t
a
t
T
o
f
f
2
O
303
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.7.11. Operation timing of FLD automatic display
P
20–P
27
P
30,
P
31
P
50,
P
51
P
60–
P
67
P
34–
P
37
S
e
g
m
e
n
t
D
i
g
i
t
D
i
g
i
t
S
P
E
PR
E
C
■
L
E
V
E
L
A
M
P
MC
H
S
U
N
M
O
N
T
U
E
W
E
D
T
H
U
F
R
I
S
A
T
●
L
R
M
3
0
2
1
8 Gr
o
u
p
K
e
y
-
m
a
t
r
i
x
P
a
n
e
l
w
i
t
h
f
l
u
o
r
e
s
c
e
n
t
d
i
s
p
l
a
y
(
F
L
D
)
●
●
●
T
d
i
s
pT
s
c
a
n
=
0
µs
F
L
D9 (
P
51)
F
L
D8 (
P
50)
F
L
D7 (
P
67)
F
L
D0 (
P
60)
F
L
D3
2–
F
L
D4
1
(
P
20–
P
27,
P
30,
P
31)
•
•
•
T
o
f
f
2
T
o
f
f
1
•
•
•
•
•
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
c
c
u
r
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
O
p
e
r
a
t
i
o
n
e
x
a
m
p
l
e
304
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.7.12. Set-up procedure for FLD automatic display (1)
0 0 0 0
b
7b
0
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
E
71
6]
P
D
3
S
e
t
P
34
–
P
37
t
o
i
n
p
u
t
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
i
n
p
u
t
1 1 1 1 1 1 1 1
b
7b
0
D
i
s
p
l
a
y
p
i
n/
p
o
r
t
s
w
i
t
c
h
o
f
P
2
,
P
3
,
P
5
a
n
d
P
6
s
e
t
-
u
p
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
91
6]
P
2
F
P
R
0 0 0 0 0 0 1 1
b
7b
0P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
A1
6]
P
3
F
P
R
S
e
t
P
30
a
n
d
P
31
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
0
,
F
L
D
4
1
)
S
e
t
P
32
–
P
37
t
o
n
o
r
m
a
l
I
/
O
o
u
t
p
u
t
p
o
r
t
s
0 0 0 0 0 0 1 1
b
7b
0P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
C1
6]
P
5
D
O
R
S
e
t
P
50
a
n
d
P
51
t
o
d
i
g
i
t
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
8
,
F
L
D
9
)
S
e
t
P
52
–
P
57
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
1 1 1 1 1 1 1 1
S
e
t
P
20
–
P
27
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
3
2
t
o
F
L
D
3
9
)
1 1 1 1 1 1 1 1
b
7b
0P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
D1
6]
P
6
D
O
R
S
e
t
P
60
–
P
67
t
o
d
i
g
i
t
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
0
t
o
F
L
D
7
)
1 0 1 0 0 0 0 1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
01
6]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
0
0
:
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
0
:
1
6
t
i
m
i
n
g
m
o
d
e
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t
1
:
S
e
l
e
c
t
i
n
g
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
XI
N)
/
3
2
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
0 1 0 0 0 0
b
7b
0F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
11
6]
F
L
D
C
O
N
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
44
t
o
P
47
F
L
D
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
P
44
t
o
P
47
F
L
D
T
o
f
f
i
s
i
n
v
a
l
i
d
b
i
t
0
:
P
e
r
f
o
r
m
n
o
r
m
a
l
l
y
P
97
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
C
M
O
S
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
S
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
H
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
1
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
T
o
f
f
2
S
E
T
/
R
E
S
E
T
c
h
a
n
g
e
b
i
t
0
:
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
r
e
s
e
t
a
t
T
o
f
f
2
(
s
e
t
a
t
T
o
f
f
1
)
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
305
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.7.13. Set-up procedure for FLD automatic display (2)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
T
d
i
s
p
,
T
o
f
f
1
a
n
d
T
o
f
f
2
t
i
m
e
s
e
t
-
u
p
1 1 0 0 1 0 0 0
T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
2
1
6
]
T
D
I
S
P
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
1
:
D
i
s
p
l
a
y
0
b
7b
0F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
0
5
0
1
6
]
F
L
D
I
C
F
L
D
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
I
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
s
e
l
e
c
t
b
i
t
b
2
b
1
b
0
0
0
0
:
L
e
v
e
l
0
(
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
)
0
0
1
:
L
e
v
e
l
1
0
1
0
:
L
e
v
e
l
2
0
1
1
:
L
e
v
e
l
3
1
0
0
:
L
e
v
e
l
4
1
0
1
:
L
e
v
e
l
5
1
1
0
:
L
e
v
e
l
6
1
1
1
:
L
e
v
e
l
7
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
S
e
t
C
8
1
6
;
T
d
i
s
p
=
(
2
0
0
+
1
)
✕
c
o
u
n
t
s
o
u
r
c
e
=
6
4
3
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 1 1 1 1 0
T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
4
1
6
]
T
O
F
F
1
S
e
t
1
E
1
6
;
T
o
f
f
1
=
3
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
9
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
1 0 1 1 0 1 0 0
T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
6
1
6
]
T
O
F
F
2
S
e
t
B
4
1
6
;
T
o
f
f
2
=
1
8
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
5
7
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 0 1 0 0 1
b
7b
0F
L
D
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
5
8
1
6
]
F
L
D
D
P
S
e
t
9
=
“
d
i
g
i
t
n
u
m
b
e
r
–
1
”
.
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
N
o
t
e
)
0
:
I
n
t
e
r
r
u
p
t
n
o
t
r
e
q
u
e
s
t
e
d
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
N
o
t
e
:
O
n
l
y
“
0
”
c
a
n
b
e
w
r
i
t
t
e
n
t
o
t
h
i
s
b
i
t
.
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
306
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.7.4 FLD operation (FLD display and key-scan using segment by software)
FLD display and key-scan using the Timer A0 interrupt are explained in detail below. Figure 2.7.14 shows
the operation timing, and Figures 2.7.15 to 2.7.17 show the set-up procedures.
Operation (1) Set both the automatic display control bit and the display start bit to “0”.
(2) Output segment data and digit data from each port during the Timer A0 interrupt processing.
(3) After finishing display of all digits, perform key-scan within during the Timer A0 interrupt
processing.
307
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.7.14. Operation timing of FLD display
P
50,
P
51
P
60–P
67
P
30,
P
31
P
20–
P
27
P
34–
P
37
S
e
g
m
e
n
t
D
i
g
i
t
S
P
E
PR
E
C
■
L
E
V
E
L
A
M
P
MC
H
S
U
N
M
O
N
T
U
E
W
E
D
T
H
U
F
R
I
S
A
T
●
L
R
M
3
0
2
1
8 Gr
o
u
p
K
e
y
-
m
a
t
r
i
x
P
a
n
e
l
w
i
t
h
f
l
u
o
r
e
s
c
e
n
t
d
i
s
p
l
a
y
(
F
L
D
)
●
●
●
S
e
g
m
e
n
t
P
51
P
50
P
67
P
60
P
20–
P
27,
P
30,
P
31
K
e
y
-
s
c
a
n
•
•
•
•
•
•
•
•
•
P
20
P
21
P
22
P
27
•
•
•
•
•
•
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
O
p
e
r
a
t
i
o
n
e
x
a
m
p
l
e
E
n
l
a
r
g
e
d
v
i
e
w
o
f
k
e
y
-
s
c
a
n
308
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
0 0 0 0
b
7b
0
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
E
71
6]
P
D
3
S
e
t
P
30
a
n
d
P
31
t
o
o
u
t
p
u
t
p
o
r
t
s
f
o
r
s
e
g
m
e
n
t
o
u
t
p
u
t
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
01
6]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
0
:
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
b
7b
0C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
[
A
d
d
r
e
s
s
0
3
8
11
6]
C
P
S
R
F
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
11
S
e
t
P
34
–
P
37
t
o
i
n
p
u
t
p
o
r
t
s
f
o
r
k
e
y
-
s
c
a
n
i
n
p
u
t
T
i
m
e
r
A
0
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
9
61
6]
T
A
0
M
R
Ti
m
e
r
m
o
d
e
(
T
i
m
e
r
A
0
)
a
n
d
f
u
n
c
t
i
o
n
s
s
e
t
-
u
p
S
e
l
e
c
t
i
o
n
o
f
t
i
m
e
r
m
o
d
e
P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
A
0O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
G
a
t
e
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
b
4
b
3
0
0
:
0
1
:
G
a
t
e
f
u
n
c
t
i
o
n
n
o
t
a
v
a
i
l
a
b
l
e
(
T
A
0I
N
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
0
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
i
n
t
i
m
e
r
m
o
d
e
)
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
b
7
b
6
0
0
:
f1
0
1
:
f8
1
0
:
f3
2
1
1
:
fC
3
2
C
o
u
n
t
s
o
u
r
c
e
p
e
r
i
o
d
f
(
XI
N)
:
1
0
M
HZ
f
(
X
cI
N)
:
3
2
.
7
6
8
k
HZ
b
7b
6C
o
u
n
t
s
o
u
r
c
e
1
0
0
n
s
8
0
0
n
s
3
.
2
µs
9
7
6
.
5
6
µs
00
01
10
11
f1
f8
f3
2
fC
3
2
0
b
7b
0
0000
b
7b
0
(
b
1
5
)(
b
8
)b
7b
0T
i
m
e
r
A
0
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
8
71
6,
0
3
8
61
6]
T
A
0
C
a
n
b
e
s
e
t
t
o
0
0
0
01
6
t
o
F
F
F
F1
6
Di
v
i
d
e
r
a
t
i
o
s
e
t
-
u
p
Cl
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
s
e
t
-
u
p
(
T
h
i
s
f
u
n
c
t
i
o
n
i
s
e
f
f
e
c
t
i
v
e
w
h
e
n
fC
3
2
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
c
o
u
n
t
s
o
u
r
c
e
.
R
e
s
e
t
t
h
e
p
r
e
s
c
a
l
e
r
f
o
r
g
e
n
e
r
a
t
i
n
g
fC
3
2
b
y
d
i
v
i
d
i
n
g
t
h
e
XC
I
N
b
y
3
2
.
)
C
l
o
c
k
p
r
e
s
c
a
l
e
r
r
e
s
e
t
f
l
a
g
0
:
N
o
e
f
f
e
c
t
1
:
P
r
e
s
c
a
l
e
r
i
s
r
e
s
e
t
(
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
i
s
“
0
”
)
100
Figure 2.7.15. Set-up procedure for FLD display (1)
309
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
1
b
7b
0C
o
u
n
t
s
t
a
r
t
f
l
a
g
[
A
d
d
r
e
s
s
0
3
8
0
1
6
]
T
A
B
S
R
C
o
u
n
t
s
t
a
r
t
f
l
a
g
s
e
t
-
u
p
0
b
7b
0T
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
0
5
5
1
6
]
T
A
0
I
C
T
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
I
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
s
e
l
e
c
t
b
i
t
b
2
b
1
b
0
0
0
0
:
L
e
v
e
l
0
(
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
)
0
0
1
:
L
e
v
e
l
1
0
1
0
:
L
e
v
e
l
2
0
1
1
:
L
e
v
e
l
3
1
0
0
:
L
e
v
e
l
4
1
0
1
:
L
e
v
e
l
5
1
1
0
:
L
e
v
e
l
6
1
1
1
:
L
e
v
e
l
7
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
N
o
t
e
)
0
:
I
n
t
e
r
r
u
p
t
n
o
t
r
e
q
u
e
s
t
e
d
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
N
o
t
e
:
O
n
l
y
“
0
”
c
a
n
b
e
w
r
i
t
t
e
n
t
o
t
h
i
s
b
i
t
.
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
T
i
m
e
r
A
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
1
Figure 2.7.16. Set-up procedure for FLD display (2)
310
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
T
A
0
i
n
t
e
r
r
u
p
t
r
o
u
t
i
n
e
P
u
s
h
re
g
i
s
t
e
r
s
a
n
d
a
n
y
o
t
h
e
r
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
P
2
,
P
3
,
P
5
a
n
d
P
6
s
e
t
-
u
p
0 0
b
7b
0
0 0
b
7b
0P
o
r
t
P
2
[
A
d
d
r
e
s
s
0
3
E
41
6]
P
2
S
e
t
“
0
”
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
s
e
g
m
e
n
t
s
P
o
r
t
P
3
[
A
d
d
r
e
s
s
0
3
E
51
6]
P
3
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
2
[
A
d
d
r
e
s
s
0
3
E
41
6]
P
2
S
e
t
s
e
g
m
e
n
t
d
a
t
a
S
e
g
m
e
n
t
d
a
t
a
s
e
t
-
u
p
0 0
b
7b
0P
o
r
t
P
3
[
A
d
d
r
e
s
s
0
3
E
51
6]
P
3
R
T
I
000000
S
e
t
“
0
”
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
s
e
g
m
e
n
t
s
0 0
b
7b
0P
o
r
t
P
5
[
A
d
d
r
e
s
s
0
3
E
91
6]
P
5
S
e
t
“
0
”
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
d
i
g
i
t
s
1 1 1 1 1 1 1 1
b
7b
0
0 0
b
7b
0P
o
r
t
P
6
[
A
d
d
r
e
s
s
0
3
E
C1
6]
P
6
S
e
t
“
0
”
t
o
p
o
r
t
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
d
i
g
i
t
s
000000
S
e
t
s
e
g
m
e
n
t
d
a
t
a
0 0
b
7b
0P
o
r
t
P
5
[
A
d
d
r
e
s
s
0
3
E
91
6]
P
2
S
e
t
d
i
g
i
t
d
a
t
a
D
i
g
i
t
d
a
t
a
s
e
t
-
u
p
0 0
b
7b
0P
o
r
t
P
6
[
A
d
d
r
e
s
s
0
3
E
C1
6]
P
6
S
e
t
d
i
g
i
t
d
a
t
a
000000
Figure 2.7.17. Set-up procedure for key-scan processing
311
FLD controller
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
This page kept blank for layout purposes.
312
FLD controller
2.7.5 FLD operation (Display with digit expander M35501FP)
The FLD controller can choose functions from those listed in Table 2.7.3. The circled items are described
in detail below. Figure 2.7.18 shows the connection example and Figure 2.7.19 shows the operation
timing, and Figures 2.7.20 and 2.7.21 show the set-up procedures.
Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp
Table 2.7.3. Selectable functions
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The grada-
tion display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF16”, the
pointer is reloaded and starts counting over again.
(4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71,
respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97).
(5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
s
c
a
n
c
o
n
t
r
o
l
(
N
o
t
e
1
)F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
yS
t
r
o
n
g
W
e
a
k
O
T
i
m
i
n
g
n
u
m
b
e
r1
6
-
t
i
m
i
n
g
3
2-
t
i
m
i
n
g
OP
9
7
d
i
m
m
e
r
o
u
t
p
u
tN
o
r
m
a
l
p
o
r
t
D
i
m
m
e
r
o
u
t
p
u
t
O
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
f
(
X
I
N
)
/
3
2
f
(
X
I
N
)
/
1
2
8
OH
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
-
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
O
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
(
N
o
t
e
2
)N
o
t
s
e
l
e
c
t
i
n
g
Se
l
e
c
t
i
n
g
O
T
o
f
f
2
S
E
T
/
R
E
S
E
TR
e
s
e
t
a
t
T
o
f
f
2
Se
t
a
t
T
o
f
f
2
O
313
FLD controller
Figure 2.7.18. Connection example of FLD automatic display (1)
D
i
g
i
t
(
1
6
)
F
l
u
o
r
e
s
c
e
n
t
d
i
s
p
l
a
y
(
F
L
D
)
P
3
0
–
P
3
7
P
1
0
–
P
1
7
P
0
0
–
P
0
7
P
2
0
–
P
2
7
S
e
g
m
e
n
t
(
5
2
)
M
3
0
2
1
8
G
r
o
u
p M
3
5
5
0
1
F
P
C
L
K
S
E
L
R
E
S
E
T
D
I
G
0
–
D
I
G
1
5
P
4
0
–
P
4
3
D
I
M
O
U
T
P
7
0
P
7
1
O
V
F
I
N
P
6
0
–
P
6
7
P
5
0
–
P
5
7
O
V
F
O
U
T
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
314
FLD controller
R
E
S
E
T
S
E
L
O
V
F
I
N
O
V
F
O
U
T
F
L
D
0
–
F
L
D
5
1
(
P
0
0
–
P
0
7
,
P
1
0
–
P
1
7
,
P
2
0
–
P
2
7
,
P
3
0
–
P
3
7
,
P
4
0
–
P
4
3
,
P
5
0
–
P
5
7
,
P
6
0
–
P
6
7
)
•
•
•
C
L
K
D
I
G
0
D
I
G
3
D
I
G
1
2
D
I
G
1
D
I
G
2
D
I
G
1
3
D
I
G
1
4
D
I
G
1
5
M
3
0
2
1
8
G
r
o
u
p
M
3
5
5
0
1
F
P
•
•
•
O
p
e
r
a
t
i
o
n
e
x
a
m
p
l
e
E
n
l
a
r
g
e
d
v
i
e
w
•
•
•
T
d
i
s
p
T
o
f
f
2
T
o
f
f
1
C
L
K
D
I
G
0
D
I
G
1
D
I
G
2
D
I
G
1
5
M
3
5
5
0
1
F
P
•
•
•
M
3
0
2
1
8
G
r
o
u
p
F
L
D
0
–
F
L
D
5
1
(
P
0
0
–
P
0
7
,
P
1
0
–
P
1
7
,
P
2
0
–
P
2
7
,
P
3
0
–
P
3
7
,
P
4
0
–
P
4
3
,
P
5
0
–
P
5
7
,
P
6
0
–
P
6
7
)
Figure 2.7.19. Operation timing of FLD automatic display
315
FLD controller
Figure 2.7.20. Set-up procedure for FLD automatic display (1)
1 1 1 1 1 1 1 1
b
7b
0
D
i
s
p
l
a
y
p
i
n
/
p
o
r
t
s
w
i
t
c
h
o
f
P
2
,
P
3
,
P
4
,
P
5
a
n
d
P
6
s
e
t
-
u
p
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
9
1
6
]
P
2
F
P
R
1 1 1 1 1 1 1 1
b
7b
0P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
A
1
6
]
P
3
F
P
R
S
e
t
P
3
0
–
P
3
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
0
t
o
F
L
D
4
7
)
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
C
1
6
]
P
5
D
O
R
S
e
t
P
5
0
–
P
5
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
8
t
o
F
L
D
1
5
)
1 1 1 1 1 1 1 1
S
e
t
P
2
0
–
P
2
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
3
2
t
o
F
L
D
3
9
)
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
D
1
6
]
P
6
D
O
R
S
e
t
P
6
0
–
P
6
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
0
t
o
F
L
D
7
)
1 0 1 0 0 0 0 1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
0
0
:
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
0
:
1
6
t
i
m
i
n
g
m
o
d
e
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t
1
:
S
e
l
e
c
t
i
n
g
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
3
2
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
0 0 0 0 1 1 1 1
b
7b
0P
o
r
t
P
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
B
1
6
]
P
4
F
P
R
S
e
t
P
4
4
–
P
4
7
t
o
n
o
r
m
a
l
I
/
O
p
o
r
t
s
S
e
t
P
4
0
–
P
4
3
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
8
t
o
F
L
D
5
1
)
1 1
b
7b
0P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
E
F
1
6
]
P
D
7
S
e
t
P
7
1
t
o
o
u
t
p
u
t
p
o
r
t
(
f
o
r
S
E
L
s
i
g
n
a
l
o
f
M
3
5
5
0
1
)
S
e
t
P
7
0
t
o
o
u
t
p
u
t
p
o
r
t
(
f
o
r
R
E
S
E
T
s
i
g
n
a
l
o
f
M
3
5
5
0
1
)
M
3
5
5
0
1
i
n
i
t
i
a
l
i
z
a
t
i
o
n
0 0
b
7b
0P
o
r
t
P
7
[
A
d
d
r
e
s
s
0
3
E
D
1
6
]
P
7
O
u
t
p
u
t
S
E
L
s
i
g
n
a
l
“
L
”
o
f
M
3
5
5
0
1
O
u
t
p
u
t
R
E
S
E
T
s
i
g
n
a
l
o
f
M
3
5
5
0
1
(
N
o
t
e
)
N
o
t
e:
T
o
r
e
m
o
v
e
r
e
s
e
t
s
t
a
t
e
,
a
f
t
e
r
r
e
t
a
i
n
i
n
g
“
L
”
l
e
v
e
l
f
o
r
2
µs
o
r
m
o
r
e
,
o
u
t
p
u
t
“
H
”
l
e
v
e
l
w
h
e
n
C
L
K
s
i
g
n
a
l
=
“
L
”
.
316
FLD controller
Figure 2.7.21. Set-up procedure for FLD automatic display (2)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
T
d
i
s
p
,
T
o
f
f
1
a
n
d
T
o
f
f
2
t
i
m
e
s
e
t
-
u
p
1 1 0 0 1 0 0 0
b
7b
0T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
2
1
6
]
T
D
I
S
P
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
1
:
D
i
s
p
l
a
y
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
S
e
t
C
8
1
6
;
T
d
i
s
p
=
(
2
0
0
+
1
)
✕
c
o
u
n
t
s
o
u
r
c
e
=
6
4
3
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 1 1 1 1 0
b
7b
0T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
4
1
6
]
T
O
F
F
1
S
e
t
1
E
1
6
;
T
o
f
f
1
=
3
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
9
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
1 0 1 1 0 1 0 0
b
7b
0T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
6
1
6
]
T
O
F
F
2
S
e
t
B
4
1
6
;
T
o
f
f
2
=
1
8
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
5
7
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 0 1 1 1 1
b
7b
0F
L
D
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
5
8
1
6
]
F
L
D
D
P
S
e
t
1
5
=
“
d
i
g
i
t
n
u
m
b
e
r
–
1
”
.
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
0 1 0 1 0 0
b
7b
0F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
1
1
6
]
F
L
D
C
O
N
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
4
4
t
o
P
4
7
F
L
D
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
P
4
4
t
o
P
4
7
F
L
D
T
o
f
f
i
s
i
n
v
a
l
i
d
b
i
t
0
:
P
e
r
f
o
r
m
n
o
r
m
a
l
l
y
P
9
7
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
1
:
D
i
m
m
e
r
o
u
t
p
u
t
C
M
O
S
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
S
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
H
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
1
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
T
o
f
f
2
S
E
T
/
R
E
S
E
T
c
h
a
n
g
e
b
i
t
0
:
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
r
e
s
e
t
a
t
T
o
f
f
2
(
s
e
t
a
t
T
o
f
f
1
)
317
FLD controller
This page kept blank for layout purposes.
318
FLD controller
2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy)
The FLD controller can choose functions from those listed in Table 2.7.4. The circled items are described
in detail below. Figure 2.7.22 shows the connection example and Figure 2.7.23 shows the operation
timing, and Figures 2.7.24 and 2.7.27 show the set-up procedures.
Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp
Table 2.7.4. Selectable functions
Note 1: When selecting the FLD blanking interrupt, any one of 1 ✕ Tdisp, 2 ✕ Tdisp, or 3 ✕ Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The grada-
tion display control data is arranged at an address which is calculated by subtracting “7016”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF16”, the
pointer is reloaded and starts counting over again.
(4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71,
respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97).
(5) Input the OVFOUT output of the M35501FP to TB2IN (P72) and count the input signals as a
count source with Timer B2. Generate the Timer A0 interrupt at FLD display intervals and
confirm the value of Timer B2. If the value is incorrect, reset the M35501FP.
(6) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
I
t
e
mS
e
t
-
u
pS
e
t
-
u
p
O
I
t
e
m
T
s
c
a
n
c
o
n
t
r
o
l
(
N
o
t
e
1
)F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
yS
t
r
o
n
g
W
e
a
k
O
T
i
m
i
n
g
n
u
m
b
e
r1
6
-
t
i
m
i
n
g
3
2-
t
i
m
i
n
g
OP
9
7
d
i
m
m
e
r
o
u
t
p
u
tN
o
r
m
a
l
p
o
r
t
D
i
m
m
e
r
o
u
t
p
u
t
O
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
f
(
X
I
N
)
/
3
2
f
(
X
I
N
)
/
1
2
8
OH
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
-
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
Se
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
O
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
(
N
o
t
e
2
)N
o
t
s
e
l
e
c
t
i
n
g
Se
l
e
c
t
i
n
g
O
T
o
f
f
2
S
E
T
/
R
E
S
E
TR
e
s
e
t
a
t
T
o
f
f
2
Se
t
a
t
T
o
f
f
2
O
319
FLD controller
Figure 2.7.22. Connection example of FLD automatic display
D
i
g
i
t
(
1
6
)
F
l
u
o
r
e
s
c
e
n
t
d
i
s
p
l
a
y
(
F
L
D
)
P
3
0
–
P
3
7
P
1
0
–
P
1
7
P
0
0
–
P
0
7
P
2
0
–
P
2
7
S
e
g
m
e
n
t
(
5
2
)
M
3
0
2
1
8
G
r
o
u
p M
3
5
5
0
1
F
P
C
L
K
S
E
L
R
E
S
E
T
D
I
G
0
–
D
I
G
1
5
P
4
0
–
P
4
3
D
I
M
O
U
T
P
7
0
P
7
1
O
V
F
I
N
P
6
0
–
P
6
7
P
5
0
–
P
5
7
O
V
F
O
U
T
C
o
n
n
e
c
t
i
o
n
e
x
a
m
p
l
e
T
B
2
I
N
320
FLD controller
R
E
S
E
T
S
E
L
O
V
FI
N
O
V
FO
U
T
•
•
•
C
L
K
D
I
G
0
D
I
G
1
D
I
G
1
4
D
I
G
1
5
M
3
5
5
0
1
F
P
•
•
•
R
E
S
E
T
S
E
L
O
V
FI
N
O
V
FO
U
T
•
•
•
C
L
K
D
I
G
0
D
I
G
1
D
I
G
1
4
D
I
G
1
5
M
3
5
5
0
1
F
P
C
o
l
u
m
n
d
i
s
c
r
e
p
a
n
c
y
o
c
c
u
r
N
o
i
s
e
•
•
•
F
L
D0–
F
L
D5
1
(
P
00–
P
07,
P
10–
P
17,
P
20–
P
27,
P
30–
P
37,
P
40–
P
43,
P
50–
P
57,
P
60–
P
67)
M
3
0
2
1
8
G
r
o
u
p
C
o
r
r
e
c
t
op
e
r
a
t
i
o
n
e
x
a
m
p
l
e
I
n
co
r
r
e
c
t
op
e
r
a
t
i
o
n
e
x
a
m
p
l
e
F
L
D0–
F
L
D5
1
(
P
00–
P
07,
P
10–
P
17,
P
20–
P
27,
P
30–
P
37,
P
40–
P
43,
P
50–
P
57,
P
60–
P
67)
M
3
0
2
1
8
G
r
o
u
p
Figure 2.7.23. Operation timing of FLD automatic display
321
FLD controller
Figure 2.7.24. Set-up procedure for FLD automatic display (1)
1 1 1 1 1 1 1 1
b
7b
0
D
i
s
p
l
a
y
p
i
n
/
p
o
r
t
s
w
i
t
c
h
o
f
P
2
,
P
3
,
P
4
,
P
5
a
n
d
P
6
s
e
t
-
u
p
P
o
r
t
P
2
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
9
1
6
]
P
2
F
P
R
1 1 1 1 1 1 1 1
b
7b
0P
o
r
t
P
3
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
A
1
6
]
P
3
F
P
R
S
e
t
P
3
0
–
P
3
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
0
t
o
F
L
D
4
7
)
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
5
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
C
1
6
]
P
5
D
O
R
S
e
t
P
5
0
–
P
5
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
8
t
o
F
L
D
1
5
)
1 1 1 1 1 1 1 1
S
e
t
P
2
0
–
P
2
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
3
2
t
o
F
L
D
3
9
)
0 0 0 0 0 0 0 0
b
7b
0P
o
r
t
P
6
d
i
g
i
t
o
u
t
p
u
t
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
D
1
6
]
P
6
D
O
R
S
e
t
P
6
0
–
P
6
7
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
0
t
o
F
L
D
7
)
1 0 1 0 0 0 0 1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
s
e
t
-
u
p
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
0
0
:
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
0
:
1
6
t
i
m
i
n
g
m
o
d
e
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t
1
:
S
e
l
e
c
t
i
n
g
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
X
I
N
)
/
3
2
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
b
i
t
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
0 0 0 0 1 1 1 1
b
7b
0P
o
r
t
P
4
F
L
D
/
p
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
B
1
6
]
P
4
F
P
R
S
e
t
P
4
4
–
P
4
7
t
o
n
o
r
m
a
l
I
/
O
p
o
r
t
s
S
e
t
P
4
0
–
P
4
3
t
o
F
L
D
o
u
t
p
u
t
p
o
r
t
s
(
F
L
D
4
8
t
o
F
L
D
5
1
)
1 1
b
7b
0P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
E
F
1
6
]
P
D
7
S
e
t
P
7
1
t
o
o
u
t
p
u
t
p
o
r
t
(
f
o
r
S
E
L
s
i
g
n
a
l
o
f
M
3
5
5
0
1
)
S
e
t
P
7
0
t
o
o
u
t
p
u
t
p
o
r
t
(
f
o
r
R
E
S
E
T
s
i
g
n
a
l
o
f
M
3
5
5
0
1
)
M
3
5
5
0
1
i
n
i
t
i
a
l
i
z
a
t
i
o
n
0 0
b
7b
0P
o
r
t
P
7
[
A
d
d
r
e
s
s
0
3
E
D
1
6
]
P
7
O
u
t
p
u
t
S
E
L
s
i
g
n
a
l
“
L
”
o
f
M
3
5
5
0
1
O
u
t
p
u
t
R
E
S
E
T
s
i
g
n
a
l
o
f
M
3
5
5
0
1
(
N
o
t
e
)
N
o
t
e:
T
o
r
e
m
o
v
e
r
e
s
e
t
s
t
a
t
e
,
a
f
t
e
r
r
e
t
a
i
n
i
n
g
“
L
”
l
e
v
e
l
f
o
r
2
µs
o
r
m
o
r
e
,
o
u
t
p
u
t
“
H
”
l
e
v
e
l
w
h
e
n
C
L
K
s
i
g
n
a
l
=
“
L
”
.
322
FLD controller
Figure 2.7.25. Set-up procedure for FLD automatic display (2)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
s
e
t
-
u
p
1 1 1 1 1 1 1 1
b
7b
0
T
d
i
s
p
,
T
o
f
f
1
a
n
d
T
o
f
f
2
t
i
m
e
s
e
t
-
u
p
1 1 0 0 1 0 0 0
b
7b
0T
d
i
s
p
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
2
1
6
]
T
D
I
S
P
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
S
e
t
C
8
1
6
;
T
d
i
s
p
=
(
2
0
0
+
1
)
✕
c
o
u
n
t
s
o
u
r
c
e
=
6
4
3
µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 1 1 1 1 0
b
7b
0T
o
f
f
1
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
4
1
6
]
T
O
F
F
1
S
e
t
1
E
1
6
;
T
o
f
f
1
=
3
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
9
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
1 0 1 1 0 1 0 0
b
7b
0T
o
f
f
2
t
i
m
e
s
e
t
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
6
1
6
]
T
O
F
F
2
S
e
t
B
4
1
6
;
T
o
f
f
2
=
1
8
0
✕
c
o
u
n
t
s
o
u
r
c
e
=
5
7
6 µs
C
o
n
d
i
t
i
o
n
s
:•
f
(
X
I
N
)
=
1
0
M
H
z
•
C
o
u
n
t
s
o
u
r
c
e
=
f
(
X
I
N
)
/
3
2
=
3
.
2
µs
1 1 1 1 1 1 1 1
b
7b
0
0 0 0 0 1 1 1 1
b
7b
0F
L
D
d
a
t
a
p
o
i
n
t
e
r
[
A
d
d
r
e
s
s
0
3
5
8
1
6
]
F
L
D
D
P
S
e
t
1
5
=
“
d
i
g
i
t
n
u
m
b
e
r
–
1
”
.
C
o
n
t
i
n
u
e
d
t
o
t
h
e
n
e
x
t
p
a
g
e
0 1 0 1 0 0
b
7b
0F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
1
1
6
]
F
L
D
C
O
N
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
P
4
4
t
o
P
4
7
F
L
D
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
P
4
4
t
o
P
4
7
F
L
D
T
o
f
f
i
s
i
n
v
a
l
i
d
b
i
t
0
:
P
e
r
f
o
r
m
n
o
r
m
a
l
l
y
P
9
7
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
1
:
D
i
m
m
e
r
o
u
t
p
u
t
C
M
O
S
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
0
:
S
e
c
t
i
o
n
o
f
T
o
f
f
d
o
e
s
N
O
T
g
e
n
e
r
a
t
e
H
i
g
h
-
b
r
e
a
k
d
o
w
n
-
v
o
l
t
a
g
e
p
o
r
t
s
:
s
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
/
n
o
t
g
e
n
e
r
a
t
e
b
i
t
1
:
S
e
c
t
i
o
n
o
f
T
o
f
f
g
e
n
e
r
a
t
e
s
T
o
f
f
2
S
E
T
/
R
E
S
E
T
c
h
a
n
g
e
b
i
t
0
:
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
d
a
t
a
i
s
r
e
s
e
t
a
t
T
o
f
f
2
(
s
e
t
a
t
T
o
f
f
1
)
0 0 1 1
b
7b
0
T
i
m
e
r
B
2
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
9
D
1
6
]
T
B
2
M
R
Ev
e
n
t
c
o
u
n
t
e
r
m
o
d
e
(
T
i
m
e
r
B
2
)
a
n
d
f
u
n
c
t
i
o
n
s
s
e
t
-
u
p
0000
S
e
l
e
c
t
i
o
n
o
f
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
C
o
u
n
t
p
o
l
a
r
i
t
y
s
e
l
e
c
t
b
i
t
b
3
b
2
0
1
:
C
o
u
n
t
s
e
x
t
e
r
n
a
l
s
i
g
n
a
l
’
s
r
i
s
i
n
g
e
d
g
e
s
I
n
v
a
l
i
d
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
E
v
e
n
t
c
l
o
c
k
s
e
l
e
c
t
0
:
I
n
p
u
t
f
r
o
m
T
B
2
I
N
p
i
n
(
N
o
t
e
)
N
o
t
e:
S
e
t
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
t
o
“
0
”
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
323
FLD controller
T
i
m
e
r
A
0
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
9
6
1
6
]
T
A
0
M
R
Ti
m
e
r
m
o
d
e
(
T
i
m
e
r
A
0
)
a
n
d
f
u
n
c
t
i
o
n
s
s
e
t
-
u
p
S
e
l
e
c
t
i
o
n
o
f
t
i
m
e
r
m
o
d
e
P
u
l
s
e
o
u
t
p
u
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
0
:
P
u
l
s
e
i
s
n
o
t
o
u
t
p
u
t
(
T
A
0
O
U
T
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
G
a
t
e
f
u
n
c
t
i
o
n
s
e
l
e
c
t
b
i
t
b
4
b
3
0
0
:
0
1
:
G
a
t
e
f
u
n
c
t
i
o
n
n
o
t
a
v
a
i
l
a
b
l
e
(
T
A
0
I
N
p
i
n
i
s
a
n
o
r
m
a
l
p
o
r
t
p
i
n
)
0
(
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
i
n
t
i
m
e
r
m
o
d
e
)
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
b
i
t
b
7
b
6
0
1
:
f
8
0
b
7b
0
0000
b
7b
0
(
b
1
5
)(
b
8
)b
7b
0T
i
m
e
r
A
0
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
8
7
1
6
,
0
3
8
6
1
6
]
T
A
0
Se
t
3
2
4
0
1
6
Di
v
i
d
e
r
a
t
i
o
(
T
i
m
e
r
A
0
)
s
e
t
-
u
p
C
o
n
t
i
n
u
e
d
f
r
o
m
t
h
e
p
r
e
v
i
o
u
s
p
a
g
e
b
7b
0
(
b
1
5
)(
b
8
)b
7b
0T
i
m
e
r
B
2
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
9
5
1
6
,
0
3
9
4
1
6
]
T
B
2
S
e
t
F
F
F
F
1
6
Di
v
i
d
e
r
a
t
i
o
(
T
i
m
e
r
B
2
)
s
e
t
-
u
p
10
1
b
7b
0C
o
u
n
t
s
t
a
r
t
f
l
a
g
[
A
d
d
r
e
s
s
0
3
8
0
1
6
]
T
A
B
S
R
C
o
u
n
t
s
t
a
r
t
f
l
a
g
s
e
t
-
u
p
0
b
7b
0T
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
0
5
5
1
6
]
T
A
0
I
C
T
i
m
e
r
A
0
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
s
e
t
-
u
p
I
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
s
e
l
e
c
t
b
i
t
b
2
b
1
b
0
0
0
0
:
L
e
v
e
l
0
(
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
)
0
0
1
:
L
e
v
e
l
1
0
1
0
:
L
e
v
e
l
2
0
1
1
:
L
e
v
e
l
3
1
0
0
:
L
e
v
e
l
4
1
0
1
:
L
e
v
e
l
5
1
1
0
:
L
e
v
e
l
6
1
1
1
:
L
e
v
e
l
7
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
N
o
t
e
)
0
:
I
n
t
e
r
r
u
p
t
n
o
t
r
e
q
u
e
s
t
e
d
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
N
o
t
e
:
O
n
l
y
“
0
”
c
a
n
b
e
w
r
i
t
t
e
n
t
o
t
h
i
s
b
i
t
.
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
T
i
m
e
r
A
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
11
T
i
m
e
r
B
2
c
o
u
n
t
s
t
a
r
t
f
l
a
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
1
:
D
i
s
p
l
a
y
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
Figure 2.7.26. Set-up procedure for FLD automatic display (3)
324
FLD controller
T
A
0
i
n
t
e
r
r
u
p
t
r
o
u
t
i
n
e
P
u
s
h
re
g
i
s
t
e
r
s
a
n
d
a
n
y
o
t
h
e
r
s
e
t
-
u
p
R
T
I
T
i
m
e
r
B
2
d
a
t
a
c
h
e
c
k
?
0 0
b
7b
0
M
3
5
5
0
1
i
n
i
t
i
a
l
i
z
a
t
i
o
n
0 1
b
7b
0P
o
r
t
P
7
[
A
d
d
r
e
s
s
0
3
E
D
1
6
]
P
7
O
u
t
p
u
t
S
E
L
s
i
g
n
a
l
“
L
”
o
f
M
3
5
5
0
1
O
u
t
p
u
t
R
E
S
E
T
s
i
g
n
a
l
“
H
”
o
f
M
3
5
5
0
1
(
N
o
t
e
)
N
o
t
e:
T
o
r
e
m
o
v
e
r
e
s
e
t
s
t
a
t
e
,
a
f
t
e
r
r
e
t
a
i
n
i
n
g
“
L
”
l
e
v
e
l
f
o
r
2
µs
o
r
m
o
r
e
,
o
u
t
p
u
t
“
H
”
l
e
v
e
l
w
h
e
n
C
L
K
s
i
g
n
a
l
=
“
L
”
.
P
o
r
t
P
7
[
A
d
d
r
e
s
s
0
3
E
D
1
6
]
P
7
O
u
t
p
u
t
S
E
L
s
i
g
n
a
l
“
L
”
o
f
M
3
5
5
0
1
O
u
t
p
u
t
R
E
S
E
T
s
i
g
n
a
l
“
L
”
o
f
M
3
5
5
0
1
S
e
t
d
i
s
p
l
a
y
d
a
t
a
t
o
F
L
D
a
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
R
A
M
b
7b
0
(
b
1
5
)(
b
8
)b
7b
0T
i
m
e
r
B
2
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
9
5
1
6
,
0
3
9
4
1
6
]
T
B
2
S
e
t
F
F
F
F
1
6
Di
v
i
d
e
r
a
t
i
o
(
T
i
m
e
r
B
2
)
s
e
t
-
u
p
1
b
7b
0C
o
u
n
t
s
t
a
r
t
f
l
a
g
[
A
d
d
r
e
s
s
0
3
8
0
1
6
]
T
A
B
S
R
C
o
u
n
t
s
t
a
r
t
f
l
a
g
s
e
t
-
u
p
T
i
m
e
r
A
0
c
o
u
n
t
s
t
a
r
t
f
l
a
g
1
:
S
t
a
r
t
s
c
o
u
n
t
i
n
g
1
1
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
a
r
t
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
1
:
D
i
s
p
l
a
y
0
b
7b
0F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
[
A
d
d
r
e
s
s
0
3
5
0
1
6
]
F
L
D
M
F
L
D
d
i
s
p
l
a
y
s
t
o
p
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
P
o
p
re
g
i
s
t
e
r
s
C
o
r
r
e
c
t
d
a
t
a
(
F
E
1
6
)
I
n
co
r
r
e
c
t
d
a
t
a
(
e
x
c
e
p
t
F
E
1
6
)
Figure 2.7.27. Set-up procedure for FLD automatic display when detecting column discrepancy
325
FLD controller
2.7.7 Precautions for FLD controller
(1) Set a value of “0316” or more to the Toff1 time set register.
(2) When displaying in the gradation display mode, select the 16-timing mode with the timing number
control bit.
326
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.8 A-D Converter
Table 2.8.1. Conversion time every operation clock
Note 1: The number of conversion cycles per one analog input pin.
Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)
2.8.1 Overview
The A-D converter used in the M30218 group operates on a successive conversion basis. The following
is an overview of the A-D converter.
(1) Mode
The A-D converter operates in one of five modes:
(a) One-shot mode
Carries out A-D conversion on input level of one specified pin only once.
(b) Repetition mode
Repeatedly carries out A-D conversion on input level of one specified pin.
(c) One-shot sweep mode
Carries out A-D conversion on input level of two or more specified pins only once.
(d) Repeated sweep mode 0
Repeatedly carries out A-D conversion on input level of two or more pins.
(e) Repeated sweep mode 1
Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from
the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of
conversion times.
(2) Operation clock
The operation clock can be selected from the following: fAD, divide-by-2 fAD, and divide-by-4 fAD. The
fAD frequency is equal to that of the CPU’s main clock.
(3) Conversion time
Number of conversion for A-D convertor varies depending on resolution as given. Table 2.8.1 shows
relation between the A-D converter operation clock and conversion time.
Sample & Hold function selected:
33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution
No Sample & Hold function:
59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution
Frequency selection bit 0
A-D converter's operation clock
Min. conversion
cycles (Note 1)
Min. conversion
time (Note 2)
8-bit mode
8-bit mode
10-bit mode
10-bit mode
01
φ
AD
=4
f
AD
φ
AD
=2
f
AD
28 X φ
AD
33 X φ
AD
11.2µs
13.2µs 6.6µs
5.6µs
Frequency selection bit 1 0 1
Invalid
φ
AD
= f
AD
2.8µs
3.3µs
327
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(4) Functions selection
(a) Sample & Hold function
Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D
conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3
cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock
for A-D conversion to 1 MHz or higher.
(b) 8-bit A-D to 10-bit A-D switching function
Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8
higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolu-
tion and 8-bit resolution are given below:
10-bit resolution (Vref X n / 210 ) – (Vref X 0.5 / 1010 ) (n = 1 to 1023), 0 (n = 0)
8-bit resolution (Vref X n / 28 ) – (Vref X 0.5 / 210 ) (n = 1 to 255), 0 (n = 0)
(c) Connecting or cutting Vref
Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the
microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1
µs or longer after connecting Vref.
The following are exsamples in which functions (a) through (c) are selected:
• One-shot mode......................................................................................................................... P332
• Repeat mode, software trigger ................................................................................................. P334
• One-shot sweep mode, software trigger................................................................................... P336
• Repeated sweep mode 0, software trigger............................................................................... P338
• Repeated sweep mode 1, software trigger............................................................................... P340
328
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.1. Memory map of A-D converter-related registers
(5) Input to A-D converter and direction register
To use the A-D converter, set the direction register of the relevant port to input.
(6) Pins related to A-D converter
(a) AN0 pin through AN7 pin Input pins of the A-D converter
(b) AVcc pin Power source pin of the analog section
(c) VREF pin Input pin of reference voltage
(d) AVss pin GND pin of the analog section
(7) A-D converter and related registers
Figure 2.8.1 shows the memory map of A-D converter-related registers, and Figures 2.8.2 through
2.8.4 show A-D converter-related registers.
004E
16
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D4
16
03D5
16
03D6
16
03D7
16
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
A-D control register 2 (ADCON2)
A-D conversion interrupt control register (ADIC)
329
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.2. A-D converter-related registers (1)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
N
o
t
e
)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
A
D
C
O
N
00
3
D
6
1
6
0
0
0
0
0
X
X
X
2
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
b
i
t0
0
0
:
A
N
0
i
s
s
e
l
e
c
t
e
d
0
0
1
:
A
N
1
i
s
s
e
l
e
c
t
e
d
0
1
0
:
A
N
2
i
s
s
e
l
e
c
t
e
d
0
1
1
:
A
N
3
i
s
s
e
l
e
c
t
e
d
1
0
0
:
A
N
4
i
s
s
e
l
e
c
t
e
d
1
0
1
:
A
N
5
i
s
s
e
l
e
c
t
e
d
1
1
0
:
A
N
6
i
s
s
e
l
e
c
t
e
d
1
1
1
:
A
N
7
i
s
s
e
l
e
c
t
e
d
C
H
0
C
H
1
C
H
2
A
-
D
o
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t
00
0
:
O
n
e
-
s
h
o
t
m
o
d
e
0
1
:
R
e
p
e
a
t
m
o
d
e
1
0
:
S
i
n
g
l
e
s
w
e
e
p
m
o
d
e
1
1
:
R
e
p
e
a
t
s
w
e
e
p
m
o
d
e
0
R
e
p
e
a
t
s
w
e
e
p
m
o
d
e
1
M
D
0
M
D
1
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
.
A
D
S
TA
-
D
c
o
n
v
e
r
s
i
o
n
s
t
a
r
t
f
l
a
g0
:
A
-
D
c
o
n
v
e
r
s
i
o
n
d
i
s
a
b
l
e
d
1
:
A
-
D
c
o
n
v
e
r
s
i
o
n
s
t
a
r
t
e
d
F
r
e
q
u
e
n
c
y
s
e
l
e
c
t
b
i
t
00
:
f
A
D
/
4
i
s
s
e
l
e
c
t
e
d
1
:
f
A
D
/
2
i
s
s
e
l
e
c
t
e
d
C
K
S
0
W
R
b
2
b
1
b
0
b
4
b
3
N
o
t
e
:
I
f
t
h
e
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
s
r
e
w
r
i
t
t
e
n
d
u
r
i
n
g
A
-
D
c
o
n
v
e
r
s
i
o
n
,
t
h
e
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
.
0
330
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.3. A-D converter-related registers (2)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
N
o
t
e
)
S
y
m
b
o
l
A
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
A
D
C
O
N
10
3
D
7
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
l
b
7b
6b
5b
4b
3b
2b
1b
0
A
-
D
s
w
e
e
p
p
i
n
s
e
l
e
c
t
b
i
t
S
C
A
N
0
S
C
A
N
1
M
D
2
B
I
T
S8
/
1
0
-
b
i
t
m
o
d
e
s
e
l
e
c
t
b
i
t0
:
8
-
b
i
t
m
o
d
e
1
:
1
0
-
b
i
t
m
o
d
e
V
C
U
TV
r
e
f
c
o
n
n
e
c
t
b
i
t
A
-
D
o
p
e
r
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
b
i
t
10
:
A
n
y
m
o
d
e
o
t
h
e
r
t
h
a
n
r
e
p
e
a
t
s
w
e
e
p
m
o
d
e
1
1
:
R
e
p
e
a
t
s
w
e
e
p
m
o
d
e
1
0
:
V
r
e
f
n
o
t
c
o
n
n
e
c
t
e
d
1
:
V
r
e
f
c
o
n
n
e
c
t
e
d
M
u
s
t
a
l
w
a
y
s
b
e
“
0
”
.
WR
W
h
e
n
s
i
n
g
l
e
s
w
e
e
p
a
n
d
r
e
p
e
a
t
s
w
e
e
p
m
o
d
e
0
a
r
e
s
e
l
e
c
t
e
d
0
0
:
A
N
0
,
A
N
1
(
2
p
i
n
s
)
0
1
:
A
N
0
t
o
A
N
3
(
4
p
i
n
s
)
1
0
:
A
N
0
t
o
A
N
5
(
6
p
i
n
s
)
1
1
:
A
N
0
t
o
A
N
7
(
8
p
i
n
s
)
b
1
b
0
W
h
e
n
r
e
p
e
a
t
s
w
e
e
p
m
o
d
e
1
i
s
s
e
l
e
c
t
e
d
0
0
:
A
N
0
(
1
p
i
n
)
0
1
:
A
N
0
,
A
N
1
(
2
p
i
n
s
)
1
0
:
A
N
0
t
o
A
N
2
(
3
p
i
n
s
)
1
1
:
A
N
0
t
o
A
N
3
(
4
p
i
n
s
)
b
1
b
0
F
r
e
q
u
e
n
c
y
s
e
l
e
c
t
b
i
t
10
:
f
A
D
/
2
o
r
f
A
D
/
4
i
s
s
e
l
e
c
t
e
d
1
:
f
A
D
i
s
s
e
l
e
c
t
e
d
C
K
S
1
N
o
t
e
:
I
f
t
h
e
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
s
r
e
w
r
i
t
t
e
n
d
u
r
i
n
g
A
-
D
c
o
n
v
e
r
s
i
o
n
,
t
h
e
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
.
00
331
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.4. A-D converter-related registers (3)
E
i
g
h
t
l
o
w
-
o
r
d
e
r
b
i
t
s
o
f
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
N
o
t
e
)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
A
D
C
O
N
20
3
D
41
6X
X
X
X
X
X
X
02
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
lWR
b
7b
6b
5b
4b
3b
2b
1b
0
A
-
D
c
o
n
v
e
r
s
i
o
n
m
e
t
h
o
d
s
e
l
e
c
t
b
i
t0
W
i
t
h
o
u
t
s
a
m
p
l
e
a
n
d
h
o
l
d
1
W
i
t
h
s
a
m
p
l
e
a
n
d
h
o
l
d
S
M
P
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
A
-
D
r
e
g
i
s
t
e
r
i
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
A
D
i
(
i
=
0
t
o
7
)0
3
C
01
6
t
o
0
3
C
F1
6I
n
d
e
t
e
r
m
i
n
a
t
e
F
u
n
c
t
i
o
nWR
(
b
1
5
)b
7b
7b
0b
0
(
b
8
)
•
D
u
r
i
n
g
1
0
-
b
i
t
m
o
d
e
T
w
o
h
i
g
h
-
o
r
d
e
r
b
i
t
s
o
f
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
•
D
u
r
i
n
g
8
-
b
i
t
m
o
d
e
W
h
e
n
r
e
a
d
,
t
h
e
c
o
n
t
e
n
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
N
o
t
e
:
I
f
t
h
e
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
s
r
e
w
r
i
t
t
e
n
d
u
r
i
n
g
A
-
D
c
o
n
v
e
r
s
i
o
n
,
t
h
e
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
i
s
i
n
d
e
t
e
r
m
i
n
a
t
e
.
332
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In one-shot mode, choose functions from those listed in Table 2.8.2. Operations of the circled items are
described below. Figure 2.8.5 shows the operation timing, and Figure 2.8.6 shows the set-up procedure.
2.8.2 Operation of A-D converter (one-shot mode)
Figure 2.8.5. Operation timing of one-shot mode
Operation
Table 2.8.2. Choosed functions
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating.
(2) After A-D conversion is completed, the content of the successive comparison register (con-
version result) is transmitted to A-D register i. At this time, the A-D conversion interrupt re-
quest bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter
stops operating.
Item Set-up
Operation clock
φAD Divided-by-4 fAD / divided-
by-2 fAD / fAD
8-bit / 10-bit
Sample & Hold Not activated
Activated
O
O
Resolution
Analog input pin One of AN0 pin to AN7 pin
O
O
A-D conversion
start flag
“1”
“0”
A-D conversion
interrupt request
bit
A-D register i
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Result
φ
AD
8-bit resolution : 28 φ
AD
cycles
10-bit resolution : 33 φ
AD
cycles
Set to “1” by software
(1) Start A-D conversion (2) A-D conversion is complete
Note: When φ
AD
frequency is less than 1MH
Z
, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φ
AD
cycles for 8-bit resolution and 59 φ
AD
cycles for 10-bit resolution.
333
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.6. Set-up procedure of one-shot mode
b7 b0
1
Setting A-D conversion start flag
A-D control register 0 [Address 03D6
16
]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Reading conversion result
Eight low-order bits of A-D conversion result
b7 b0
(b15) (b8)b7 b0
A-D register 0 [Address 03C1
16
, 03C0
16
] AD0
A-D register 1 [Address 03C3
16
, 03C2
16
] AD1
A-D register 2 [Address 03C5
16
, 03C4
16
] AD2
A-D register 3 [Address 03C7
16
, 03C6
16
] AD3
A-D register 4 [Address 03C9
16
, 03C8
16
] AD4
A-D register 5 [Address 03CB
16
, 03CA
16
] AD5
A-D register 6 [Address 03CD
16
, 03CC
16
] AD6
A-D register 7 [Address 03CF
16
, 03CE
16
] AD7
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Start A-D conversion
Stop A-D conversion
b7 b0
Setting A-D control register 0 and A-D control register 1
A-D control register 0 [Address 03D6
16
]
ADCON0
Analog input pin select bit (Note)
0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected
b2 b1 b0
b7 b0
A-D control register 1 [Address 03D7
16
]
ADCON1
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in one-shot mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
One-shot mode is selected (Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
0000
Invalid in one-shot mode
Vref connect bit
1 : Vref connected
Nothing is arranged for these bits.
Fix “0” to these bits.
00 01
b7 b0
Selecting Sample and hold
A-D control register 2 [Address 03D4
16
]
ADCON2
A-D conversion method select bit
1 : With sample and hold
1
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
334
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In repeat mode, choose functions from those listed in Table 2.8.3. Operations of the circled items are
described below. Figure 2.8.7 shows timing chart, and Figure 2.8.8 shows the set-up procedure.
2.8.3 Operation of A-D Converter (in repeat mode)
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating.
(2) After the first conversion is completed, the content of the successive comparison register
(conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit
does not go to “1”.
(3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by
software. The conversion result is transmitted to A-D register i every time a conversion is
completed.
Table 2.8.3. Choosed functions
Operation
Figure 2.8.7. Operation timing of repeat mode
A-D conversion
start flag “1”
“0”
A-D register i Result
Set to “1” by software
φAD
8-bit resolution : 28
φAD
cycles
10-bit resolution : 33
φAD
cycles
(1) Start A-D conversion (2) Conversion result is transferred to the A-D register
(3) A-D conversion
is complete
Cleared to “0” by software
A-D conversion
Result
Stop Convert Convert
Convert
Stop
Note: When
φAD
frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49
φAD
cycles for 8-bit resolution and 59
φAD
cycles
for 10-bit resolution.
8-bit resolution : 28
φAD
cycles
10-bit resolution : 33
φAD
cycles
Item Set-up
Operation clock
φ
AD
Divided-by-4 f
AD
/ divided-
by-2 f
AD
/ f
AD
8-bit / 10-bit
Sample & Hold Not activated
Activated
O
O
Resolution
Analog input pin One of AN
0
pin
to AN
7
pin
O
O
335
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.8. Set-up procedure of repeat mode
b7 b0
1
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Transmitting conversion result to A-D register i
Eight low-order bits of A-D conversion result
b7 b0
(b15) (b8)b7 b0
A-D register 0 [Address 03C116, 03C016] AD0
A-D register 1 [Address 03C316, 03C216] AD1
A-D register 2 [Address 03C516, 03C416] AD2
A-D register 3 [Address 03C716, 03C616] AD3
A-D register 4 [Address 03C916, 03C816] AD4
A-D register 5 [Address 03CB16, 03CA16] AD5
A-D register 6 [Address 03CD16, 03CC16] AD6
A-D register 7 [Address 03CF16, 03CE16] AD7
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
b7 b0
Setting A-D control register 0 and A-D control register 1
A-D control register 0 [Address 03D6 16]
ADCON0
Analog input pin select bit (Note)
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
b2 b1 b0
b7 b0 A-D control register 1 [Address 03D7 16]
ADCON1
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Repeat mode is selected (Note)
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
0001
Invalid in Repeat mode
Vref connect bit
1 : Vref connected
Nothing is arranged for these bits.
Fix “0” to these bits
00 01
Nothing is arranged for this bit.
Fix “0” to this bit.
Start A-D conversion
b7 b0
0
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
b7 b0
Selecting Sample and hold
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
1
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
336
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In single sweep mode, choose functions from those listed in Table 2.8.4. Operations of the circled items
are described below. Figure 2.8.9 shows timing chart, and Figure 2.8.10 shows the set-up procedure.
2.8.4 Operation of A-D Converter (in single sweep mode)
Figure 2.8.9. Operation timing of single sweep mode
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion
on voltage input to the AN0 pin.
(2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to A-D register 0. The A-D
converter converts all analog input pins selected by the user. The conversion result is trans-
mitted to A-D register i corresponding to each pin, every time conversion on one pin is com-
pleted.
(3) When the A-D conversion on all the analog input pins selected is completed, the A-D conver-
sion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”.
The A-D converter stops operating.
Table 2.8.4. Choosed functions
Item ItemSet-up Set-up
Operation clock
φ
AD Divided-by-4 fAD / divided-
by-2 fAD / fAD
8-bit / 10-bit
O
Resolution
Analog input pin AN0 and AN1 (2 pins) / AN0
to AN3 (4 pins) / AN0 to AN5
(6 pins) / AN0 to AN7 (8 pins)
O
O
Sample & Hold Not activated
ActivatedO
Cleared to “0” when interrupt request is accepted, or cleared by software
A-D conversion
start flag “1”
“0”
A-D register 0
A-D register 1
φAD
A-D register i Result
Result
Result
Set to “1” by software
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(1) Start A-D conversion After A-D conversion on AN0 pin is complete,
A-D converter begins converting all pins selected A-D conversion
is complete
(2)
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
(3)
A-D conversion
interrupt request
bit
“1”
“0”
337
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.10. Set-up procedure of single sweep mode
b7 b0
1
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Reading conversion result
Eight low-order bits of A-D conversion result
b7 b0
(b15) (b8)b7 b0
A-D register 0 [Address 03C116, 03C016] AD0
A-D register 1 [Address 03C316, 03C216] AD1
A-D register 2 [Address 03C516, 03C416] AD2
A-D register 3 [Address 03C716, 03C616] AD3
A-D register 4 [Address 03C916, 03C816] AD4
A-D register 5 [Address 03CB16, 03CA16] AD5
A-D register 6 [Address 03CD16, 03CC16] AD6
A-D register 7 [Address 03CF16, 03CE16] AD7
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Start A-D conversion
Stop A-D conversion
b7 b0
Setting A-D control register 0 and A-D control register 1
A-D control register 0
[Address 03D616] ADCON0
A-D sweep pin select bit (Note)
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
b7 b0 A-D control register 1 [Address 03D7 16]
ADCON1
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in Single sweep mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Single sweep mode is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
0010
Vref connect bit
1 : Vref connected
00 01
Invalid in single sweep mode
b7 b0
Selecting Sample and hold
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
1
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Nothing is arranged for these bits.
Fix “0” to these bits.
338
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In repeat sweep mode 0, choose functions from those listed in Table 2.8.5. Operations of the circled items
are described below. Figure 2.8.11 shows timing chart, and Figure 2.8.12 shows the set-up procedure.
2.8.5 Operation of A-D Converter (in repeat sweep mode 0)
Operation
Table 2.8.5. Choosed functions
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion
on voltage input to the AN0 pin.
(2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to A-D register 0.
(3) The A-D converter converts all pins selected by the user. The conversion result is transmitted
to A-D register i corresponding to each pin every time A-D conversion on the pin is com-
pleted. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by
software.
Figure 2.8.11. Operation timing of repeat sweep mode 0
Item ItemSet-up Set-up
Operation clock
φ
AD Divided-by-4 fAD / divided-
by-2 fAD / fAD
8-bit / 10-bit
O
Resolution
Analog input pin AN0 and AN1 (2 pins) / AN0
to AN3 (4 pins) / AN0 to AN5
(6 pins) / AN0 to AN7 (8 pins)
O
O
Sample & Hold Not activated
ActivatedO
(2) AN1 conversion begins after AN0
conversion is complete
A-D
conversion
start flag “1”
“0”
A-D register 0
A-D register 1
φAD
A-D register i Result
Result
Result
8-bit resolution : 28
φAD
cycles
10-bit resolution : 33
φAD
cycles 8-bit resolution : 28
φAD
cycles
10-bit resolution : 33
φAD
cycles
(3) Consecutive conversion A-D conversion
is complete
(1) Start A-D conversion
Set to “1” by software. Cleared to “0” by software
Note: When
φAD
frequency is less than 1MH
Z
, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49
φAD
cycles for 8-bit resolution and 59
φAD
cycles for 10-bit resolution.
(4)
339
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.12. Set-up procedure of repeat sweep mode 0
b7 b0
1
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Transmitting conversion result to A-D register i
Eight low-order bits of A-D conversion result
b7 b0
(b15) (b8)b7 b0
A-D register 0 [Address 03C116, 03C016] AD0
A-D register 1 [Address 03C316, 03C216] AD1
A-D register 2 [Address 03C516, 03C416] AD2
A-D register 3 [Address 03C716, 03C616] AD3
A-D register 4 [Address 03C916, 03C816] AD4
A-D register 5 [Address 03CB16, 03CA16] AD5
A-D register 6 [Address 03CD16, 03CC16] AD6
A-D register 7 [Address 03CF16, 03CE16] AD7
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Start A-D conversion
b7 b0
0
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
b7 b0
Selecting Sample and hold
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
b7 b0
Setting A-D control register 0 and A-D control register 1
A-D control register 0
[Address 03D616] ADCON0
A-D sweep pin select bit (Note)
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
b7 b0 A-D control register 1 [Address 03D716]
ADCON1
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat sweep mode 0)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Repeat sweep mode 0 is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
0011
Vref connect bit
1 : Vref connected
00 01
Invalid in repeat sweep mode 0
1
Repeatedly carries out A-D conversion on pins
selected through the A-D sweep pin select bit.
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
Nothing is arranged for these bits.
Fix “0” to these bits.
340
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.8.6 Operation of A-D Converter (in repeat sweep mode 1)
Figure 2.8.14. Operation timing of repeat sweep mode 1
In repeat sweep mode 1, choose functions from those listed in Table 2.8.6. Operations of the circled items are
described below. Figure 2.8.13 shows ANi pin's sweep sequence, Figure 2.8.14 shows timing chart, and Figure
2.8.15 shows the set-up procedure.
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage
input to the AN0 pin.
(2) After the A-D conversion on voltage input to the AN 0 pin is completed, the content of the successive
comparison register (conversion result) is transmitted to A-D register 0.
(3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter
carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conver-
sion from the AN0 pin again. (See Figure 2.8.13.) The conversion result is transmitted to A-D register i
every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”.
Table 2.8.6. Choosed functions
Figure 2.8.13. ANi pin's sweep sequence in repeat sweep mode 1
Item ItemSet-up Set-up
Operation clock φ
AD
Divided-by-4 f
AD
/ divided-
by-2 f
AD
/ f
AD
8-bit / 10-bit
O
Resolution
Analog input pin An
0
(1 pin) / AN
0
and AN
1
(2
pins) / AN
0
to AN
2
(3 pins) /
AN
0
to AN
3
(4 pins)
O
O
Sample & Hold Not activated
Activated
O
When AN
0
is selected
Converted analog input pin
Time
0000000000
1234567
12
.
.
.
When AN
0
, AN
1
are selected
Converted analog input pin
Time
0000000
1111111
234567
.
.
.
0
2
Converted analog input pin
Time
0000000
222222
34567
.
.
.
3
111111
When AN
0
to AN
2
are selected
Converted analog input pin
Time
000000
33332
4567
.
.
.
11111
22223
4
When AN
0
to AN
3
are selected
A-D
conversion
start flag “1”
“0”
A-D register 0
A-D register 1
φAD
A-D register 2
Result
Result
Result
Set to “1” by software
Result
Cleared to “0” by software
(2) (3) Consecutive conversion
8-bit resolution :
28
φAD
cycles
10-bit resolution :
33
φAD
cycles
A-D
conversion
is complete
(4)
Conversion result is
transfered to A-D
conversion register 0
Note: When
φ
AD
frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49
φ
AD
cycles for 8-bit resolution and 59
φ
AD
cycles for 10-bit resolution.
8-bit resolution :
28
φAD
cycles
10-bit resolution :
33
φAD
cycles
8-bit resolution :
28
φAD
cycles
10-bit resolution :
33
φAD
cycles
8-bit resolution :
28
AD
cycles
10-bit resolution :
33
AD
cycles
(1) Start AN
0
pin conversion
341
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.15. Set-up procedure of repeat sweep mode 1
b7 b0
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
1 : A-D conversion started
Transmitting conversion result to A-D register i
Eight low-order bits of A-D conversion result
b7 b0
(b15) (b8)b7 b0
A-D register 0 [Address 03C116, 03C016] AD0
A-D register 1 [Address 03C316, 03C216] AD1
A-D register 2 [Address 03C516, 03C416] AD2
A-D register 3 [Address 03C716, 03C616] AD3
A-D register 4 [Address 03C916, 03C816] AD4
A-D register 5 [Address 03CB16, 03CA16] AD5
A-D register 6 [Address 03CD16, 03CC16] AD6
A-D register 7 [Address 03CF16, 03CE16] AD7
During 10-bit mode
Two high-order bits of A-D conversion result
During 8-bit mode
When read, the content is indeterminate
Start A-D conversion
b7 b0
0
Setting A-D conversion start flag
A-D control register 0 [Address 03D6 16]
ADCON0
A-D conversion start flag
0 : A-D conversion disabled
Stop A-D conversion
b7 b0
Selecting Sample and hold
A-D control register 2 [Address 03D4 16]
ADCON2
A-D conversion method select bit
1 : With sample and hold
b7 b0
Setting A-D control register 0 and A-D control register 1
A-D control register 0
[Address 03D616] ADCON0
A-D sweep pin select bit (Note)
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
b1 b0
b7 b0 A-D control register 1 [Address 03D7 16]
ADCON1
A-D operation mode select bit 1 (Note)
0 (Must always be “0” in repeat sweep mode 1)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Repeat sweep mode 1 is selected
(Note)
Nothing is arranged for this bit.
Fix “0” to this bit.
A-D conversion start flag
0 : A-D conversion disabled
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
0011
Vref connect bit
1 : Vref connected
00 11
Invalid in repeat sweep mode 1
1
Converts non-selected pin after converting pins
selected through the A-D sweep pin select bit.
Note: Rewrite to analog input pin select bit after changing A-D operation mode.
1
Nothing is arranged for these bits.
Fix “0” to these bits.
342
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.8.7 Precautions for A-D Converter
Figure 2.8.16. Use of capacitors to reduce noice
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1,
and to bit 0 of A-D control register 2 when A-D conversion is stopped.
In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after
an elapse of 1 µs or longer.
(2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the VREF
pin from an independent source. It is recommended to connect a capacitor between the AVss
pin and the AVcc pin, between the AVss pin and the VREF pin, and between the AVss pin and
the analog input pin (ANi). Figure 2.8.16 shows an example of connecting the capacitors to
these pins.
(3) Set the direction register of the the port corresponding to a pin to be used as an analog input
pin to input.
(4) Rewrite to analog input pin after changing A-D operation mode. The two cannot be set at the
same time.
(5) When using the one-shot or single sweep mode
Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
(6) When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
AV
SS
AV
CC
V
REF
AN
i
Microcomputer
C1 C2
C3
C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF
(for reference)
Use thick and shortest possible wiring
to connect capacitors.
Note
1:
Note
2:
V
CC
343
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) The A-D converter compares the reference voltage (Vref) generated internally based on the
contents of the successive comparison register with the analog input voltage (VIN) input from
the analog input pin. Each bit of the comparison result is stored in the successive comparison
register until analog-to-digital conversion (successive comparison method) is complete. If a
trigger occurs, the A-D converter carries out the following:
1. Fixes bit 9 of the successive comparison register.
Compares Vref with VIN: [In this instance, the contents of the successive comparison
register are “10000000002” (default).]
Bit 9 of the successive comparison register varies depending on the comparison re-
sult as follows.
If Vref < VIN, then “1” is assigned to bit 9.
If Vref > VIN, then “0” is assigned to bit 9.
2. Fixes bit 8 of the successive comparison register.
Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN.
Bit 8 of the successive comparison register varies depending on the comparison
result as follows:
If Vref < VIN, then “1” is assigned to bit 8.
If Vref > VIN, then “0” is assigned to bit 8.
3. Fixes bit 7 through bit 0 of the successive comparison register.
Carries out step 2 above on bit 7 through bit 0.
After bit 0 is fixed, the contents of the successive comparison register (conversion
result) are transmitted to A-D register i.
Vref is generated based on the latest content of the successive comparison register. Table
2.8.7 shows the relationship of the successive comparison register contents and Vref. Table
2.8.8 shows how the successive comparison register and Vref vary while A-D conversion is in
progress. Figure 2.8.17 shows theoretical A-D conversion characteristics.
2.8.8 Method of A-D Conversion (10-bit mode)
Table 2.8.7. Relationship of the successive comparison register contents and Vref
Successive approximation register : n Vref (V)
x–
1024
V
REF
2048
V
REF
n
00
1 to1023
344
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.8.17. Theoretical A-D conversion characteristics (10-bit mode)
Table 2.8.8. Variation of the successive comparison register and Vref while A-D conversion is in
progress (10-bit mode)
1
1
n
9
000000000
000000000
100000000
n
9
n
8
10000000
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
n
1
0
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
n
1
n
0
b9 b0
1st comparison result
2nd comparison result
Successive approximation register V
ref
change
A-D converter stopped
1st comparison
2nd comparison
3rd comparison
10th comparison
Conversion complete
V
REF
± ±
2
V
REF
4
V
REF
8
V
REF
± ...... ± V
REF
1024 – 2048
V
REF
[V]
2[V]
–
2
V
REF
2048
V
REF
[V]
± ±
2
V
REF
4
V
REF
8
V
REF
– 2048
V
REF
[V]
4
n
9
= 1 +
n
9
= 0 –
n
8
= 1 +
8
V
REF
n
8
= 0 –
±
2
V
REF
4
V
REF
– 2048
V
REF
[V]
4
V
REF
V
REF
8
V
REF
This data transfers to the bit 0
to bit 9 of A-D register.
000
16
001
16
002
16
003
16
3FE
16
3FF
16
Result of A-D conversion
Analog input voltage
V
REF
1024 x 1 V
REF
1024 x 2 V
REF
1024x 3 x 1021
V
REF
1024 V
REF
1024 x 1022 V
REF
1024 x 1023 V
REF
V
REF
1024 x 0.5
Theoretical A-D
conversion characteristic
Ideal A-D conversion
characteristic
0
345
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D
conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter,
the voltage compared is different by 3 VREF/2048 (see what are underscored in Table 2.8.9),
and differences in stepping points of output codes occur as shown in Figure 2.8.18.
2.8.9 Method of A-D Conversion (8-bit mode)
Figure 2.8.18. The level conversion characteristics of 8-bit mode and 8-bit A-D converter
Table 2.8.9. The comparison voltage in 8-bit mode compared to 8-bit A-D converter
Comparison
voltage
Vref
8-bit mode 8-bit A-D converter
–
2
8
V
REF
2
10
V
REF
nx 0.5 x –
2
8
V
REF
2
8
V
REF
nx 0.5
n = 0
n = 1 to 255
00
x
07
05
06
03
00
02
Analog input voltage (mV)
Output code
(Result of A-D conversion)
02
01
00
Analog input voltage (mV)
Output code
(Result of A-D conversion)
04
02
01
00
01
10-bit
mode
8-bit
mode
8bit-mode
10bit-mode
08
09
10 30
17.5 37.5
(Note)
Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V)
Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V)
Note: Differences in stepping points of output code for analog input voltage.
346
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 2.8.10. Variation of the successive comparison register and Vref while A-D conversion is in
progress (8-bit mode)
Figure 2.8.19. Theoretical A-D conversion characteristics (8-bit mode)
1
1
n
9
000000000
000000000
100000000
n
9
n
8
10000000
n
9
n
8
n
7
n
6
n
5
n
4
n
3
100
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
00
b9 b0
1st comparison result
2nd comparison result
Successive approximation register
V
ref
change
A-D converter stopped
1st comparison
2nd comparison
3rd comparison
8th comparison
Conversion
complete
± ±
2
V
REF
4
V
REF
8
V
REF
± ...... ± V
REF
256 – 2048
V
REF
[V]
2
V
REF
[V]
–
2
V
REF
2048
V
REF
[V]
±
2
V
REF
4
V
REF
– 2048
V
REF
[V]
± ±
2
V
REF
4
V
REF
8
V
REF
– 2048
V
REF
[V]
4
4
V
REF
n
9
= 1 + V
REF
n
9
= 0 –
8
V
REF
n
8
= 1 +
8
V
REF
n
8
= 0 –
This data transfers to bit 0 to
bit 7 of A-D register.
00
16
01
16
02
16
03
16
FE
16
FF
16
Result of A-D conversion
Analog input voltage
x 2
V
REF
256 V
REF
256 x 3 x 4
V
REF
256 V
REF
256 x 254 V
REF
256 x 255 V
REF
V
REF
2048 x 3
Theoretical A-D conversion
characteristic of general 8-bit
A-D converter
0
V
REF
256 x 1
Theoretical A-D conversion
characteristic in the 8-bit mode
347
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.8.10 Absolute Accuracy and Differential Non-Linearity Error
• Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A-D conversion
characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at
the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of
outputting an equal code based on the theoretical A-D conversion characteristics, is used as an ana-
log input voltage. For example, if 10-bit resolution is used and if VREF (reference voltage) = 5.12 V,
then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input
voltages. If analog input voltage is 25 mV, “absolute accuracy = ±3LSB” refers to the fact that actual
A-D conversion falls on a range from “00216” to “00816” though an output code, “00516”, can be ex-
pected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included
in absolute accuracy.
Also, all the output codes for analog input voltage between VREF and AVcc becomes “3FF16”.
Figure 2.8.20. Absolute accuracy (10-bit resolution)
000
16
001
16
002
16
003
16
004
16
005
16
006
16
0
Analog input voltage (mV)
Theoretical A-D conversion
characteristic
510152025303540455055
007
16
008
16
009
16
00A
16
00B
16
+3LSB
–3LSB
Output code
(result of A-D conversion)
348
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
• Differential non-linearity error
Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A-
D conversion characteristics (an analog input width that can meet the expectation of outputting an
equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal
code). If 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, “differential non-linearity
error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10
mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV (see 5.2 A-D
converter's standard characteristics).
Figure 2.8.21. Differential non-linearity error (10-bit resolution)
000
16
001
16
002
16
003
16
004
16
005
16
006
16
0
Analog input voltage (mV)
Differential non-linear error
51015202530354045
007
16
008
16
009
16
Output code
(result of A-D conversion)
1LSB width for theoretical A-D
conversion characteristic
349
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.8.11 Internal Equivalent Circuit of Analog Input
Figure 2.8.22 shows the internal equivalent circuit of analog input.
Figure 2.8.22. Internal equivalent circuit to analog input
ON resistor
approx. 2kΩ
A-D successive conversion
register
Analog input voltage
AVcc
AVss
Chopper-type
amplifier
A-D conversion
interrupt request
Vcc Vss
V
IN
A-D control register 0
Comparison voltage
Comparison reference voltage (Vref) generator
V
REF
AVss
Vref
b2 b1 b0
Vcc
Vss
AN i
Wiring resistor
approx. 0.2kΩ
ON resistor
approx. 0.6kΩ
SW2
Sampling
control signal
SW1
C = Approx. 3.0pF
SW3
SW4
AMP
ON resistor,
approx. 5kΩ
SW2
Reference control
signal
Resistor
ladder
Control signal
for SW2
Control signal
for SW3
Connect to
Connect to
Comparison
Connect to
Connect to
Sampling
i ladder-type
switches i ladder-type wiring
resistors
ON resistor
approx. 0.6kΩ
AN0
Parasitic
diode
SW1
SW1 conducts only on the ports selected for analog input.
SW2 and SW3 are open when A-D conversion is not in
progress; their status varies as shown by the waveforms in
the diagrams on the left.
SW4 conducts only when A-D conversion is not in progress.
Parasitic
diode
Warning: Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
(i = 8) (i = 8)
350
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.8.23 has to be
completed within a specified period of time. With T as the specified time, time T is the time that switches
SW2 and SW3 are connected to O in Figure 2.8.22. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D
converter’s resolution be Y.
Vc is generally VC = VIN {1 – e }
And when t = T, VC=VIN – VIN=VIN(1 – )
e =
– =ln
Hence, R0 = – – R
Each value is R = 7.8 kΩ, C = 3 pF, T = 0.3 us in the A-D conversion mode with sample & hold. For
example, when the A-D converter’s resolution is 10 bits and precision (error) of the A-D converter is 0.1
LSB, Y = 10, X = 0.1LSB. Hence,
R0 = – –7.8 X103 3.0 X 103
2.8.12 Sensor’s Output Impedance under A-D Conversion
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con-
verter turns out to be approximately 3.0 kΩ. Tables 2.8.11 and 2.8.12 show output impedance values
based on the LSB values.
Figure 2.8.23 A circuit equivalent to the A-D conversion terminal
C (R0 +R)
T
C (R0 + R)
T
–
C (R0 + R)
t
–
Y
XY
X
Y
X
Y
X
C • ln
T
Y
X
3.0 X 10 –12 • ln 1024
0.1
0.3 X 10-6
V
C
C (3.0pF)
V
IN
Microprocessor's inside
Sensor-equivalent circuit
R (7.8kW)
R
0
351
A-D Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 2.8.11. Output impedance values based on the LSB values (1)
Table 2.8.12. Output impedance values based on the LSB values (2)
f(X
IN
)
(MHz) Cycle
(µs) Sampling time
(µs) R (kohm) C (pF) Accuracy
(LSB) R0 (kohm)
10 0.1 0.3
(3 ✕ cycle, sample &
hold bit is enabled)
7.8 3.0 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
3.0
4.5
5.3
5.9
6.4
6.8
7.2
7.5
7.8
8.1
10 0.1 0.2
(2 ✕ cycle, sample &
hold bit is disabled)
7.8 3.0 0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.4
0.9
1.3
1.7
2.0
2.2
2.4
2.6
2.8
f(X
IN
)
(MHz) Cycle
(µs) Sampling time
(µs) R (kohm) C (pF) Accuracy
(LSB) R0 (kohm)
10 0.1 0.3
(3 ✕ cycle, sample &
hold bit is enabled)
7.8 3.0 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
4.9
7.0
8.2
9.1
9.9
10.5
11.1
11.7
12.1
12.6
10 0.1 0.2
(2 ✕ cycle, sample &
hold bit is disabled)
7.8 3.0 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.7
2.1
2.9
3.5
4.0
4.4
4.8
5.2
5.5
5.8
352
D-A Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.9 D-A Converter
Figure 2.9.2. D-A converter-related registers
Figure 2.9.1. Memory map of D-A converter-related registers
2.9.1 Overview
The D-A converter used in the M30218 group is based on the 8-bit R-2R technique.
(1) Output voltage
The D-A converter outputs voltage within a range from 0 V to VREF. The output voltage is determined
by VREF/(256) X the D-A register contents.
The D-A converter is not effected by the Vref connection bit of the A-D converter.
(2) Conversion time
tsu = 3 µs
(3) Output from the D-A converter and the direction register
To use the D-A converter, do not set the direction register of the relevant port to output.
(4) Pins related to the D-A converter
• DA0 pin, DA1 pin Output pins of the D-A converter
• AVcc pin The power source pin of the analog section
• VREF pin Input pin of the reference voltage
• AVss pin The GND pin of the analog section
(5) Registers related to the D-A converter
Figure 2.9.1 shows the memory map of D-A converter-related registers, and Figure 2.9.2 shows D-A
converter-related registers.
(6) Note
D-A output pins shared with P97 and P96. The two pins are input ports and floating at the reset.
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
D-A control register
Symbol Address When reset
DACON 03DC
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
D-A0 output enable bit
DA0E
Bit symbol Bit name Function R W
0 : Output disabled
1 : Output enabled
D-A1 output enable bit 0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
Symbol Address When reset
DAi (i = 0,1) 03D8
16
,
03DA
16
Indeterminate
WR
b7 b0
Function R W
Output value of D-A conversion
353
D-A Converter
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
The following is the D-A converter operation. Figure 2.9.3 shows the set-up procedure.
2.9.2 D-A Converter Operation
(1) Writing a value to the D-A register i starts D-A conversion.
(2) Setting the D-Ai output enable bit to “1” outputs an analog signal on the DAi pin.
(3) The D-A converter continues outputting an analog signal until the D-A output enable bit is set
to “0”.
Operation
Figure 2.9.3. Set-up procedure of D-A converter
Setting D-A register
D-A register 0 [Address 03D8
16
] DA0
D-A register 1 [Address 03DA
16
] DA1
Output value of D-A conversion
b7 b0
D-A0 output enable bit
1 : Output enabled
Setting D-A control register
D-A Control register [Address 03DC
16
]
DACON
b7 b0
D-A1 output enable bit
1 : Output enabled
354
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.10 DMAC
2.10.1 Overview
DMAC transfers one data item held in the source address to the destination address every time a transfer
request is generated. The following is a DMAC overview.
(1) Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of
24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the
address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The links between the source and destination are as follows:
(a) A fixed address from an arbitrary 1M bytes space
(b) An arbitrary 1M bytes space from a fixed address
(c) A fixed address from another fixed address
(2) The number of bits of data transferred
The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is se-
lected, up to 128 K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt occurs when the transfer counter underflows.
(3) DMA transfer factor ________ ________
The DMA transfer factor can be selected from the following 15 factors: falling edge of INT0/INT1 pin,
timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt request through timer
B2 interrupt request, UART0 transmission interrupt request, UART0 reception interrupt request,
UART1 transmission interrupt request, UART1 reception interrupt request, A-D conversion interrupt
request, and software trigger.
When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interrupt
request bit. When other factor is selected, DMA transfer is generated by generating corresponding
interrupt request.
(4) Channel priority
If DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0.
(5) Writing to a register
When writing to the source register or the destination register with DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to
a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with
‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to, as in normal conditions.
(6) Reading to a register
The reload register can be read to, as in normal conditions.
355
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(7) Switching function
(a) Switching between one-shot transfer and repeated transfer
'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows.
'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter
underflows. The reload is carried out for the transfer counter and on the address pointer subjected to
forward direction.
The following are examples of operation in which the options listed are selected.
• A fixed address from an arbitrary 1M byte space, one-shot transfer........................................ P358
• An arbitrary 1M byte space from a fixed address, repeated transfer........................................ P360
(8) Registers related to DMAC
Figure 2.10.1 shows the memory map of DMAC-related registers, and Figures 2.10.2 and 2.10.3 show
DMAC-related registers.
Figure 2.10.1. Memory map of DMAC-related registers
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002C
15
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003C
16
004B
16
004C
16
03B8
16
03B9
16
03BA
16
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA0 destination pointer (DAR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
356
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.10.2. DMAC-related registers (1)
D
M
A
i
r
e
q
u
e
s
t
c
a
u
s
e
s
e
l
e
c
t
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
D
M
i
S
L
(
i
=
0
,
1
)0
3
B
8
1
6
,
0
3
B
A
1
6
0
0
1
6
B
i
t
n
a
m
e
F
u
n
c
t
i
o
n
R
B
i
t
s
y
m
b
o
l
W
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
D
M
A
r
e
q
u
e
s
t
c
a
u
s
e
s
e
l
e
c
t
b
i
t
D
S
E
L
0
D
S
E
L
1
D
S
E
L
2
D
S
E
L
3
S
o
f
t
w
a
r
e
D
M
A
r
e
q
u
e
s
t
b
i
t
I
f
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
i
s
s
e
l
e
c
t
e
d
,
a
D
M
A
r
e
q
u
e
s
t
i
s
g
e
n
e
r
a
t
e
d
b
y
s
e
t
t
i
n
g
t
h
i
s
b
i
t
t
o
“
1
”
(
W
h
e
n
r
e
a
d
,
t
h
e
v
a
l
u
e
o
f
t
h
i
s
b
i
t
i
s
a
l
w
a
y
s
“
0
”
)
D
S
R
D
M
A
i
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
D
M
i
C
O
N
(
i
=
0
,
1
)0
0
2
C
1
6
,
0
0
3
C
1
6
0
0
0
0
0
X
0
0
2
B
i
t
n
a
m
e
F
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
R
W
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
T
r
a
n
s
f
e
r
u
n
i
t
b
i
t
s
e
l
e
c
t
b
i
t
0
:
1
6
b
i
t
s
1
:
8
b
i
t
s
D
M
B
I
T
D
M
A
S
L
D
M
A
S
D
M
A
E
R
e
p
e
a
t
t
r
a
n
s
f
e
r
m
o
d
e
s
e
l
e
c
t
b
i
t
0
:
S
i
n
g
l
e
t
r
a
n
s
f
e
r
1
:
R
e
p
e
a
t
t
r
a
n
s
f
e
r
D
M
A
r
e
q
u
e
s
t
b
i
t
(
N
o
t
e
1
)
0
:
D
M
A
n
o
t
r
e
q
u
e
s
t
e
d
1
:
D
M
A
r
e
q
u
e
s
t
e
d
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
0
:
F
i
x
e
d
1
:
F
o
r
w
a
r
d
D
M
A
e
n
a
b
l
e
b
i
t
S
o
u
r
c
e
a
d
d
r
e
s
s
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
(
N
o
t
e
3
)
D
e
s
t
i
n
a
t
i
o
n
a
d
d
r
e
s
s
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
(
N
o
t
e
3
)
0
:
F
i
x
e
d
1
:
F
o
r
w
a
r
d
D
S
D
D
A
D
N
o
t
e
1
:
D
M
A
r
e
q
u
e
s
t
c
a
n
b
e
c
l
e
a
r
e
d
b
y
r
e
s
e
t
t
i
n
g
t
h
e
b
i
t
.
N
o
t
e
2
:
T
h
i
s
b
i
t
c
a
n
o
n
l
y
b
e
s
e
t
t
o
“
0
”
.
N
o
t
e
3
:
S
o
u
r
c
e
a
d
d
r
e
s
s
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
a
n
d
d
e
s
t
i
n
a
t
i
o
n
a
d
d
r
e
s
s
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
b
i
t
c
a
n
n
o
t
b
e
s
e
t
t
o
“
1
”
s
i
m
u
l
t
a
n
e
o
u
s
l
y
.
b
3
b
2
b
1
b
0
0
0
0
0
:
F
a
l
l
i
n
g
e
d
g
e
o
f
I
N
T
0
/
I
N
T
1
p
i
n
(
N
o
t
e
)
0
0
0
1
:
S
o
f
t
w
a
r
e
t
r
i
g
g
e
r
0
0
1
0
:
T
i
m
e
r
A
0
0
0
1
1
:
T
i
m
e
r
A
1
0
1
0
0
:
T
i
m
e
r
A
2
0
1
0
1
:
T
i
m
e
r
A
3
0
1
1
0
:
T
i
m
e
r
A
4
0
1
1
1
:
T
i
m
e
r
B
0
1
0
0
0
:
T
i
m
e
r
B
1
1
0
0
1
:
T
i
m
e
r
B
2
1
0
1
0
:
U
A
R
T
0
t
r
a
n
s
m
i
t
1
0
1
1
:
U
A
R
T
0
r
e
c
e
i
v
e
1
1
0
0
:
U
A
R
T
1
t
r
a
n
s
m
i
t
1
1
0
1
:
U
A
R
T
1
r
e
c
e
i
v
e
1
1
1
0
:
A
-
D
c
o
n
v
e
r
s
i
o
n
1
1
1
1
:
I
n
h
i
b
i
t
e
d
N
o
t
e
:
A
d
d
r
e
s
s
0
3
B
8
1
6
i
s
f
o
r
I
N
T
0
;
a
d
d
r
e
s
s
0
3
B
A
1
6
i
s
f
o
r
I
N
T
1
.
(
N
o
t
e
2
)
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
“
0
”
.
357
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.10.3. DMAC-related registers (2)
b7 b0 b7 b0
(b8)(b15)
Function
RW
• Transfer counter
Set a value one less than the transfer count
Symbol Address When reset
TCR0 0029
16
, 0028
16
Indeterminate
TCR1 0039
16
, 0038
16
Indeterminate
DMAi transfer counter (i = 0, 1)
Transfer count
specification
0000
16
to FFFF
16
b7
(b23) b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function
RW
• Source pointer
Stores the source address
Symbol Address When reset
SAR0 0022
16
to 0020
16
Indeterminate
SAR1 0032
16
to 0030
16
Indeterminate
DMAi source pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Symbol Address When reset
DAR0 0026
16
to 0024
16
Indeterminate
DAR1 0036
16
to 0034
16
Indeterminate
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
RW
• Destination pointer
Stores the destination address
DMAi destination pointer (i = 0, 1)
Transfer count
specification
00000
16
to FFFFF
16
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
A
A
A
A
A
A
358
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the
circled items are described below. Figure 2.10.4 shows an example of operation and Figure 2.10.5
shows the set-up procedure.
2.10.2 Operation of DMAC (one-shot transfer mode)
Figure 2.10.4. Example of operation of one-shot transfer mode
Table 2.10.1. Choosed functions
Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer
is completed. The DMA interrupt request bit changes to “1” simultaneously.
Item
Transfer space
Unit of transfer
Set-up
O
O
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
8 bits
16 bits
Dummy
cycle Source
Source Dummy
cycle
Dummy
cycle
BCLK
Address bus
RD signal
WR signal
Data bus
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
Write signal to
software DMAi
request bit
CPU use Source
Source Dummy
cycle
Indeterminate 0016
• In the case in which the number of transfer times is set to 2.
(1) Request signal for a DMA transfer occurs
Cleared to “0” when interrupt request is
accepted, or cleared by software
(2) Data transfer begins
CPU use
CPU use
FF16
(3) Underflow
CPU useCPU use
CPU use
Destination Destination
Destination
Destination
0116
359
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.10.5. Set-up procedure of one-shot transfer mode
When software DMA request bit = “1”
Setting DMAi request cause select register
DMAi request cause select register (i = 0, 1) [Address 03B8
16
, 03BA
16
]
DMiSL(i = 0, 1)
DMA request cause select bit
0 0 0 1 : Software trigger
b3 b2 b1 b0
b7 b0
01000
Software DMA request bit
Set to “0”
Setting DMAi control register
DMAi control register (i = 0, 1) [Address 002C
16
, 003C
16
]
DMiCON(i = 0, 1)
Transfer unit bit select bit
1 : 8 bits
Repeat transfer mode select bit
0 : Single transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
1 : Forward
(Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
0 : Fixed
(Bit 4 and bit 5 cannot be set to “1” simultaneously)
b7 b0
010001
Setting DMAi source pointer
Source pointer
Stores the source address
b7 b0
(b15) (b8)b7 b0
b7 b0
(b16)
(b23)
DMA0 source pointer [Address 0022
16
to 0020
16
] SAR0
DMA1 source pointer [Address 0032
16
to 0030
16
] SAR1
b3
(b19)
Setting DMAi destination pointer
Destination pointer
Stores the destination address
b7 b0
(b15) (b8)b7 b0b7 b0
(b16)(b23)
DMA0 destination pointer [Address 0026
16
to 0024
16
] DAR0
DMA1 destination pointer [Address 0036
16
to 0034
16
] DAR1
b3
(b19)
Setting DMAi transfer counter
Transfer counter
Set a value one less than the transfer count
b0
(b8)b7 b0
DMA0 transfer counter [Address 0029
16
, 0028
16
] TCR0
DMA1 transfer counter [Address 0039
16
, 0038
16
] TCR1
b0
(b15)
Setting DMAi control register
DMAi control register (i = 0, 1) [Address 002C
16
, 003C
16
]
DMiCON(i = 0, 1)
DMA enable bit
1 : Enabled
b7 b0
1
Note: Clear DMA request bit simultaneously again.
Start DMA transmission
360
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled
items are described below. Figure 2.10.6 shows an example of operation and Figure 2.10.7 shows the
set-up procedure.
2.10.3 Operation of DMAC (repeated transfer mode)
Figure 2.10.6. Example of operation of repeated transfer mode
Table 2.10.2. Choosed functions
(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
Operation
O
Item
Transfer space
Unit of transfer
Set-up
O
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
8 bits
16 bits
Source
Source Source
BCLK
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit • In the case in which the number of transfer times is set to 2.
RD signal
WR signal
Address bus
Data bus
“1”
Write signal to
software DMAi
request bit
Source
Indeterminate 0016
Dummy cycle
CPU use
CPU use
(3) Underflow
FF16
CPU use
Source
CPU use
Cleared to “0” when interrupt request is accepted, or cleared by software
CPU use
CPU use
0016
CPU use Source
CPU use
Destination
0116 0116
Destination Destination Dummy cycle
Destination Dummy cycle
Destination Dummy cycle
Dummy cycle
Destination Dummy cycle
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
361
DMAC
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.10.7. Set-up procedure of repeated transfer mode
When software DMA request bit = “1”
Setting DMAi request cause select register
DMAi request cause select register (i = 0, 1) [Address 03B8
16
, 03BA
16
]
DMiSL(i = 0, 1)
b7 b0
01000
Software DMA request bit
Set to “0”
Setting DMAi control register
DMAi control register (i = 0, 1) [Address 002C
16
, 003C
16
]
DMiCON(i = 0, 1)
Transfer unit bit select bit
0
: 16 bits
Repeat transfer mode select bit
1 : Repeat transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously)
b7 b0
100010
Setting DMAi source pointer
Source pointer
Stores the source address
b7 b0
(b15) (b8)b7 b0b7 b0
(b16)(b23)
DMA0 source pointer [Address 0022
16
to 0020
16
] SAR0
DMA1 source pointer [Address 0032
16
to 0030
16
] SAR1
b3
(b19)
Setting DMAi destination pointer
Destination pointer
Stores the destination address
b7 b0
(b15) (b8)b7 b0b7 b0
(b16)(b23)
DMA0 destination pointer [Address 0026
16
to 0024
16
] DAR0
DMA1 destination pointer [Address 0036
16
to 0034
16
] DAR1
b3
(b19)
Setting DMAi transfer counter
Transfer counter
Set a value one less than the transfer count
b0 b7 b0
DMA0 transfer counter [Address 0029
16
, 0028
16
] TCR0
DMA1 transfer counter [Address 0039
16
, 0038
16
] TCR1
b0
(b15)
Setting DMAi control register
DMAi control register (i = 0, 1) [Address 002C
16
, 003C
16
]
DMiCON(i = 0, 1)
DMA enable bit
1 : Enabled
b7 b0
1
Note: Clear DMA request bit simultaneously again.
DMA request cause select bit
0 0 0 1 : Software trigger
b3 b2 b1 b0
Start DMA transmission
(b8)
362
CRC Calculation Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.11.1 Overview
Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data
by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using
the CRC calculation circuit allows generation of CRC code. A polynomial counter is used for the polyno-
mial generation.
(1) Registers related to CRC calculation circuit
Figure 2.11.1 shows the memory map of CRC-related registers, and Figure 2.11.2 shows CRC- re-
lated registers.
2.11 CRC Calculation Circuit
Figure 2.11.1. Memory map of CRC-related registers
Figure 2.11.2. CRC-related registers
03BC
16
03BD
16
03BE
16
CRC data register (CRCD)
CRC input register (CRCIN)
S
y
m
b
o
lA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
C
R
C
D0
3
B
D
1
6
,
0
3
B
C
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
b
7b
0b
7b
0
(
b
1
5
)(
b
8
)
C
R
C
d
a
t
a
r
e
g
i
s
t
e
r
W
R
C
R
C
c
a
l
c
u
l
a
t
i
o
n
r
e
s
u
l
t
o
u
t
p
u
t
r
e
g
i
s
t
e
r
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
0
0
0
0
1
6
t
o
F
F
F
F
1
6
S
y
m
b
oA
d
d
r
e
s
sW
h
e
n
r
e
s
e
t
C
R
C
I
N0
3
B
E
1
6
I
n
d
e
t
e
r
m
i
n
a
t
e
b
7b
0
C
R
C
i
n
p
u
t
r
e
g
i
s
t
e
r
W
R
D
a
t
a
i
n
p
u
t
r
e
g
i
s
t
e
r
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
0
0
1
6
t
o
F
F
1
6
363
CRC Calculation Circuit
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.11.2 Operation of CRC Calculation Circuit
The following describes the operation of the CRC calculation. Figure 2.11.3 shows an example of calcu-
lation data 012316 using the CRC calculation circuit.
Operation (1) The CRC calculation circuit sets an initial value in the CRC data register.
(2) Writing 1 byte data to the CRC input register generates CRC code based on the data register.
CRC code generation for 1 byte data finishes in two machine cycles.
(3) The CRC calculation circuit detects an error by means of comparing the CRC-checking data
with the content of the CRC data register, after the next data is written to the CRC input
register.
(4) The content of CRC data register after all data is written becomes CRC code.
Figure 2.11.3. Calculation example using the CRC calculation circuit
b15 b0
(1) Setting 0000
16
CRC data register CRCD
[03BD
16
, 03BC
16
]
b0b7
b15 b0
(2) Setting 01
16
CRC input register CRCIN
[03BE
16
]
2 cycles
After CRC calculation is complete
CRC data register CRCD
[03BD
16
, 03BC
16
]
1189
16
Stores CRC code
b0b7
b15 b0
(3) Setting 23
16
CRC input register CRCIN
[03BE
16
]
After CRC calculation is complete
CRC data register CRCD
[03BD
16
, 03BC
16
]
0A41
16
Stores CRC code
The code resulting from sending 01
16
in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X
16
+ X
12
+ X
5
+ 1), becomes the remainder resulting from dividing (1000 0000) X
16
by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189
16
in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000
LSB MSB
LSB MSB
98 1 1
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
364
Watchdog Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.12.1 Overview
The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an
overview of the watchdog timer.
(1) Watchdog timer start procedure
When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register
initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog
timer, once started operating, cannot be stopped by any means other than stopping conditions.
(2) Watchdog timer stop conditions
The watchdog timer stops in any one of the following states:
(a) Period in which the CPU is in stopped state
(b) Period in which the CPU is in waiting state
(c) Period in which the microcomputer is in hold state
(3) Watchdog timer initialization
The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count.
(a) When the watchdog timer writes to the watchdog timer start register while a count is in progress
(b) When the watchdog timer underflows
(4) Runaway detection
When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to
the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt
occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer
interrupt, set the software reset bit to “1” to reset software.
(5) Watchdog timer cycle
The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the
prescaler selected.
2.12 Watchdog Timer
Table 2.12.1. The watchdog timer cycle
CM07 CM06 CM17 CM16 BCLK WDC7 Period
0
0
0
0
0
1
0 0 0 10MHz
0 0 1 5MHz
0 1 0 2.5MHz
0 1 1 0.625MHz
1 Invalid Invalid 1.25MHz
Invalid Invalid Invalid 32kHz
0
1
0
1
0
1
0
1
0
1
Invalid
Approx. 52.4ms (Note)
Approx. 419.4ms (Note)
Approx. 104.9ms (Note)
Approx. 838.9ms (Note)
Approx. 209.7ms (Note)
Approx. 1.68s (Note)
Approx. 838.9ms (Note)
Approx. 6.71s (Note)
Approx. 419.4ms (Note)
Approx. 3.36s (Note)
Approx. 2s (Note)
Note: An error due to the prescaler occurs.
365
Watchdog Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.12.1. Memory map of watchdog timer-related registers
Figure 2.12.2. Watchdog timer-related registers
(6) Registers related to the watchdog timer
Figure 2.12.1 shows the memory map of watchdog timer-related registers, and Figure 2.12.2 shows
watchdog timer-related registers.
000E16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Watchdog timer control register
Symbol Address When reset
WDC 000F
16
000XXXXX
2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E
16
Indeterminate
WR
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
16
”
regardless of whatever value is written.
Reserved bit
Reserved bit Must always be set to “0”
Must always be set to “0”
00
AA
AA
AA
AA
A
A
AA
A
AA
A
A
A
366
Watchdog Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.12.2 Operation of Watchdog Timer
The following is an operation of the watchdog timer. Figure 2.12.3 shows the operation timing, and Figure
2.12.4 shows the set-up procedure.
(1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and
causes it to start a down count.
(2) With a count in progress, writing to the watchdog timer start register again initializes the
watchdog timer to 7FFF16 and causes it to resume counting.
(3) Either executing the WAIT instruction or going to the stopped state causes the watchdog
timer to hold the count in progress and to stop counting. The watchdog timer resumes count-
ing after returning from the execution of the WAIT instruction or from the stopped state.
(4) If the watchdog timer underflows, it is initialized to 7FFF16 and continues counting. At this
time, a watchdog timer interrupt occurs.
Operation
Figure 2.12.3. Operation timing of watchdog timer
(1) Start count
Write signal to the
watchdog timer
start register
7FFF
16
0000
16
“H”
“L”
(4) Generate
watchdog timer
interrupt
(2) Write operation
(3)In stopped state, or WAIT
instruction is executing, etc
367
Watchdog Timer
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.12.4. Set-up procedure of watchdog timer
Reserved bit
Must always be “0”
Watchdog timer control register [Address 000F
16
]
WDC
Setting watchdog timer control register
b7 b0
Setting watchdog timer start register
The watchdog timer is initialized and starts counting with a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
16
”
regardless of the value written.
Watchdog timer start register [Address 000E
16
]
WDTS
b0b7
Software reset
Software reset bit
The device is reset when this bit is set to “1”. The value of this bit
is “0” when read.
Processor mode register 0 [Address 0004
16
]
PM0
b7 b0
1
Generating watchdog
timer interrupt
00
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
368
Address Match Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.13.1 Overview
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor.
The following is an overview of the address match interrupt.
(1) Enabling/disabling the address match interrupt
The address match interrupt enable bit can be used to enable and disable an address match interrupt.
It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag).
(2) Timing of the address match interrupt
An interrupt occurs immediately before executing the instruction in the address indicated by the ad-
dress match interrupt register. Set the first address of the instruction in the address match interrupt
register. Setting a half address of an instruction or an address of tabulated data does not generate an
address match interrupt.
The first instruction of an interrupt routine does not generate an address match interrupt either.
(3) Returning from an address match interrupt
The return address put in the stack when an address match interrupt occurs depends on the instruc-
tion not yet executed (the instruction the address match interrupt register indicates). The return ad-
dress is not put in the stack. For this reason, to return from an address match interrupt, either rewrite
the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to
the state as it was before the interrupt occurred and return by use of a jump instruction.
Figure 2.13.1 shows unexecuted instructions and corresponding the stacked addresses.
2.13 Address Match Interrupt
<Instructions whose address is added to by 2 when an address match interrupt occurs>
• 16-bit operation code instructions
• 8-bit operation code instructions given below
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest = A0/A1)
<Instructions whose address is added to by 1 when an address match interrupt occurs>
• Instructions other than those listed above
Figure 2.13.1. Unexecuted instructions and corresponding stacked addresses
(4) How to determine an address match interrupt
Address match interrupts can be set at two different locations. However, both location will have the
same vector address. Therefore, it is necessary to determine which interrupt has occurred; address
match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which
interrupt has occurred according to the first part of the address match interrupt routine.
369
Address Match Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.13.2. Memory map of address match interrupt-related registers
(5) Registers related to the address match interrupt
Figure 2.13.2 shows the memory map of address match interrupt-related registers, and Figure 2.13.3
shows address match interrupt-related registers.
Figure 2.13.3. Address match interrupt-related registers
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Address match interrupt enable register (AIER)
B
i
t
n
a
m
eB
i
t
s
y
m
b
o
l
S
y
m
b
o
lA
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
A
I
E
R0
0
0
9
1
6
X
X
X
X
X
X
0
0
2
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
F
u
n
c
t
i
o
nWR
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
0
e
n
a
b
l
e
b
i
t
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
A
I
E
R
0
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
1
e
n
a
b
l
e
b
i
t
A
I
E
R
1
S
y
m
b
o
lA
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
R
M
A
D
00
0
1
2
1
6
t
o
0
0
1
0
1
6
X
0
0
0
0
0
1
6
R
M
A
D
10
0
1
6
1
6
t
o
0
0
1
4
1
6
X
0
0
0
0
0
1
6
b
7b
6b
5b
4b
3b
2b
1b
0
WR
A
d
d
r
e
s
s
s
e
t
t
i
n
g
r
e
g
i
s
t
e
r
f
o
r
a
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
F
u
n
c
t
i
o
nV
a
l
u
e
s
t
h
a
t
c
a
n
b
e
s
e
t
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
i
(
i
=
0
,
1
)
0
0
0
0
0
1
6
t
o
F
F
F
F
F
1
6
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
b
0b
7b
0b
3
(
b
1
9
)(
b
1
6
)b
7b
0
(
b
1
5
)(
b
8
)
b
7
(
b
2
3
)
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
370
Address Match Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.13.2 Operation of Address Match Interrupt
The following is an operation of address match interrupt. Figure 2.13.4 shows the set-up procedure of
address match interrupt, and Figure 2.13.5 shows the overview of the address match interrupt handling
routine.
Operation (1) The address match interrupt handling routine sets an address to be used to cause the ad-
dress match interrupt register to generate an interrupt.
(2) Setting the address match enable flag to “1” enables an interrupt to occur.
(3) An address match interrupt occurs immediately before the instruction in the address indicated
by the address match interrupt register as a program is executed.
Figure 2.13.4. Set-up procedure of address match interrupt
Can be set to “00000
16
” to “FFFFF
16
”
b7 b0
(b23) (b16) b7 b0
Address match interrupt register 0 [Address 0012
16
to 0010
16
]
RMAD0
Address match interrupt register 1 [Address 0016
16
to 0014
16
]
RMAD1
Setting address match interrupt enable register
Address match interrupt enable register [Address 0009
16
]
AIER
Address match interrupt 0 enable bit
1: Interrupt enabled
b7 b0
Setting address match interrupt register
b7 b0
(b15) (b8)
b4
(b20) b3
(b19)
Address match interrupt 1 enable bit
1: Interrupt enabled
371
Address Match Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.13.5. Overview of the address match interrupt handling routine
Address match interrupt routine
[1] Storing registers
[2] Determining the interrupt address
Address match 0?
Address match 0 program
[3] Rewriting the stack
Restoring registers
REIT
No
Yes Address match 1?
Address match 1 program
No
Yes
Handling an error
[1] Storing the contents of the registers holding the main program status to be kept.
[2] Determining the interrupt address
Determining which factor generated the interrupt.
[3] Rewriting the stack
Rewriting the return address.
Explanation:
372
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.14 Power Control
2.14.1 Overview
‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators,
or decreasing the operation clock. The following is a description of the three available power control
modes:
(1) Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK
selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 2.14.1 shows the state transition diagram of the above modes.
373
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.14.1. State transition diagram of power control mode
T
r
a
n
s
i
t
i
o
n
o
f
s
t
o
p
m
o
d
e
,
w
a
i
t
m
o
d
e
T
r
a
n
s
i
t
i
o
n
o
f
n
o
r
m
a
l
m
o
d
e
R
e
s
e
t
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
8
m
o
d
e
)
I
n
t
e
r
r
u
p
t
C
M
1
0
=
“
1
”
A
l
l
o
s
c
i
l
l
a
t
o
r
s
s
t
o
p
p
e
dC
P
U
o
p
e
r
a
t
i
o
n
s
t
o
p
p
e
d
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
8
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
/
8
C
M
0
7
=
“
0
”
C
M
0
6
=
“
1
”
L
o
w
-
s
p
e
e
d
m
o
d
e
H
i
g
h
-
s
p
e
e
d
m
o
d
e
M
a
i
n
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
S
u
b
c
l
o
c
k
i
s
s
t
o
p
p
e
d
M
a
i
n
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
S
u
b
c
l
o
c
k
i
s
s
t
o
p
p
e
d
M
a
i
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
S
u
b
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
M
a
i
n
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
S
u
b
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
L
o
w
p
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
m
o
d
e
H
i
g
h
-
s
p
e
e
d
/
m
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
L
o
w
-
s
p
e
e
d
/
l
o
w
p
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
m
o
d
e
N
o
r
m
a
l
m
o
d
e
S
t
o
p
m
o
d
e
S
t
o
p
m
o
d
e
S
t
o
p
m
o
d
e
A
l
l
o
s
c
i
l
l
a
t
o
r
s
s
t
o
p
p
e
d
A
l
l
o
s
c
i
l
l
a
t
o
r
s
s
t
o
p
p
e
d
W
a
i
t
m
o
d
e
W
a
i
t
m
o
d
e
W
a
i
t
m
o
d
e
C
P
U
o
p
e
r
a
t
i
o
n
s
t
o
p
p
e
d
C
P
U
o
p
e
r
a
t
i
o
n
s
t
o
p
p
e
d
I
n
t
e
r
r
u
p
t
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
I
n
t
e
r
r
u
p
t
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
I
n
t
e
r
r
u
p
t
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
C
M
1
0
=
“
1
”
I
n
t
e
r
r
u
p
t
I
n
t
e
r
r
u
p
t
C
M
1
0
=
“
1
”
B
C
L
K
:
f
(
X
I
N
)
/
2
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
0
”
C
M
1
6
=
“
1
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
2
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
/
1
6
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
1
”
C
M
1
6
=
“
1
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
1
6
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
/
4
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
1
”
C
M
1
6
=
“
0
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
4
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
0
”
C
M
1
6
=
“
0
”B
C
L
K
:
f
(
X
I
N
)
/
8
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
8
m
o
d
e
)
C
M
0
7
=
“
0
”
C
M
0
6
=
“
1
”
H
i
g
h
-
s
p
e
e
d
m
o
d
e
B
C
L
K
:
f
(
X
I
N
)
/
2
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
0
”
C
M
1
6
=
“
1
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
2
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
/
1
6
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
1
”
C
M
1
6
=
“
1
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
1
6
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
/
4
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
1
”
C
M
1
6
=
“
0
”
M
e
d
i
u
m
-
s
p
e
e
d
m
o
d
e
(
d
i
v
i
d
e
d
-
b
y
-
4
m
o
d
e
)
B
C
L
K
:
f
(
X
I
N
)
C
M
0
7
=
“
0
”
C
M
0
6
=
“
0
”
C
M
1
7
=
“
0
”
C
M
1
6
=
“
0
”
B
C
L
K
:
f
(
X
C
I
N
)
C
M
0
7
=
“
1
”
B
C
L
K
:
f
(
X
C
I
N
)
C
M
0
7
=
“
1
”
M
a
i
n
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
S
u
b
c
l
o
c
k
i
s
o
s
c
i
l
l
a
t
i
n
g
C
M
0
7
=
“
0
”
(
N
o
t
e
1
,
3
)
C
M
0
7
=
“
0
”
(
N
o
t
e
1
)
C
M
0
6
=
“
1
”
C
M
0
4
=
“
0
”
C
M
0
7
=
“
1
”
(
N
o
t
e
2
)
C
M
0
7
=
“
0
”
(
N
o
t
e
1
)
C
M
0
6
=
“
0
”
(
N
o
t
e
3
)
C
M
0
4
=
“
1
”
C
M
0
7
=
“
1
”
(
N
o
t
e
2
)
C
M
0
5
=
“
1
”
C
M
0
5
=
“
0
”C
M
0
5
=
“
1
”
C
M
0
4
=
“
0
”C
M
0
4
=
“
1
”
C
M
0
6
=
“
0
”
(
N
o
t
e
s
1
,
3
)
C
M
0
6
=
“
1
”
C
M
0
4
=
“
0
”C
M
0
4
=
“
1
”
(
N
o
t
e
s
1
,
3
)
N
o
t
e
1
:S
w
i
t
c
h
c
l
o
c
k
a
f
t
e
r
o
s
c
i
l
l
a
t
i
o
n
o
f
m
a
i
n
c
l
o
c
k
i
s
s
u
f
f
i
c
i
e
n
t
l
y
s
t
a
b
l
e
.
N
o
t
e
2
:S
w
i
t
c
h
c
l
o
c
k
a
f
t
e
r
o
s
c
i
l
l
a
t
i
o
n
o
f
s
u
b
c
l
o
c
k
i
s
s
u
f
f
i
c
i
e
n
t
l
y
s
t
a
b
l
e
.
N
o
t
e
3
:C
h
a
n
g
e
C
M
0
6
a
f
t
e
r
c
h
a
n
g
i
n
g
C
M
1
7
a
n
d
C
M
1
6
.
N
o
t
e
4
:T
r
a
n
s
i
t
i
n
a
c
c
o
r
d
a
n
c
e
w
i
t
h
a
r
r
o
w
.
(
R
e
f
e
r
t
o
t
h
e
f
o
l
l
o
w
i
n
g
f
o
r
t
h
e
t
r
a
n
s
i
t
i
o
n
o
f
n
o
r
m
a
l
m
o
d
e
.
)
374
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(2) Switching the driving capacity of the oscillation circuit
Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing
the driving capacity after the oscillation stabilizes allows for further reduction in power consumption.
(3) Clearing stop mode and wait mode
The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting
hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor
interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a
mode, that interrupt is processed. Table 2.14.1 shows the interrupts that can be used for clearing a
stop mode and wait mode.
(4) BCLK in returning from wait mode or stop mode
(a) Returning from wait mode
The processor immediately returns to the BCLK, which was in use before entering wait mode.
(b) Returning from stop mode
CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17,
CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts
operating in divided-by-8 mode.
When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and
CM07 all do not change state. In this case, when restored from stop mode, the device starts operat-
ing in low-speed mode.
Table 2.14.1. Interrupts available for clearing stop mode and wait mode
Can be used when an external clock in clock synchronous serial I/O mode is selected.
Can be used when the external signal is being counted in event counter mode.
Can be used in one-shot mode and one-shot sweep mode.
Note 1:
Note 2:
Note 3:
CM02 = 0
Impossible
Impossible
Note 3
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Impossible
Impossible
Impossible
Note 1
Note 1
Note 1
Note 1
Impossible
Impossible
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Possible
Possible
Possible
Possible
Possible
Possible
DMA0 interrupt
DMA1 interrupt
A-D interrupt
UART0 transmit interrupt
UART0 receive interrupt
UART1 transmit interrupt
UART1 receive interrupt
SI/O automatic transfer interrupt
FLD interrupt
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
INT0 interrupt
INT1 interrupt
INT2 interrupt
INT3 interrupt
INT4 interrupt
INT5 interrupt
Wait mode
Interrupt for clearing Stop mode
CM02 = 1
Impossible
Impossible
Impossible
Note 1
Note 1
Note 1
Note 1
Impossible
Impossible
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Possible
Possible
Possible
Possible
Possible
Possible
375
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(5) Sequence of returning from stop mode
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read-
ing address 0000016. The interrupt request bit of the interrupt written in address 0000016 will
then be set to “0”.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Figure 2.14.2 shows the sequence of returning from stop mode.
Figure 2.14.2. Sequence of returning from stop mode
(6) Registers related to power control
Figure 2.14.3 shows the memory map of power control-related registers, and Figure 2.14.4 shows
power control-related registers.
Address
00000
Interrupt
information
BCLK
Address bus
Data bus
Indeterminate SP-2 SP-4 vec vec+2
Indeterminate
SP-2
contents SP-4
contents vec
contents vec+2
contents
PC
Writing “1” to CM10
(all clock stop control bit)
Oscillation start-upStop mode Interrupt sequence approximately 20 cycle (16µ sec)
(Single-chip mode, f(XIN) = 10MHz)
RD
WR
Indeterminate
Operated by divided-by-8 mode
INTi
Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
Note:
376
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.14.4. Power control-related registers
Figure 2.14.3. Memory map of power control-related registers
0006
16
0007
16
System clock control register 0 (CM0)
System clock control register 1 (CM1)
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 000616 4816
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P97/DA0
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
WAIT peripheral function
clock stop bit 0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
XCIN-XCOUT drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port XC select bit 0 : I/O port
1 : XCIN-XCOUT generation
Main clock (XIN-XOUT)
stop bit (Note 3, 4, 5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A 16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so X IN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 000716 2016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note4) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A 16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006 16) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. X CIN and XCOUT turn high-
impedance state.
CM15 XIN-XOUT drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Always set to “0”
Reserved bit Always set to “0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Always set to “0”
Reserved bit Always set to “0”
00
377
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.14.2 Stop Mode Set-Up
(1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the
processor to go into stop mode.
Operation
Settings and operation for entering stop mode are described here.
Figure 2.14.5. Example of stop mode set-up
All clocks off (stop mode)
b7 b0
(3) Canceling protect
Protect register [Address 000A
16
]
PRCR
1
Enables writing to system clock control registers 0 and 1
(addresses 0006
16
and 0007
16
)
1 : Write-enabled
(3) All clocks off (stop mode)
b7 b0
System clock control register 1 [Address 0007
16
]
CM1
0000
Reserved bit
Must be set to “0”
All clock stop control bit
1 : All clocks off (stop mode)
1
Interrupt control register
SiTIC(i=0, 1) [Address 0051
16
, 0053
16
]
SiRIC(i=0, 1) [Address 0052
16
, 0054
16
]
TAiIC(i=0 to 4) [Address 0055
16
to 0059
16
]
TBiIC(i=0 to 2) [Address 005A
16
to 005C
16
]
(1) Setting interrupt to cancel stop mode
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the stop mode is higher than
the processor interrupt priority(IPL).
Interrupt priority level select bit
b7 b0
INTiIC(i=0 to 2) [Address 005D
16
to 005F
16
]
INTiIC(i=3 to 5) [Address 0047
16
to 0049
16
]
Make sure that the interrupt priority level of the
interrupt which is used to cancel the stop mode is
higher than the processor interrupt priority(IPL).
Interrupt priority level select bit
b7 b0
0
Reserved bit
Must be set to “0”
System clock control register 0
[Address 0006
16
] CM0
(3) Setting operation clock after returning from stop mode
On
Main clock (X
IN
-X
OUT
) stop bit
b7 b0
System clock select bit
X
IN
, X
OUT
As this register becomes setting mentioned above when
operating with X
IN
(count source of BCLK is X
IN
),
the user does not need to set it again.
00
System clock control register 0
[Address 0006
16
] CM0
X
CIN
-X
COUT
generation
Port X
C
select bit
b7 b0
System clock select bit
X
CIN
, X
COUT
As this register becomes setting mentioned above when operating with X
CIN
(count source of BCLK is X
CIN
), the user does not need to set it again.
When operating with X
IN
, set port Xc select bit to “1” before setting system clock
select bit to “1”. The both bits cannot be set at the same time.
11
(When operating with X
CIN
after returning)(When operating with X
IN
after returning)
(2) Interrupt enable flag (I flag) “1”
378
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.14.3 Wait Mode Set-Up
Figure 2.14.6. Example of wait mode set-up
Settings and operation for entering wait mode are described here.
(1) Enables the interrupt used for returning from wait mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clears the protection and changes the content of the system clock control register.
(4) Executes the WAIT instruction.
Operation
Wait mode
(3) Canceling protect
b7 b0
Protect register [Address 000A
16
]
PRCR
1
Enables writing to system clock control registers 0 and 1
(addresses 0006
16
and 0007
16
)
1 : Write-enabled
(4) WAIT instruction
(3) Control of CPU clock
Note: When switching the system clock, it is necessary
to wait for the oscillation to stabilize.
b7 b0
WAIT peripheral function clock stop bit
0 : Do not stop f
1
, f
8
, f
32
in wait mode
1 : Stop f
1
, f
8
, f
32
in wait mode
Port X
C
select bit
0 : I/O port
1 : X
CIN
-X
COUT
generation
Main clock (X
IN
-X
OUT
) stop bit
0 : On
1 : Off
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit (Note)
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
System clock control register 0
[Address 0006
16
] CM0
b7 b0
System clock control register 1
[Address 0007
16
] CM10000
Reserved bit
Must be set to “0”
Main clock division select bit
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
Interrupt control register
ADIC [Address 004E
16
]
ASIOC [Address 004F
16
]
FLDIC [Address 0050
16
]
SiTIC(i=0, 1) [Address 0051
16
, 0053
16
]
SiRIC(i=0, 1) [Address 0052
16
, 0054
16
]
TAiIC(i=0 to 4) [Address 0055
16
to 0059
16
]
TBiIC(i=0 to 2) [Address 005A
16
to 005C
16
]
(1) Setting interrupt to cancel wait mode
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
WAIT instruction is executed.
Interrupt priority level select bit
b7 b0
INTiIC(i=0 to 2) [Address 005D
16
to 005F
16
]
INTiIC(i=3 to 5) [Address 0047
16
to 0049
16
]
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Interrupt priority level select bit
b7 b0
0
Reserved bit
Must be set to “0”
(2) Interrupt enable flag (I flag) “1”
379
Power Control
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until
main clock oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either
from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within
the instruction queue are prefetched and then the program stops. So put at least four NOPs
in succession either to the WAIT instruction or to the instruction that sets the every-clock stop
bit to 1.
(3) Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to
which the count source is going to be switched must be oscillating stably. Allow a wait time in
software for the oscillation to stabilize before switching over the clock.
(4) Suggestions to reduce power consumption
• Ports
The processor retains the state of each programmable I/O port even when it goes to
wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in
input ports that float. When entering wait mode or stop mode, set non-used ports to
input and stabilize the potential.
(a) A-D converter
A current always flows in the VREF pin. When entering wait mode or stop mode, set
the Vref connection bit to “0” so that no current flows into the VREF pin.
(b) D-A converter
The processor retains the D-A state even when entering wait mode or stop mode.
Disable the output from the D-A converter then work on the programmable I/O ports.
(c) Stopping peripheral functions
In wait mode, stop non-used wait peripheral functions using the peripheral function
clock stop bit.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(e) External clock
When using an external clock input for the CPU clock, set the main clock stop bit to
“1”. Setting the main clock stop bit to “1” causes the XOUT pin not to operate and the
power consumption goes down (when using an external clock input, the clock signal
is input regardless of the content of the main clock stop bit).
2.14.4 Precautions in Power Control
380
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
2.15 Programmable I/O Ports
2.15.1 Overview
Forty-eight programmable I/O ports and forty high-breakdown-voltage output ports are available. I/O pins
also serve as I/O pins for built-in peripheral functions.
Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In
addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. Ports P2, P3, and
P40–P43 are high-breakdown-voltage P-channel open-drain output structure. These ports have no pull-
up resistance.
The following is an overview of the programmable I/O ports:
(1) Writing to a port register
With the direction register set to output, the level of the written values from each relevant pin is output
by writing to a port register. The output level conforms to CMOS output or P-channel open-drain
output. “L” level of port which is built-in pull-down resistor is apply voltage to the VEE pin. Writing to the
port register, with the direction register set to input, inputs a value to the port register, but nothing is
output to the relevant pins. The output level remains floating.
(2) Reading a port register
With the direction register set to output, reading a port register takes out the content of the port regis-
ter, not the content of the pin. When the FLD controller is used, reading the port register takes out FLD
output. With the direction register set to input, reading the port register takes out the content of the pin.
(3) Exclusive high-breakdown-voltage output port
There are 40 exclusive output Ports: P0 to P2, P5 and P6.
All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output
ports except P2 have built-in pull-down resistance.
(4) Setting pull-up
The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the
four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is
not effective in ports whose direction register is set to output.
Do not set pull-up of corresponding pin when XCIN/XCOUT is set or a port is used as A-D input.
381
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(5) I/O functions of built-in peripheral devices
Table 2.15.1 shows relation between ports and I/O functions of built-in peripheral devices.
Table 2.15.1. Relation between ports and I/O functions of built-in peripheral devices
(6) Examples of working on non-used pins
Table 2.15.2 contains examples of working on non-used pins. There are shown here for mere ex-
amples. In practical use, make suitable changes and perform sufficient evaluation in compliance with
you application.
(a) Single-chip mode
Table 2.15.2. Examples of working on unused pins in single-chip mode
Port
P0 to P3 Internal peripheral device I/O pins
FLD controller output pins
FLD controller output pinsP4
0
to P4
3
P5, P6
P7
0
to P7
2
Timer B0 to B2 input pins
P7
3
Timer A0 I/O pin
P7
4
to P7
7
Timer A1 to A4 input pins/UART1 I/O pins
P8
0
to P8
5
External interrupt input pins
P8
6
, P8
7
Sub-clock input pins
P9
0
to P9
5
P9
6
A-D converter input pins
P9
7
D-A converter output pin/ X
IN
division clock output pin
/ DIM signal output pin of FLD controller
FLD controller output pins/UART0 I/O pinsP4
4
to P4
7
P10
0
to P10
7
D-A converter output pin/Clock I/O pin of serial I/O with automatic transfer function
FLD controller output pins
I/O pins of serial I/O with automatic transfer function
Pin name Connection
Ports P3, P4, P7 to P10
XOUT (Note 2), VEE
After setting for input mode, connect every pin to V SS or VCC via a
resistor; or after setting for output mode, leave these pins open.
(Note 1)
Open
AVSS, VREF Connect to VSS
If setting these pins in output mode and opening them, ports are in input mode until switched into
output mode by use of software after reset. Thus the voltage levels of the pins become unstable,
and there can be instances in which the power source current increases while the ports are in
input mode.
In view of an instance in which the contents of the direction registers change due to a runaway
generated by noise or other causes, setting the contents of the direction registers periodically by
use of software increases program reliability.
When an external clock is input to the X IN pin.
Note 1:
Note 2:
Ports P0 to P2, P5, P6
Open
382
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(7) Registers related to the programmable I/O ports
Figure 2.15.1 shows the memory map of programmable I/O ports-related registers, and Figures
2.15.2 to 2.15.4 show programmable I/O ports-related registers.
Figure 2.15.1. Memory map of programmable I/O ports-related registers
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03FC
16
03FD
16
03FE
16
03FF
16
Port P0 (P0)
Port P1 (P1)
Port P2 (P2)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P6 (P6)
Port P7 (P7)
Port P7 direction register (PD7)
Port P8 (P8)
Port P8 direction register (PD8)
Port P9 (P9)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
0359
16
035A
16
035B
16
035C
16
035D
16
P3 FLD/port switch register (P3FPR)
P5 digit output set register (P5DOR)
P6 digit output set register (P6DOR)
P4 FLD/port switch register (P4FPR)
P2 FLD/port switch register (P2FPR)
383
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.15.2. Programmable I/O ports-related registers (1)
Figure 2.15.3. Programmable I/O ports-related registers (2)
P
o
r
t
P
i
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
S
y
m
b
o
lA
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
P
D
i
(
i
=
3
t
o
1
0
,
e
x
c
e
p
t
5
,
6
)0
3
E
7
1
6
,
0
3
E
A
1
6
,
0
3
E
F
1
6
00
1
6
0
3
F
2
1
6
,
0
3
F
3
1
6
,
0
3
F
6
1
6
00
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
nB
i
t
s
y
m
b
o
lW
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
D
i
_
0P
o
r
t
P
i
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
1P
o
r
t
P
i
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
2P
o
r
t
P
i
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
3P
o
r
t
P
i
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
4P
o
r
t
P
i
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
5P
o
r
t
P
i
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
6P
o
r
t
P
i
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
D
i
_
7P
o
r
t
P
i
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
0
:
I
n
p
u
t
m
o
d
e
(
F
u
n
c
t
i
o
n
s
a
s
a
n
i
n
p
u
t
p
o
r
t
)
1
:
O
u
t
p
u
t
m
o
d
e
(
F
u
n
c
t
i
o
n
s
a
s
a
n
o
u
t
p
u
t
p
o
r
t
)
(
i
=
3
t
o
1
0
e
x
c
e
p
t
5
,
6
)
Port Pi register
Symbol Addres When reset
Pi (i = 0 to 10) 03E0
16
, 03E1
16
, 03E4
16
, 03E5
16
, 03E8
16
Indeterminate
03E9
16
, 03EC
16
, 03ED
16
, 03F0
16
, 03F1
16
, 03F4
16
Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 10)
384
Programmable I/O Ports
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 2.15.4. Programmable I/O ports-related registers (3)
P
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
S
y
m
b
o
l
A
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
P
U
R
0
0
3
FD
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
U
0
1P
4
4
t
o
P
4
7
p
u
l
l
-
u
p
P
U
0
6P
7
0
t
o
P
7
3
p
u
l
l
-
u
p
P
U
0
7P
7
4
t
o
P
7
7
p
u
l
l
-
u
p
P
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
S
y
m
b
o
l
A
d
d
r
e
s
s
W
h
e
n
r
e
s
e
t
P
U
R
1
0
3
F
E
1
6
0
0
1
6
B
i
t
n
a
m
eF
u
n
c
t
i
o
n
B
i
t
s
y
m
b
o
l
W
R
b
7b
6b
5b
4b
3b
2b
1b
0
P
U
1
0P
8
0
t
o
P
8
3
p
u
l
l
-
u
p
P
U
1
1P
8
4
t
o
P
8
7
p
u
l
l
-
u
p
P
U
1
2P
9
0
t
o
P
9
3
p
u
l
l
-
u
p
P
U
1
3P
9
4
t
o
P
9
7
p
u
l
l
-
u
p
P
U
1
4P
1
0
0
t
o
P
1
0
3
p
u
l
l
-
u
p
P
U
1
5P
1
0
4
t
o
P
1
0
7
p
u
l
l
-
u
p
T
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
i
s
p
u
l
l
e
d
h
i
g
h
w
i
t
h
a
p
u
l
l
-
u
p
r
e
s
i
s
t
o
r
0
:
N
o
t
p
u
l
l
e
d
h
i
g
h
1
:
P
u
l
l
e
d
h
i
g
h
T
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
i
s
p
u
l
l
e
d
h
i
g
h
w
i
t
h
a
p
u
l
l
-
u
p
r
e
s
i
s
t
o
r
0
:
N
o
t
p
u
l
l
e
d
h
i
g
h
1
:
P
u
l
l
e
d
h
i
g
h
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
e
s
e
b
i
t
s
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
T
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
p
o
r
t
i
s
p
u
l
l
e
d
h
i
g
h
w
i
t
h
a
p
u
l
l
-
u
p
r
e
s
i
s
t
o
r
0
:
N
o
t
p
u
l
l
e
d
h
i
g
h
1
:
P
u
l
l
e
d
h
i
g
h
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
I
n
a
n
a
t
t
e
m
p
t
t
o
w
r
i
t
e
t
o
t
h
i
s
b
i
t
,
w
r
i
t
e
“
0
”
.
T
h
e
v
a
l
u
e
,
i
f
r
e
a
d
,
t
u
r
n
s
o
u
t
t
o
b
e
i
n
d
e
t
e
r
m
i
n
a
t
e
.
Chapter 3
Examples of Peripheral functions Applications
386
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
This chapter presents applications in which peripheral functions built in the M30218 are used. They are
shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For
basic use, see Chapter 2 Peripheral Functions Usage.
Here follows the list of applications that appear in this chapter.
• 3.1 Long-period timers.............................................................................................................. P388
• 3.2 Variable-period variable-duty PWM output......................................................................... P392
• 3.3 Delayed one-shot output .................................................................................................... P396
• 3.4 Buzzer output ..................................................................................................................... P400
• 3.5 Solution for external interrupt pins shortage....................................................................... P402
• 3.6 Memory to memory DMA transfer ...................................................................................... P404
• 3.7 Controlling power using stop mode .................................................................................... P408
• 3.8 Controlling power using wait mode..................................................................................... P412
Applications
387
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Applications
This page kept blank for layout purposes.
388
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
3.1 Long-Period Timers
Overview
Specifications
Operation
Figure 3.1.1. Operation timing of long-period timers
In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit
prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection dia-
gram, and Figures 3.1.3 and 3.1.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Event counter mode of timer A
(1) Set timer A0 to timer mode, and set timer A1 to event counter mode.
(2) Perform a count on count source f1 using timer A0 to count for 1 ms, and perform a count
on timer A0 using timer A1 to count for 1 second.
(3) Connect a 10-MHz oscillator to XIN.
(1) Setting the count start flag to “1” causes the counter to begin counting. The counter of
timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. The
counter of timer A1 performs a down count on underflows in timer A0.
(3) If the counter of timer A1 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A1 interrupt request bit goes to “1”.
FFFF16
l
000016
Timer A0 counter
content (hex)
l = reload register content
Timer A1 count
start flag “1”
“0”
Timer A1 interrupt
request bit “1”
“0”
Timer A0 interrupt
request bit “1”
“0”
Timer A0 count
start flag “1”
“0”
Timer A1 counter
content (hex)
000016
n
FFFF16
Time
(1) Start count
Start count.
Time
n = reload register content
Set to “1” by software
Set to “1” by software
Cleard “0” by software
Cleared to “0” when interrupt request is accepted, or cleared by software
(2) Timer A0 underflow (3) Timer A1 underflow
389
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.1.2. Connection diagram of long-period timers
f
1
f
8
f
32
f
C32
Timer A0
Timer A1
Timer A0 interrupt request bit
Timer A1 interrupt request bit
Used for timer mode
Used for event counter mode
390
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.1.3. Set-up procedure of long-period timers (1)
Continued to the next page
Setting timer A0
Selecting timer mode and functions
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Timer A0 mode register [Address 0396 16]
TA0MR
Gate function select bit
0 0 : Gate function not available (TA0 IN pin is a normal port pin)
b4 b3
Selection of timer mode
b7 b0
00000
0 (Must always be “0” in timer mode)
Count source select bit
0 0 : f1
b7 b6
000
Setting divide ratio
b7 b0
(b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]
TA0
2716 0F16
Selecting event counter mode and each function
Setting timer A1
Pulse output function select bit
0 : Pulse is not output (TA1OUT pin is a normal port pin)
Timer A1 mode register [Address 0397 16]
TA1MR
Up/down switching cause select bit
0 : Up/down flag content
Selection of event counter mode
Fix to “0” when counting timer overflow flag
Count operation type select bit
0 : Reload type
0 (Must always be “0” in event counter mode)
Count polarity select bit
b7 b0
010000 00
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6 Count
source 100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
391
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.1.4. Set-up procedure of long-period timers (2)
Start counting
Continued from the previous page
b7 b0
Trigger select register [Address 0383
16
]
TRGSR
Timer A1 event/trigger select bit
1 0 : TA0 overflow is selected
b1 b0
01
Setting trigger select register
Setting divide ratio
b7 b0
(b15) (b8) b7 b0
Timer A1 register [Address 0389
16
, 0388
16
]
TA1
03
16
E7
16
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
b7 b0
11
392
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM out-
put. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and
Figures 3.2.3 and 3.2.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• One-shot timer mode of timer A
(1)
Set timer A0 in timer mode, and set timer A1 in one-shot timer mode with pulse-output function.
(2) Set 1 ms, the PWM period, to timer A0. Set 500 µs, the width of PWM “H” pulse, to timer A1.
Both timer A0 and timer A1 use f1 for the count source.
(3) Connect a 10-MHz oscillator to XIN.
(1) Setting the count start flag to “1” causes the counter of timer A0 to begin counting. The
counter of timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit gose to “1”.
(3)
An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When
the counter of timer A1 begins counting, the output level of the TA1
OUT
pin gose to “H”.
(4) As soon as the count of the counter of timer A1 becomes “000016”, the output level of TA1OUT
pin gose to “L”, and the counter reloads the content of the reload register and stops counting.
At the same time, the timer A1 interrupt request bit gose to “1”.
3.2 Variable-Period Variable-Duty PWM Output
Overview
Specifications
Operation
393
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.2.2. Connection diagram of variable-period variable-duty PWM output
Figure 3.2.1. Operation timing of variable-period variable-duty PWM output
FFFF16
l
000016
Timer A0 counter
content (hex)
l = reload register content
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
Timer A1 counter
content (hex)
000116
n
FFFF16
Time
(1) Timer A0 start count
Time
Timer A1 count
start flag
Timer A1 interrupt
request bit
Timer A0 interrupt
request bit
Timer A0 count
start flag
PWM pulse output
from TA1OUT pin “H”
“L”
n = reload register content
AAA
AAA
Set to “1” by software
Set to “1” by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
1ms 500µs
(2) Timer A0 underflow
(3) Timer A1 start count
(4) Timer A1 stop count
f
1
f
8
f
32
f
C32
Timer A0
Timer A1
Timer A0 interrupt request bit
Timer A1 interrupt request bit
Used for timer mode (Set to period)
Used for one-shot timer mode (Set to “H” width)
394
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1)
Continued to the next page
Setting timer A0
Pulse output function select bit
0 : Pulse is not output (TA0
OUT
pin is a normal port pin)
Selecting timer mode and functions
Timer A0 mode register [Address 0396
16
]
TA0MR
Gate function select bit
0 0 :
Gate function not available (TA0
IN
pin is a normal port pin)
b4 b3
Selection of timer mode
b7 b0
00000
0 (Must always be “0” in timer mode)
Count source select bit
0 0 : f
1
b7 b6
00 0
Setting divide ratio
b7 b0
(b15) (b8) b7 b0
Timer A0 register [Address 0387
16
, 0386
16
]
TA0
27
16
0F
16
Setting timer A1
Pulse output function select bit
1 : Pulse is output
Selecting one-shot timer mode and functions
Timer A1 mode register [Address 0397
16
]
TA1MR
External trigger select bit (Invalid when choosing timer's overflow as trigger)
Selection of one-shot timer mode
b7 b0
10011
0 (Must always be “0” in one-shot timer mode)
Trigger select bit
1 : Selected by event/trigger select register
000
Count source select bit
0 0 : f
1
b7 b6
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
395
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2)
Start counting
Continued from the previous page
b7 b0
Trigger select register [Address 0383
16
]
TRGSR
Timer A1 event/trigger select bit
1 0 : TA0 overflow is selected
b1 b0
01
Setting trigger select register
Setting one-shot timer's time
b7 b0
(b15) (b8) b7 b0
Timer A1 register [Address 0389
16
, 0388
16
]
TA1
13
16
88
16
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
b7 b0
11
396
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
The following are steps of outputting a pulse only once after a specified elapse since an external
trigger is input. Figure 3.3.1 shows the operation timing, Figure 3.3.2 shows the connection dia-
gram, and Figures 3.3.3 and 3.3.4 show the set-up procedure.
Use the following peripheral function:
• One-shot timer mode of timer A
(1) Set timer A0 in one-shot timer mode, and set timer A1 in one-shot timer mode with pulse-
output function.
(2) Set 1 ms, an interval before a pulse is output, in timer A0; and set 50 µs, a pulse width, in timer
A1. Both timer A0 and timer A1 use f1 for the count source.
(3) Connect a 10-MHz oscillator to XIN.
(1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of
timer A0 to count.
(2) If an effective edge, selected by use of the external trigger select bit, is input to the TA0IN pin,
the counter begins a down count. The counter of timer A0 performs a down count on count
source f1.
(3) As soon as the counter of timer A0 becomes “000016”, the counter reloads the content of the
reload register and stops counting. At this time, the timer A0 interrupt request bit gose to “1”.
(4) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting.
When timer A1 begins counting, the output level of the TA1OUT pin gose to “H”.
(5) As soon as the counter of timer A1 becomes “000016”, the output level of the TA1OUT pin
gose to “L”, the counter reloads the content of the reload register, and stops counting. At this
time, timer A1 interrupt request bit gose to “1”.
3.3 Delayed One-Shot Output
Overview
Specifications
Operation
397
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.3.1. Operation timing of delayed one-shot output
Figure 3.3.2. Connection diagram of delayed one-shot output
FFFF16
l
000116
Timer A0 counter
content (hex)
l = reload register content
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
Timer A1 counter
content (hex)
000116
n
FFFF16
Time
(2) Timer A0 start count
Time
Timer A1 count
start flag
Timer A1 interrupt
request bit
Timer A0 interrupt
request bit
Timer A0 count
start flag
Input signal from
TA0IN pin
PWM pulse output
from TA1OUT pin
Set to “1” by software
Set to “1” by software
“H”
“L”
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
“H”
“L” 1ms 50µs
(1) Count enabled
(3) Timer A0 stop count
(4) Timer A1 start count
(5) Timer A1 stop count
n = reload register content
f
1
f
8
f
32
f
C32
Timer A0
Timer A1
Timer A0 interrupt request bit
Timer A1 interrupt request bit
Used for one-shot timer mode
Used for one-shot timer mode
TA0
IN
pin input
398
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.3.3. Set-up procedure of delayed one-shot output (1)
Continued to the next page
Setting timer A0
Setting one-shot start flag
(Select TA0
IN
pin to input TA0 trigger)
b7 b0
One-shot start flag [Address 0382
16
]
ONSF
Timer A0 event/trigger select bit
0 0 : Input on TA0
IN
is selected (Note)
b7 b6
Note: Set the corresponding port direction register to “0”.
Setting delay time
b7 b0
(b15) (b8) b7 b0
Timer A0 register [Address 0387
16
, 0386
16
]
TA0
27
16
10
16
Pulse output function select bit
0 : Pulse is not output (TA0
OUT
pin is normal port pin)
Selecting one-shot timer mode and functions
Timer A0 mode register [Address 0396
16
]
TA0MR
External trigger select bit
0 : Falling edge of TA0
IN
pin's input signal
Selection of one-shot timer mode
b7 b0
10001
0 (Must always be “0” in one-shot timer mode)
Count source select bit
0 0 : f
1
b7 b6
Trigger select bit
1 : Selected by event/trigger select register
000
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
399
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.3.4. Set-up procedure of delayed one-shot output (2)
Start counting
Continued from the previous page
Setting one-shot timer's time
b7 b0
(b15) (b8) b7 b0
Timer A1 register [Address 0389
16
, 0388
16
]
TA1
01
16
F4
16
Setting count start flag
Count start flag [Address 0380
16
]
TABSR
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
b7 b0
11
Setting timer A1
Selecting one-shot timer mode and functions
Pulse output function select bit
1 : Pulse is output (TA1
OUT
pin is pulse output pin)
Timer A1 mode register [Address 0397
16
]
TA1MR
External trigger select bit
Invalid when choosing timer's overflow
Selection of one-shot timer mode
b7 b0
10011
0 (Must always be “0” in one-shot timer mode)
Count source select bit
0 0 : f
1
b7 b6
Trigger select bit
1 : Selected by event/trigger select register
000
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
Setting trigger select register
(Set timer A0 to trigger timer A1)
b7 b0
Trigger select register [Address 0383
16
]
TRGSR
01
Timer A1 event/trigger select bit
1 0 : TA0 overflow is selected
b1 b0
400
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
3.4 Buzzer Output
Overview
Specifications
Operation
Figure 3.4.1. Operation timing of buzzer output
The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and
Figure 3.4.2 shows the set-up procedure.
Use the following peripheral function:
• The pulse-outputting function in timer mode of timer A.
(1) Sound a 2-kHz buzz beep by use of timer A0.
(2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the
port high-impedance, and stabilize the potential resulting from pulling up.
(3) Connect a 10-MHz oscillator to XIN.
(1) The microcomputer begins performing a count on timer A0. Timer A0 has disabled interrupts.
(2) The microcomputer begins pulse output by setting the pulse output function select bit to
“Pulse output effected”. P75 changes into TA0OUT pin and outputs 2-kHz pulses.
(3) The microcomputer stops outputting pulses by setting the pulse output function select bit to
“Pulse output not effected”. P75 goes to an input pin, and the output from the pin becomes
high-impedance.
“0”
“1”
“0”
“1”
Timer A0
overflow timing
Count start flag
Pulse output
function select bit
P7
5
output
“0”
“1”
High-impedance High-impedance
(1) Start count (2) Buzzer output ON (3) Buzzer output OFF
401
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.4.2. Set-up procedure of buzzer output
Initialization of timer A0
b7 b0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0
OUT
pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0
IN
pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
0 0 : f
1
Timer A0 mode register
TA0MR [Address 0396
16
]
0000 0000
Timer A0 register
TA0 [Address 0387
16
, 0386
16
]
b15 b8 b7 b0
09
16
C4
16
b7 b0
Count start flag [Address 0380
16
]
TABSR
b7 b0
Timer A0 count start flag
1 : Starts counting
1
Initialization of port P7 direction register
b7 b0
Port P7
5
direction register
0 : Input mode
0Port P7 direction register [Address 03EF
16
]
PD7
b7 b0
Pulse output function select bit
1 : Pulse is output (Port P7
5
is TA0
OUT
output pin)
Timer A0 mode register [Address 0396
16
]
TA0MR
Buzzer ON
1
b7 b0
Pulse output function select bit
0 : Pulse is not output
Timer A0 mode register [Address 0396
16
]
TA0MR
Buzzer OFF
0
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f1
f8
f32
fC32
402
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
3.5 Solution for External Interrupt Pins Shortage
Overview
Specifications
Operation
The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up
procedure.
Use the following peripheral function:
• Event counter mode of timer A
(1) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
(1) Set timer A0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer A0.
(2) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
403
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins
Initialization of timer A0
b7 b0
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TA0
OUT
pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
0 (Must always be “0” in event counter mode)
Timer A0 mode register
TA0MR [Address 0396
16
]
0000 1000
Up/down flag [Address 0384
16
]
UDF
b7 b0
Timer A0 up/down flag
0 : Down count
0
Setting interrupt priority levels in timer A0
b7 b0
Timer A0 interrupt control register [Address 0055
16
]
TA0IC
Interrupt control level (set a value 1 to 7)
Setting interrupt enable flag (I flag)
b7 b0
Timer A0 count start flag
1 : Starts counting
Count start flag [Address 0380
16
]
TABSR
1
Initialization of port P7 direction register
b7 b0
Port P7
3
direction register
0 : Input mode
0Port P7 direction register [Address 03EF
16
]
PD7
Timer A0 register
TA0 [Address 0387
16
, 0386
16
]
b15 b8 b7 b0
00
16
00
16
b7 b0
404
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
3.6 Memory to Memory DMA Transfer
The following are steps for changing both source address and destination address to transfer
data from memory to another. The DMA transfer utilizes the workings that assign a higher priority
to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure
3.6.1 shows the operation timing, Figure 3.6.2 shows the block diagram, and Figures 3.6.3 and
3.6.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Two DMAC channels
• One-byte temporary RAM (address 080016)
(1) Transfer the content of memory extending over 128 bytes from address F800016 to a 128-
byte area starting from address 0040016. Transfer the content every time a timer A0 interrupt
request occurs.
(2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from
built-in memory to the destination.
(1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 trans-
fer request occur simultaneously, the former is executed first.
(2) DMA0 receives a transfer request and transfers data from the source to the built-in memory.
At this time, the source address is incremented.
(3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to
the destination. At this time, the destination address is incremented.
Overview
Specifications
Operation
Figure 3.6.1. Operation timing of memory to memory DMA transfer
DMAC Applications
Timer A0
transfer request
Address bus
“0”
“1”
“0”
“1”
“0”
“1”
(1) Transfer request generation
(2) Start DMA0 transferring
(3) Start DMA1 transferring
Instruction cycle DMA0 operation DMA1 operation
F8000
16
0800
16
0800
16
00400
16
WR signal
RD signal
Source address
Destination address
Source address
Destination address
The DMA0 operation and DMA1 operation are not necessarily executed in succession
due to the a cycle steal operation.
The instruction cycle varies from instruction to instruction.
Since the parts of the RD and WR signals shown in short-dash lines vary in step with
writing to the internal RAM, waveforms are not output to the RD and WR pins.
Note 1:
Note 2:
Note 3:
405
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.6.2. Block diagram of memory to memory DMA transfer
DMAC Applications
00400
16
0047F
16
Source area
Data transfer by DMA0
F8000
16
F807F
16
Destination area
Data transfer by DMA1
800
16
Temporary RAM
F8000
16
content
F8001
16
content
F8002
16
content
F807F
16
content
406
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.6.3. Set-up procedure of memory to memory DMA transfer (1)
DMAC applications
Continued to the next page
Initialization of DMA0
b7 b0
DMA request cause select bit
b3 b2 b1 b0
0 0 1 0 : Timer A0
DMA0 request cause select register
DM0SL [Address 03B8
16
]
0100 0
Software DMA request bit
0 : Software is not generated
b15 b8 b7 b0
8016 0016 DMA0 source pointer SAR0 [Address 0022
16
, 0021
16
, 0020
16
]
b7 b0
b23 b16
0F16
b7 b0 b15 b8 b7 b0
0816 0016 DMA0 destination DAR0 [Address 0026
16
, 0025
16
, 0024
16
]
pointer
b7 b0
b23 b16
0016
b7 b0
b15 b8 b7 b0
0016 7F16 DMA0 transfer counter TCR0 [Address 0029
16
, 0028
16
]
b7 b0
Transfer unit bit select bit
1 : 8 bits
Repeat transfer mode select bit
1 : Repeat transfer
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
1 : Forward
Destination address direction
select bit
0 : Fixed
b7 b0
DMA0 control register
DM0CON [Address 002C16]
110 101
b15 b8 b7 b0
0816 0016 DMA1 source pointer SAR1 [Address 0032
16
, 0031
16
, 0030
16
]
b7 b0
b23 b16
0016
b7 b0 b15 b8 b7 b0
0416 0016
b7 b0
b23 b16
0016
b7 b0
b15 b8 b7 b0
0016 7F16 DMA1 transfer counter TCR1 [Address 0039
16
, 0038
16
]
b7 b0
Initialization of DMA1
b7 b0
DMA request cause select bit
b3 b2 b1 b0
0 0 1 0 : Timer A0
DMA0 request cause select register
DM1SL [Address 03BA
16
]
0100 0
Software DMA request bit
0 : Software is not generated
Transfer unit bit select bit
1 : 8 bits
Repeat transfer mode select bit
1 : Repeat transfer
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
0 : Fixed
Destination address direction
select bit
1 : Forward
b7 b0
DMA1 control register
DM1CON [Address 003C16]
110 110
DMA1 destination
pointer DAR1 [Address 0036
16
, 0035
16
, 0034
16
]
407
Timer A Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.6.4. Set-up procedure of memory to memory DMA transfer (2)
DMAC applications
Timer A0 count start flag
1 : Starts counting
Continued from the previous page
Initialization of timer A0
Timer A0 mode register
TA0MR [Address 0396
16
]
Timer A0 register
TA0 [Address 0387, 0386
16
]
b15 b8 b7 b0
27
16
0F
16
b7 b0
b7 b0
1
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0
OUT
pin is a normal port pin)
Gate function select bit
b4 b3
0 0 :
Gate function not available (TA0
IN
pin is a normal port pin)
0 (Must always be fixed to “0” in timer mode)
Count source select bit
b7 b6
0 0 : f
1
Count source period
f(X
IN
) : 10MH
Z
f(Xc
IN
) : 32.768kH
Z
b7 b6
Count
source
100ns
800ns
3.2µs
976.56µs
00
01
10
11
f
1
f
8
f
32
f
C32
b7 b0
0000000 0
Count start flag [Address 0380
16
]
TABSR
408
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Overview
Specifications
Operation
3.7 Controlling Power Using Stop Mode
The following are steps for controlling power using stop mode. Figure 3.7.1 shows the operation
timing, Figure 3.7.2 shows an example of circuit, and Figures 3.7.3 and 3.7.4 show the set-up
procedure.
Use the following peripheral functions:
________
• INT5 interrupt
• Stop mode
(1) Use INT5 for the INT interrupt. Use the P85/INT5 pin as an input pin.
________
(2) When a INT5 interrupt request occurs, the stop mode is cleared.
________
(1) Enable INT5 interrupt and set the pull-up function to the P85 pin.
________
(2) Stop XIN to enter the stop mode. Enable INT5 interrupt at this time.
________
(3) When a INT5 interrupt request occurs by falling edge input to the P85 pin, the stop mode is
cleared. Execute the return processing for the other interrupts, which are stopped, in the
________
INT5 interrupt processing and others.
Figure 3.7.1. Operation timing of controlling power using stop mode
(1) Enter stop mode
(2) Clear stop mode
(3) Return processing
INT5 input
INT5 interrupt processing
CPU clock
Stop mode
409
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.7.2. Example of circuit of controling power using stop mode
P8
5
/ INT5
V
REF
I/O port
Key input
410
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.7.3. Set-up procedure of controlling power using stop mode (1)
Canceling protect
Protect register [Address 000A
16
]
PRCR
b7 b0
1
Enables writing to system clock control registers 0 and 1
(addresses 0006
16
and 0007
16
)
1 : Write-enabled
Main
NOP instruction X 5 INT5 interrupt request generation
Initial condition
b7 b0
Pull-up control register 2
[Address 03FE
16
]
PUR2
P8
4
to P8
7
pulled high
1
Port P8 direction register
[Address 03F2
16
]
PD8
b7 b0
0
Set P8
5
to input port
Interrupt enable level (IPL) = 0
Interrupt enable flag (I) = 1
INT5 interrupt control register
[Address 0049
16
]
INT5IC
Interrupt priority level select bit
Set higher value than the present IPL
b7 b0
100
Setting interrupt except stop mode cancel
I
nterrupt control register DMiIC(i=0, 1) [Address 004B
16
, 004C
16
]
ADIC [Address 004E
16
]
ASIOIC [Address 004F
16
]
FLDIC [Address 0050
16
]
SiTIC(i=0, 1) [Address 0051
16
, 0053
16
]
SiRIC(i=0, 1) [Address 0052
16
, 0054
16
]
TAiIC(i=0 to 4) [Address 0055
16
to 0059
16
]
TBiIC(i=0 to 2) [Address 005A
16
to 005C
16
]
Interrupt priority level select bit
000 : Interrupt disabled
b7 b0
000
Interrupt priority level select bit
000 : Interrupt disabled
b7 b0
000 INTiIC(i=0 to 4) [Address 0047
16
to 0048
16
]
[Address 005D
16
to 005F
16
]
0
Reserved bit
Always set to “0”
All clocks off (stop mode)
System clock control register 1 [Address 0007
16
]
CM1
b7 b0
All clock stop control bit
1 : All clocks off (stop mode)
10000
Reserved bit
Always set to “0”
Setting operation clock after returning from stop mode
System clock control register 0
[Address 0006
16
]
CM0
X
CIN
-X
COUT
generation
Port X
C
select bit
b7 b0
System clock select bit
X
CIN
, X
COUT
As this register becomes setting mentioned above when operating with X
CIN
(count source of BCLK is X
CIN
), the user does not need to set it again.
When operating with X
IN
, set port Xc select bit to “1” before setting system
clock select bit to “1”. The both bits cannot be set at the same time.
11
(When operating with XCIN after returning)
System clock control register 0
[Address 0006
16
]
CM0
On
Main clock (X
IN
-X
OUT
) stop bit
b7 b0
System clock select bit
X
IN
, X
OUT
As this register becomes setting mentioned above when
operating with X
IN
(count source of BCLK is X
IN
),
the user does not need to set it again.
00
(When operating with XIN after returning)
Polarity select bit
0 : Selects falling edge
Reserved bit
Always set to “0”
00
411
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.7.4. Set-up procedure of controlling power using stop mode (2)
INT5 interrupt
Store the registers
REIT instruction
Restore the registers
I
nterrupt control register DMiIC(i=0, 1) [Address 004B
16
, 004C
16
]
ADIC [Address 004E
16
]
ASIOIC [Address 004F
16
]
FLDIC [Address 0050
16
]
SiTIC(i=0, 1) [Address 0051
16
, 0053
16
]
SiRIC(i=0, 1) [Address 0052
16
, 0054
16
]
TAiIC(i=0 to 4) [Address 0055
16
to 0059
16
]
TBiIC(i=0 to 2) [Address 005A
16
to 005C
16
]
Interrupt priority level select bit
Set interrupt priority level of used interrupt to
these bits again
b7 b0
Interrupt priority level select bit
Set interrupt priority level of used
interrupt to these bits again
b7 b0
000 INTiIC(i=0 to 4) [Address 0047
16
to 0048
16
]
[Address 005D
16
to 005F
16
]
0
Always set to “0”
Returning interrupt except stop mode cancel
412
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
3.8 Controling Power Using Wait Mode
The following are steps for controling power using wait mode. Figure 3.8.1 shows the operation
timing, and Figures 3.8.2 to 3.8.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer B
• Wait mode
A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide
whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered;
if F_WIT = “0”, the wait mode is cleared.
(1) Connect a 32.768-kHz oscillator to XCIN to serve as the timer count source. As interrupts
occur every one second, which is a count the timer reaches, the controller returns from wait
mode and count the clock using a program.
________
(2) Clear wait mode if a INT0 interrupt request occurs.
(1) Switch the system clock from XIN to XCIN to get low-speed mode.
_______
(2)
Stop XIN and enter wait mode. In this instance, enable the timer B2 interrupt and the INT0 interrupt.
(3) When a timer B2 interrupt request occurs (at 1-second intervals), start supplying the BCLK
from XCIN.
At this time, count the clock within the routine that handles the timer B2 interrupts and enter
wait mode again.
_______
(4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within
_______
the INT0 interrupt, and switch the BCLK count source to XIN after oscillation is stabilized.
Overview
Specifications
Operation
Figure 3.8.1. Operation timing of controling power using wait mode
Timer B2
interrupt processing
Timer B overflow
X
CIN
X
OUT
BCLK
INT
0
(1) Shift to low-speed mode
(2) Stop X
IN
(3) Timer B2 interrupt (4) INT
0
interrupt
“H”
“L”
High-speed
Low-speed Low-speed Low-speed Low-speed
High-speed
413
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.8.2. Set-up procedure of controlling power using wait mode (1)
Main
Setting interrupt except clearing wait mode
Interrupt control register DMiIC (i = 0, 1) [Address 004B
16
, 004C
16
]
ADIC [Address 004E
16
]
ASIOIC [Address 004F
16
]
FLDIC [Address 0050
16
]
SiTIC (i = 0, 1) [Address 0051
16
, 0053
16
]
SiRIC (i = 0, 1) [Address 0052
16
, 0054
16
]
TAiIC (i = 0 to 4) [Address 0055
16
to 0059
16
]
TBiIC (i = 0 to 2) [Address 005A
16
to 005C
16
]
INTiIC (i =1 to 5) [Address 0047
16
to 0049
16
]
[Address 005E
16
, 005F
16
]
b7 b0
000
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Interrupt disabled
Initial condition
Interrupt priority level (IPL) = 0
Interrupt enable flag (I) = 1
b15 b8 b7 b0
03
16
FF
16
Timer B2 register [Address 0395
16
, 0394
16
]
TB2
b7 b0
1Clock prescaler reset flag [Address 0381
16
]
CPSRF
Rrescaler is reset
b7 b0
Count start flag [Address 0380
16
]
TABSR
1
TB2 start counting
b7 b0
100 Timer B2 interrupt control register [Address 005C
16
]
TB2IC
TB2 interrupt priority level
System clock select bit
0 : X
IN
-X
OUT
b7 b0
WAIT state internal clock stop bit
001 System clock control register 0 [Address 0006
16
]
CM0
Port Xc select bit
1 : Functions as X
CIN
-X
COUT
oscillator
Main clock (X
IN
-X
OUT
) stop bit
0 : Oscillating
Main clock divide ratio select bit 0
X
CIN
-X
COUT
drive capacity select bit
b7 b0
Timer B2 mode register [Address 039D
16
]
TB2MR
100
1
Operation mode select bit
b1 b0
0 0 : Timer mode
Count source select bit
b7 b6
1 1 : f
C32
(f(X
CIN
) divided by 32)
b7 b0
100 INT0 interrupt control register [Address 005D
16
]
INT0IC
INT0 interrupt priority level
Continued to the next page
0
414
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.8.3. Set-up procedure of controlling power using wait mode (2)
Canceling protect
Protect register [Address 000A
16
]
PRCR
b7 b0
1
Enables writing to system clock control registers 0 and 1 (address 0006
16
and 0007
16
)
1 : write-enabled
Switching system clock
b7 b0
System clock select bit
1 : X
CIN
-X
COUT
1System clock control register 0 [Address 0006
16
]
CM0
b7 b0
Main clock (X
IN
-X
OUT
) stop bit
1 : Off
1System clock control register 0 [Address 0006
16
]
CM0
Stopping main clock
[F_WIT] = 1
WAIT instruction
Switching system clock
b7 b0
System clock select bit
0 : X
IN
-X
OUT
0System clock control register 0 [Address 0006
16
]
CM0
b7 b0
Main clock (X
IN
-X
OUT
) stop bit
0 : On
0System clock control register 0 [Address 0006
16
]
CM0
Starting main clock oscillator
[F_WIT] : 1
=
≠
TB2 interrupt request generated
INT0 interrupt request generated
NOP instruction X 5
Continued from the previous page
Wait until the main clock has stabilized
415
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 3.8.4. Set-up procedure of controlling power using wait mode (3)
Store the registers
Restore the registers
REIT instruction
[F_WIT] = 0
INT0 interrupt
Store the registers
Restore the registers
REIT instruction
Counting clock
Timer B2 interrupt
416
Controlling Power Applications
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
This page kept blank for layout purposes.
Chapter 4
Interrupt
418
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable
flag (I flag) or whose interrupt priority cannot be changed by priority level.
Figure 4.1.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
4.1 Overview of Interrupt
4.1.1 Type of Interrupts
Figure 4.1.1 lists the types of interrupts.
419
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.1.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
420
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset ____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs. For address match interrupt, see 2.13 Address match Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt
These are interrupts DMA generates.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt
This is an interrupt that the SI/O automatic transfer generates.
• FLD interrupt
This is an interrupt that FLD generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates.
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT5 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
421
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
- FFFF816 to FFFFB16 -
Reset FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
4.1.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt
vector table. Set the first address of the interrupt routine in each vector table. Two types of interrupt
vector tables are available — fixed vector table in which addresses are fixed and variable vector
table in which addresses can be varied by the setting.
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 4.1.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 4.1.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
422
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Table 4.1.2. Interrupts assigned to the variable vector tables and addresses of vector tables
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 4.1.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Software interrupt number Interrupt source
Vector table address
Address (L) to address (H) Remarks
Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0
+44 to +47 (Note) Software interrupt number 11
+48 to +51 (Note)Software interrupt number 12
+56 to +59 (Note)Software interrupt number 14
+68 to +71 (Note)Software interrupt number 17
+72 to +75 (Note)Software interrupt number 18
+76 to +79 (Note)Software interrupt number 19
+80 to +83 (Note)Software interrupt number 20
+84 to +87 (Note)Software interrupt number 21
+88 to +91 (Note)Software interrupt number 22
+92 to +95 (Note)Software interrupt number 23
+96 to +99 (Note)Software interrupt number 24
+100 to +103 (Note)Software interrupt number 25
+104 to +107 (Note)Software interrupt number 26
+108 to +111 (Note)Software interrupt number 27
+112 to +115 (Note)Software interrupt number 28
+116 to +119 (Note)Software interrupt number 29
+120 to +123 (Note)Software interrupt number 30
+124 to +127 (Note)Software interrupt number 31
+128 to +131 (Note)Software interrupt number 32
+252 to +255 (Note)Software interrupt number 63
to
Note : Address relative to address in interrupt table register (INTB).
Cannot be masked I flagto
A-D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer B0
Timer B1
INT0
INT1
Software interrupt
+28 to +31 (Note) INT3Software interrupt number 7
+32 to +35 (Note) INT4Software interrupt number 8
+36 to +39 (Note) INT5Software interrupt number 9
DMA0
DMA1
+60 to +63 (Note)Software interrupt number 15 SI/O automatic transfer
+64 to +67 (Note)Software interrupt number 16 FLD
Timer A4
Timer B2
INT2
423
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.2.1. Memory map of the interrupt control registers
4.2 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 4.2.1 shows the memory map of the interrupt control registers, and Figure 4.2.2 shows the interrupt
control registers.
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A1 interrupt control register (TA1IC)
Timer A3 interrupt control register (TA3IC)
UART0 transmit interrupt control register (S0TIC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
Timer A4 interrupt control register (TA4IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control regster(S1TIC)
UART1 receive interrupt control register(S1RIC)
DMA1 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
A-D conversion interrupt control register (ADIC)
SI/O2 transmit interrupt control register (ASIOIC)
FLD interrupt control register (FLDIC)
INT4 interrupt control register (INT4IC)
INT5 interrupt control register (INT5IC)
INT3 interrupt control register (INT3IC)
424
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.2.2. Interrupt control registers
Symbol Address When reset
INTiIC(i=0 to 5) 005D16 to 005F16 XX00X0002
004716 to 004916
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
ILVL0
IR
POL
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
(Note1)
Interrupt control register(Note2)
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
A
A
AA
AA
Bit name FunctionBit symbol WR
Symbol Address When reset
DMiIC(i=0, 1) 004B16 to 004C16 XXXXX0002
ADIC 004E16 XXXXX0002
ASIOIC 004F16 XXXXX0002
FLDIC 005016 XXXXX0002
SiTIC(i=0, 1) 005116, 005316 XXXXX0002
SiRIC(i=0, 1) 005216, 005416 XXXXX0002
TAiIC(i=0 to 4) 005516 to 005916 XXXXX0002
TBiIC(i=0 to 2) 005A16 to 005C16 XXXXX0002
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
(Note1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
425
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt
4.2.1 Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in the
following timing:
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
effect as the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
acceptance of the interrupt is effective as the next instruction is executed.
4.2.2 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Previous
instruction REIT Interrupt sequence
Time
Interrupt request generated Determination whether or not to
accept interrupt request
Previous
instruction FSET I Interrupt sequence
Next instruction
Interrupt request generated Determination whether or not to
accept interrupt request
When changed by REIT instruction
When changed by FCLR, FSET, POPC, or LDC instruction
(If I flag is changed from 0 to 1 by REIT instruction)
(If I flag is changed from 0 to 1 by FSET instruction)
Time
426
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels en-
abled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 4.2.2. Interrupt levels enabled according
to the contents of the IPL
Table 4.2.1. Settings of interrupt priority levels
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in
the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction
that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes
effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the
instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in
the instruction used.
Interrupt priority
level select bit Interrupt priority
level Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL2 IPL1 IPL0
IPL
427
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.2.4 Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ;
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
428
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.3.1 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 4.3.1 shows the interrupt response time.
Figure 4.3.1. Interrupt response time
4.3 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the interrupt sequence is executed.
429
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Interrupt sources without priority levels
7
Value set in the IPL
Watchdog timer
Other Not changed
0
4.3.2 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 4.3.2 is set in the IPL.
Table 4.3.2. Relationship between interrupts without interrupt priority levels and IPL
Table 4.3.1. Time required for executing the interrupt sequence
Reset
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 4.3.1.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 4.3.2. Time required for executing the interrupt sequence
Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Indeterminate
123456789 101112 13 14 15 16 17 18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000 Indeterminate SP-2 SP-4 vec vec+2 PC
BCLK
Address bus
Data bus
W
R
430
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.3.3 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 4.3.3 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Figure 4.3.3. State of stack before and after acceptance of interrupt request
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLGL)
Content of previous stack
Stack area
Flag register
(FLGH)Program
counter (PCH)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB LSB
Program counter (PCL)
Program counter (PCM)
431
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.3.4. Operation of saving registers
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 4.3.4 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(2) Stack pointer (SP) contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)Program
counter (PC
H
)
Flag register
(FLG
H
)Program
counter (PC
H
)
432
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.5 Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted (see Figure 4.5.1).
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 4.5.2 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
4.4 Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
433
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.5.1. Maskable interrupts priorities (peripheral I/O interrupts)
Figure 4.5.2. Hardware interrupts priorities
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
A-D conversion
DMA1
Timer A0
UART1 transmission
UART0 transmission
DMA0
INT1
INT2
INT0
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
INT4
INT5
INT3
SI/O2 automatic transfer
FLD
434
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
4.6 Multiple Interrupts
The state when control branched to an interrupt routine is described below:
· The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
· The interrupt request bit of the accepted interrupt is set to “0”.
· The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned to
the accepted interrupt.
Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned
a priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts.
An interrupt request that is not accepted because of low priority will be held. If the condition following is met
when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request
being held is accepted.
Interrupt priority level of the interrupt request being held > Returned the IPL
435
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 4.6.1. Multiple interrupts
Main routine
Reset
I = 0
IPL = 0
I = 1
Interrupt 1
I = 0
IPL = 3
I = 1
Interrupt 2
I = 0
IPL = 5
REIT
I = 1
IPL = 3
Interrupt 3
REIT
I = 1
IPL = 0
Interrupt 3
I = 0
IPL = 2
REIT
I = 1
IPL = 0
Interrupt 1
Interrupt priority level = 3
Interrupt 2
Interrupt 3
Interrupt priority level = 5
Interrupt priority level = 2
Not acknowledged because
of low interrupt priority
Interrupt request
generated
Nesting
Time
: Automatically executed.
: Be sure to set in software.
I : Interrupt enable flag
IPL : Processor interrupt priority level
Main routine instructions
are not executed.
Multiple interrupts
436
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
______
Figure 4.7.1. Switching condition of INT interrupt request
4.7 Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
(3) External interrupt _______
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
_______
through INT5 regardless of the CPU operation clock.
________ ________
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”. Figure 4.7.1 shows the procedure for
______
changing the INT interrupt generate factor.
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt enable flag to “1”
(Enable interrupt)
437
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
(4) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ;
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
438
Interrupt
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
This page kept blank for layout purposes.
Chapter 5
Standard Characteristics
440
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
5.1 Standard DC Characteristics
The standard characteristics given in this section are examples of M30218MC-XXXXFP. The contents of
these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
5.1.1 Standard Ports Characteristics
Figures 5.1.1 through 5.1.6 show the standard ports characteristics.
441
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 5.1.1. IOH - VOH standard characteristics of ports P44 to P47, P7 to P10 (VCC = 5V)
Figure 5.1.2. IOL - VOL standard characteristics of ports P44to P47, P7 to P10 (VCC = 5V)
012345
–50
–25
I
OH
[mA]
V
OH
[V]
Ta = 90 °C
Ta = –20 °C
Ta = 25 °C
V
CC
= 5 V
CMOS ports
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
012345
50
25
I
OL
[mA]
V
OL
[V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Ta = 90 °C
Ta = 25 °C
V
CC
= 5 V
CMOS ports
Ta = –20 °C
442
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 5.1.3. IOH - VOH standard characteristics of ports P44to P47, P7 to P10 (VCC = 3V)
Figure 5.1.4. IOL - VOL standard characteristics of ports P44to P47, P7 to P10 (VCC = 3V)
0 1.5 3
–20
–10
I
OH
[mA]
V
OH
[V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Ta = 90 °C
Ta = 25 °C
V
CC
= 3 V
CMOS ports
Ta = –20 °C
0 1.5 3
–20
–10
I
OL
[mA]
V
OL
[V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Ta = 90 °C
Ta = 25 °C
V
CC
= 3 V
CMOS ports
Ta = –20 °C
443
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figure 5.1.5. IOH - VOH standard characteristics of ports P0 to P3, P40 to P43, P5, P6 (VCC = 5V)
Figure 5.1.6. IOL - VOL standard characteristics of ports P0 to P3, P40 to P43, P5, P6 (VCC = 3V)
012345
–100
–50
I
OH
[mA]
V
OH
[V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Ta = 90 °CTa = 25 °C
V
CC
= 5 V
High-breakdown-voltage ports
Ta = –20 °C
0 1.5 3
–50
–25
I
OH
[mA]
V
OH
[V]
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Ta = 90 °C
Ta = 25 °C
V
CC
= 3 V
High-breakdown-voltage ports
Ta = –20 °C
444
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
5.1.2 Characteristics of ICC-f(XIN)
Figures 5.1.7 and 5.1.8 show the Characteristics of ICC-f(XIN).
Figures 5.1.7. Characteristics of ICC-f(XIN) (VCC = 5V)
20
15
10
5
0024681012
X
IN
/ 1
I
CC
[mA]
f(X
IN
) [MHz]
V
CC
= 5 V
25
• Measurement conditions :
V
CC
= 5V, Ta = 25˚C, f(X
IN
) : square waveform input, single-chip mode
When access to ROM and RAM
• Register setting condition
X
IN
- X
OUT
drive capacity select bit = “1” (HIGH)
Main clock (X
IN
- X
OUT
) stop bit = “0” (On)
X
IN
/ 2
X
IN
/ 4
X
IN
/ 8
X
IN
/ 16
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
445
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Figures 5.1.8. Characteristics of ICC-f(XIN) (VCC = 3V)
20
15
10
5
0024681012
I
CC
[mA]
f(X
IN
) [MHz]
• Measurement conditions :
V
CC
= 3V, Ta = 25˚C, f(X
IN
) : square waveform input, single-chip mode
When access to ROM and RAM
• Register setting condition
X
IN
- X
OUT
drive capacity select bit = “1” (HIGH)
Main clock (X
IN
- X
OUT
) stop bit = “0” (On)
V
CC
= 3 V
X
IN
X
IN
/ 2
X
IN
/ 4
X
IN
/ 8
X
IN
/ 16
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
446
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
5.2 Standard Characteristics of A-D Converter
The standard characteristics given in this section are an example of M30218MC-XXXXFP. The contents
of these examples cannot be guaranteed. For standardize values, see “Electric characteristics”.
Figures 5.2.1 and 5.2.2 show the standard characteristics of the A-D converter.
The line on the top side of the graph represents absolute errors.
The line on the bottom side of the graph represents the width of input voltage bearing the equal output code.
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Measurement conditions (VCC = 5.12V, VREF = 5.12V, f(XIN) = 10MHz, Ta˚C)
Figure 5.2.1. Standard characteristics of the A-D converter
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
0 256 512 768 1024
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
M30218MC with sample & hold, 10 bit characteristics of A-D conversion
φAD = XIN = 10 MHz
AVcc = Vcc = Vref = 5.12 V
1 LSB = 5 mV
Absolute error [LSB]
A-D conversion output code
Absolute error [LSB] (without a quantization error)
Differential non-linearity error [LSB]
447
Standard Characteristics
Figure 5.2.2. Standard characteristics of the A-D converter
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(XIN) = 3.5MHz, Ta = 25˚C)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 64 128 192 256
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
M30218MC
8
bit, characteristics of A-D conversion
AVcc = Vcc = Vref = 3.072V
1 LSB = 12 mV
φ
AD
= X
IN
/2, X
IN
= 3.5 MHz
Absolute error [LSB]
A-D conversion output code
Absolute error [LSB] (without a quantization error)
Differential non-linearity error [LSB]
448
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
5.3 Standard Characteristics of D-A Converter
The standard characteristics given in this section are an example of M30218MC-XXXXFP. The contents of
these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
Figures 5.3.1 and 5.3.2 show the standard characteristics of the D-A converter.
The line on the bottom side of the graph represents absolute errors. This indicates the difference between
the measurement and the ideal analog value corresponding to the input code.
The line on the top side of the graph represents the variation width of analog output value corresponding to
1-bit variation in the input code.
449
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
Measurement conditions (VCC = 5.12V, VREF = 5.12V, f(XIN) = 10MHz, Ta = 25˚C)
Figure 5.3.1. Characteristics of the D-A converter
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
-30
-20
-10
0
10
20
30
0 32 64 96 128
-30
-20
-10
0
10
20
30
M30218MC 8 bit, characteristics of D-A conversion
Absolute accuracy
[mV]
1 LSB WIDTH = 20mV
Absolute accuracy [mV]
D-A input code
AVcc = Vcc = Vref = 5.12V
1LSB = 20mV
X
IN
= 10 MHz
-30
-20
-10
0
10
20
30
128 160 192 224 256-30
-20
-10
0
10
20
30
Absolute accuracy [mV]
D-A input code
450
Standard Characteristics
Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(XIN) = 3.5MHz, Ta = 25˚C)
Figure 5.3.2. Characteristics of the D-A converter
Note: Data described here are characteristic examples. The data values are not guaranteed.
Refer to section “Electrical characteristics” for rated values.
-50
-40
-30
-20
-10
0
10
20
30
40
50
0 32 64 96 128-50
-40
-30
-20
-10
0
10
20
30
40
50
M30218FC/MC 8 bit, characteristics of D-A conversion
Absolute accuracy
[mV]
1 LSB WIDTH = 20mV
Absolute accuracy [mV]
D-A input code
AVcc = Vcc = Vref = 3.072V
1LSB = 12mV
X
IN
= 3.5 MHz
-50
-40
-30
-20
-10
0
10
20
30
40
50
128 160 192 224 256-50
-40
-30
-20
-10
0
10
20
30
40
50
Absolute accuracy [mV]
D-A input code
451
Standard Characteristics
M
i
t
s
u
b
i
s
h
i
m
i
c
r
o
c
o
m
p
u
t
e
r
s
M
3
0
2
1
8
G
r
o
u
p
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
S
M
I
C
R
O
C
O
M
P
U
T
E
R
5.4 Standard Characteristics of Pull-Up Resistor
Figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor.
Figure 5.4.1. Example of the standard characteristics of the pull-up resistor
5.0
–200.0
V
I
(V)
0 1.0 2.0 3.0 4.0
–40.0
–100.0
–160.0
I
I
(µA)
Vcc = 5 V
Note: Data described here are characteristic examples. The data values are not guaranteed.
Vcc = 3 V
MITSUBISHI Single-Chip Microcomputer
User's Manual
M30218 Group
Dec. Second Edition 1999
REV.A1
Editioned by
Committee of editing of Mitsubishi Semiconductor USER'S MANUAL
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
Rev. Rev.
No. date
A First Edition 991125
A1 The followings are updated: 991221
Page 56 Figure 39: FLDC mode register
b3b2 (at rising edge of each digit)
10 : 2 X Tdisp
Page 447 Figure 5.2.2, Page 450 Figure 5.3.2 : Measurement conditions....f(XIN)=3.5MHz
REVISION DESCRIPTION LIST M30218 GROUP USER’S MANUAL
(1/1)
Revision Description
