NCV8501D50R2G - ON SEMICONDUCTOR

January, 2009 − Rev. 29

1Publication Order Number:

NCV8501/D

NCV8501 Series

Micropower 150 mA LDO

Linear Regulators

with ENABLE, DELAY,

RESET, and Monitor FLAG

The NCV8501 is a family of precision micropower voltage

regulators. Their output current capability is 150 mA. The family has

output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V.

The output voltage is accurate within ±2.0% with a maximum

dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature

drawing only 90 mA with a 100 mA load. This part is ideal for any and

all battery operated microprocessor equipment.

Microprocessor control logic includes an active RESET (with

DELAY), and a FLAG monitor which can be used to provide an early

warning signal to the microprocessor of a potential impending RESET

signal. The use of the FLAG monitor allows the microprocessor to

finish any signal processing before the RESET shuts the

microprocessor down.

The active RESET circuit operates correctly at an output voltage as

low as 1.0 V. The RESET function is activated during the power up

sequence or during normal operation if the output voltage drops

outside the regulation limits.

The regulator is protected against reverse battery, short circuit, and

thermal overload conditions. The device can withstand load dump

transients making it suitable for use in automotive environments. The

device has also been optimized for EMC conditions.

Features

•Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V

•±2.0% Output

•Low 90 mA Quiescent Current

•Fixed or Adjustable Output Voltage

•Active RESET

•ENABLE

•150 mA Output Current Capability

•Fault Protection

♦+60 V Peak Transient Voltage

♦−15 V Reverse Voltage

♦Short Circuit

♦Thermal Overload

•Early Warning through FLAG/MON Leads

•NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

•These are Pb−Free Devices

SO−8

D SUFFIX

CASE 751

See detailed ordering and shipping information in the package

dimensions section on page 14 of this data sheet.

ORDERING INFORMATION

SOIC 16 LEAD

WIDE BODY

EXPOSED PAD

PDW SUFFIX

CASE 751AG

http://onsemi.com

SO−8

SOW−16

E PAD

x = Voltage Ratings as Indicated Below:

A = Adjustable

2 = 2.5 V

3 = 3.3 V

5 = 5.0 V

8 = 8.0 V

0 = 10 V

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

MARKING DIAGRAMS

8501x

AWLYYWWG

8501x

ALYW

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GNDNC

FLAG

ENABLE

VADJ

MON

VOUT

VIN

PIN CONNECTIONS, ADJUSTABLE OUTPUT

SO−8

GNDDELAY

RESET

ENABLE

FLAG

MON

VOUT

VIN

PIN CONNECTIONS, FIXED OUTPUT

SO−8

ENABLEMON

116

NCVIN

NCNC

GNDNC

NCNC

NCVOUT

FLAGVADJ

SOW−16 E PAD

ENABLEMON

116

DELAYVIN

NCNC

GNDNC

NCNC

NCVOUT

RESETFLAG

SOW−16 E PAD

VOUT

GND

VIN

NCV8501

10 mF

10 k

RRST

RESET

10 mF

Microprocessor

DELAY

CDELAY

VBAT VDD

FLAG

Figure 1. Application Diagram

MON

RFLG

10 k

VADJ

(Adjustable

Output Only)

I/O I/O

ENABLE

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MAXIMUM RATINGS*

Rating Value Unit

VIN (dc) −15 to 45 V

Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) 60 V

Operating Voltage 45 V

VOUT (dc) −0.3 to 16 V

Voltage Range (RESET, FLAG)−0.3 to 10 V

Input Voltage Range (MON)

Input Voltage Range (VAOJ)

−0.3 to 10

−0.3 to 16

Input Voltage Range (ENABLE) −0.3 to 10** V

ESD Susceptibility (Human Body Model) 2.0 kV

Junction Temperature, TJ−40 to +150 °C

Storage Temperature, TS−55 to 150 °C

Package Thermal Resistance, SO−8: Junction−to−Case, RqJC

Junction−to−Ambient, RqJA

165

°C/W

Package Thermal Resistance, SOW−16 E PAD: Junction−to−Case, RqJC

Junction−to−Ambient, RqJA

Junction−to−Pin, RqJP (Note 1)

°C/W

Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2) 260 Peak

(Note 3)

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

*During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply.

Thermal dissipation must be observed closely.

**Reference Figure 15 for switched−battery ENABLE application.

1. Measured to pin 16.

2. 150 second maximum above 217°C.

3. −5°C / +0°C allowable conditions.

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ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option

(Note 4); unless otherwise specified.)

Characteristic Test Conditions Min Typ Max Unit

Output Stage

Output Voltage for 2.5 V Option 6.5 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA

5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA

2.450

2.425

2.5

2.550

2.575

Output Voltage for 3.3 V Option 7.3 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA

5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA

3.234

3.201

3.3

3.366

3.399

Output Voltage for 5.0 V Option 9.0 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA

6.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA

4.90

4.85

5.0

5.10

5.15

Output Voltage for 8.0 V Option 9.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 7.76 8.0 8.24 V

Output Voltage for 10 V Option 11 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 9.7 10 10.3 V

Output Voltage for Adjustable Option VOUT = VADJ (Unity Gain)

6.5 V < VIN < 16 V, 100 mA < IOUT < 150 mA

5.5 V < VIN < 26 V, 100 mA < IOUT < 150 mA

1.254

1.242

1.280

1.306

1.318

Dropout Voltage (VIN − VOUT)

(5.0 V, 8.0 V, 10 V, and

Adj. > 5.0 V Options Only)

IOUT = 150 mA

IOUT = 1.0 mA

−

400

100

600

150

Load Regulation VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA −30 5.0 30 mV

Line Regulation [VOUT(Typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA −15 60 mV

Quiescent Current, Low Load

2.5 V Option

3.3 V Option

5.0 V Option

8.0 V Option

10 V Option

Adjustable Option

IOUT = 100 mA, VIN = 12 V, MON = VOUT

−

100

125

150

Quiescent Current, Medium Load

All Options

IOUT = 75 mA, VIN = 14 V, MON = VOUT −4.0 6.0 mA

Quiescent Current, High Load

All Options

IOUT = 150 mA, VIN = 14 V, MON = VOUT −12 19 mA

Quiescent Current, (IQ)

Sleep Mode

ENABLE = 0 V, VIN = 12 V −12 30 mA

Current Limit −151 300 −mA

Short Circuit Output Current VOUT = 0 V 40 190 −mA

Thermal Shutdown (Guaranteed by Design) 150 180 −°C

Reset Function (RESET)

RESET Threshold for 2.5 V Option

HIGH (VRH)

LOW (VRL)

5.5 V ≤ VIN ≤ 26 V (Note 5)

VOUT Increasing

VOUT Decreasing

2.28

2.25

2.350

2.300

0.98 × VOUT

0.97 × VOUT

RESET Threshold for 3.3 V Option

HIGH (VRH)

LOW (VRL)

5.5 V ≤ VIN ≤ 26 V (Note 5)

VOUT Increasing

VOUT Decreasing

3.00

2.97

3.102

3.036

0.98 × VOUT

0.97 × VOUT

RESET Threshold for 5.0 V Option

HIGH (VRH)

LOW (VRL)

VOUT Increasing

VOUT Decreasing

4.55

4.50

4.70

4.60

0.98 × VOUT

0.97 × VOUT

RESET Threshold for 8.0 V Option

HIGH (VRH)

LOW (VRL)

VOUT Increasing

VOUT Decreasing

7.05

7.00

7.52

7.36

0.98 × VOUT

0.97 × VOUT

4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.

5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation.

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ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option

(Note 4); unless otherwise specified.)

Characteristic UnitMaxTypMinTest Conditions

Reset Function (RESET)

RESET Threshold for 10 V Option

HIGH (VRH)

LOW (VRL)

VOUT Increasing

VOUT Decreasing

8.60

8.50

9.40

9.20

0.98 × VOUT

0.97 × VOUT

Output Voltage

Low (VRLO)1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k −0.1 0.4 V

DELAY Switching Threshold (VDT)−1.4 1.8 2.2 V

DELAY Low Voltage VOUT < RESET Threshold Low(min) − − 0.1 V

DELAY Charge Current DELAY = 1.0 V, VOUT > VRH 1.5 2.5 3.5 mA

DELAY Discharge Current DELAY = 1.0 V, VOUT = 1.5 V 5.0 − − mA

FLAG/Monitor

Monitor Threshold Increasing and Decreasing 1.10 1.20 1.31 V

Hysteresis −20 50 100 mV

Input Current MON = 2.0 V −0.5 0.1 0.5 mA

Output Saturation Voltage MON = 0 V, IFLAG = 1.0 mA −0.1 0.4 V

Voltage Adjust (Adjustable Output only)

Input Current VADJ = 1.28 V −0.5 −0.5 mA

ENABLE

Input Threshold Low

High

−

3.0

−

0.5

−

Input Current ENABLE = 5.0 V −1.0 5.0 mA

4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.

5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation.

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PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT

Package Pin Number

Pin Symbol Function

SO−8

SOW−16

E PAD

1 7 VIN Input Voltage.

2 8 MON Monitor. Input for early warning comparator. If not needed connect to VOUT.

3 9 ENABLE ENABLE control for the IC. A high powers the device up.

4 3−6, 10−12,

14, 15

NC No connection.

5 13 GND Ground. All GND leads must be connected to Ground.

6 16 FLAG Open collector output from early warning comparator.

7 1 VADJ Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage.

8 2 VOUT ±2.0%, 150 mA output.

PACKAGE PIN DESCRIPTION, FIXED OUTPUT

Package Pin Number

Pin Symbol Function

SO−8

SOW−16

E PAD

1 7 VIN Input Voltage.

2 8 MON Monitor. Input for early warning comparator. If not needed connect to VOUT.

3 9 ENABLE ENABLE control for the IC. A high powers the device up.

4 10 DELAY Timing capacitor for RESET function.

5 13 GND Ground. All GND leads must be connected to Ground.

6 16 RESET Active reset (accurate to VOUT ≥ 1.0 V)

7 1 FLAG Open collector output from early warning comparator.

8 2 VOUT ±2.0%, 150 mA output.

−3−6, 11, 12,

14, 15

NC No connection.

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TYPICAL PERFORMANCE CHARACTERISTICS

−40

VOUT (V)

4.98

Temperature (°C)

4.99

5.00

5.01

−25 −10 1255 203550658095110

VOUT = 5.0 V

VIN = 14 V

IOUT = 5.0 mA

Figure 2. Output Voltage vs. Temperature

−40

VOUT (V)

3.27

Temperature (°C)

3.32

3.33

3.35

−25 −10 1255 203550658095110

3.34

3.29

3.30

3.31

3.28

VOUT = 3.3 V

VIN = 14 V

IOUT = 5.0 mA

Figure 3. Output Voltage vs. Temperature

Figure 4. Quiescent Current vs. Output Current Figure 5. Quiescent Current vs. Output Current

+25°C

−40°C

IQ (mA)

IOUT (mA)

0.2

0.4

0.6

0.8

1.0

1.2

510152025

+125°C

VIN = 12 V

IQ (mA)

IOUT (mA)

15 30 45 60 14075 90 105 120 135

+25°C

−40°C

+125°C

VIN = 12 V

IQ (mA)

VIN (V)

8101214 2616 18 20 22 24

IOUT = 10 mA

IOUT = 50 mA

IOUT = 100 mA

T = 25°C

Figure 6. Quiescent Current vs. Input Voltage Figure 7. Quiescent Current vs. Input Voltage

IOUT = 100 mA

IQ (mA)

VIN (V)

100

120

8101214 2

16 18 20 22 24

T = 25°C

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TYPICAL PERFORMANCE CHARACTERISTICS

+25°C

−40°C

+125°C

Dropout Voltage (mV)

IOUT (mA)

150

200

250

300

350

400

450

25 50 75 100 150

100

125

Figure 8. Dropout Voltage vs. Output Current

VOUT = 5.0 V, 8.0 V, or 10 V

Quiescent Current (mA)

−40

Temperature (°C)

−25 −10 1255 203550658095110

Figure 9. Sleep Mode IQ vs. Temperature

VIN = 12 V

0.01

0.1

1.0

100

1000

0 102030 5060708090100110

OUTPUT CURRENT (mA)

ESR (W)

CVout = 10 mF

CVout = 0.1 mF

Unstable Region

Stable Region

0.01

0.1

1.0

100

1000

0 102030405060708090100

OUTPUT CURRENT (mA)

ESR (W)

CVOUT = 10 mF

10 V

8 V

5 V

3.3 V

2.5 V

Unstable Region

Stable Region

Figure 10. Output Stability with Output

Voltage Change

Figure 11. Output Stability with Output

Capacitor Change

0.1 10 100

(kHz)

(dB)

Iout = 150 mA

1.0

Figure 12. Audio Frequency Power Supply

Rejection Ratio

Iout = 10 mA

Iout = 80 mA

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VIN

RESET

VOUT

FLAG

Delay

Figure 13. Block Diagram

GND

MON

Current Source

(Circuit Bias)

Current Limit

Sense

Error Amplifier

VBG

IBIAS

VBG

IBIAS

VBG

IBIAS

+−

−

Bandgap

Reference

Thermal

Protection

1.8 V

3.0 mA

20 k

Adjustable

Version only

VADJ

ENABLE

Fixed Voltage only

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CIRCUIT DESCRIPTION

REGULATOR CONTROL FUNCTIONS

The NCV8501 contains the microprocessor compatible

control function RESET (Figure 14).

Figure 14. Reset and Delay Circuit Wave Forms

VIN

VOUT

RESET

DELAY

(VDT)

Threshold

DELAY

Threshold

RESET

TdTd

RESET Function

A RESET signal (low voltage) is generated as the IC

powers up until VOUT is within 6.0% of the regulated output

voltage, or when VOUT drops out of regulation,and is lower

than 8.0% below the regulated output voltage. Hysteresis is

included in the function to minimize oscillations.

The RESET output is an open collector NPN transistor,

controlled by a low voltage detection circuit. The circuit is

functionally independent of the rest of the IC thereby

guaranteeing that the RESET signal is valid for VOUT as low

as 1.0 V.

ENABLE Function

The part stays in a low IQ sleep mode when the ENABLE

pin is held low. The part has an internal pull down if the pin

is left floating. This is intended for failure modes only. An

external connection (active pulldown, resistor, or switch) for

normal operation is recommended.

The integrity of the ENABLE pin allows it to be tied

directly to the battery line through an external resistor. It will

withstand load dump potentials in this configuration.

Figure 15. ENABLE Function

VIN VOUT

GND

NCV8501

ENABLE

VBAT

10 k

DELAY Function

The reset delay circuit provides a programmable (by

external capacitor) delay on the RESET output lead.

The DELAY lead provides source current (typically 2.5 mA)

to the external DELAY capacitor during the following

proceedings:

1. During Power Up (once the regulation threshold

has been verified).

2. After a reset event has occurred and the device is

back in regulation. The DELAY capacitor is

discharged when the regulation (RESET threshold)

has been violated. This is a latched incident. The

capacitor will fully discharge and wait for the

device to regulate before going through the delay

time event again.

FLAG/Monitor Function

An on−chip comparator is provided to perform an early

warning to the microprocessor of a possible reset signal. The

reset signal typically turns the microprocessor off

instantaneously. This can cause unpredictable results with

the microprocessor. The signal received from the FLAG pin

will allow the microprocessor time to complete its present

task before shutting down. This function is performed by a

comparator referenced to the bandgap reference. The actual

trip point can be programmed externally using a resistor

divider to the input monitor (MON) (Figure 16). The typical

threshold is 1.20 V on the MON pin.

Figure 16. FLAG/Monitor Function

VBAT

VIN

MON

VOUT

COUT

VCC

I/O

RESET

FLAG

RESET

GND

DELAY

NCV8501

RADJ

Voltage Adjust

Figure 17 shows the device setup for a user configurable

output voltage. The feedback to the VADJ pin is taken from

a voltage divider referenced to the output voltage. The loop

is balanced around the Unity Gain threshold (1.28 V

typical).

Figure 17. Adjustable Output Voltage

VOUT

VADJ

NCV8501 15 k

5.1 k

COUT

≈5.0 V

1.28 V

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APPLICATION NOTES

Figure 18. Additional Output Current

NCV8501

VIN VOUT

VADJ

0.1 mF

VBAT

5.0 V

MJD31C

294 k

100 k

47 mF

>1 Amp

Adding Capability

Figure 18 shows how the adjustable version of parts can

be used with an external pass transistor for additional current

capability. The setup as shown will provide greater than 1

Amp of output current.

FLAG MONITOR

Figure 19 shows the FLAG Monitor waveforms as a result

of the circuit depicted in Figure 16. As the output voltage

falls (VOUT), the Monitor threshold is crossed. This causes

the voltage on the FLAG output to go low sending a warning

signal to the microprocessor that a RESET signal may occur

in a short period of time. TWAR NI N G is the time the

microprocessor has to complete the function it is currently

working on and get ready for the RESET shutdown signal.

Figure 19. FLAG Monitor Circuit Waveform

VOUT

MON

RESET

FLAG Monitor

Ref. Voltage

TWARNING

FLAG

Figure 20. Test and Application Circuit Showing

Output Compensation

VIN VOUT

COUT**

10 mF

RRST

RESET

CIN*

0.1 mFNCV8501

*CIN required if regulator is located far from the power supply filter

**COUT required for stability. Capacitor must operate at minimum

temperature expected

SETTING THE DELAY TIME

The delay time is controlled by the Reset Delay Low

Voltage, Delay Switching Threshold, and the Delay Charge

Current. The delay follows the equation:

tDELAY +ƪCDELAY(Vdt *Reset Delay Low Voltage)ƫ

Delay Charge Current

Example:

Using CDELAY = 33 nF.

Assume reset Delay Low Voltage = 0.

Use the typical value for Vdt = 1.8 V.

Use the typical value for Delay Charge Current = 2.5 mA.

tDELAY +ƪ33 nF(1.8 *0)ƫ

2.5 mA+23.8 ms

STABILITY CONSIDERATIONS

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: start−up

delay, load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints.

The value for the output capacitor COUT shown in Figure 20

should work for most applications, however it is not

necessarily the optimized solution.

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UNDERSTANDING THE NCV8501 ENABLE PIN

INPUT CURRENT

Figure 21. NCV8501 Enable Function Equivalent

Circuit

VCC

GND

ENABLE

5μA

20K

1.2M

11V 7V

~3.85V

Z1 Z2

R2 D1

1.25VZ3

D2 D3

Internal

power

rail

D6 Internal

reference

(max)

Z1, R1, and Z2 provide ESD and overvoltage protection.

Note that, for ENABLE pin voltages in excess of 10 V, an

external series resistor is required to limit the current into

Z1.

For ENABLE pin voltages less than +7 V, the 5 mA

(maximum value) current source dominates the input

current, as the opposing P1 base current is negligible by

comparison.

For ENABLE pin voltages between +7 V and +11 V, the

input current is given by:

5 mA + ((VENABLE − 7) / 20 kW)

For ENABLE pin voltages in excess of 10 V (Z1

breakover voltage can be as low as 10 V), the input current

is dominated by the external series resistor. For the case

where VENABLE = 12 V; REXT = 10 kW, the input current can

be up to (2 V/10 kW), = 200 mA.

The ENABLE threshold is that voltage required to

achieve ~3.85 V at the base of N1, or approximately (3.85 V

− 2 Vbe). At +20°C, this threshold is ~2.55 V. At −40°C, it

can be as high as 3 V.

If the value of REXT is increased to ~200 kW, to reduce

ENABLE input current, then the worst−case drop across

REXT must be added to 3 V to determine the effective

maximum ENABLE threshold. At VENABLE < 7 V, we only

need to consider the 5 mA current sink.

Max effective threshold = 3 V + (5 mA * 220 kW)

= 3 V + 1.1 V

= 4.1 V

CALCULATING POWER DISSIPATION IN A

SINGLE OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output

regulator (Figure 22) is:

PD(max) +[VIN(max) *VOUT(min)]IOUT(max)

)VIN(max)IQ

(eq. 1)

where:

VIN(max) is the maximum input voltage,

VOUT(min) is the minimum output voltage,

IOUT(max) is the maximum output current for the

application, and

IQ is the quiescent current the regulator consumes at

IOUT(max).

Once the value of PD(max) is known, the maximum

permissible value of RqJA can be calculated:

RQJA +150C*TA

(eq. 2)

The value of RqJA can then be compared with those in the

package section of the data sheet. Those packages with

RqJA

’s less than the calculated value in Equation 2 will keep

the die temperature below 150°C.

In some cases, none of the packages will be sufficient to

dissipate the heat generated by the IC, and an external

heatsink will be required.

SMART

REGULATOR®

Control

Features

IOUT

IIN

Figure 22. Single Output Regulator with Key

Performance Parameters Labeled

VIN VOUT

}

Figure 23. 16 Lead SOW (Exposed Pad), qJA as a

Function of the Pad Copper Area (2 oz. Cu

Thickness), Board Material = 0.0625, G−10/R−4

100

Thermal Resistance,

Junction to Ambient, RqJA, (°C/W)

Copper Area (mm2)

200 400 800

600

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HEATSINKS

A heatsink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

determine the value of RqJA:

RqJA +RqJC )RqCS )RqSA (eq. 3)

where:

RqJC = the junction−to−case thermal resistance,

RqCS = the case−to−heatsink thermal resistance, and

RqSA = the heatsink−to−ambient thermal resistance.

RqJC appears in the package section of the data sheet. Like

RqJA, it too is a function of package type. RqCS and RqSA are

functions of the package type, heatsink and the interface

between them. These values appear in heatsink data sheets

of heatsink manufacturers.

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ORDERING INFORMATION

Device Output Voltage Package Shipping†

NCV8501DADJG Adjustable SO−8

(Pb−Free) 98 Units/Rail

NCV8501DADJR2G Adjustable SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDWADJG Adjustable SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDWADJR2G Adjustable SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

NCV8501D25G 2.5 V SO−8

(Pb−Free) 98 Units/Rail

NCV8501D25R2G 2.5 V SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDW25G 2.5 V SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDW25R2G 2.5 V SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

NCV8501D33G 3.3 V SO−8

(Pb−Free) 98 Units/Rail

NCV8501D33R2G 3.3 V SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDW33G 3.3 V SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDW33R2G 3.3 V SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

NCV8501D50G 5.0 V SO−8

(Pb−Free) 98 Units/Rail

NCV8501D50R2G 5.0 V SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDW50G 5.0 V SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDW50R2G 5.0 V SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

NCV8501D80G 8.0 V SO−8

(Pb−Free) 98 Units/Rail

NCV8501D80R2G 8.0 V SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDW80G 8.0 V SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDW80R2G 8.0 V SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

NCV8501D100G 10 V SO−8

(Pb−free) 98 Units/Rail

NCV8501D100R2G 10 V SO−8

(Pb−Free) 2500 Tape & Reel

NCV8501PDW100G 10 V SOW−16 Exposed Pad

(Pb−Free) 47 Units/Rail

NCV8501PDW100R2G 10 V SOW−16 Exposed Pad

(Pb−Free) 1000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

NCV8501 Series

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NCV8501 Series

http://onsemi.com

PACKAGE DIMENSIONS

SOIC 16 LEAD WIDE BODY, EXPOSED PAD

PDW SUFFIX

CASE 751AG−01

ISSUE A

−W−

−U−

0.25 (0.010) W

−T−

SEATING

PLANE

D16 PL

0.25 (0.010) TUW

S S

DETAIL E

R x 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.

14 PL

PIN 1 I.D.

16 9

TOP SIDE

0.10 (0.004) T

EXPOSED PAD 18

BACK SIDE

DIM

MIN MAX MIN MAX

INCHES

10.15 10.45 0.400 0.411

MILLIMETERS

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.50 0.90 0.020 0.035

G1.27 BSC 0.050 BSC

H3.45 3.66 0.136 0.144

J0.25 0.32 0.010 0.012

K0.00 0.10 0.000 0.004

L4.72 4.93 0.186 0.194

M0 7 0 7

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

____

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.350

0.175

0.050

0.376

0.188

0.200

0.074

DIMENSIONS: INCHES

0.024 0.150

Exposed

Pad

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCV8501/D

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

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Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative