5-1
FAST AND LS TTL DATA
OCTAL D FLIP-FLOP WITH CLEAR
The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of
eight D-Type Flip-Flops with a Common Clock and an asynchronous active
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
inch lead spacing.
•8-Bit High Speed Register
•Parallel Register
•Common Clock and Master Reset
•Input Clamp Diodes Limit High-Speed Termination Effects
18 17 16 15 14 13
1234567
20 19
8
VCC
MR
Q7D7D6Q6D5
Q5D4
Q0D0D1Q1Q2D2D3910
Q
3
GND
12 11
Q4CP
CONNECTION DIAGRAM DIP (TOP VIEW)
PIN NAMES LOADING (Note a)
HIGH LOW
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
D0–D7Data Inputs 0.5 U.L. 0.25 U.L.
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.
Q0–Q7Register Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
TRUTH TABLE
MR CP DxQx
L X X L
H H H
H L L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM
CP
MR
D0D1D2D3D4D5D6D7
Q0Q1Q2Q3Q4Q5Q6Q7
CP D
CD QCP D
CD QCP D
CD QCP D
CD QCP D
CD QCP D
CD QCP D
CD QCP D
CD Q
14
1
26
73 84
59
11
12
13
15
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
17 18
16 19
SN54/74LS273
OCTAL D FLIP-FLOP
WITH CLEAR
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20 1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-2
FAST AND LS TTL DATA
SN54/74LS273
FUNCTIONAL DESCRIPTION
The SN54/74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the setup
and hold time requirements of the D inputs is transferred to the
Q outputs on the LOW-to-HIGH transition of the clock input.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
V
OH
O
u
t
pu
t
HIGH
V
o
lt
age 74 2.7 3.5 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 27 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Input Clock Frequency 30 40 MHz Figure 1
tPHL Propagation Delay, MR to Q Output 18 27 ns Figure 2
tPLH
tPHL Propagation Delay, Clock to Output 17
18 27
27 ns Figure 1
5-3
FAST AND LS TTL DATA
SN54/74LS273
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
twPulse Width, Clock or Clear 20 ns Figure 1
tsData Setup T ime 20 ns Figure 1
thHold T ime 5.0 ns Figure 1
trec Recovery Time 25 ns Figure 2
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
1.3 V
1.3 V 1.3 V 1.3 V 1.3 VCP
D
Qn
ts(H) th(H) ts(L) th(L)
1/f max
tPLH
tPLH
tPHL
tPHL
MR
CP
Qn
Qn
1.3 V
1.3 V
1.3 V
1.3 V1.3 V
1.3 V
trec
tPHL
tPLH
tW
1.3 V 1.3 V 1.3 V
*
tW
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
