EMBEDDED ULTRA-LOW POWER Intel486TM SX PROCESSOR Ultra-Low Power Version of the Intel486TM 176-Lead Thin Quad Flat Pack (TQFP) SX Processor -- 32-Bit RISC Technology Core -- 8-Kbyte Write-Through Cache -- Four Internal Write Buffers -- Burst Bus Cycles -- Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices -- Intel System Management Mode (SMM) -- Boundary Scan (JTAG) Separate Voltage Supply for Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal for Embedded Battery-Operated and Hand-Held Applications 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32 32-Bit Data Bus 32 Linear Address Core Clock Clock Control CLK Input 32 PCD PWT Barrel Shifter Register File Base/ Index Bus 32 Segmentation Unit Descriptor Registers Limit and Attribute PLA ALU Bus Interface 2 Paging Unit Cache Unit 20 Physical Address Translation Lookaside Buffer 8 Kbyte Cache 32 32 Address Drivers Write Buffers 4 x 32 Data Bus Bus Control Displacement Bus 32 Prefetcher MicroInstruction Code Stream Control ROM Instruction Decode D31-D0 32 Transceivers 128 Control & Protection Test Unit A31-A2 BE3#- BE0# 32-Byte Code Queue 2x16 Bytes 24 Decoded Instruction Path Request Sequencer Burst Bus Control Bus Size Control Cache Control Boundary Scan Control ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# STPCLK# BRDY# BLAST# BS16# BS8# KEN# FLUSH# AHOLD EADS# TCK TMS TDI TD0 A5850-01 Figure 1. Embedded Ultra-Low Power Intel486TM SX Processor Block Diagram (c) INTEL CORPORATION, 1997 December 1997 Order Number: 272731-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Embedded Ultra-Low Power Intel486TM SX processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1997 *Third-party brands and names are the property of their respective owners. Contents Embedded Ultra-Low Power Intel486TM SX Processor 1.0 INTRODUCTION ........................................................................................................................................ 1 1.1 Features ............................................................................................................................................. 1 1.2 Family Members ................................................................................................................................. 2 2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3 3.0 PIN DESCRIPTIONS ................................................................................................................................. 3 3.1 Pin Assignments ................................................................................................................................. 3 3.2 Pin Quick Reference ........................................................................................................................... 7 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 15 4.1 Separate Supply Voltages ................................................................................................................ 15 4.2 Fast Clock Restart ............................................................................................................................ 17 4.3 Level-Keeper Circuits ....................................................................................................................... 18 4.4 Low-Power Features ........................................................................................................................ 19 4.4.1 Auto Clock Freeze ................................................................................................................. 19 4.5 CPUID Instruction ............................................................................................................................. 19 4.5.1 Operation of the CPUID Instruction ....................................................................................... 19 4.6 Identification After Reset .................................................................................................................. 20 4.7 Boundary Scan (JTAG) .................................................................................................................... 21 4.7.1 Device Identification ............................................................................................................... 21 4.7.2 Boundary Scan Register Bits and Bit Order ........................................................................... 21 5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 22 5.1 Maximum Ratings ............................................................................................................................. 22 5.2 DC Specifications ............................................................................................................................. 22 5.3 AC Specifications ............................................................................................................................. 25 5.4 Capacitive Derating Curves .............................................................................................................. 32 6.0 MECHANICAL DATA .............................................................................................................................. 33 6.1 Package Dimensions ........................................................................................................................ 33 6.2 Package Thermal Specifications ...................................................................................................... 34 FIGURES Figure 1. Embedded Ultra-Low Power Intel486TM SX Processor Block Diagram ...................................... i Figure 2. Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor .... 4 Figure 3. Example of Supply Voltage Power Sequence ......................................................................... 16 Figure 4. Stop Clock State Diagram with Typical Power Consumption Values ...................................... 17 Figure 5. CLK Waveform ........................................................................................................................ 28 Figure 6. Input Setup and Hold Timing ................................................................................................... 28 Figure 7. Input Setup and Hold Timing ................................................................................................... 29 Figure 8. Output Valid Delay Timing ....................................................................................................... 29 Figure 9. Maximum Float Delay Timing .................................................................................................. 30 iii Contents Figure 10. TCK Waveform ........................................................................................................................ 30 Figure 11. Test Signal Timing Diagram ..................................................................................................... 31 Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition ..................................................................................................... 32 Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition ..................................................................................................... 32 Figure 14. Package Mechanical Specifications for the 176 Lead TQFP Package .................................... 33 TABLES Table 1. The Embedded Ultra-Low Power Intel486TM SX Processor ....................................................... 2 Table 2. Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor ........ 5 Table 3. Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor ............................................................................................................ 6 Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions ...................................................... 7 Table 5. Output Pins .............................................................................................................................. 12 Table 6. Input/Output Pins ..................................................................................................................... 13 Table 7. Test Pins .................................................................................................................................. 13 Table 8. Input Pins ................................................................................................................................. 14 Table 9. CPUID Instruction Description ................................................................................................. 19 Table 10. Boundary Scan Component Identification Code ...................................................................... 21 Table 11. Absolute Maximum Ratings ..................................................................................................... 22 Table 12. Operating Supply Voltages ...................................................................................................... 22 Table 13. DC Specifications ..................................................................................................................... 23 Table 14. Active ICC Values ..................................................................................................................... 24 Table 15. Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values .......................................... 24 Table 16. AC Characteristics ................................................................................................................... 25 Table 17. AC Specifications for the Test Access Port ............................................................................. 27 Table 18. Thermal Resistance ................................................................................................................. 34 Table 19. Maximum Ambient Temperature (TA) ...................................................................................... 34 iv Embedded Ultra-Low Power Intel486TM SX Processor 1.0 INTRODUCTION This data sheet describes the embedded Ultra-Low Power (ULP) Intel486TM SX processor. It is intended for embedded battery-operated and hand-held applications. The embedded ULP Intel486 SX processor provides all of the features of the Intel486 SX processor except for the external data-bus parity logic and the processor-upgrade pin. The processor typically uses 20% to 50% less power than the Intel486 SX processor. Additionally, the embedded ULP Intel486 SX processor external data bus has level-keeper circuitry and a fast-recovery core clock which are vital for ultra-low-power system designs. The processor is available in a Thin Quad Flat Package (TQFP) enabling low-profile component implementation. The embedded ULP Intel486 SX processor consists of a 32-bit integer processing unit, an on-chip cache, and a memory management unit. The design ensures full instruction-set compatibility with the 8086, 8088, 80186, 80286, Intel386TM SX, Intel386 DX, and all versions of Intel486 processors. 1.1 Features * On-Chip Memory Management Unit -- Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both segmentation and paging are supported. * Burst Cycles -- Burst transfers allow a new double word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. * Write Buffers -- The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. * Bus Backoff -- When another bus master needs control of the bus during a processor initiated bus cycle, the embedded ULP Intel486 SX processor floats its bus signals, then restarts the cycle when the bus becomes available again. * Instruction Restart -- Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. The embedded ULP Intel486 SX processor offers these features of the Intel486 SX processor: * Dynamic Bus Sizing -- External controllers can dynamically alter the effective width of the data bus. Bus widths of 8, 16, or 32 bits can be used. * 32-bit RISC-Technology Core -- The embedded ULP Intel486 SX processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. * Boundary Scan (JTAG) -- Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture. * Single Cycle Execution -- Many instructions execute in a single clock cycle. * Intel System Management Mode (SMM) -- A unique Intel architecture operating mode provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software. * Instruction Pipelining -- Overlapped instruction fetching, decoding, address translation and execution. * On-Chip Cache with Cache Consistency Support -- An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. * External Cache Control -- Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency. * I/O Restart -- An I/O instruction interrupted by a System Management Interrupt (SMI#) can automatically be restarted following the execution of the RSM instruction. * Stop Clock -- The embedded ULP Intel486 SX processor has a stop clock control mechanism that provides two low-power states: a Stop Grant state (40-85 mW typical, depending on input clock frequency) and a Stop Clock state (~60 W typical, with input clock frequency of 0 MHz). 1 Embedded Ultra-Low Power Intel486TM SX Processor * Auto HALT Power Down -- After the execution of a HALT instruction, the embedded ULP Intel486 SX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state (40-85 mW typical, depending on input clock frequency). The embedded ULP Intel486 SX processor differs from the Intel486 SX processor in the following areas: * Processor Upgrade Removed -- The UP# signal is not provided. * Parity Signals Removed -- The DP3-DP0 and PCHK# signals are not provided. * Separate Processor-Core Power -- While the embedded ULP Intel486 SX processor requires a supply voltage of 3.3 V, the processor core has dedicated VCC pins and operates with a supply voltage as low as 2.4 V. * Small, Low-Profile Package -- The 176-Lead Thin Quad Flat Pack (TQFP) package is approximately 26 mm square and only 1.5 mm in height. This is approximately the diameter and thickness of a U.S. quarter. The embedded ULP Intel486 SX processor is ideal for embedded hand-held and battery-powered applications. * Level Keeper Circuits -- The embedded ULP Intel486 SX processor has level-keeper circuits for its 32-bit external data bus signals. They retain valid high and low logic voltage levels when the processor is in the Stop Grant and Stop Clock states. This is a power-saving improvement from the floating data bus of the Intel486 SX processor. * Auto Clock Freeze -- The embedded ULP Intel486 SX processor monitors bus events and internal activity. The Auto Clock Freeze feature automatically controls internal clock distribution, turning off clocks to internal units when they are idle. This power-saving function is transparent to the embedded system. * Fast Clock Restart -- The embedded ULP Intel486 SX processor requires only eight clock periods to synchronize its internal clock with the CLK input signal. This provides for faster transition from the Stop Clock State to the Normal State. For 33-MHz operation, this synchronization time is only 240 ns compared with 1 ms (PLL startup latency) for the Intel486 processor. 1.2 Family Members Table 1 shows the embedded ULP Intel486 SX processor and briefly describes its characteristics. Table 1. The Embedded Ultra-Low Power Intel486TM SX Processor Product Supply Voltage (VCCP) FA80486SXSF-33 2 3.3 V Processor Core Supply Voltage (VCC) Processor Frequency Package (MHz) 2.4 V to 3.3 V 25 2.7 V to 3.3 V 33 176-Lead TQFP Embedded Ultra-Low Power Intel486TM SX Processor 2.0 HOW TO USE THIS DOCUMENT The embedded ULP Intel486 SX processor has characteristics similar to the Intel486 SX processor. This document describes the new features of the embedded ULP Intel486 SX processor. Some Intel486 SX processor information is also included to minimize the dependence on the reference documents. For a complete set of documentation related to the embedded ULP Intel486 SX processor, use this document in conjunction with the following reference documents: * Embedded Intel486TM Processor Family Developer's Manual -- Order No. 273021 * Embedded Intel486TM Processor Hardware Reference Manual -- Order No. 273025 * Intel Application Note AP-485 -- Intel Processor Identification with the CPUID Instruction -- Order No. 241618 3.0 PIN DESCRIPTIONS 3.1 Pin Assignments The following figures and tables show the pin assignments for the 176-pin Thin Quad Flat Pack (TQFP) package of the embedded ULP Intel486 SX processor. Included are: * Figure 2, Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor (pg. 4) * Table 2, Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor (pg. 5) * Table 3, Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor (pg. 6) * Table 4, Embedded ULP Intel486TM SX Processor Pin Descriptions (pg. 7) * Table 5, Output Pins (pg. 13) * Table 6, Input/Output Pins (pg. 13) * Table 7, Test Pins (pg. 14) * Table 8, Input Pins (pg. 14) The tables and figures show "no-connects" as "N/C." These pins should always remain unconnected. Connecting N/C pins to VCC, VCCP, VSS, or any other signal pin can result in component malfunction or incompatibility with future steppings of the embedded ULP Intel486 SX processor. 3 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 ADS# A2 VSS VCCP VSS VSS VCCP A3 A4 A5 RESERVED# A6 A7 A8 VSS VCC A9 A10 VCCP VSS VCC A11 A12 VCC A13 A14 VCCP VSS A15 A16 A17 VSS VCCP TDI TMS A18 A19 A20 VCCP VCCP A21 A22 A23 A24 Embedded Ultra-Low Power Intel486TM SX Processor 176-Lead TQFP (top view) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VSS VSS VCCP A25 A26 A27 A28 VCCP A29 A30 A31 VSS D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCCP D5 D6 VCCP N/C D7 VSS D8 D9 VSS VCC D10 D11 D12 D13 VSS VCCP D14 D15 EADS# A20M# RESET VSS FLUSH# INTR NMI SRESET SMIACT# VCC VSS VCCP SMI# TDO VCC STPCLK# D31 D30 D29 D28 VCC VCCP VSS D27 D26 D25 D24 VCCP VSS D23 D22 D21 VCCP VSS D20 D19 D18 VCC D17 VSS VSS VCCP D16 VSS BLAST# VCC PLOCK# LOCK# VSS VCCP N/C BRDY# BOFF# BS16# BS8# VCC N/C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC VSS CLK HLDA W/R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC M/IO# D/C# PWT PCD VCCP VSS VCC Figure 2. Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor 4 Embedded Ultra-Low Power Intel486TM SX Processor Table 2. Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor Pin # Description Pin # Description Pin # Description Pin # Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 BLAST# VCC PLOCK# LOCK# VSS VCCP N/C BRDY# BOFF# BS16# BS8# VCC N/C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC VSS CLK HLDA W/R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC M/IO# D/C# PWT PCD VCCP VSS VCC 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 EADS# A20M# RESET VSS FLUSH# INTR NMI SRESET SMIACT# VCC VSS VCCP SMI# TDO VCC STPCLK# D31 D30 D29 D28 VCC VCCP VSS D27 D26 D25 D24 VCCP VSS D23 D22 D21 VCCP VSS D20 D19 D18 VCC D17 VSS VSS VCCP D16 VSS 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 D15 D14 VCCP VSS D13 D12 D11 D10 VCC VSS D9 D8 VSS D7 N/C VCCP D6 D5 VCCP VSS VCC VCC VSS VCC VCC VSS VCC D4 D3 D2 D1 D0 VSS A31 A30 A29 VCCP A28 A27 A26 A25 VCCP VSS VSS 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 A24 A23 A22 A21 VCCP VCCP A20 A19 A18 TMS TDI VCCP VSS A17 A16 A15 VSS VCCP A14 A13 VCC A12 A11 VCC VSS VCCP A10 A9 VCC VSS A8 A7 A6 RESERVED# A5 A4 A3 VCCP VSS VSS VCCP VSS A2 ADS# 5 Embedded Ultra-Low Power Intel486TM SX Processor Table 3. Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486TM SX Processor 6 Address Pin # Data Pin # Control Pin # N/C VCCP VCC VSS A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 175 169 168 167 165 164 163 160 159 155 154 152 151 148 147 146 141 140 139 136 135 134 133 129 128 127 126 124 123 122 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 120 119 118 117 116 106 105 102 100 99 96 95 94 93 90 89 87 83 81 80 79 76 75 74 71 70 69 68 64 63 62 61 AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK D/C# HLDA HOLD KEN# LOCK# M/IO# PCD PLOCK# PWT RESERVED# RDY# TCK W/R# A20M# EADS# FLUSH# INTR NMI RESET SMI# SMIACT# SRESET STPCLK# TDO ADS# TDI TMS W/R# 19 33 34 35 36 1 9 8 32 10 11 27 39 28 18 15 4 38 41 3 40 166 14 20 29 46 45 49 50 51 47 57 53 52 60 58 176 143 142 29 7 13 103 6 31 42 56 66 72 77 86 91 104 107 125 130 137 138 144 150 158 170 173 2 12 16 21 22 24 25 37 44 54 59 65 82 97 109 110 112 113 115 153 156 161 5 17 23 26 30 43 48 55 67 73 78 84 85 88 92 98 101 108 111 114 121 131 132 145 149 157 162 171 172 174 Embedded Ultra-Low Power Intel486TM SX Processor 3.2 Pin Quick Reference The following is a brief pin description. For detailed signal descriptions refer to Appendix A, "Signal Descriptions," in the Embedded Intel486TM Processor Family Developer's Manual, order No. 273021. Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 1 of 6) Symbol Type CLK I Name and Function Clock provides the fundamental timing and internal operating frequency for the embedded ULP Intel486 SX processor. All external timing parameters are specified with respect to the rising edge of CLK. ADDRESS BUS A31-A4 I/O A3-A2 O BE3# O BE2# O BE1# O BE0# O Address Lines A31-A2, together with the byte enable signals, BE3#-BE0#, define the physical area of memory or input/output space accessed. Address lines A31-A4 are used to drive addresses into the embedded ULP Intel486 SX processor to perform cache line invalidation. Input signals must meet setup and hold times t22 and t23. A31-A2 are not driven during bus or address hold. Byte Enable signals indicate active bytes during read and write cycles. During the first cycle of a cache fill, the external system should assume that all byte enables are active. BE3#-BE0# are active LOW and are not driven during bus hold. BE3# applies to D31-D24 BE2# applies to D23-D16 BE1# applies to D15-D8 BE0# applies to D7-D0 DATA BUS D31-D0 I/O Data Lines. D7-D0 define the least significant byte of the data bus; D31-D24 define the most significant byte of the data bus. These signals must meet setup and hold times t22 and t23 for proper operation on reads. These pins are driven during the second and subsequent clocks of write cycles. 7 Embedded Ultra-Low Power Intel486TM SX Processor Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 2 of 6) Symbol Type Name and Function BUS CYCLE DEFINITION M/IO# O D/C# O Memory/Input-Output, Data/Control and Write/Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. W/R# O M/IO# D/C# W/R# Bus Cycle Initiated 0 0 0 Interrupt Acknowledge 0 0 1 HALT/Special Cycle (see details below) 0 1 0 I/O Read 0 1 1 I/O Write 1 0 0 Code Read 1 0 1 Reserved 1 1 0 Memory Read 1 1 1 Memory Write HALT/Special Cycle Cycle Name BE3# - BE0# A4-A2 Shutdown 1110 000 HALT 1011 000 Stop Grant bus cycle 1011 100 LOCK# O Bus Lock indicates that the current bus cycle is locked. The embedded ULP Intel486 SX processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. PLOCK# O Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the embedded ULP Intel486 SX processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). The embedded ULP Intel486 SX processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold. BUS CONTROL ADS# 8 O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold. Embedded Ultra-Low Power Intel486TM SX Processor Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 3 of 6) Symbol Type RDY# I Name and Function Non-burst Ready input indicates that the current bus cycle is complete. RDY# indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the embedded ULP Intel486 SX processor in response to a write. RDY# is ignored when the bus is idle and at the end of the first clock of the bus cycle. RDY# is active during address hold. Data can be returned to the embedded ULP Intel486 SX processor while AHOLD is active. RDY# is active LOW and is not provided with an internal pull-up resistor. RDY# must satisfy setup and hold times t16 and t17 for proper chip operation. BURST CONTROL BRDY# I Burst Ready input performs the same function during a burst cycle that RDY# performs during a non-burst cycle. BRDY# indicates that the external system has presented valid data in response to a read or that the external system has accepted data in response to a write. BRDY# is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data presented on the data bus is strobed into the embedded ULP Intel486 SX processor when BRDY# is sampled active. If RDY# is returned simultaneously with BRDY#, BRDY# is ignored and the burst cycle is prematurely aborted. BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must satisfy the setup and hold times t16 and t17. O Burst Last signal indicates that the next time BRDY# is returned, the burst bus cycle is complete. BLAST# is active for both burst and non-burst bus cycles. BLAST# is active LOW and is not driven during bus hold. RESET I Reset input forces the embedded ULP Intel486 SX processor to begin execution at a known state. The processor cannot begin executing instructions until at least 1 ms after VCC, VCCP, and CLK have reached their proper DC and AC specifications. The RESET pin must remain active during this time to ensure proper processor operation. However, for warm resets, RESET should remain active for at least 15 CLK periods. RESET is active HIGH. RESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock. INTR I Maskable Interrupt indicates that an external interrupt has been generated. When the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated. The embedded ULP Intel486 SX processor generates two locked interrupt acknowledge bus cycles in response to the INTR pin going active. INTR must remain active until the interrupt acknowledges have been performed to ensure processor recognition of the interrupt. BLAST# INTERRUPTS INTR is active HIGH and is not provided with an internal pull-down resistor. INTR is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock. NMI I Non-Maskable Interrupt request signal indicates that an external non-maskable interrupt has been generated. NMI is rising-edge sensitive and must be held LOW for at least four CLK periods before this rising edge. NMI is not provided with an internal pull-down resistor. NMI is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock. 9 Embedded Ultra-Low Power Intel486TM SX Processor Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 4 of 6) Symbol Type Name and Function SRESET I Soft Reset pin duplicates all functionality of the RESET pin except that the SMBASE register retains its previous value. For soft resets, SRESET must remain active for at least 15 CLK periods. SRESET is active HIGH. SRESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock. SMI# I System Management Interrupt input invokes System Management Mode (SMM). SMI# is a falling-edge triggered signal which forces the embedded ULP Intel486 SX processor into SMM at the completion of the current instruction. SMI# is recognized on an instruction boundary and at each iteration for repeat string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a currently executing SMM. The embedded ULP Intel486 SX processor latches the falling edge of one pending SMI# signal while it is executing an existing SMI#. The nested SMI# is not recognized until after the execution of a Resume (RSM) instruction. SMIACT# O System Management Interrupt Active, an active LOW output, indicates that the embedded ULP Intel486 SX processor is operating in SMM. It is asserted when the processor begins to execute the SMI# state save sequence and remains active LOW until the processor executes the last state restore cycle out of SMRAM. STPCLK# I Stop Clock Request input signal indicates a request was made to turn off or change the CLK input frequency. When the embedded ULP Intel486 SX processor recognizes a STPCLK#, it stops execution on the next instruction boundary (unless superseded by a higher priority interrupt), empties all internal pipelines and write buffers, and generates a Stop Grant bus cycle. STPCLK# is active LOW. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used. STPCLK# is an asynchronous signal, but must remain active until the embedded ULP Intel486 SX processor issues the Stop Grant bus cycle. STPCLK# may be de-asserted at any time after the processor has issued the Stop Grant bus cycle. BUS ARBITRATION 10 BREQ O Bus Request signal indicates that the embedded ULP Intel486 SX processor has internally generated a bus request. BREQ is generated whether or not the processor is driving the bus. BREQ is active HIGH and is never floated. HOLD I Bus Hold Request allows another bus master complete control of the embedded ULP Intel486 SX processor bus. In response to HOLD going active, the processor floats most of its output and input/output pins. HLDA is asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The embedded ULP Intel486 SX processor remains in this state until HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation. HLDA O Hold Acknowledge goes active in response to a hold request presented on the HOLD pin. HLDA indicates that the embedded ULP Intel486 SX processor has given the bus to another local bus master. HLDA is driven active in the same clock that the processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold. Embedded Ultra-Low Power Intel486TM SX Processor Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 5 of 6) Symbol Type Name and Function BOFF# I Backoff input forces the embedded ULP Intel486 SX processor to float its bus in the next clock. The processor floats all pins normally floated during bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher priority than RDY# or BRDY#; if both are returned in the same clock, BOFF# takes effect. The embedded ULP Intel486 SX processor remains in bus hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted the cycle is restarted. BOFF# is active LOW and must meet setup and hold times t18 and t19 for proper operation. CACHE INVALIDATION AHOLD I Address Hold request allows another bus master access to the embedded ULP Intel486 SX processor's address bus for a cache invalidation cycle. The processor stops driving its address bus in the clock following AHOLD going active. Only the address bus is floated during address hold, the remainder of the bus remains active. AHOLD is active HIGH and is provided with a small internal pull-down resistor. For proper operation, AHOLD must meet setup and hold times t18 and t19. EADS# I External Address - This signal indicates that a valid external address has been driven onto the embedded ULP Intel486 SX processor address pins. This address is used to perform an internal cache invalidation cycle. EADS# is active LOW and is provided with an internal pull-up resistor. EADS# must satisfy setup and hold times t12 and t13 for proper operation. CACHE CONTROL KEN# I Cache Enable pin is used to determine whether the current cycle is cacheable. When the embedded ULP Intel486 SX processor generates a cycle that can be cached and KEN# is active one clock before RDY# or BRDY# during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one clock before RDY# during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN# is active LOW and is provided with a small internal pull-up resistor. KEN# must satisfy setup and hold times t14 and t15 for proper operation. FLUSH# I Cache Flush input forces the embedded ULP Intel486 SX processor to flush its entire internal cache. FLUSH# is active LOW and need only be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for recognition in any specific clock. PAGE CACHEABILITY PWT PCD O O Page Write-Through and Page Cache Disable pins reflect the state of the page attribute bits, PWT and PCD, in the page table entry, page directory entry or control register 3 (CR3) when paging is enabled. When paging is disabled, the embedded ULP Intel486 SX processor ignores the PCD and PWT bits and assumes they are zero for the purpose of caching and driving PCD and PWT pins. PWT and PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and W/R#). PWT and PCD are active HIGH and are not driven during bus hold. PCD is masked by the cache disable bit (CD) in Control Register 0. 11 Embedded Ultra-Low Power Intel486TM SX Processor Table 4. Embedded ULP Intel486TM SX Processor Pin Descriptions (Sheet 6 of 6) Symbol Type Name and Function BUS SIZE CONTROL BS16# BS8# I I Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the embedded ULP Intel486 SX processor to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are sampled every clock. The processor uses the state of these pins in the clock before Ready to determine bus size. These signals are active LOW and are provided with internal pull-up resistors. These inputs must satisfy setup and hold times t14 and t15 for proper operation. I Address Bit 20 Mask pin, when asserted, causes the embedded ULP Intel486 SX processor to mask physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M# emulates the address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is active LOW and should be asserted only when the embedded ULP Intel486 SX processor is in real mode. This pin is asynchronous but should meet setup and hold times t20 and t21 for recognition in any specific clock. For proper operation, A20M# should be sampled HIGH at the falling edge of RESET. ADDRESS MASK A20M# TEST ACCESS PORT TCK I Test Clock, an input to the embedded ULP Intel486 SX processor, provides the clocking function required by the JTAG Boundary scan feature. TCK is used to clock state information (via TMS) and data (via TDI) into the component on the rising edge of TCK. Data is clocked out of the component (via TDO) on the falling edge of TCK. TCK is provided with an internal pull-up resistor. TDI I Test Data Input is the serial input used to shift JTAG instructions and data into the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR TAP controller states. During all other Test Access Port (TAP) controller states, TDI is a "don't care." TDI is provided with an internal pull-up resistor. TDO O Test Data Output is the serial output used to shift JTAG instructions and data out of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR TAP controller states. At all other times TDO is driven to the high impedance state. TMS I Test Mode Select is decoded by the JTAG TAP to select test logic operation. TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller, TMS is provided with an internal pull-up resistor. I Reserved is reserved for future use. This pin MUST be connected to an external pull-up resistor circuit. The recommended resistor value is 10 kOhms. RESERVED PINS RESERVED# 12 Embedded Ultra-Low Power Intel486TM SX Processor Table 5. Output Pins Output Signal Name Active Level BREQ HIGH Previous State HLDA HIGH As per HOLD Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States1 BE3#-BE0# LOW * Previous State PWT, PCD HIGH * Previous State W/R#, M/IO#, D/C# HIGH/LOW * Previous State LOCK# LOW * HIGH (inactive) PLOCK# LOW * HIGH (inactive) ADS# LOW * HIGH (inactive) BLAST# LOW A3-A2 HIGH SMIACT# LOW * * Previous State * Previous State Previous State NOTES: 1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating. Table 6. Input/Output Pins Output Signal Name Active Level D31-D0 HIGH A31-A4 HIGH Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States1,2 * Level-Keeper * * Previous State NOTES: 1. The term "Level-Keeper" means that the processor maintains the most recent logic level applied to the signal pin. This conserves power by preventing the signal pin from floating. If a system component, other than the processor, temporarily drives these signal pins and then floats them, the processor forces and maintains the most recent logic levels that were applied by the system component. 2. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating. 13 Embedded Ultra-Low Power Intel486TM SX Processor Table 7. Test Pins Name Input or Output Sampled/ Driven On TCK Input N/A TDI Input Rising Edge of TCK TDO Output Failing Edge of TCK TMS Input Rising Edge of TCK Table 8. Input Pins Name Active Level Synchronous/ Asynchronous Internal Pull-Up/ Pull-Down CLK RESET HIGH Asynchronous SRESET HIGH Asynchronous Pull-Down HOLD HIGH Synchronous AHOLD HIGH Synchronous Pull-Down EADS# LOW Synchronous Pull-Up BOFF# LOW Synchronous Pull-Up FLUSH# LOW Asynchronous Pull-Up A20M# LOW Asynchronous Pull-Up BS16#, BS8# LOW Synchronous Pull-Up KEN# LOW Synchronous Pull-Up RDY# LOW Synchronous BRDY# LOW Synchronous INTR HIGH Asynchronous NMI HIGH Asynchronous SMI# LOW Asynchronous Pull-Up STPCLK# LOW Asynchronous Pull-Up1 TCK HIGH Pull-Up TDI HIGH Pull-Up TMS HIGH Pull-Up Pull-Up RESERVED# NOTE: 1. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used. 14 Embedded Ultra-Low Power Intel486TM SX Processor 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW The embedded ULP Intel486 SX processor architecture is essentially the same as the 3.3 V Intel486 SX processor with a 1X clock (CLK) input. Refer to the Embedded Intel486TM Processor Family Developer's Manual, order number 273032, for a description of the ULP Intel486 SX processor. The following notes supplement the information in the manual. * The information pertaining to parity signals for the external data bus does not apply. The embedded ULP Intel486 SX processor does not have DP0#, DP1#, DP2#, DP3# and PCHK# signal pins. * References to the Upgrade Power Down Mode do not apply. The embedded ULP Intel486 SX processor does not have the UP# signal pin and does not support the Intel OverDrive(R) processor. * References to "VCC" are called "VCCP" by the embedded ULP Intel486 SX processor when the supply voltage pertains to the processor's external interface drivers and receivers. The term "VCC" pertains only to the processor core supply voltage of the embedded ULP Intel486 SX processor. Information about the split-supply voltage is provided in this datasheet. * The Phase-Locked Loop (PLL) of the 1X clock (CLK) input has been replaced by a proprietary Differential Delay Line (DDL) that has a faster startup and recovery time. Datasheet references to the PLL and its 1 ms recovery time are replaced with the DDL circuit and its eight-CLK recovery time. Information about the DDL and startup and recovery latency is provided in this datasheet. * The embedded ULP Intel486 SX processor has level-keeper circuits for its external 32-bit data bus signals (D31-D0). The Intel486 SX processor floats its data bus instead. More information about the level-keeper circuitry is provided in this datasheet. * The datasheet describes the processor supplycurrent consumption for the Auto HALT Power Down, Stop Grant, and Stop Clock states. This supply-current consumption for the embedded ULP Intel486 SX processor is much less than that of the Intel486 SX processor. Information about power consumption and these states is provided in this datasheet. * The CPU ID, Boundary-Scan (JTAG) ID, and boundary-scan register bits for the embedded ULP Intel486 SX processor are in this datasheet. * The embedded ULP Intel486 SX processor has one pin reserved for possible future use. This pin is an input signal, pin 166. It is called RESERVED# and must be connected to a 10-K pull-up resistor. 4.1 Separate Supply Voltages The embedded ULP Intel486 SX processor has separate voltage-supply planes for its internal coreprocessor circuits and its external driver/receiver circuits. The supply voltage for the internal core processor is named VCC and the supply voltage for the external circuits is named VCCP. For a single-supply voltage design, the embedded ULP Intel486 SX processor is functional at 3.3 V 0.3 V. In this type of system design, the processor's VCC and VCCP pins must be tied to the same power plane. Even though VCCP must be 3.3 V 0.3 V, the processor's external-output circuits can drive TTLcompatible components. However, the processor's external-input circuits do not allow connection to TTL-compatible components. Section 5.2, DC Specifications (pg. 22) contains the DC specifications for the processor's input and output signals. For lower-power operation, a separate, lower voltage for VCC can be chosen, but VCCP must be 3.3 V 0.3 V. Any voltage value between 2.4 V and 3.3 V can be chosen for VCC for guaranteed processor operation up to 25 MHz. The embedded ULP Intel486 SX processor can also operate at 33 MHz, provided the VCC value chosen is between 2.7 V and 3.3 V. Section 5.2, DC Specifications (pg. 22) defines supply voltage specifications. In systems with separate VCC and VCCP power planes, the processor-core voltage supply must always be less than or equal to the processor's external-interface voltage supply; e.g., the system design must guarantee: VCC VCCP Violating this relationship causes excessive power consumption. Limited testing has shown no component damage when this relationship is violated. However, prolonged violation is not recommended and component integrity is not guaranteed. 15 Embedded Ultra-Low Power Intel486TM SX Processor The VCC VCCP relationship must also be guaranteed by the system design during power-up and power-down sequences. Refer to Figure 3. Even though VCC must be less than or equal to VCCP, it is recommended that the system's power-on sequence allows VCC to quickly achieve its operational level once VCCP achieves its operational level. Similarly, the power-down sequence should allow VCCP to power down quickly after VCC is below the operational voltage level. These recommendations are given to keep power consumption at a minimum. Deviating from the recommendations does not create a component reliability problem, but power consumption of the processor's external interface circuits increases beyond normal operating values. VCC and VCCP (V) VCCP VCCP min VCC VCC min 0V TIME POWER ON POWER OFF Figure 3. Example of Supply Voltage Power Sequence 16 Embedded Ultra-Low Power Intel486TM SX Processor 4.2 Fast Clock Restart The embedded ULP Intel486 SX processor has an integrated proprietary differential delay line (DDL) circuit for internal clock generation. The DDL is driven by the CLK input signal provided by the external system. During normal operation, the external system must guarantee that the CLK signal maintains its frequency so that the clock period deviates no more than 250 ps/CLK. This state, called the Normal State, is shown in Figure 4. To increase or decrease the CLK frequency more quickly than this, the system must interrupt the processor with the STPCLK# signal. Once the processor indicates that it is in the Stop Grant State, the system can adjust the CLK signal to the new frequency, wait a minimum of eight CLK periods, then force the processor to return to the normal operational state by deactivating the STPCLK# interrupt. This wait of eight CLK periods is much faster than the 1 ms wait required by earlier Intel486 SX processor products. While in the Stop Grant State, the external system may deactivate the CLK signal to the processor. This forces the processor to the Stop Clock State -- the state in which the processor consumes the least power. Once the system reactivates the CLK signal, the processor transitions to the Stop Grant State within eight CLK periods. Normal operation can be resumed by deactivating the STPCLK# interrupt signal. Here again, the embedded ULP Intel486 SX processor recovers from the Stop Clock State much faster than the 1 ms PLL recovery of earlier Intel486 SX processors. HALT asserted and HALT bus cycle generated 4 Auto HALT Power Down State 1 Normal State Normal Execution CLK Running 40 - 85 mWatts INTR, NMI, SMI# RESET, SRESET STPCLK# asserted and Stop Grant bus cycle generated EADS# STPCLK# deasserted and HALT bus cycle generated STPCLK# deasserted STPCLK# asserted and Stop Grant bus cycle generated EADS# 5 Stop Clock Snoop State One Clock PowerUp Perform Cache Invalidation 2 Stop Grant State CLK Running 40 - 85 mWatts Stop CLK Start CLK plus DDL Startup Latency 3 Stop Clock State Internal Powerdown CLK Stopped ~ 60 Watts Figure 4. Stop Clock State Diagram with Typical Power Consumption Values 17 Embedded Ultra-Low Power Intel486TM SX Processor 4.3 Level-Keeper Circuits To obtain the lowest possible power consumption during the Stop Grant and Stop Clock states, system designers must ensure that: * input signals with pull-up resistors are not driven LOW * input signals with pull-down resistors are not driven HIGH See Table 8, Input Pins (pg. 14) for the list of signals with internal pull-up and pull-down resistors. All other input pins except A31-A4 and D31-D0 must be driven to the power supply rails to ensure lowest possible current consumption. During the Stop Grant and Stop Clock states, most processor output signals maintain their previous condition, which is the level they held when entering the Stop Grant state. In response to HOLD driven active during the Stop Grant state when the CLK input is running, the embedded ULP Intel486 SX processor generates HLDA and floats all output and input/output signals which are floated during the HOLD/HLDA state. When HOLD is deasserted, processor signals which maintain their previous state return to the state they were in prior to the HOLD/HLDA sequence. The data bus (D31-D0) also maintains its previous state during the Stop Grant and Stop Clock states, but does so differently, as described in the following paragraphs. The embedded ULP Intel486 SX processor's data bus pins (D31-D0) have level keepers which maintain their previous states while in the Stop Grant and Stop Clock states. In response to HOLD driven active during the Stop Grant state when the CLK input is running, the embedded ULP Intel486 SX processor generates HLDA and floats D31-D0 throughout the HOLD/HLDA cycles. When HOLD is deasserted, the processor's D31-D0 signals return to the states they were in prior to the HOLD/HLDA sequence. 18 At all other times during the Stop Grant and Stop Clock states, the processor maintains the logic levels of D31-D0. When the external system circuitry drives D31-D0 to different logic levels, the processor flips its D31-D0 logic levels to match the ones driven by the external system. The processor maintains (keeps) these new levels even after the external circuitry stops driving D31-D0. For some system designs, external resistors may not be required on D31- D0 (they are required on previous Intel486 SX processor designs). System designs that never request Bus Hold during the Stop Grant and Stop Clock states might not require external resistors. If the system design uses Bus Hold during these states, the processor disables the level-keepers and floats the data bus. This type of design would require some kind of data bus termination to minimize power consumption. It is strongly recommended that the D31-D0 pins do not have network resistors connected. External resistors used in the system design must be of a sufficient resistance value to "flip" the level-keeper circuitry and eliminate potential DC paths. The level-keeper circuit is designed to allow an external 27-K pull-up resistor to switch the D31-D0 circuits to a logic-HIGH level even though the levelkeeper attempts to keep a logic-LOW level. In general, pull-up resistors smaller than 27 K can be used as well as those greater than or equal to 1 M. Pull-down resistors, when connected to D31-D0, should be least 800 K. Embedded Ultra-Low Power Intel486TM SX Processor 4.4 Low-Power Features As with other Intel486 processors, the embedded ULP Intel486 SX processor minimizes power consumption by providing the Auto HALT Power Down, Stop Grant, and Stop Clock states (see Figure 4). The embedded ULP Intel486 SX processor has an Auto Clock Freeze feature that further conserves power by judiciously deactivating its internal clocks while in the Normal Execution Mode. The power-conserving mechanism is designed such that it does not degrade processor performance or require changes to AC timing specifications. 4.4.1 Auto Clock Freeze To reduce power consumption, during the following bus cycles -- under certain conditions -- the processor slows-up or freezes some internal clocks: * Data-Read Wait Cycles (Memory, I/O and Interrupt Acknowledge) * Data-Write Wait Cycles (Memory, I/O) * HOLD/HLDA Cycles * AHOLD Cycles * BOFF Cycles Power is conserved during the wait periods in these cycles until the appropriate external-system signals are sent to the processor. These signals include: The embedded ULP Intel486 SX processor also reduces power consumption by temporarily freezing the clocks of its internal logic blocks. When a logic block is idle or in a wait state, its clock is frozen. 4.5 CPUID Instruction The embedded ULP Intel486 SX processor supports the CPUID instruction (see Table 9). Because not all Intel processors support the CPUID instruction, a simple test can determine if the instruction is supported. The test involves the processor's ID Flag, which is bit 21 of the EFLAGS register. If software can change the value of this flag, the CPUID instruction is available. The actual state of the ID Flag bit is irrelevant and provides no significance to the hardware. This bit is cleared (reset to zero) upon device reset (RESET or SRESET) for compatibility with Intel486 processor designs that do not support the CPUID instruction. CPUID-instruction details are provided here for the embedded ULP Intel486 SX processor. Refer to Intel Application Note AP-485 Intel Processor Identification with the CPUID Instruction (Order No. 241618) for a description that covers all aspects of the CPUID instruction and how it pertains to other Intel processors. 4.5.1 Operation of the CPUID Instruction The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX. * READY * NMI, SMI#, INTR, and RESET * BOFF# * FLUSH# * EADS# * BS8#, BS16# and KEN# transitions Table 9. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks Parameter passed in EAX Description (Input Value) 9 0 Vendor (Intel) ID String 14 1 Processor Identification 9 >1 Undefined (Do Not Use) 19 Embedded Ultra-Low Power Intel486TM SX Processor Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon instruction execution are shown in the following table. 31-------------24 23-----------16 15--------------8 7--------------0 High Value (= 1) EAX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Vendor ID String EBX u (75) n (6E) e (65) G (47) (ASCII EDX I (49) e (65) n (6E) i (69) Characters) ECX l (6C) e (65) t (74) n (6E) The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are: Processor Signature EAX 31---------------------------14 13,12 11----8 7----4 3----0 (Do Not Use) 00 0100 0010 XXXX Intel Reserved Processor Type Family Model Stepping (Intel releases information about stepping numbers as needed) 31--------------------------------------------------------------------------------------------------0 Intel Reserved EBX Intel Reserved (Do Not Use) ECX Intel Reserved Feature Flags EDX 4.6 31----------------------------------------------------------------------------2 1 0------------------------------------------------------------------------------0 1 0 0 VME FPU Identification After Reset Processor Identification - Upon reset, the EDX register contains the processor signature: 31---------------------------14 Processor Signature EDX 13,12 11----8 7----4 3----0 (Do Not Use) 00 0100 0010 XXXX Intel Reserved Processor Type Family Model Stepping (Intel releases information about stepping numbers as needed) 20 Embedded Ultra-Low Power Intel486TM SX Processor 4.7 Boundary Scan (JTAG) 4.7.1 Device Identification Table 10 shows the 32-bit code for the embedded ULP Intel486 SX processor which is loaded into the Device Identification Register. Table 10. Boundary Scan Component Identification Code Version Part Number Mfg ID 1 009H = Intel 0=5V 1=3.3 V Intel Architecture Type Family 0100 = Intel486 CPU Family Model 00010 = embedded ULP Intel486 SX processor 31----28 27 26-----------21 20----17 16--------12 11------------1 0 XXXX 1 000001 0100 00010 00000001001 1 VCC (Intel releases information about version numbers as needed) Boundary Scan Component Identification Code = x828 2013 (Hex) 4.7.2 Boundary Scan Register Bits and Bit Order The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N/C) signals of the embedded ULP Intel486 SX processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. * WRCTL controls D31-D0 * ABUSCTL controls A31-A2 * BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, and PCD * MISCCTL controls HLDA, and BREQ The following is the bit order of the embedded ULP Intel486 SX processor boundary scan register: TDO A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, Reserved, D0, D1, D2, D3, D4, D5, D6, D7, Reserved, D8, D9, D10, D11, D12, D13, D14, D15, Reserved, D16, D17, D18, D19, D20, D21, D22, D23, Reserved, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, Reserved, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL TDI 21 Embedded Ultra-Low Power Intel486TM SX Processor 5.0 5.1 ELECTRICAL SPECIFICATIONS Maximum Ratings Table 11 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the embedded ULP Intel486 SX processor contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications. Table 11. Absolute Maximum Ratings Case Temperature under Bias -65 C to +110 C Storage Temperature -65 C to +150 C DC Voltage on Any Pin with Respect to Ground -0.5 V to VCCP + 0.5 V Supply Voltage VCC with Respect to VSS -0.5 V to +4.6 V Supply Voltage VCCP with Respect to VSS -0.5 V to +4.6 V 5.2 DC Specifications The following tables show the operating supply voltages, DC I/O specifications, and component power consumption for the embedded ULP Intel486 SX processor. Table 12. Operating Supply Voltages Product VCCP Range1 Max. CLK Frequency 25 FA80486SXSF-33 3.3 V 0.3 V VCC Range2 2.4 V min 3.3 V max 33 VCC Fluctuation 2.7 V min at 2.4 V 0.2 V +0.3 V/-0.2 V at 2.7 V 0.3 V at 3.0 V VCC 2.7 V < VCC < 3.0 V VCC 3.3 V 3.3 V max NOTES: 1. In all cases, VCCP must be VCC. 2. VCC may be set to any voltage within the VCC Range. The setting determines the allowed VCC Fluctuation. 22 Embedded Ultra-Low Power Intel486TM SX Processor Table 13. DC Specifications TCASE=0 C to +85 C Symbol Parameter Min. Max. Unit VIL Input LOW Voltage -0.3 +0.8 V VIH Input HIGH Voltage 2.0 VCCP +0.3 V VIHC Input HIGH Voltage of CLK V CCP -0.6 VCCP +0.3 V VOL Output LOW Voltage IOL = 2.0 mA 0.4 V IOL = 100 A 0.2 V VOH Notes Note 1 Output HIGH Voltage IOH = -2.0 mA IOH = -100 A V 2.4 VCCP -0.2 V ILI Input Leakage Current 15 A Note 2 IIH Input Leakage Current 200 A Note 3 IIL Input Leakage Current 400 A Note 4 ILO Output Leakage Current 15 A CIN Input Capacitance 10 pF COUT I/O or Output Capacitance 10 pF Note 5 CCLK CLK Capacitance 6 pF Note 5 Note 5 NOTES: 1. All inputs except CLK. 2. This parameter is for inputs without pull-up or pull-down resistors and 0V VIN VCCP. 3. This parameter is for inputs with pull-down resistors and VIH = 2.4V, and for level-keeper pins at V=0.4V. 4. This parameter is for inputs with pull-up resistors and VIL = 0.4V, and for level-keeper pins at V=2.4V. 5. FC=1 MHz. Not 100% tested. 23 Embedded Ultra-Low Power Intel486TM SX Processor Table 14. Active ICC Values TCASE=0 C to +85 C Symbol ICC1 Parameter Frequency Supply Voltage Typical ICC Max. ICC ICC Active 25 MHz VCC = 2.4 0.2 V 120 mA 195 mA VCC = 3.3 0.3 V 165 mA 260 mA 33 MHz VCC = 2.7 0.2 V 180 mA 280 mA VCC = 3.3 0.3 V 220 mA 345 mA ICC Active 25 MHz VCCP = 3.3 0.3 V 9 mA 30 mA 1 (VCCP pins) 33 MHz VCCP = 3.3 0.3 V 12 mA 40 mA 1 (VCC pins) ICC2 Notes NOTES: 1. These parameters are for CL = 50 pF Table 15. Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values TCASE= 0 C to +85 C Symbol Parameter Frequency Supply Voltage Typical ICC Max. ICC Notes ICCS0 ICC Stop Clock 0 MHz VCC = 2.4 0.2 V 4 A 120 A Note 1 VCC = 2.7 0.2 V 4 A 130 A VCC = 3.3 0.3 V 5 A 150 A 0 MHz VCCP = 3.3 0.3 V 3 A 80 A 25 MHz VCC = 2.4 0.2 V 14 mA 25 mA VCC = 3.3 0.3 V 20 mA 30 mA 33 MHz VCC = 2.7 0.2 V 20 mA 30 mA VCC = 3.3 0.3 V 25 mA 35 mA 25 MHz VCCP = 3.3 0.3 V 425 A 1.5 mA 33 MHz VCCP = 3.3 0.3 V 610 A 2.0 mA (VCC pins) ICCS2 ICC Stop Clock (VCCP pins) ICCS1 ICC Stop Grant, Auto HALT Power Down (VCC pins) ICCS3 ICC Stop Grant, Auto HALT Power Down (VCCP pins) NOTES: 1. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. For all input signals, the VIH and VIL levels must be equal to VCCP and 0V, respectively, to meet the ICC Stop Clock specifications. 24 Embedded Ultra-Low Power Intel486TM SX Processor 5.3 AC Specifications The AC specifications for the embedded ULP Intel486 SX processor are given in this section. Table 16. AC Characteristics (Sheet 1 of 2) valid over the operating supply voltages listed in Table 12, Operating Supply Voltages (pg. 22). TCASE= 0 C to +85 C; CL= 50 pF Symbol Parameter 2.4V VCC < 2.7V 2.7V VCC 3.3V Min Max Min Max Unit Notes Frequency 0 25 0 33 MHz Note 1 40 ns Note 1 250 ps/CLK Note 2 t1 CLK Period t1a CLK Period Stability 30 t2 CLK High Time 14 11 ns at 2V t3 CLK Low Time 14 11 ns at 0.8V t4 CLK Fall Time 4 3 ns 2V to 0.8V Note 3 t5 CLK Rise Time 4 3 ns 0.8V to 2V Note 3 t6 A2-A31, PWT, PCD, BE0#BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# Valid Delay 16 ns t7 A2-A31, PWT, PCD, BE0#BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, Float Delay 20 ns t8a BLAST#, PLOCK# Valid Delay t9 BLAST#, PLOCK# Float Delay t10 D0-D31 Write Delay t11 D0-D31 Float Delay t12 EADS# Setup Time 8 6 ns t13 EADS# Hold Time 3 3 ns t14 BS16#, BS8#, KEN# Setup Time 8 6 ns t15 BS16#, BS8#, KEN# Hold Time 3 3 ns t16 RDY#, BRDY# Setup Time 8 6 ns t17 RDY#, BRDY# Hold Time 3 3 ns t18 HOLD, AHOLD Setup Time 10 6 ns t18a BOFF# Setup Time 10 9 ns 250 3 19 3 28 3 24 3 28 3 20 3 28 20 ns 20 ns 19 ns 20 ns Note 3 Note 3 Note 3 25 Embedded Ultra-Low Power Intel486TM SX Processor Table 16. AC Characteristics (Sheet 2 of 2) valid over the operating supply voltages listed in Table 12, Operating Supply Voltages (pg. 22). TCASE= 0 C to +85 C; CL= 50 pF Symbol Parameter 2.4V VCC < 2.7V Min Max 2.7V VCC 3.3V Min Max Unit t19 HOLD, AHOLD, BOFF# Hold Time 3 3 ns t20 FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Setup Time 10 6 ns t21 FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Hold Time 3 3 ns t22 D0-D31, A4-A31 Read Setup Time 6 6 ns t23 D0-D31, A4-A31 Read Hold Time 3 3 ns Notes NOTES: 1. 0 Hz operation is tested and guaranteed by the STPCLK# and Stop Grant bus cycle protocol. 0 Hz < CLK < 8 MHz operation is confirmed by design characterization, but not 100% tested in production. 2. Specification t1a is applicable only when CLK frequency is changed without STPCLK# / STOP GRANT bus cycle protocol. 3. Not 100% tested, guaranteed by design characterization. 4. CLK reference voltage for timing measurement is 1.5 V except t2 through t5. Other signals are measured at 1.5 V. 26 Embedded Ultra-Low Power Intel486TM SX Processor . Table 17. AC Specifications for the Test Access Port Symbol Parameter 2.2 V Vcc < 3.0 V Vcc = 3.3 0.3 V Min Max Min 5 Max 8 Unit Figure MHz 10 Notes t24 TCK Frequency t25 TCK Period 200 125 ns 10 Note 1 t26 TCK High Time 65 40 ns 10 @ 2.0V t27 TCK Low Time 65 ns 10 @0.8V t28 TCK Rise Time ns 10 Note 2 t29 TCK Fall Time t30 TDI, TMS Setup Time 16 t31 TDI, TMS Hold Time 20 t32 TDO Valid Delay 3 t33 TDO Float Delay t34 All Outputs (except TDO) Valid Delay t35 All Outputs (except TDO) Float Delay t36 All Inputs (except TDI, TMS, TCK) Setup Time 16 t37 All Inputs (except TDI, TMS, TCK) Hold Time 35 40 15 8 15 8 8 10 46 80 10 Note 2 11 Note 3 ns 11 Note 3 30 ns 11 Note 3 36 ns 11 Notes 3, 4 30 ns 11 Note 3 36 ns 11 Notes 3, 4 8 ns 11 Note 3 15 ns 11 Note 3 3 52 3 ns ns 3 88 NOTES: 1. TCK period CLK period. 2. Rise/Fall Times are measured between 0.8 V and 2.0 V. Rise/Fall times can be relaxed by 1 ns per 10 ns increase in TCK period. 3. Parameter measured from TCK. 4. Not 100% tested, guaranteed by design characterization. 27 Embedded Ultra-Low Power Intel486TM SX Processor 2.0 V CLK 2.0 V 1.5 V 1.5 V 0.8 V 0.8 V t2 t3 t4 t5 t1 tx ty 1.5 V tx = input setup times ty = input hold times, output float, valid and hold times Figure 5. CLK Waveform Tx Tx Tx Tx CLK t12 t13 t14 t15 t18 t19 t20 t21 t22 t23 EADS# BS8#, BS16#, KEN# BOFF#, AHOLD, HOLD RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A4-A31 (READ) Figure 6. Input Setup and Hold Timing 28 Embedded Ultra-Low Power Intel486TM SX Processor Tx T2 Tx CLK t16 t17 RDY#, BRDY# 1.5 V t23 t22 D0-D31 1.5 V Figure 7. Input Setup and Hold Timing Tx Tx Tx Tx CLK MIN A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# MAX t6 VALID n VALID n+1 MIN MAX t10 D0-D31 VALID n VALID n+1 MIN t8a BLAST#, PLOCK# VALID n MAX VALID n+1 Figure 8. Output Valid Delay Timing 29 Embedded Ultra-Low Power Intel486TM SX Processor Tx Tx Tx CLK t6 A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ MIN t7 VALID t10 D31-D0 MIN t11 VALID t8a BLAST#, PLOCK# MIN t9 VALID Figure 9. Maximum Float Delay Timing 2.0 V 2.0 V t27 TCK 0.8 V 0.8 V t28 t26 t29 t25 Figure 10. TCK Waveform 30 Embedded Ultra-Low Power Intel486TM SX Processor 1.5 V TCK t31 t30 TMS TDI VALID t33 t32 VALID TDO t35 t34 VALID OUTPUT t36 INPUT VALID t37 VALID Figure 11. Test Signal Timing Diagram 31 Embedded Ultra-Low Power Intel486TM SX Processor 5.4 Capacitive Derating Curves The following graphs are the capacitive derating curves for the embedded ULP Intel486 SX processor. nom+7 nom+6 Delay (ns) nom+5 nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 125 150 Capacitive Load (pF) NOTE: This graph will not be linear outside of the capacitive range shown. nom = nominal value from the AC Characteristics table. Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-toHigh Transition Delay (ns) nom+5 nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 Capacitive Load (pF) 125 150 NOTE: This graph will not be linear outside of the capacitive range shown. nom = nominal value from the AC Characteristics table. Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Highto-Low Transition 32 Embedded Ultra-Low Power Intel486TM SX Processor 6.0 MECHANICAL DATA This section describes the packaging dimensions and thermal specifications for the embedded ULP Intel486 SX processor. 6.1 Package Dimensions 26.0 0.40 24.0 0.10 176 133 1 132 0 Min 10 Max 0.10 0.10 0.60 0.20 0.50 0.10 1.50 0.20 44 0.10 0.10 89 0.16 Min o.28 Max 45 88 NOTES: Height measurements same as width measurements Units: mm A4586-01 Figure 14. Package Mechanical Specifications for the 176-Lead TQFP Package 33 Embedded Ultra-Low Power Intel486TM SX Processor 6.2 Package Thermal Specifications The embedded ULP Intel486 SX processor is specified for operation when the case temperature (TC) is within the range of 0C to 85C. TC may be measured in any environment to determine whether the processor is within the specified operating range. The ambient temperature (TA) can be calculated from JC and JA from the following equations: TJ = TC + P * JC Where TJ, TA, TC equals Junction, Ambient and Case Temperature respectively. JC, JA equals Junction-to-Case and Junction-to-Ambient thermal Resistance, respectively. Maximum Power Consumption (P) is defined as P= V (typ) * ICC (max) P= [VCC (typ) * ICC1 (max)] + [VCCP (typ) * ICC2(max)] where: ICC1 is the VCC supply current ICC2 is the VCCP supply current TA = TJ - P * JA TC = TA + P * [JA - JC] Values for JA and JC are given in the following tables for each product at its maximum operating frequencies. TA = TC - P * [JA - JC] Table 18. Thermal Resistance (C/W) JC and JA for the 176-Lead TQFP Package JC (C/W) JA (C/W) with no airflow 4.3 33.6 The following table shows maximum ambient temperatures of the embedded ULP Intel486 SX processor for each product and maximum operating frequencies. These temperatures are calculated using ICC1 and ICC2 values measured during component-validation testing using VCCP=3.6 V and worst-case VCC values. Table 19. Maximum Ambient Temperature (TA) 176-Lead TQFP Package Frequency 25 MHz 33 MHz 34 VCC TA (C) with no airflow 2.4 V 76 3.3 V 65 2.7 V 69 3.3 V 59